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drm/radeon/kms/pm: track current voltage (v2)
[net-next-2.6.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
771fe6b9 32#include "drmP.h"
3ce0a23d 33#include "radeon_drm.h"
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
771fe6b9 40
3ce0a23d
JG		 41#define PFP_UCODE_SIZE 576
42#define PM4_UCODE_SIZE 1792
d8f60cfc 43#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 44#define R700_PFP_UCODE_SIZE 848
45#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 46#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 49#define EVERGREEN_RLC_UCODE_SIZE 768
3ce0a23d
JG		 50
51/* Firmware Names */
52MODULE_FIRMWARE("radeon/R600_pfp.bin");
53MODULE_FIRMWARE("radeon/R600_me.bin");
54MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55MODULE_FIRMWARE("radeon/RV610_me.bin");
56MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57MODULE_FIRMWARE("radeon/RV630_me.bin");
58MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59MODULE_FIRMWARE("radeon/RV620_me.bin");
60MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61MODULE_FIRMWARE("radeon/RV635_me.bin");
62MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63MODULE_FIRMWARE("radeon/RV670_me.bin");
64MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65MODULE_FIRMWARE("radeon/RS780_me.bin");
66MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67MODULE_FIRMWARE("radeon/RV770_me.bin");
68MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69MODULE_FIRMWARE("radeon/RV730_me.bin");
70MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 72MODULE_FIRMWARE("radeon/R600_rlc.bin");
73MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 74MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 76MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 80MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 82MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 83MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 84MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 85MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
3ce0a23d
JG		 86
87int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 88
1a029b76 89/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 90int r600_mc_wait_for_idle(struct radeon_device *rdev);
91void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 92void r600_fini(struct radeon_device *rdev);
45f9a39b 93void r600_irq_disable(struct radeon_device *rdev);
771fe6b9 94
ce8f5370 95void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 96{
97 int i;
98
ce8f5370
AD		 99 rdev->pm.dynpm_can_upclock = true;
100 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 101
102 /* power state array is low to high, default is first */
103 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
104 int min_power_state_index = 0;
105
106 if (rdev->pm.num_power_states > 2)
107 min_power_state_index = 1;
108
ce8f5370
AD		 109 switch (rdev->pm.dynpm_planned_action) {
110 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 111 rdev->pm.requested_power_state_index = min_power_state_index;
112 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 113 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 114 break;
ce8f5370 115 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 116 if (rdev->pm.current_power_state_index == min_power_state_index) {
117 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 118 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 119 } else {
120 if (rdev->pm.active_crtc_count > 1) {
121 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 122 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 123 continue;
124 else if (i >= rdev->pm.current_power_state_index) {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.current_power_state_index;
127 break;
128 } else {
129 rdev->pm.requested_power_state_index = i;
130 break;
131 }
132 }
133 } else
134 rdev->pm.requested_power_state_index =
135 rdev->pm.current_power_state_index - 1;
136 }
137 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 138 /* don't use the power state if crtcs are active and no display flag is set */
139 if ((rdev->pm.active_crtc_count > 0) &&
140 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
141 clock_info[rdev->pm.requested_clock_mode_index].flags &
142 RADEON_PM_MODE_NO_DISPLAY)) {
143 rdev->pm.requested_power_state_index++;
144 }
a48b9b4e 145 break;
ce8f5370 146 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 147 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
148 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 149 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 150 } else {
151 if (rdev->pm.active_crtc_count > 1) {
152 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 153 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 154 continue;
155 else if (i <= rdev->pm.current_power_state_index) {
156 rdev->pm.requested_power_state_index =
157 rdev->pm.current_power_state_index;
158 break;
159 } else {
160 rdev->pm.requested_power_state_index = i;
161 break;
162 }
163 }
164 } else
165 rdev->pm.requested_power_state_index =
166 rdev->pm.current_power_state_index + 1;
167 }
168 rdev->pm.requested_clock_mode_index = 0;
169 break;
ce8f5370 170 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 171 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
172 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 173 rdev->pm.dynpm_can_upclock = false;
58e21dff 174 break;
ce8f5370 175 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 176 default:
177 DRM_ERROR("Requested mode for not defined action\n");
178 return;
179 }
180 } else {
181 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
182 /* for now just select the first power state and switch between clock modes */
183 /* power state array is low to high, default is first (0) */
184 if (rdev->pm.active_crtc_count > 1) {
185 rdev->pm.requested_power_state_index = -1;
186 /* start at 1 as we don't want the default mode */
187 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 188 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 189 continue;
190 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
191 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
192 rdev->pm.requested_power_state_index = i;
193 break;
194 }
195 }
196 /* if nothing selected, grab the default state. */
197 if (rdev->pm.requested_power_state_index == -1)
198 rdev->pm.requested_power_state_index = 0;
199 } else
200 rdev->pm.requested_power_state_index = 1;
201
ce8f5370
AD		 202 switch (rdev->pm.dynpm_planned_action) {
203 case DYNPM_ACTION_MINIMUM:
a48b9b4e 204 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 205 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 206 break;
ce8f5370 207 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 208 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
209 if (rdev->pm.current_clock_mode_index == 0) {
210 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 211 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 212 } else
213 rdev->pm.requested_clock_mode_index =
214 rdev->pm.current_clock_mode_index - 1;
215 } else {
216 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 217 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 218 }
d7311171
AD		 219 /* don't use the power state if crtcs are active and no display flag is set */
220 if ((rdev->pm.active_crtc_count > 0) &&
221 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
222 clock_info[rdev->pm.requested_clock_mode_index].flags &
223 RADEON_PM_MODE_NO_DISPLAY)) {
224 rdev->pm.requested_clock_mode_index++;
225 }
a48b9b4e 226 break;
ce8f5370 227 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 228 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
229 if (rdev->pm.current_clock_mode_index ==
230 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
231 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 232 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 233 } else
234 rdev->pm.requested_clock_mode_index =
235 rdev->pm.current_clock_mode_index + 1;
236 } else {
237 rdev->pm.requested_clock_mode_index =
238 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 239 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 240 }
241 break;
ce8f5370 242 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 243 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
244 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 245 rdev->pm.dynpm_can_upclock = false;
58e21dff 246 break;
ce8f5370 247 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 248 default:
249 DRM_ERROR("Requested mode for not defined action\n");
250 return;
251 }
252 }
253
ce8a3eb2
AD		 254 DRM_DEBUG("Requested: e: %d m: %d p: %d\n",
255 rdev->pm.power_state[rdev->pm.requested_power_state_index].
256 clock_info[rdev->pm.requested_clock_mode_index].sclk,
257 rdev->pm.power_state[rdev->pm.requested_power_state_index].
258 clock_info[rdev->pm.requested_clock_mode_index].mclk,
259 rdev->pm.power_state[rdev->pm.requested_power_state_index].
260 pcie_lanes);
a48b9b4e
AD		 261}
262
ce8f5370
AD		 263static int r600_pm_get_type_index(struct radeon_device *rdev,
264 enum radeon_pm_state_type ps_type,
265 int instance)
bae6b562 266{
ce8f5370
AD		 267 int i;
268 int found_instance = -1;
bae6b562 269
ce8f5370
AD		 270 for (i = 0; i < rdev->pm.num_power_states; i++) {
271 if (rdev->pm.power_state[i].type == ps_type) {
272 found_instance++;
273 if (found_instance == instance)
274 return i;
a424816f 275 }
ce8f5370
AD		 276 }
277 /* return default if no match */
278 return rdev->pm.default_power_state_index;
279}
280
281void rs780_pm_init_profile(struct radeon_device *rdev)
282{
283 if (rdev->pm.num_power_states == 2) {
284 /* default */
285 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
286 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
287 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
288 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
289 /* low sh */
290 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
291 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
292 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
293 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 294 /* mid sh */
295 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
296 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 299 /* high sh */
300 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
302 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
304 /* low mh */
305 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 309 /* mid mh */
310 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 314 /* high mh */
315 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
317 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
319 } else if (rdev->pm.num_power_states == 3) {
320 /* default */
321 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
322 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
325 /* low sh */
326 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
327 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 330 /* mid sh */
331 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
332 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
333 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 335 /* high sh */
336 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
337 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
338 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
340 /* low mh */
341 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
342 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 345 /* mid mh */
346 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 350 /* high mh */
351 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
352 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
353 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
355 } else {
356 /* default */
357 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
358 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
359 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
361 /* low sh */
362 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
363 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 366 /* mid sh */
367 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
368 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
369 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
370 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 371 /* high sh */
372 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
373 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
374 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
375 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
376 /* low mh */
377 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
378 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
380 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 381 /* mid mh */
382 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
385 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 386 /* high mh */
387 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
388 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
389 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
391 }
392}
bae6b562 393
ce8f5370
AD		 394void r600_pm_init_profile(struct radeon_device *rdev)
395{
396 if (rdev->family == CHIP_R600) {
397 /* XXX */
398 /* default */
399 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
400 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
401 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 402 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 403 /* low sh */
404 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
405 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
406 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 407 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 408 /* mid sh */
409 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
410 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
411 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
412 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 413 /* high sh */
414 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
415 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
416 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 417 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 418 /* low mh */
419 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
420 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
421 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 422 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 423 /* mid mh */
424 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
425 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
426 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
427 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 428 /* high mh */
429 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
430 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
431 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 432 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 433 } else {
434 if (rdev->pm.num_power_states < 4) {
435 /* default */
436 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
440 /* low sh */
4bff5171
AD		 441 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
442 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 443 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 444 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
445 /* mid sh */
446 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
447 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
448 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
449 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 450 /* high sh */
4bff5171
AD		 451 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
452 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 453 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
454 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
455 /* low mh */
4bff5171
AD		 456 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
457 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 458 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 459 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
460 /* low mh */
461 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
462 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
463 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
464 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 465 /* high mh */
4bff5171
AD		 466 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
467 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 468 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
469 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
470 } else {
471 /* default */
472 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
473 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
474 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
475 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
476 /* low sh */
4bff5171
AD		 477 if (rdev->flags & RADEON_IS_MOBILITY) {
478 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
479 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
480 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
481 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
482 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21 483 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 484 } else {
485 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
486 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
487 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
488 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
489 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 490 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
491 }
492 /* mid sh */
493 if (rdev->flags & RADEON_IS_MOBILITY) {
494 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
495 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
496 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
497 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
500 } else {
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
502 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
503 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
504 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
506 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
4bff5171 507 }
ce8f5370 508 /* high sh */
4bff5171
AD		 509 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
510 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
511 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
512 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
ce8f5370
AD		 513 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
514 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
515 /* low mh */
4bff5171
AD		 516 if (rdev->flags & RADEON_IS_MOBILITY) {
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
518 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
519 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
520 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
521 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21 522 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 523 } else {
524 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
525 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
526 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
527 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
528 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 529 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
530 }
531 /* mid mh */
532 if (rdev->flags & RADEON_IS_MOBILITY) {
533 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
534 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
535 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
536 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
537 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
539 } else {
540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
541 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
542 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
543 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
544 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
4bff5171 546 }
ce8f5370 547 /* high mh */
4bff5171
AD		 548 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
549 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
550 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
551 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
ce8f5370
AD		 552 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
554 }
555 }
bae6b562
AD		 556}
557
49e02b73
AD		 558void r600_pm_misc(struct radeon_device *rdev)
559{
7ac9aa5a
AD		 560 int requested_index = rdev->pm.requested_power_state_index;
561 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
562 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
563
4d60173f
AD		 564 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
565 if (voltage->voltage != rdev->pm.current_vddc) {
566 radeon_atom_set_voltage(rdev, voltage->voltage);
567 rdev->pm.current_vddc = voltage->voltage;
568 }
569 }
49e02b73
AD		 570}
571
def9ba9c
AD		 572bool r600_gui_idle(struct radeon_device *rdev)
573{
574 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
575 return false;
576 else
577 return true;
578}
579
e0df1ac5
AD		 580/* hpd for digital panel detect/disconnect */
581bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
582{
583 bool connected = false;
584
585 if (ASIC_IS_DCE3(rdev)) {
586 switch (hpd) {
587 case RADEON_HPD_1:
588 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
589 connected = true;
590 break;
591 case RADEON_HPD_2:
592 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
593 connected = true;
594 break;
595 case RADEON_HPD_3:
596 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
597 connected = true;
598 break;
599 case RADEON_HPD_4:
600 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
601 connected = true;
602 break;
603 /* DCE 3.2 */
604 case RADEON_HPD_5:
605 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
606 connected = true;
607 break;
608 case RADEON_HPD_6:
609 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
610 connected = true;
611 break;
612 default:
613 break;
614 }
615 } else {
616 switch (hpd) {
617 case RADEON_HPD_1:
618 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
619 connected = true;
620 break;
621 case RADEON_HPD_2:
622 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
623 connected = true;
624 break;
625 case RADEON_HPD_3:
626 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
627 connected = true;
628 break;
629 default:
630 break;
631 }
632 }
633 return connected;
634}
635
636void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 637 enum radeon_hpd_id hpd)
e0df1ac5
AD		 638{
639 u32 tmp;
640 bool connected = r600_hpd_sense(rdev, hpd);
641
642 if (ASIC_IS_DCE3(rdev)) {
643 switch (hpd) {
644 case RADEON_HPD_1:
645 tmp = RREG32(DC_HPD1_INT_CONTROL);
646 if (connected)
647 tmp &= ~DC_HPDx_INT_POLARITY;
648 else
649 tmp |= DC_HPDx_INT_POLARITY;
650 WREG32(DC_HPD1_INT_CONTROL, tmp);
651 break;
652 case RADEON_HPD_2:
653 tmp = RREG32(DC_HPD2_INT_CONTROL);
654 if (connected)
655 tmp &= ~DC_HPDx_INT_POLARITY;
656 else
657 tmp |= DC_HPDx_INT_POLARITY;
658 WREG32(DC_HPD2_INT_CONTROL, tmp);
659 break;
660 case RADEON_HPD_3:
661 tmp = RREG32(DC_HPD3_INT_CONTROL);
662 if (connected)
663 tmp &= ~DC_HPDx_INT_POLARITY;
664 else
665 tmp |= DC_HPDx_INT_POLARITY;
666 WREG32(DC_HPD3_INT_CONTROL, tmp);
667 break;
668 case RADEON_HPD_4:
669 tmp = RREG32(DC_HPD4_INT_CONTROL);
670 if (connected)
671 tmp &= ~DC_HPDx_INT_POLARITY;
672 else
673 tmp |= DC_HPDx_INT_POLARITY;
674 WREG32(DC_HPD4_INT_CONTROL, tmp);
675 break;
676 case RADEON_HPD_5:
677 tmp = RREG32(DC_HPD5_INT_CONTROL);
678 if (connected)
679 tmp &= ~DC_HPDx_INT_POLARITY;
680 else
681 tmp |= DC_HPDx_INT_POLARITY;
682 WREG32(DC_HPD5_INT_CONTROL, tmp);
683 break;
684 /* DCE 3.2 */
685 case RADEON_HPD_6:
686 tmp = RREG32(DC_HPD6_INT_CONTROL);
687 if (connected)
688 tmp &= ~DC_HPDx_INT_POLARITY;
689 else
690 tmp |= DC_HPDx_INT_POLARITY;
691 WREG32(DC_HPD6_INT_CONTROL, tmp);
692 break;
693 default:
694 break;
695 }
696 } else {
697 switch (hpd) {
698 case RADEON_HPD_1:
699 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
700 if (connected)
701 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
702 else
703 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
704 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
705 break;
706 case RADEON_HPD_2:
707 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
708 if (connected)
709 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
710 else
711 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
712 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
713 break;
714 case RADEON_HPD_3:
715 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
716 if (connected)
717 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
718 else
719 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
720 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
721 break;
722 default:
723 break;
724 }
725 }
726}
727
728void r600_hpd_init(struct radeon_device *rdev)
729{
730 struct drm_device *dev = rdev->ddev;
731 struct drm_connector *connector;
732
733 if (ASIC_IS_DCE3(rdev)) {
734 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
735 if (ASIC_IS_DCE32(rdev))
736 tmp |= DC_HPDx_EN;
737
738 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
739 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
740 switch (radeon_connector->hpd.hpd) {
741 case RADEON_HPD_1:
742 WREG32(DC_HPD1_CONTROL, tmp);
743 rdev->irq.hpd[0] = true;
744 break;
745 case RADEON_HPD_2:
746 WREG32(DC_HPD2_CONTROL, tmp);
747 rdev->irq.hpd[1] = true;
748 break;
749 case RADEON_HPD_3:
750 WREG32(DC_HPD3_CONTROL, tmp);
751 rdev->irq.hpd[2] = true;
752 break;
753 case RADEON_HPD_4:
754 WREG32(DC_HPD4_CONTROL, tmp);
755 rdev->irq.hpd[3] = true;
756 break;
757 /* DCE 3.2 */
758 case RADEON_HPD_5:
759 WREG32(DC_HPD5_CONTROL, tmp);
760 rdev->irq.hpd[4] = true;
761 break;
762 case RADEON_HPD_6:
763 WREG32(DC_HPD6_CONTROL, tmp);
764 rdev->irq.hpd[5] = true;
765 break;
766 default:
767 break;
768 }
769 }
770 } else {
771 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
772 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
773 switch (radeon_connector->hpd.hpd) {
774 case RADEON_HPD_1:
775 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
776 rdev->irq.hpd[0] = true;
777 break;
778 case RADEON_HPD_2:
779 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
780 rdev->irq.hpd[1] = true;
781 break;
782 case RADEON_HPD_3:
783 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
784 rdev->irq.hpd[2] = true;
785 break;
786 default:
787 break;
788 }
789 }
790 }
003e69f9
JG		 791 if (rdev->irq.installed)
792 r600_irq_set(rdev);
e0df1ac5
AD		 793}
794
795void r600_hpd_fini(struct radeon_device *rdev)
796{
797 struct drm_device *dev = rdev->ddev;
798 struct drm_connector *connector;
799
800 if (ASIC_IS_DCE3(rdev)) {
801 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
802 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
803 switch (radeon_connector->hpd.hpd) {
804 case RADEON_HPD_1:
805 WREG32(DC_HPD1_CONTROL, 0);
806 rdev->irq.hpd[0] = false;
807 break;
808 case RADEON_HPD_2:
809 WREG32(DC_HPD2_CONTROL, 0);
810 rdev->irq.hpd[1] = false;
811 break;
812 case RADEON_HPD_3:
813 WREG32(DC_HPD3_CONTROL, 0);
814 rdev->irq.hpd[2] = false;
815 break;
816 case RADEON_HPD_4:
817 WREG32(DC_HPD4_CONTROL, 0);
818 rdev->irq.hpd[3] = false;
819 break;
820 /* DCE 3.2 */
821 case RADEON_HPD_5:
822 WREG32(DC_HPD5_CONTROL, 0);
823 rdev->irq.hpd[4] = false;
824 break;
825 case RADEON_HPD_6:
826 WREG32(DC_HPD6_CONTROL, 0);
827 rdev->irq.hpd[5] = false;
828 break;
829 default:
830 break;
831 }
832 }
833 } else {
834 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
835 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
836 switch (radeon_connector->hpd.hpd) {
837 case RADEON_HPD_1:
838 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
839 rdev->irq.hpd[0] = false;
840 break;
841 case RADEON_HPD_2:
842 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
843 rdev->irq.hpd[1] = false;
844 break;
845 case RADEON_HPD_3:
846 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
847 rdev->irq.hpd[2] = false;
848 break;
849 default:
850 break;
851 }
852 }
853 }
854}
855
771fe6b9 856/*
3ce0a23d 857 * R600 PCIE GART
771fe6b9 858 */
3ce0a23d
JG		 859void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
860{
861 unsigned i;
862 u32 tmp;
863
2e98f10a
DA		 864 /* flush hdp cache so updates hit vram */
865 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
866
3ce0a23d
JG		 867 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
868 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
869 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
870 for (i = 0; i < rdev->usec_timeout; i++) {
871 /* read MC_STATUS */
872 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
873 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
874 if (tmp == 2) {
875 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
876 return;
877 }
878 if (tmp) {
879 return;
880 }
881 udelay(1);
882 }
883}
884
4aac0473 885int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 886{
4aac0473 887 int r;
3ce0a23d 888
4aac0473
JG		 889 if (rdev->gart.table.vram.robj) {
890 WARN(1, "R600 PCIE GART already initialized.\n");
891 return 0;
892 }
3ce0a23d
JG		 893 /* Initialize common gart structure */
894 r = radeon_gart_init(rdev);
4aac0473 895 if (r)
3ce0a23d 896 return r;
3ce0a23d 897 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 898 return radeon_gart_table_vram_alloc(rdev);
899}
900
901int r600_pcie_gart_enable(struct radeon_device *rdev)
902{
903 u32 tmp;
904 int r, i;
905
906 if (rdev->gart.table.vram.robj == NULL) {
907 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
908 return -EINVAL;
771fe6b9 909 }
4aac0473
JG		 910 r = radeon_gart_table_vram_pin(rdev);
911 if (r)
912 return r;
82568565 913 radeon_gart_restore(rdev);
bc1a631e 914
3ce0a23d
JG		 915 /* Setup L2 cache */
916 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
917 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
918 EFFECTIVE_L2_QUEUE_SIZE(7));
919 WREG32(VM_L2_CNTL2, 0);
920 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
921 /* Setup TLB control */
922 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
923 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
924 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
925 ENABLE_WAIT_L2_QUERY;
926 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
927 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
928 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
929 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
930 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
931 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
932 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
933 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
934 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
935 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
936 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
937 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
938 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
939 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
940 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 941 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 942 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
943 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
944 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
945 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
946 (u32)(rdev->dummy_page.addr >> 12));
947 for (i = 1; i < 7; i++)
948 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 949
3ce0a23d
JG		 950 r600_pcie_gart_tlb_flush(rdev);
951 rdev->gart.ready = true;
771fe6b9
JG		 952 return 0;
953}
954
3ce0a23d 955void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 956{
3ce0a23d 957 u32 tmp;
4c788679 958 int i, r;
771fe6b9 959
3ce0a23d
JG		 960 /* Disable all tables */
961 for (i = 0; i < 7; i++)
962 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 963
3ce0a23d
JG		 964 /* Disable L2 cache */
965 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
966 EFFECTIVE_L2_QUEUE_SIZE(7));
967 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
968 /* Setup L1 TLB control */
969 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
970 ENABLE_WAIT_L2_QUERY;
971 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
973 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
974 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
982 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
983 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
984 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 985 if (rdev->gart.table.vram.robj) {
4c788679
JG		 986 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
987 if (likely(r == 0)) {
988 radeon_bo_kunmap(rdev->gart.table.vram.robj);
989 radeon_bo_unpin(rdev->gart.table.vram.robj);
990 radeon_bo_unreserve(rdev->gart.table.vram.robj);
991 }
4aac0473
JG		 992 }
993}
994
995void r600_pcie_gart_fini(struct radeon_device *rdev)
996{
f9274562 997 radeon_gart_fini(rdev);
4aac0473
JG		 998 r600_pcie_gart_disable(rdev);
999 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1000}
1001
1a029b76
JG		 1002void r600_agp_enable(struct radeon_device *rdev)
1003{
1004 u32 tmp;
1005 int i;
1006
1007 /* Setup L2 cache */
1008 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1009 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1010 EFFECTIVE_L2_QUEUE_SIZE(7));
1011 WREG32(VM_L2_CNTL2, 0);
1012 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1013 /* Setup TLB control */
1014 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1015 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1016 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1017 ENABLE_WAIT_L2_QUERY;
1018 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1019 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1020 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1021 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1023 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1027 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1028 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1029 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1030 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1031 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1032 for (i = 0; i < 7; i++)
1033 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1034}
1035
771fe6b9
JG		 1036int r600_mc_wait_for_idle(struct radeon_device *rdev)
1037{
3ce0a23d
JG		 1038 unsigned i;
1039 u32 tmp;
1040
1041 for (i = 0; i < rdev->usec_timeout; i++) {
1042 /* read MC_STATUS */
1043 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1044 if (!tmp)
1045 return 0;
1046 udelay(1);
1047 }
1048 return -1;
771fe6b9
JG		 1049}
1050
a3c1945a 1051static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1052{
a3c1945a 1053 struct rv515_mc_save save;
3ce0a23d
JG		 1054 u32 tmp;
1055 int i, j;
771fe6b9 1056
3ce0a23d
JG		 1057 /* Initialize HDP */
1058 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1059 WREG32((0x2c14 + j), 0x00000000);
1060 WREG32((0x2c18 + j), 0x00000000);
1061 WREG32((0x2c1c + j), 0x00000000);
1062 WREG32((0x2c20 + j), 0x00000000);
1063 WREG32((0x2c24 + j), 0x00000000);
1064 }
1065 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1066
a3c1945a 1067 rv515_mc_stop(rdev, &save);
3ce0a23d 1068 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1069 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1070 }
a3c1945a 1071 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1072 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1073 /* Update configuration */
1a029b76
JG		 1074 if (rdev->flags & RADEON_IS_AGP) {
1075 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1076 /* VRAM before AGP */
1077 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1078 rdev->mc.vram_start >> 12);
1079 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1080 rdev->mc.gtt_end >> 12);
1081 } else {
1082 /* VRAM after AGP */
1083 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1084 rdev->mc.gtt_start >> 12);
1085 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1086 rdev->mc.vram_end >> 12);
1087 }
1088 } else {
1089 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1090 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1091 }
3ce0a23d 1092 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 1093 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1094 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1095 WREG32(MC_VM_FB_LOCATION, tmp);
1096 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1097 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1a029b76 1098 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
3ce0a23d 1099 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1100 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1101 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1102 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1103 } else {
1104 WREG32(MC_VM_AGP_BASE, 0);
1105 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1106 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1107 }
3ce0a23d 1108 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1109 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1110 }
a3c1945a 1111 rv515_mc_resume(rdev, &save);
698443d9
DA		 1112 /* we need to own VRAM, so turn off the VGA renderer here
1113 * to stop it overwriting our objects */
d39c3b89 1114 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1115}
1116
d594e46a
JG		 1117/**
1118 * r600_vram_gtt_location - try to find VRAM & GTT location
1119 * @rdev: radeon device structure holding all necessary informations
1120 * @mc: memory controller structure holding memory informations
1121 *
1122 * Function will place try to place VRAM at same place as in CPU (PCI)
1123 * address space as some GPU seems to have issue when we reprogram at
1124 * different address space.
1125 *
1126 * If there is not enough space to fit the unvisible VRAM after the
1127 * aperture then we limit the VRAM size to the aperture.
1128 *
1129 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1130 * them to be in one from GPU point of view so that we can program GPU to
1131 * catch access outside them (weird GPU policy see ??).
1132 *
1133 * This function will never fails, worst case are limiting VRAM or GTT.
1134 *
1135 * Note: GTT start, end, size should be initialized before calling this
1136 * function on AGP platform.
1137 */
1138void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1139{
1140 u64 size_bf, size_af;
1141
1142 if (mc->mc_vram_size > 0xE0000000) {
1143 /* leave room for at least 512M GTT */
1144 dev_warn(rdev->dev, "limiting VRAM\n");
1145 mc->real_vram_size = 0xE0000000;
1146 mc->mc_vram_size = 0xE0000000;
1147 }
1148 if (rdev->flags & RADEON_IS_AGP) {
1149 size_bf = mc->gtt_start;
1150 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1151 if (size_bf > size_af) {
1152 if (mc->mc_vram_size > size_bf) {
1153 dev_warn(rdev->dev, "limiting VRAM\n");
1154 mc->real_vram_size = size_bf;
1155 mc->mc_vram_size = size_bf;
1156 }
1157 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1158 } else {
1159 if (mc->mc_vram_size > size_af) {
1160 dev_warn(rdev->dev, "limiting VRAM\n");
1161 mc->real_vram_size = size_af;
1162 mc->mc_vram_size = size_af;
1163 }
1164 mc->vram_start = mc->gtt_end;
1165 }
1166 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1167 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1168 mc->mc_vram_size >> 20, mc->vram_start,
1169 mc->vram_end, mc->real_vram_size >> 20);
1170 } else {
1171 u64 base = 0;
1172 if (rdev->flags & RADEON_IS_IGP)
1173 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1174 radeon_vram_location(rdev, &rdev->mc, base);
1175 radeon_gtt_location(rdev, mc);
1176 }
1177}
1178
3ce0a23d 1179int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1180{
3ce0a23d 1181 u32 tmp;
5885b7a9 1182 int chansize, numchan;
771fe6b9 1183
3ce0a23d 1184 /* Get VRAM informations */
771fe6b9 1185 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1186 tmp = RREG32(RAMCFG);
1187 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1188 chansize = 16;
3ce0a23d 1189 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1190 chansize = 64;
1191 } else {
1192 chansize = 32;
1193 }
5885b7a9
AD		 1194 tmp = RREG32(CHMAP);
1195 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1196 case 0:
1197 default:
1198 numchan = 1;
1199 break;
1200 case 1:
1201 numchan = 2;
1202 break;
1203 case 2:
1204 numchan = 4;
1205 break;
1206 case 3:
1207 numchan = 8;
1208 break;
771fe6b9 1209 }
5885b7a9 1210 rdev->mc.vram_width = numchan * chansize;
3ce0a23d
JG		 1211 /* Could aper size report 0 ? */
1212 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1213 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1214 /* Setup GPU memory space */
1215 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1216 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1217 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1218 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1219
06b6476d
AD		 1220 if (rdev->flags & RADEON_IS_IGP)
1221 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f47299c5 1222 radeon_update_bandwidth_info(rdev);
3ce0a23d 1223 return 0;
771fe6b9
JG		 1224}
1225
3ce0a23d
JG		 1226/* We doesn't check that the GPU really needs a reset we simply do the
1227 * reset, it's up to the caller to determine if the GPU needs one. We
1228 * might add an helper function to check that.
1229 */
1230int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1231{
a3c1945a 1232 struct rv515_mc_save save;
3ce0a23d
JG		 1233 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1234 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1235 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1236 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1237 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1238 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1239 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1240 S_008010_GUI_ACTIVE(1);
1241 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1242 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1243 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1244 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1245 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1246 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1247 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1248 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1249 u32 tmp;
771fe6b9 1250
1a029b76
JG		 1251 dev_info(rdev->dev, "GPU softreset \n");
1252 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1253 RREG32(R_008010_GRBM_STATUS));
1254 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1255 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1256 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1257 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1258 rv515_mc_stop(rdev, &save);
1259 if (r600_mc_wait_for_idle(rdev)) {
1260 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1261 }
3ce0a23d 1262 /* Disable CP parsing/prefetching */
90aca4d2 1263 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1264 /* Check if any of the rendering block is busy and reset it */
1265 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1266 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1267 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1268 S_008020_SOFT_RESET_DB(1) |
1269 S_008020_SOFT_RESET_CB(1) |
1270 S_008020_SOFT_RESET_PA(1) |
1271 S_008020_SOFT_RESET_SC(1) |
1272 S_008020_SOFT_RESET_SMX(1) |
1273 S_008020_SOFT_RESET_SPI(1) |
1274 S_008020_SOFT_RESET_SX(1) |
1275 S_008020_SOFT_RESET_SH(1) |
1276 S_008020_SOFT_RESET_TC(1) |
1277 S_008020_SOFT_RESET_TA(1) |
1278 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1279 S_008020_SOFT_RESET_VGT(1);
1a029b76 1280 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1281 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1282 RREG32(R_008020_GRBM_SOFT_RESET);
1283 mdelay(15);
3ce0a23d 1284 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1285 }
1286 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1287 tmp = S_008020_SOFT_RESET_CP(1);
1288 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1289 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1290 RREG32(R_008020_GRBM_SOFT_RESET);
1291 mdelay(15);
3ce0a23d 1292 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1293 /* Wait a little for things to settle down */
225758d8 1294 mdelay(1);
1a029b76
JG		 1295 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1296 RREG32(R_008010_GRBM_STATUS));
1297 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1298 RREG32(R_008014_GRBM_STATUS2));
1299 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1300 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1301 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1302 return 0;
1303}
1304
225758d8
JG		 1305bool r600_gpu_is_lockup(struct radeon_device *rdev)
1306{
1307 u32 srbm_status;
1308 u32 grbm_status;
1309 u32 grbm_status2;
1310 int r;
1311
1312 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1313 grbm_status = RREG32(R_008010_GRBM_STATUS);
1314 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1315 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1316 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1317 return false;
1318 }
1319 /* force CP activities */
1320 r = radeon_ring_lock(rdev, 2);
1321 if (!r) {
1322 /* PACKET2 NOP */
1323 radeon_ring_write(rdev, 0x80000000);
1324 radeon_ring_write(rdev, 0x80000000);
1325 radeon_ring_unlock_commit(rdev);
1326 }
1327 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1328 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1329}
1330
a2d07b74 1331int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1332{
1333 return r600_gpu_soft_reset(rdev);
1334}
1335
1336static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1337 u32 num_backends,
1338 u32 backend_disable_mask)
1339{
1340 u32 backend_map = 0;
1341 u32 enabled_backends_mask;
1342 u32 enabled_backends_count;
1343 u32 cur_pipe;
1344 u32 swizzle_pipe[R6XX_MAX_PIPES];
1345 u32 cur_backend;
1346 u32 i;
1347
1348 if (num_tile_pipes > R6XX_MAX_PIPES)
1349 num_tile_pipes = R6XX_MAX_PIPES;
1350 if (num_tile_pipes < 1)
1351 num_tile_pipes = 1;
1352 if (num_backends > R6XX_MAX_BACKENDS)
1353 num_backends = R6XX_MAX_BACKENDS;
1354 if (num_backends < 1)
1355 num_backends = 1;
1356
1357 enabled_backends_mask = 0;
1358 enabled_backends_count = 0;
1359 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1360 if (((backend_disable_mask >> i) & 1) == 0) {
1361 enabled_backends_mask |= (1 << i);
1362 ++enabled_backends_count;
1363 }
1364 if (enabled_backends_count == num_backends)
1365 break;
1366 }
1367
1368 if (enabled_backends_count == 0) {
1369 enabled_backends_mask = 1;
1370 enabled_backends_count = 1;
1371 }
1372
1373 if (enabled_backends_count != num_backends)
1374 num_backends = enabled_backends_count;
1375
1376 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1377 switch (num_tile_pipes) {
1378 case 1:
1379 swizzle_pipe[0] = 0;
1380 break;
1381 case 2:
1382 swizzle_pipe[0] = 0;
1383 swizzle_pipe[1] = 1;
1384 break;
1385 case 3:
1386 swizzle_pipe[0] = 0;
1387 swizzle_pipe[1] = 1;
1388 swizzle_pipe[2] = 2;
1389 break;
1390 case 4:
1391 swizzle_pipe[0] = 0;
1392 swizzle_pipe[1] = 1;
1393 swizzle_pipe[2] = 2;
1394 swizzle_pipe[3] = 3;
1395 break;
1396 case 5:
1397 swizzle_pipe[0] = 0;
1398 swizzle_pipe[1] = 1;
1399 swizzle_pipe[2] = 2;
1400 swizzle_pipe[3] = 3;
1401 swizzle_pipe[4] = 4;
1402 break;
1403 case 6:
1404 swizzle_pipe[0] = 0;
1405 swizzle_pipe[1] = 2;
1406 swizzle_pipe[2] = 4;
1407 swizzle_pipe[3] = 5;
1408 swizzle_pipe[4] = 1;
1409 swizzle_pipe[5] = 3;
1410 break;
1411 case 7:
1412 swizzle_pipe[0] = 0;
1413 swizzle_pipe[1] = 2;
1414 swizzle_pipe[2] = 4;
1415 swizzle_pipe[3] = 6;
1416 swizzle_pipe[4] = 1;
1417 swizzle_pipe[5] = 3;
1418 swizzle_pipe[6] = 5;
1419 break;
1420 case 8:
1421 swizzle_pipe[0] = 0;
1422 swizzle_pipe[1] = 2;
1423 swizzle_pipe[2] = 4;
1424 swizzle_pipe[3] = 6;
1425 swizzle_pipe[4] = 1;
1426 swizzle_pipe[5] = 3;
1427 swizzle_pipe[6] = 5;
1428 swizzle_pipe[7] = 7;
1429 break;
1430 }
1431
1432 cur_backend = 0;
1433 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1434 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1435 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1436
1437 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1438
1439 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1440 }
1441
1442 return backend_map;
1443}
1444
1445int r600_count_pipe_bits(uint32_t val)
1446{
1447 int i, ret = 0;
1448
1449 for (i = 0; i < 32; i++) {
1450 ret += val & 1;
1451 val >>= 1;
1452 }
1453 return ret;
771fe6b9
JG		 1454}
1455
3ce0a23d
JG		 1456void r600_gpu_init(struct radeon_device *rdev)
1457{
1458 u32 tiling_config;
1459 u32 ramcfg;
d03f5d59
AD		 1460 u32 backend_map;
1461 u32 cc_rb_backend_disable;
1462 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1463 u32 tmp;
1464 int i, j;
1465 u32 sq_config;
1466 u32 sq_gpr_resource_mgmt_1 = 0;
1467 u32 sq_gpr_resource_mgmt_2 = 0;
1468 u32 sq_thread_resource_mgmt = 0;
1469 u32 sq_stack_resource_mgmt_1 = 0;
1470 u32 sq_stack_resource_mgmt_2 = 0;
1471
1472 /* FIXME: implement */
1473 switch (rdev->family) {
1474 case CHIP_R600:
1475 rdev->config.r600.max_pipes = 4;
1476 rdev->config.r600.max_tile_pipes = 8;
1477 rdev->config.r600.max_simds = 4;
1478 rdev->config.r600.max_backends = 4;
1479 rdev->config.r600.max_gprs = 256;
1480 rdev->config.r600.max_threads = 192;
1481 rdev->config.r600.max_stack_entries = 256;
1482 rdev->config.r600.max_hw_contexts = 8;
1483 rdev->config.r600.max_gs_threads = 16;
1484 rdev->config.r600.sx_max_export_size = 128;
1485 rdev->config.r600.sx_max_export_pos_size = 16;
1486 rdev->config.r600.sx_max_export_smx_size = 128;
1487 rdev->config.r600.sq_num_cf_insts = 2;
1488 break;
1489 case CHIP_RV630:
1490 case CHIP_RV635:
1491 rdev->config.r600.max_pipes = 2;
1492 rdev->config.r600.max_tile_pipes = 2;
1493 rdev->config.r600.max_simds = 3;
1494 rdev->config.r600.max_backends = 1;
1495 rdev->config.r600.max_gprs = 128;
1496 rdev->config.r600.max_threads = 192;
1497 rdev->config.r600.max_stack_entries = 128;
1498 rdev->config.r600.max_hw_contexts = 8;
1499 rdev->config.r600.max_gs_threads = 4;
1500 rdev->config.r600.sx_max_export_size = 128;
1501 rdev->config.r600.sx_max_export_pos_size = 16;
1502 rdev->config.r600.sx_max_export_smx_size = 128;
1503 rdev->config.r600.sq_num_cf_insts = 2;
1504 break;
1505 case CHIP_RV610:
1506 case CHIP_RV620:
1507 case CHIP_RS780:
1508 case CHIP_RS880:
1509 rdev->config.r600.max_pipes = 1;
1510 rdev->config.r600.max_tile_pipes = 1;
1511 rdev->config.r600.max_simds = 2;
1512 rdev->config.r600.max_backends = 1;
1513 rdev->config.r600.max_gprs = 128;
1514 rdev->config.r600.max_threads = 192;
1515 rdev->config.r600.max_stack_entries = 128;
1516 rdev->config.r600.max_hw_contexts = 4;
1517 rdev->config.r600.max_gs_threads = 4;
1518 rdev->config.r600.sx_max_export_size = 128;
1519 rdev->config.r600.sx_max_export_pos_size = 16;
1520 rdev->config.r600.sx_max_export_smx_size = 128;
1521 rdev->config.r600.sq_num_cf_insts = 1;
1522 break;
1523 case CHIP_RV670:
1524 rdev->config.r600.max_pipes = 4;
1525 rdev->config.r600.max_tile_pipes = 4;
1526 rdev->config.r600.max_simds = 4;
1527 rdev->config.r600.max_backends = 4;
1528 rdev->config.r600.max_gprs = 192;
1529 rdev->config.r600.max_threads = 192;
1530 rdev->config.r600.max_stack_entries = 256;
1531 rdev->config.r600.max_hw_contexts = 8;
1532 rdev->config.r600.max_gs_threads = 16;
1533 rdev->config.r600.sx_max_export_size = 128;
1534 rdev->config.r600.sx_max_export_pos_size = 16;
1535 rdev->config.r600.sx_max_export_smx_size = 128;
1536 rdev->config.r600.sq_num_cf_insts = 2;
1537 break;
1538 default:
1539 break;
1540 }
1541
1542 /* Initialize HDP */
1543 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1544 WREG32((0x2c14 + j), 0x00000000);
1545 WREG32((0x2c18 + j), 0x00000000);
1546 WREG32((0x2c1c + j), 0x00000000);
1547 WREG32((0x2c20 + j), 0x00000000);
1548 WREG32((0x2c24 + j), 0x00000000);
1549 }
1550
1551 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1552
1553 /* Setup tiling */
1554 tiling_config = 0;
1555 ramcfg = RREG32(RAMCFG);
1556 switch (rdev->config.r600.max_tile_pipes) {
1557 case 1:
1558 tiling_config |= PIPE_TILING(0);
1559 break;
1560 case 2:
1561 tiling_config |= PIPE_TILING(1);
1562 break;
1563 case 4:
1564 tiling_config |= PIPE_TILING(2);
1565 break;
1566 case 8:
1567 tiling_config |= PIPE_TILING(3);
1568 break;
1569 default:
1570 break;
1571 }
d03f5d59 1572 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1573 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d
JG		 1574 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1575 tiling_config |= GROUP_SIZE(0);
961fb597 1576 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1577 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1578 if (tmp > 3) {
1579 tiling_config |= ROW_TILING(3);
1580 tiling_config |= SAMPLE_SPLIT(3);
1581 } else {
1582 tiling_config |= ROW_TILING(tmp);
1583 tiling_config |= SAMPLE_SPLIT(tmp);
1584 }
1585 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1586
1587 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1588 cc_rb_backend_disable |=
1589 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1590
1591 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1592 cc_gc_shader_pipe_config |=
1593 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1594 cc_gc_shader_pipe_config |=
1595 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1596
1597 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1598 (R6XX_MAX_BACKENDS -
1599 r600_count_pipe_bits((cc_rb_backend_disable &
1600 R6XX_MAX_BACKENDS_MASK) >> 16)),
1601 (cc_rb_backend_disable >> 16));
1602
1603 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1604 WREG32(GB_TILING_CONFIG, tiling_config);
1605 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1606 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1607
3ce0a23d 1608 /* Setup pipes */
d03f5d59
AD		 1609 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1610 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1611 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1612
d03f5d59 1613 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1614 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1615 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1616
1617 /* Setup some CP states */
1618 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1619 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1620
1621 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1622 SYNC_WALKER | SYNC_ALIGNER));
1623 /* Setup various GPU states */
1624 if (rdev->family == CHIP_RV670)
1625 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1626
1627 tmp = RREG32(SX_DEBUG_1);
1628 tmp |= SMX_EVENT_RELEASE;
1629 if ((rdev->family > CHIP_R600))
1630 tmp |= ENABLE_NEW_SMX_ADDRESS;
1631 WREG32(SX_DEBUG_1, tmp);
1632
1633 if (((rdev->family) == CHIP_R600) ||
1634 ((rdev->family) == CHIP_RV630) ||
1635 ((rdev->family) == CHIP_RV610) ||
1636 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1637 ((rdev->family) == CHIP_RS780) ||
1638 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1639 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1640 } else {
1641 WREG32(DB_DEBUG, 0);
1642 }
1643 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1644 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1645
1646 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1647 WREG32(VGT_NUM_INSTANCES, 0);
1648
1649 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1650 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1651
1652 tmp = RREG32(SQ_MS_FIFO_SIZES);
1653 if (((rdev->family) == CHIP_RV610) ||
1654 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1655 ((rdev->family) == CHIP_RS780) ||
1656 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1657 tmp = (CACHE_FIFO_SIZE(0xa) |
1658 FETCH_FIFO_HIWATER(0xa) |
1659 DONE_FIFO_HIWATER(0xe0) |
1660 ALU_UPDATE_FIFO_HIWATER(0x8));
1661 } else if (((rdev->family) == CHIP_R600) ||
1662 ((rdev->family) == CHIP_RV630)) {
1663 tmp &= ~DONE_FIFO_HIWATER(0xff);
1664 tmp |= DONE_FIFO_HIWATER(0x4);
1665 }
1666 WREG32(SQ_MS_FIFO_SIZES, tmp);
1667
1668 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1669 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1670 */
1671 sq_config = RREG32(SQ_CONFIG);
1672 sq_config &= ~(PS_PRIO(3) |
1673 VS_PRIO(3) |
1674 GS_PRIO(3) |
1675 ES_PRIO(3));
1676 sq_config |= (DX9_CONSTS |
1677 VC_ENABLE |
1678 PS_PRIO(0) |
1679 VS_PRIO(1) |
1680 GS_PRIO(2) |
1681 ES_PRIO(3));
1682
1683 if ((rdev->family) == CHIP_R600) {
1684 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1685 NUM_VS_GPRS(124) |
1686 NUM_CLAUSE_TEMP_GPRS(4));
1687 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1688 NUM_ES_GPRS(0));
1689 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1690 NUM_VS_THREADS(48) |
1691 NUM_GS_THREADS(4) |
1692 NUM_ES_THREADS(4));
1693 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1694 NUM_VS_STACK_ENTRIES(128));
1695 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1696 NUM_ES_STACK_ENTRIES(0));
1697 } else if (((rdev->family) == CHIP_RV610) ||
1698 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1699 ((rdev->family) == CHIP_RS780) ||
1700 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1701 /* no vertex cache */
1702 sq_config &= ~VC_ENABLE;
1703
1704 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1705 NUM_VS_GPRS(44) |
1706 NUM_CLAUSE_TEMP_GPRS(2));
1707 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1708 NUM_ES_GPRS(17));
1709 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1710 NUM_VS_THREADS(78) |
1711 NUM_GS_THREADS(4) |
1712 NUM_ES_THREADS(31));
1713 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1714 NUM_VS_STACK_ENTRIES(40));
1715 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1716 NUM_ES_STACK_ENTRIES(16));
1717 } else if (((rdev->family) == CHIP_RV630) ||
1718 ((rdev->family) == CHIP_RV635)) {
1719 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1720 NUM_VS_GPRS(44) |
1721 NUM_CLAUSE_TEMP_GPRS(2));
1722 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1723 NUM_ES_GPRS(18));
1724 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1725 NUM_VS_THREADS(78) |
1726 NUM_GS_THREADS(4) |
1727 NUM_ES_THREADS(31));
1728 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1729 NUM_VS_STACK_ENTRIES(40));
1730 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1731 NUM_ES_STACK_ENTRIES(16));
1732 } else if ((rdev->family) == CHIP_RV670) {
1733 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1734 NUM_VS_GPRS(44) |
1735 NUM_CLAUSE_TEMP_GPRS(2));
1736 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1737 NUM_ES_GPRS(17));
1738 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1739 NUM_VS_THREADS(78) |
1740 NUM_GS_THREADS(4) |
1741 NUM_ES_THREADS(31));
1742 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1743 NUM_VS_STACK_ENTRIES(64));
1744 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1745 NUM_ES_STACK_ENTRIES(64));
1746 }
1747
1748 WREG32(SQ_CONFIG, sq_config);
1749 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1750 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1751 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1752 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1753 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1754
1755 if (((rdev->family) == CHIP_RV610) ||
1756 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1757 ((rdev->family) == CHIP_RS780) ||
1758 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1759 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1760 } else {
1761 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1762 }
1763
1764 /* More default values. 2D/3D driver should adjust as needed */
1765 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1766 S1_X(0x4) | S1_Y(0xc)));
1767 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1768 S1_X(0x2) | S1_Y(0x2) |
1769 S2_X(0xa) | S2_Y(0x6) |
1770 S3_X(0x6) | S3_Y(0xa)));
1771 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1772 S1_X(0x4) | S1_Y(0xc) |
1773 S2_X(0x1) | S2_Y(0x6) |
1774 S3_X(0xa) | S3_Y(0xe)));
1775 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1776 S5_X(0x0) | S5_Y(0x0) |
1777 S6_X(0xb) | S6_Y(0x4) |
1778 S7_X(0x7) | S7_Y(0x8)));
1779
1780 WREG32(VGT_STRMOUT_EN, 0);
1781 tmp = rdev->config.r600.max_pipes * 16;
1782 switch (rdev->family) {
1783 case CHIP_RV610:
3ce0a23d 1784 case CHIP_RV620:
ee59f2b4
AD		 1785 case CHIP_RS780:
1786 case CHIP_RS880:
3ce0a23d
JG		 1787 tmp += 32;
1788 break;
1789 case CHIP_RV670:
1790 tmp += 128;
1791 break;
1792 default:
1793 break;
1794 }
1795 if (tmp > 256) {
1796 tmp = 256;
1797 }
1798 WREG32(VGT_ES_PER_GS, 128);
1799 WREG32(VGT_GS_PER_ES, tmp);
1800 WREG32(VGT_GS_PER_VS, 2);
1801 WREG32(VGT_GS_VERTEX_REUSE, 16);
1802
1803 /* more default values. 2D/3D driver should adjust as needed */
1804 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1805 WREG32(VGT_STRMOUT_EN, 0);
1806 WREG32(SX_MISC, 0);
1807 WREG32(PA_SC_MODE_CNTL, 0);
1808 WREG32(PA_SC_AA_CONFIG, 0);
1809 WREG32(PA_SC_LINE_STIPPLE, 0);
1810 WREG32(SPI_INPUT_Z, 0);
1811 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1812 WREG32(CB_COLOR7_FRAG, 0);
1813
1814 /* Clear render buffer base addresses */
1815 WREG32(CB_COLOR0_BASE, 0);
1816 WREG32(CB_COLOR1_BASE, 0);
1817 WREG32(CB_COLOR2_BASE, 0);
1818 WREG32(CB_COLOR3_BASE, 0);
1819 WREG32(CB_COLOR4_BASE, 0);
1820 WREG32(CB_COLOR5_BASE, 0);
1821 WREG32(CB_COLOR6_BASE, 0);
1822 WREG32(CB_COLOR7_BASE, 0);
1823 WREG32(CB_COLOR7_FRAG, 0);
1824
1825 switch (rdev->family) {
1826 case CHIP_RV610:
3ce0a23d 1827 case CHIP_RV620:
ee59f2b4
AD		 1828 case CHIP_RS780:
1829 case CHIP_RS880:
3ce0a23d
JG		 1830 tmp = TC_L2_SIZE(8);
1831 break;
1832 case CHIP_RV630:
1833 case CHIP_RV635:
1834 tmp = TC_L2_SIZE(4);
1835 break;
1836 case CHIP_R600:
1837 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1838 break;
1839 default:
1840 tmp = TC_L2_SIZE(0);
1841 break;
1842 }
1843 WREG32(TC_CNTL, tmp);
1844
1845 tmp = RREG32(HDP_HOST_PATH_CNTL);
1846 WREG32(HDP_HOST_PATH_CNTL, tmp);
1847
1848 tmp = RREG32(ARB_POP);
1849 tmp |= ENABLE_TC128;
1850 WREG32(ARB_POP, tmp);
1851
1852 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1853 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1854 NUM_CLIP_SEQ(3)));
1855 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1856}
1857
1858
771fe6b9
JG		 1859/*
1860 * Indirect registers accessor
1861 */
3ce0a23d
JG		 1862u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1863{
1864 u32 r;
1865
1866 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1867 (void)RREG32(PCIE_PORT_INDEX);
1868 r = RREG32(PCIE_PORT_DATA);
1869 return r;
1870}
1871
1872void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1873{
1874 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1875 (void)RREG32(PCIE_PORT_INDEX);
1876 WREG32(PCIE_PORT_DATA, (v));
1877 (void)RREG32(PCIE_PORT_DATA);
1878}
1879
3ce0a23d
JG		 1880/*
1881 * CP & Ring
1882 */
1883void r600_cp_stop(struct radeon_device *rdev)
1884{
1885 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1886}
1887
d8f60cfc 1888int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1889{
1890 struct platform_device *pdev;
1891 const char *chip_name;
d8f60cfc
AD		 1892 const char *rlc_chip_name;
1893 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1894 char fw_name[30];
1895 int err;
1896
1897 DRM_DEBUG("\n");
1898
1899 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1900 err = IS_ERR(pdev);
1901 if (err) {
1902 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1903 return -EINVAL;
1904 }
1905
1906 switch (rdev->family) {
d8f60cfc
AD		 1907 case CHIP_R600:
1908 chip_name = "R600";
1909 rlc_chip_name = "R600";
1910 break;
1911 case CHIP_RV610:
1912 chip_name = "RV610";
1913 rlc_chip_name = "R600";
1914 break;
1915 case CHIP_RV630:
1916 chip_name = "RV630";
1917 rlc_chip_name = "R600";
1918 break;
1919 case CHIP_RV620:
1920 chip_name = "RV620";
1921 rlc_chip_name = "R600";
1922 break;
1923 case CHIP_RV635:
1924 chip_name = "RV635";
1925 rlc_chip_name = "R600";
1926 break;
1927 case CHIP_RV670:
1928 chip_name = "RV670";
1929 rlc_chip_name = "R600";
1930 break;
3ce0a23d 1931 case CHIP_RS780:
d8f60cfc
AD		 1932 case CHIP_RS880:
1933 chip_name = "RS780";
1934 rlc_chip_name = "R600";
1935 break;
1936 case CHIP_RV770:
1937 chip_name = "RV770";
1938 rlc_chip_name = "R700";
1939 break;
3ce0a23d 1940 case CHIP_RV730:
d8f60cfc
AD		 1941 case CHIP_RV740:
1942 chip_name = "RV730";
1943 rlc_chip_name = "R700";
1944 break;
1945 case CHIP_RV710:
1946 chip_name = "RV710";
1947 rlc_chip_name = "R700";
1948 break;
fe251e2f
AD		 1949 case CHIP_CEDAR:
1950 chip_name = "CEDAR";
45f9a39b 1951 rlc_chip_name = "CEDAR";
fe251e2f
AD		 1952 break;
1953 case CHIP_REDWOOD:
1954 chip_name = "REDWOOD";
45f9a39b 1955 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 1956 break;
1957 case CHIP_JUNIPER:
1958 chip_name = "JUNIPER";
45f9a39b 1959 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 1960 break;
1961 case CHIP_CYPRESS:
1962 case CHIP_HEMLOCK:
1963 chip_name = "CYPRESS";
45f9a39b 1964 rlc_chip_name = "CYPRESS";
fe251e2f 1965 break;
3ce0a23d
JG		 1966 default: BUG();
1967 }
1968
fe251e2f
AD		 1969 if (rdev->family >= CHIP_CEDAR) {
1970 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1971 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 1972 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 1973 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 1974 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1975 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 1976 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1977 } else {
1978 pfp_req_size = PFP_UCODE_SIZE * 4;
1979 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 1980 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 1981 }
1982
d8f60cfc 1983 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 1984
1985 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1986 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1987 if (err)
1988 goto out;
1989 if (rdev->pfp_fw->size != pfp_req_size) {
1990 printk(KERN_ERR
1991 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1992 rdev->pfp_fw->size, fw_name);
1993 err = -EINVAL;
1994 goto out;
1995 }
1996
1997 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1998 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1999 if (err)
2000 goto out;
2001 if (rdev->me_fw->size != me_req_size) {
2002 printk(KERN_ERR
2003 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2004 rdev->me_fw->size, fw_name);
2005 err = -EINVAL;
2006 }
d8f60cfc
AD		 2007
2008 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2009 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2010 if (err)
2011 goto out;
2012 if (rdev->rlc_fw->size != rlc_req_size) {
2013 printk(KERN_ERR
2014 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2015 rdev->rlc_fw->size, fw_name);
2016 err = -EINVAL;
2017 }
2018
3ce0a23d
JG		 2019out:
2020 platform_device_unregister(pdev);
2021
2022 if (err) {
2023 if (err != -EINVAL)
2024 printk(KERN_ERR
2025 "r600_cp: Failed to load firmware \"%s\"\n",
2026 fw_name);
2027 release_firmware(rdev->pfp_fw);
2028 rdev->pfp_fw = NULL;
2029 release_firmware(rdev->me_fw);
2030 rdev->me_fw = NULL;
d8f60cfc
AD		 2031 release_firmware(rdev->rlc_fw);
2032 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2033 }
2034 return err;
2035}
2036
2037static int r600_cp_load_microcode(struct radeon_device *rdev)
2038{
2039 const __be32 *fw_data;
2040 int i;
2041
2042 if (!rdev->me_fw || !rdev->pfp_fw)
2043 return -EINVAL;
2044
2045 r600_cp_stop(rdev);
2046
2047 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2048
2049 /* Reset cp */
2050 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2051 RREG32(GRBM_SOFT_RESET);
2052 mdelay(15);
2053 WREG32(GRBM_SOFT_RESET, 0);
2054
2055 WREG32(CP_ME_RAM_WADDR, 0);
2056
2057 fw_data = (const __be32 *)rdev->me_fw->data;
2058 WREG32(CP_ME_RAM_WADDR, 0);
2059 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2060 WREG32(CP_ME_RAM_DATA,
2061 be32_to_cpup(fw_data++));
2062
2063 fw_data = (const __be32 *)rdev->pfp_fw->data;
2064 WREG32(CP_PFP_UCODE_ADDR, 0);
2065 for (i = 0; i < PFP_UCODE_SIZE; i++)
2066 WREG32(CP_PFP_UCODE_DATA,
2067 be32_to_cpup(fw_data++));
2068
2069 WREG32(CP_PFP_UCODE_ADDR, 0);
2070 WREG32(CP_ME_RAM_WADDR, 0);
2071 WREG32(CP_ME_RAM_RADDR, 0);
2072 return 0;
2073}
2074
2075int r600_cp_start(struct radeon_device *rdev)
2076{
2077 int r;
2078 uint32_t cp_me;
2079
2080 r = radeon_ring_lock(rdev, 7);
2081 if (r) {
2082 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2083 return r;
2084 }
2085 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2086 radeon_ring_write(rdev, 0x1);
fe251e2f
AD		 2087 if (rdev->family >= CHIP_CEDAR) {
2088 radeon_ring_write(rdev, 0x0);
2089 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
2090 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2091 radeon_ring_write(rdev, 0x0);
2092 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 2093 } else {
2094 radeon_ring_write(rdev, 0x3);
2095 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 2096 }
2097 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2098 radeon_ring_write(rdev, 0);
2099 radeon_ring_write(rdev, 0);
2100 radeon_ring_unlock_commit(rdev);
2101
2102 cp_me = 0xff;
2103 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2104 return 0;
2105}
2106
2107int r600_cp_resume(struct radeon_device *rdev)
2108{
2109 u32 tmp;
2110 u32 rb_bufsz;
2111 int r;
2112
2113 /* Reset cp */
2114 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2115 RREG32(GRBM_SOFT_RESET);
2116 mdelay(15);
2117 WREG32(GRBM_SOFT_RESET, 0);
2118
2119 /* Set ring buffer size */
2120 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
d6f28938 2121 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2122#ifdef __BIG_ENDIAN
d6f28938 2123 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2124#endif
d6f28938 2125 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 2126 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2127
2128 /* Set the write pointer delay */
2129 WREG32(CP_RB_WPTR_DELAY, 0);
2130
2131 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2132 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2133 WREG32(CP_RB_RPTR_WR, 0);
2134 WREG32(CP_RB_WPTR, 0);
2135 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
2136 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
2137 mdelay(1);
2138 WREG32(CP_RB_CNTL, tmp);
2139
2140 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2141 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2142
2143 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2144 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2145
2146 r600_cp_start(rdev);
2147 rdev->cp.ready = true;
2148 r = radeon_ring_test(rdev);
2149 if (r) {
2150 rdev->cp.ready = false;
2151 return r;
2152 }
2153 return 0;
2154}
2155
2156void r600_cp_commit(struct radeon_device *rdev)
2157{
2158 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2159 (void)RREG32(CP_RB_WPTR);
2160}
2161
2162void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2163{
2164 u32 rb_bufsz;
2165
2166 /* Align ring size */
2167 rb_bufsz = drm_order(ring_size / 8);
2168 ring_size = (1 << (rb_bufsz + 1)) * 4;
2169 rdev->cp.ring_size = ring_size;
2170 rdev->cp.align_mask = 16 - 1;
2171}
2172
655efd3d
JG		 2173void r600_cp_fini(struct radeon_device *rdev)
2174{
2175 r600_cp_stop(rdev);
2176 radeon_ring_fini(rdev);
2177}
2178
3ce0a23d
JG		 2179
2180/*
2181 * GPU scratch registers helpers function.
2182 */
2183void r600_scratch_init(struct radeon_device *rdev)
2184{
2185 int i;
2186
2187 rdev->scratch.num_reg = 7;
2188 for (i = 0; i < rdev->scratch.num_reg; i++) {
2189 rdev->scratch.free[i] = true;
2190 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
2191 }
2192}
2193
2194int r600_ring_test(struct radeon_device *rdev)
2195{
2196 uint32_t scratch;
2197 uint32_t tmp = 0;
2198 unsigned i;
2199 int r;
2200
2201 r = radeon_scratch_get(rdev, &scratch);
2202 if (r) {
2203 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2204 return r;
2205 }
2206 WREG32(scratch, 0xCAFEDEAD);
2207 r = radeon_ring_lock(rdev, 3);
2208 if (r) {
2209 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2210 radeon_scratch_free(rdev, scratch);
2211 return r;
2212 }
2213 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2214 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2215 radeon_ring_write(rdev, 0xDEADBEEF);
2216 radeon_ring_unlock_commit(rdev);
2217 for (i = 0; i < rdev->usec_timeout; i++) {
2218 tmp = RREG32(scratch);
2219 if (tmp == 0xDEADBEEF)
2220 break;
2221 DRM_UDELAY(1);
2222 }
2223 if (i < rdev->usec_timeout) {
2224 DRM_INFO("ring test succeeded in %d usecs\n", i);
2225 } else {
2226 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2227 scratch, tmp);
2228 r = -EINVAL;
2229 }
2230 radeon_scratch_free(rdev, scratch);
2231 return r;
2232}
2233
81cc35bf
JG		 2234void r600_wb_disable(struct radeon_device *rdev)
2235{
4c788679
JG		 2236 int r;
2237
81cc35bf
JG		 2238 WREG32(SCRATCH_UMSK, 0);
2239 if (rdev->wb.wb_obj) {
4c788679
JG		 2240 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2241 if (unlikely(r != 0))
2242 return;
2243 radeon_bo_kunmap(rdev->wb.wb_obj);
2244 radeon_bo_unpin(rdev->wb.wb_obj);
2245 radeon_bo_unreserve(rdev->wb.wb_obj);
81cc35bf
JG		 2246 }
2247}
2248
2249void r600_wb_fini(struct radeon_device *rdev)
2250{
2251 r600_wb_disable(rdev);
2252 if (rdev->wb.wb_obj) {
4c788679 2253 radeon_bo_unref(&rdev->wb.wb_obj);
81cc35bf
JG		 2254 rdev->wb.wb = NULL;
2255 rdev->wb.wb_obj = NULL;
2256 }
2257}
2258
2259int r600_wb_enable(struct radeon_device *rdev)
3ce0a23d
JG		 2260{
2261 int r;
2262
2263 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 2264 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2265 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
3ce0a23d 2266 if (r) {
4c788679 2267 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
3ce0a23d
JG		 2268 return r;
2269 }
4c788679
JG		 2270 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2271 if (unlikely(r != 0)) {
2272 r600_wb_fini(rdev);
3ce0a23d
JG		 2273 return r;
2274 }
4c788679 2275 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
81cc35bf 2276 &rdev->wb.gpu_addr);
3ce0a23d 2277 if (r) {
4c788679
JG		 2278 radeon_bo_unreserve(rdev->wb.wb_obj);
2279 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
81cc35bf 2280 r600_wb_fini(rdev);
3ce0a23d
JG		 2281 return r;
2282 }
4c788679
JG		 2283 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2284 radeon_bo_unreserve(rdev->wb.wb_obj);
3ce0a23d 2285 if (r) {
4c788679 2286 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
81cc35bf 2287 r600_wb_fini(rdev);
3ce0a23d
JG		 2288 return r;
2289 }
2290 }
2291 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2292 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2293 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2294 WREG32(SCRATCH_UMSK, 0xff);
2295 return 0;
2296}
2297
3ce0a23d
JG		 2298void r600_fence_ring_emit(struct radeon_device *rdev,
2299 struct radeon_fence *fence)
2300{
d8f60cfc 2301 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
44224c3f
AD		 2302
2303 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2304 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2305 /* wait for 3D idle clean */
2306 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2307 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2308 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
3ce0a23d
JG		 2309 /* Emit fence sequence & fire IRQ */
2310 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2311 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2312 radeon_ring_write(rdev, fence->seq);
d8f60cfc
AD		 2313 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2314 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2315 radeon_ring_write(rdev, RB_INT_STAT);
3ce0a23d
JG		 2316}
2317
3ce0a23d
JG		 2318int r600_copy_blit(struct radeon_device *rdev,
2319 uint64_t src_offset, uint64_t dst_offset,
2320 unsigned num_pages, struct radeon_fence *fence)
2321{
ff82f052
JG		 2322 int r;
2323
2324 mutex_lock(&rdev->r600_blit.mutex);
2325 rdev->r600_blit.vb_ib = NULL;
2326 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2327 if (r) {
2328 if (rdev->r600_blit.vb_ib)
2329 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2330 mutex_unlock(&rdev->r600_blit.mutex);
2331 return r;
2332 }
a77f1718 2333 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 2334 r600_blit_done_copy(rdev, fence);
ff82f052 2335 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2336 return 0;
2337}
2338
3ce0a23d
JG		 2339int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2340 uint32_t tiling_flags, uint32_t pitch,
2341 uint32_t offset, uint32_t obj_size)
2342{
2343 /* FIXME: implement */
2344 return 0;
2345}
2346
2347void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2348{
2349 /* FIXME: implement */
2350}
2351
2352
2353bool r600_card_posted(struct radeon_device *rdev)
2354{
2355 uint32_t reg;
2356
2357 /* first check CRTCs */
2358 reg = RREG32(D1CRTC_CONTROL) |
2359 RREG32(D2CRTC_CONTROL);
2360 if (reg & CRTC_EN)
2361 return true;
2362
2363 /* then check MEM_SIZE, in case the crtcs are off */
2364 if (RREG32(CONFIG_MEMSIZE))
2365 return true;
2366
2367 return false;
2368}
2369
fc30b8ef 2370int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 2371{
2372 int r;
2373
779720a3
AD		 2374 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2375 r = r600_init_microcode(rdev);
2376 if (r) {
2377 DRM_ERROR("Failed to load firmware!\n");
2378 return r;
2379 }
2380 }
2381
a3c1945a 2382 r600_mc_program(rdev);
1a029b76
JG		 2383 if (rdev->flags & RADEON_IS_AGP) {
2384 r600_agp_enable(rdev);
2385 } else {
2386 r = r600_pcie_gart_enable(rdev);
2387 if (r)
2388 return r;
2389 }
3ce0a23d 2390 r600_gpu_init(rdev);
c38c7b64
JG		 2391 r = r600_blit_init(rdev);
2392 if (r) {
2393 r600_blit_fini(rdev);
2394 rdev->asic->copy = NULL;
2395 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2396 }
ff82f052
JG		 2397 /* pin copy shader into vram */
2398 if (rdev->r600_blit.shader_obj) {
2399 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2400 if (unlikely(r != 0))
2401 return r;
2402 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2403 &rdev->r600_blit.shader_gpu_addr);
2404 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
7923c615 2405 if (r) {
ff82f052 2406 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
7923c615
AD		 2407 return r;
2408 }
2409 }
d8f60cfc 2410 /* Enable IRQ */
d8f60cfc
AD		 2411 r = r600_irq_init(rdev);
2412 if (r) {
2413 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2414 radeon_irq_kms_fini(rdev);
2415 return r;
2416 }
2417 r600_irq_set(rdev);
2418
3ce0a23d
JG		 2419 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2420 if (r)
2421 return r;
2422 r = r600_cp_load_microcode(rdev);
2423 if (r)
2424 return r;
2425 r = r600_cp_resume(rdev);
2426 if (r)
2427 return r;
81cc35bf
JG		 2428 /* write back buffer are not vital so don't worry about failure */
2429 r600_wb_enable(rdev);
3ce0a23d
JG		 2430 return 0;
2431}
2432
28d52043
DA		 2433void r600_vga_set_state(struct radeon_device *rdev, bool state)
2434{
2435 uint32_t temp;
2436
2437 temp = RREG32(CONFIG_CNTL);
2438 if (state == false) {
2439 temp &= ~(1<<0);
2440 temp |= (1<<1);
2441 } else {
2442 temp &= ~(1<<1);
2443 }
2444 WREG32(CONFIG_CNTL, temp);
2445}
2446
fc30b8ef
DA		 2447int r600_resume(struct radeon_device *rdev)
2448{
2449 int r;
2450
1a029b76
JG		 2451 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2452 * posting will perform necessary task to bring back GPU into good
2453 * shape.
2454 */
fc30b8ef 2455 /* post card */
e7d40b9a 2456 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2457 /* Initialize clocks */
2458 r = radeon_clocks_init(rdev);
2459 if (r) {
2460 return r;
2461 }
2462
2463 r = r600_startup(rdev);
2464 if (r) {
2465 DRM_ERROR("r600 startup failed on resume\n");
2466 return r;
2467 }
2468
62a8ea3f 2469 r = r600_ib_test(rdev);
fc30b8ef
DA		 2470 if (r) {
2471 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2472 return r;
2473 }
38fd2c6f
RM		 2474
2475 r = r600_audio_init(rdev);
2476 if (r) {
2477 DRM_ERROR("radeon: audio resume failed\n");
2478 return r;
2479 }
2480
fc30b8ef
DA		 2481 return r;
2482}
2483
3ce0a23d
JG		 2484int r600_suspend(struct radeon_device *rdev)
2485{
4c788679
JG		 2486 int r;
2487
38fd2c6f 2488 r600_audio_fini(rdev);
3ce0a23d
JG		 2489 /* FIXME: we should wait for ring to be empty */
2490 r600_cp_stop(rdev);
bc1a631e 2491 rdev->cp.ready = false;
0c45249f 2492 r600_irq_suspend(rdev);
81cc35bf 2493 r600_wb_disable(rdev);
4aac0473 2494 r600_pcie_gart_disable(rdev);
bc1a631e 2495 /* unpin shaders bo */
30d2d9a5
JG		 2496 if (rdev->r600_blit.shader_obj) {
2497 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2498 if (!r) {
2499 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2500 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2501 }
2502 }
3ce0a23d
JG		 2503 return 0;
2504}
2505
2506/* Plan is to move initialization in that function and use
2507 * helper function so that radeon_device_init pretty much
2508 * do nothing more than calling asic specific function. This
2509 * should also allow to remove a bunch of callback function
2510 * like vram_info.
2511 */
2512int r600_init(struct radeon_device *rdev)
771fe6b9 2513{
3ce0a23d 2514 int r;
771fe6b9 2515
3ce0a23d
JG		 2516 r = radeon_dummy_page_init(rdev);
2517 if (r)
2518 return r;
2519 if (r600_debugfs_mc_info_init(rdev)) {
2520 DRM_ERROR("Failed to register debugfs file for mc !\n");
2521 }
2522 /* This don't do much */
2523 r = radeon_gem_init(rdev);
2524 if (r)
2525 return r;
2526 /* Read BIOS */
2527 if (!radeon_get_bios(rdev)) {
2528 if (ASIC_IS_AVIVO(rdev))
2529 return -EINVAL;
2530 }
2531 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2532 if (!rdev->is_atom_bios) {
2533 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2534 return -EINVAL;
e7d40b9a 2535 }
3ce0a23d
JG		 2536 r = radeon_atombios_init(rdev);
2537 if (r)
2538 return r;
2539 /* Post card if necessary */
72542d77
DA		 2540 if (!r600_card_posted(rdev)) {
2541 if (!rdev->bios) {
2542 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2543 return -EINVAL;
2544 }
3ce0a23d
JG		 2545 DRM_INFO("GPU not posted. posting now...\n");
2546 atom_asic_init(rdev->mode_info.atom_context);
2547 }
2548 /* Initialize scratch registers */
2549 r600_scratch_init(rdev);
2550 /* Initialize surface registers */
2551 radeon_surface_init(rdev);
7433874e 2552 /* Initialize clocks */
5e6dde7e 2553 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2554 r = radeon_clocks_init(rdev);
2555 if (r)
2556 return r;
2557 /* Fence driver */
2558 r = radeon_fence_driver_init(rdev);
2559 if (r)
2560 return r;
700a0cc0
JG		 2561 if (rdev->flags & RADEON_IS_AGP) {
2562 r = radeon_agp_init(rdev);
2563 if (r)
2564 radeon_agp_disable(rdev);
2565 }
3ce0a23d 2566 r = r600_mc_init(rdev);
b574f251 2567 if (r)
3ce0a23d 2568 return r;
3ce0a23d 2569 /* Memory manager */
4c788679 2570 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2571 if (r)
2572 return r;
d8f60cfc
AD		 2573
2574 r = radeon_irq_kms_init(rdev);
2575 if (r)
2576 return r;
2577
3ce0a23d
JG		 2578 rdev->cp.ring_obj = NULL;
2579 r600_ring_init(rdev, 1024 * 1024);
2580
d8f60cfc
AD		 2581 rdev->ih.ring_obj = NULL;
2582 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2583
4aac0473
JG		 2584 r = r600_pcie_gart_init(rdev);
2585 if (r)
2586 return r;
2587
779720a3 2588 rdev->accel_working = true;
fc30b8ef 2589 r = r600_startup(rdev);
3ce0a23d 2590 if (r) {
655efd3d
JG		 2591 dev_err(rdev->dev, "disabling GPU acceleration\n");
2592 r600_cp_fini(rdev);
75c81298 2593 r600_wb_fini(rdev);
655efd3d
JG		 2594 r600_irq_fini(rdev);
2595 radeon_irq_kms_fini(rdev);
75c81298 2596 r600_pcie_gart_fini(rdev);
733289c2 2597 rdev->accel_working = false;
3ce0a23d 2598 }
733289c2
JG		 2599 if (rdev->accel_working) {
2600 r = radeon_ib_pool_init(rdev);
2601 if (r) {
db96380e 2602 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2603 rdev->accel_working = false;
db96380e
JG		 2604 } else {
2605 r = r600_ib_test(rdev);
2606 if (r) {
2607 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2608 rdev->accel_working = false;
2609 }
733289c2 2610 }
3ce0a23d 2611 }
dafc3bd5
CK		 2612
2613 r = r600_audio_init(rdev);
2614 if (r)
2615 return r; /* TODO error handling */
3ce0a23d
JG		 2616 return 0;
2617}
2618
2619void r600_fini(struct radeon_device *rdev)
2620{
dafc3bd5 2621 r600_audio_fini(rdev);
3ce0a23d 2622 r600_blit_fini(rdev);
655efd3d
JG		 2623 r600_cp_fini(rdev);
2624 r600_wb_fini(rdev);
d8f60cfc
AD		 2625 r600_irq_fini(rdev);
2626 radeon_irq_kms_fini(rdev);
4aac0473 2627 r600_pcie_gart_fini(rdev);
655efd3d 2628 radeon_agp_fini(rdev);
3ce0a23d
JG		 2629 radeon_gem_fini(rdev);
2630 radeon_fence_driver_fini(rdev);
2631 radeon_clocks_fini(rdev);
4c788679 2632 radeon_bo_fini(rdev);
e7d40b9a 2633 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2634 kfree(rdev->bios);
2635 rdev->bios = NULL;
2636 radeon_dummy_page_fini(rdev);
2637}
2638
2639
2640/*
2641 * CS stuff
2642 */
2643void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2644{
2645 /* FIXME: implement */
2646 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2647 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2648 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2649 radeon_ring_write(rdev, ib->length_dw);
2650}
2651
2652int r600_ib_test(struct radeon_device *rdev)
2653{
2654 struct radeon_ib *ib;
2655 uint32_t scratch;
2656 uint32_t tmp = 0;
2657 unsigned i;
2658 int r;
2659
2660 r = radeon_scratch_get(rdev, &scratch);
2661 if (r) {
2662 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2663 return r;
2664 }
2665 WREG32(scratch, 0xCAFEDEAD);
2666 r = radeon_ib_get(rdev, &ib);
2667 if (r) {
2668 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2669 return r;
2670 }
2671 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2672 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2673 ib->ptr[2] = 0xDEADBEEF;
2674 ib->ptr[3] = PACKET2(0);
2675 ib->ptr[4] = PACKET2(0);
2676 ib->ptr[5] = PACKET2(0);
2677 ib->ptr[6] = PACKET2(0);
2678 ib->ptr[7] = PACKET2(0);
2679 ib->ptr[8] = PACKET2(0);
2680 ib->ptr[9] = PACKET2(0);
2681 ib->ptr[10] = PACKET2(0);
2682 ib->ptr[11] = PACKET2(0);
2683 ib->ptr[12] = PACKET2(0);
2684 ib->ptr[13] = PACKET2(0);
2685 ib->ptr[14] = PACKET2(0);
2686 ib->ptr[15] = PACKET2(0);
2687 ib->length_dw = 16;
2688 r = radeon_ib_schedule(rdev, ib);
2689 if (r) {
2690 radeon_scratch_free(rdev, scratch);
2691 radeon_ib_free(rdev, &ib);
2692 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2693 return r;
2694 }
2695 r = radeon_fence_wait(ib->fence, false);
2696 if (r) {
2697 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2698 return r;
2699 }
2700 for (i = 0; i < rdev->usec_timeout; i++) {
2701 tmp = RREG32(scratch);
2702 if (tmp == 0xDEADBEEF)
2703 break;
2704 DRM_UDELAY(1);
2705 }
2706 if (i < rdev->usec_timeout) {
2707 DRM_INFO("ib test succeeded in %u usecs\n", i);
2708 } else {
2709 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2710 scratch, tmp);
2711 r = -EINVAL;
2712 }
2713 radeon_scratch_free(rdev, scratch);
2714 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2715 return r;
2716}
2717
d8f60cfc
AD		 2718/*
2719 * Interrupts
2720 *
2721 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2722 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2723 * writing to the ring and the GPU consuming, the GPU writes to the ring
2724 * and host consumes. As the host irq handler processes interrupts, it
2725 * increments the rptr. When the rptr catches up with the wptr, all the
2726 * current interrupts have been processed.
2727 */
2728
2729void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2730{
2731 u32 rb_bufsz;
2732
2733 /* Align ring size */
2734 rb_bufsz = drm_order(ring_size / 4);
2735 ring_size = (1 << rb_bufsz) * 4;
2736 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2737 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2738 rdev->ih.rptr = 0;
d8f60cfc
AD		 2739}
2740
0c45249f 2741static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2742{
2743 int r;
2744
d8f60cfc
AD		 2745 /* Allocate ring buffer */
2746 if (rdev->ih.ring_obj == NULL) {
4c788679
JG		 2747 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2748 true,
2749 RADEON_GEM_DOMAIN_GTT,
2750 &rdev->ih.ring_obj);
d8f60cfc
AD		 2751 if (r) {
2752 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2753 return r;
2754 }
4c788679
JG		 2755 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2756 if (unlikely(r != 0))
2757 return r;
2758 r = radeon_bo_pin(rdev->ih.ring_obj,
2759 RADEON_GEM_DOMAIN_GTT,
2760 &rdev->ih.gpu_addr);
d8f60cfc 2761 if (r) {
4c788679 2762 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2763 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2764 return r;
2765 }
4c788679
JG		 2766 r = radeon_bo_kmap(rdev->ih.ring_obj,
2767 (void **)&rdev->ih.ring);
2768 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2769 if (r) {
2770 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2771 return r;
2772 }
2773 }
d8f60cfc
AD		 2774 return 0;
2775}
2776
2777static void r600_ih_ring_fini(struct radeon_device *rdev)
2778{
4c788679 2779 int r;
d8f60cfc 2780 if (rdev->ih.ring_obj) {
4c788679
JG		 2781 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2782 if (likely(r == 0)) {
2783 radeon_bo_kunmap(rdev->ih.ring_obj);
2784 radeon_bo_unpin(rdev->ih.ring_obj);
2785 radeon_bo_unreserve(rdev->ih.ring_obj);
2786 }
2787 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2788 rdev->ih.ring = NULL;
2789 rdev->ih.ring_obj = NULL;
2790 }
2791}
2792
45f9a39b 2793void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2794{
2795
45f9a39b
AD		 2796 if ((rdev->family >= CHIP_RV770) &&
2797 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2798 /* r7xx asics need to soft reset RLC before halting */
2799 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2800 RREG32(SRBM_SOFT_RESET);
2801 udelay(15000);
2802 WREG32(SRBM_SOFT_RESET, 0);
2803 RREG32(SRBM_SOFT_RESET);
2804 }
2805
2806 WREG32(RLC_CNTL, 0);
2807}
2808
2809static void r600_rlc_start(struct radeon_device *rdev)
2810{
2811 WREG32(RLC_CNTL, RLC_ENABLE);
2812}
2813
2814static int r600_rlc_init(struct radeon_device *rdev)
2815{
2816 u32 i;
2817 const __be32 *fw_data;
2818
2819 if (!rdev->rlc_fw)
2820 return -EINVAL;
2821
2822 r600_rlc_stop(rdev);
2823
2824 WREG32(RLC_HB_BASE, 0);
2825 WREG32(RLC_HB_CNTL, 0);
2826 WREG32(RLC_HB_RPTR, 0);
2827 WREG32(RLC_HB_WPTR, 0);
2828 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2829 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2830 WREG32(RLC_MC_CNTL, 0);
2831 WREG32(RLC_UCODE_CNTL, 0);
2832
2833 fw_data = (const __be32 *)rdev->rlc_fw->data;
45f9a39b
AD		 2834 if (rdev->family >= CHIP_CEDAR) {
2835 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2836 WREG32(RLC_UCODE_ADDR, i);
2837 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2838 }
2839 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2840 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2841 WREG32(RLC_UCODE_ADDR, i);
2842 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2843 }
2844 } else {
2845 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2846 WREG32(RLC_UCODE_ADDR, i);
2847 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2848 }
2849 }
2850 WREG32(RLC_UCODE_ADDR, 0);
2851
2852 r600_rlc_start(rdev);
2853
2854 return 0;
2855}
2856
2857static void r600_enable_interrupts(struct radeon_device *rdev)
2858{
2859 u32 ih_cntl = RREG32(IH_CNTL);
2860 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2861
2862 ih_cntl |= ENABLE_INTR;
2863 ih_rb_cntl |= IH_RB_ENABLE;
2864 WREG32(IH_CNTL, ih_cntl);
2865 WREG32(IH_RB_CNTL, ih_rb_cntl);
2866 rdev->ih.enabled = true;
2867}
2868
45f9a39b 2869void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2870{
2871 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2872 u32 ih_cntl = RREG32(IH_CNTL);
2873
2874 ih_rb_cntl &= ~IH_RB_ENABLE;
2875 ih_cntl &= ~ENABLE_INTR;
2876 WREG32(IH_RB_CNTL, ih_rb_cntl);
2877 WREG32(IH_CNTL, ih_cntl);
2878 /* set rptr, wptr to 0 */
2879 WREG32(IH_RB_RPTR, 0);
2880 WREG32(IH_RB_WPTR, 0);
2881 rdev->ih.enabled = false;
2882 rdev->ih.wptr = 0;
2883 rdev->ih.rptr = 0;
2884}
2885
e0df1ac5
AD		 2886static void r600_disable_interrupt_state(struct radeon_device *rdev)
2887{
2888 u32 tmp;
2889
2890 WREG32(CP_INT_CNTL, 0);
2891 WREG32(GRBM_INT_CNTL, 0);
2892 WREG32(DxMODE_INT_MASK, 0);
2893 if (ASIC_IS_DCE3(rdev)) {
2894 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2895 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2896 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2897 WREG32(DC_HPD1_INT_CONTROL, tmp);
2898 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2899 WREG32(DC_HPD2_INT_CONTROL, tmp);
2900 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2901 WREG32(DC_HPD3_INT_CONTROL, tmp);
2902 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2903 WREG32(DC_HPD4_INT_CONTROL, tmp);
2904 if (ASIC_IS_DCE32(rdev)) {
2905 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2906 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2907 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2908 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2909 }
2910 } else {
2911 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2912 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2913 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2914 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2915 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2916 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2917 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2918 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2919 }
2920}
2921
d8f60cfc
AD		 2922int r600_irq_init(struct radeon_device *rdev)
2923{
2924 int ret = 0;
2925 int rb_bufsz;
2926 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2927
2928 /* allocate ring */
0c45249f 2929 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2930 if (ret)
2931 return ret;
2932
2933 /* disable irqs */
2934 r600_disable_interrupts(rdev);
2935
2936 /* init rlc */
2937 ret = r600_rlc_init(rdev);
2938 if (ret) {
2939 r600_ih_ring_fini(rdev);
2940 return ret;
2941 }
2942
2943 /* setup interrupt control */
2944 /* set dummy read address to ring address */
2945 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2946 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2947 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2948 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2949 */
2950 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2951 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2952 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2953 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2954
2955 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2956 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2957
2958 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2959 IH_WPTR_OVERFLOW_CLEAR |
2960 (rb_bufsz << 1));
2961 /* WPTR writeback, not yet */
2962 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2963 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2964 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2965
2966 WREG32(IH_RB_CNTL, ih_rb_cntl);
2967
2968 /* set rptr, wptr to 0 */
2969 WREG32(IH_RB_RPTR, 0);
2970 WREG32(IH_RB_WPTR, 0);
2971
2972 /* Default settings for IH_CNTL (disabled at first) */
2973 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2974 /* RPTR_REARM only works if msi's are enabled */
2975 if (rdev->msi_enabled)
2976 ih_cntl |= RPTR_REARM;
2977
2978#ifdef __BIG_ENDIAN
2979 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2980#endif
2981 WREG32(IH_CNTL, ih_cntl);
2982
2983 /* force the active interrupt state to all disabled */
45f9a39b
AD		 2984 if (rdev->family >= CHIP_CEDAR)
2985 evergreen_disable_interrupt_state(rdev);
2986 else
2987 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 2988
2989 /* enable irqs */
2990 r600_enable_interrupts(rdev);
2991
2992 return ret;
2993}
2994
0c45249f 2995void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 2996{
45f9a39b 2997 r600_irq_disable(rdev);
d8f60cfc 2998 r600_rlc_stop(rdev);
0c45249f
JG		 2999}
3000
3001void r600_irq_fini(struct radeon_device *rdev)
3002{
3003 r600_irq_suspend(rdev);
d8f60cfc
AD		 3004 r600_ih_ring_fini(rdev);
3005}
3006
3007int r600_irq_set(struct radeon_device *rdev)
3008{
e0df1ac5
AD		 3009 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3010 u32 mode_int = 0;
3011 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3012 u32 grbm_int_cntl = 0;
f2594933 3013 u32 hdmi1, hdmi2;
d8f60cfc 3014
003e69f9
JG		 3015 if (!rdev->irq.installed) {
3016 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
3017 return -EINVAL;
3018 }
d8f60cfc 3019 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3020 if (!rdev->ih.enabled) {
3021 r600_disable_interrupts(rdev);
3022 /* force the active interrupt state to all disabled */
3023 r600_disable_interrupt_state(rdev);
d8f60cfc 3024 return 0;
79c2bbc5 3025 }
d8f60cfc 3026
f2594933 3027 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 3028 if (ASIC_IS_DCE3(rdev)) {
f2594933 3029 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3030 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3031 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3032 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3033 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3034 if (ASIC_IS_DCE32(rdev)) {
3035 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3036 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3037 }
3038 } else {
f2594933 3039 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3040 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3041 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3042 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3043 }
3044
d8f60cfc
AD		 3045 if (rdev->irq.sw_int) {
3046 DRM_DEBUG("r600_irq_set: sw int\n");
3047 cp_int_cntl |= RB_INT_ENABLE;
3048 }
3049 if (rdev->irq.crtc_vblank_int[0]) {
3050 DRM_DEBUG("r600_irq_set: vblank 0\n");
3051 mode_int |= D1MODE_VBLANK_INT_MASK;
3052 }
3053 if (rdev->irq.crtc_vblank_int[1]) {
3054 DRM_DEBUG("r600_irq_set: vblank 1\n");
3055 mode_int |= D2MODE_VBLANK_INT_MASK;
3056 }
e0df1ac5
AD		 3057 if (rdev->irq.hpd[0]) {
3058 DRM_DEBUG("r600_irq_set: hpd 1\n");
3059 hpd1 |= DC_HPDx_INT_EN;
3060 }
3061 if (rdev->irq.hpd[1]) {
3062 DRM_DEBUG("r600_irq_set: hpd 2\n");
3063 hpd2 |= DC_HPDx_INT_EN;
3064 }
3065 if (rdev->irq.hpd[2]) {
3066 DRM_DEBUG("r600_irq_set: hpd 3\n");
3067 hpd3 |= DC_HPDx_INT_EN;
3068 }
3069 if (rdev->irq.hpd[3]) {
3070 DRM_DEBUG("r600_irq_set: hpd 4\n");
3071 hpd4 |= DC_HPDx_INT_EN;
3072 }
3073 if (rdev->irq.hpd[4]) {
3074 DRM_DEBUG("r600_irq_set: hpd 5\n");
3075 hpd5 |= DC_HPDx_INT_EN;
3076 }
3077 if (rdev->irq.hpd[5]) {
3078 DRM_DEBUG("r600_irq_set: hpd 6\n");
3079 hpd6 |= DC_HPDx_INT_EN;
3080 }
f2594933
CK		 3081 if (rdev->irq.hdmi[0]) {
3082 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3083 hdmi1 |= R600_HDMI_INT_EN;
3084 }
3085 if (rdev->irq.hdmi[1]) {
3086 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3087 hdmi2 |= R600_HDMI_INT_EN;
3088 }
2031f77c
AD		 3089 if (rdev->irq.gui_idle) {
3090 DRM_DEBUG("gui idle\n");
3091 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3092 }
d8f60cfc
AD		 3093
3094 WREG32(CP_INT_CNTL, cp_int_cntl);
3095 WREG32(DxMODE_INT_MASK, mode_int);
2031f77c 3096 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 3097 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 3098 if (ASIC_IS_DCE3(rdev)) {
f2594933 3099 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3100 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3101 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3102 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3103 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3104 if (ASIC_IS_DCE32(rdev)) {
3105 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3106 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3107 }
3108 } else {
f2594933 3109 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3110 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3111 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3112 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3113 }
d8f60cfc
AD		 3114
3115 return 0;
3116}
3117
e0df1ac5
AD		 3118static inline void r600_irq_ack(struct radeon_device *rdev,
3119 u32 *disp_int,
3120 u32 *disp_int_cont,
3121 u32 *disp_int_cont2)
d8f60cfc 3122{
e0df1ac5
AD		 3123 u32 tmp;
3124
3125 if (ASIC_IS_DCE3(rdev)) {
3126 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3127 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3128 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3129 } else {
3130 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3131 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3132 *disp_int_cont2 = 0;
3133 }
d8f60cfc 3134
e0df1ac5 3135 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3136 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3137 if (*disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3138 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5 3139 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3140 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
e0df1ac5 3141 if (*disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3142 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
e0df1ac5
AD		 3143 if (*disp_int & DC_HPD1_INTERRUPT) {
3144 if (ASIC_IS_DCE3(rdev)) {
3145 tmp = RREG32(DC_HPD1_INT_CONTROL);
3146 tmp |= DC_HPDx_INT_ACK;
3147 WREG32(DC_HPD1_INT_CONTROL, tmp);
3148 } else {
3149 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3150 tmp |= DC_HPDx_INT_ACK;
3151 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3152 }
3153 }
3154 if (*disp_int & DC_HPD2_INTERRUPT) {
3155 if (ASIC_IS_DCE3(rdev)) {
3156 tmp = RREG32(DC_HPD2_INT_CONTROL);
3157 tmp |= DC_HPDx_INT_ACK;
3158 WREG32(DC_HPD2_INT_CONTROL, tmp);
3159 } else {
3160 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3161 tmp |= DC_HPDx_INT_ACK;
3162 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3163 }
3164 }
3165 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3166 if (ASIC_IS_DCE3(rdev)) {
3167 tmp = RREG32(DC_HPD3_INT_CONTROL);
3168 tmp |= DC_HPDx_INT_ACK;
3169 WREG32(DC_HPD3_INT_CONTROL, tmp);
3170 } else {
3171 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3172 tmp |= DC_HPDx_INT_ACK;
3173 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3174 }
3175 }
3176 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3177 tmp = RREG32(DC_HPD4_INT_CONTROL);
3178 tmp |= DC_HPDx_INT_ACK;
3179 WREG32(DC_HPD4_INT_CONTROL, tmp);
3180 }
3181 if (ASIC_IS_DCE32(rdev)) {
3182 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3183 tmp = RREG32(DC_HPD5_INT_CONTROL);
3184 tmp |= DC_HPDx_INT_ACK;
3185 WREG32(DC_HPD5_INT_CONTROL, tmp);
3186 }
3187 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3188 tmp = RREG32(DC_HPD5_INT_CONTROL);
3189 tmp |= DC_HPDx_INT_ACK;
3190 WREG32(DC_HPD6_INT_CONTROL, tmp);
3191 }
3192 }
f2594933
CK		 3193 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3194 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3195 }
3196 if (ASIC_IS_DCE3(rdev)) {
3197 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3198 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3199 }
3200 } else {
3201 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3202 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3203 }
3204 }
d8f60cfc
AD		 3205}
3206
3207void r600_irq_disable(struct radeon_device *rdev)
3208{
e0df1ac5 3209 u32 disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc
AD		 3210
3211 r600_disable_interrupts(rdev);
3212 /* Wait and acknowledge irq */
3213 mdelay(1);
e0df1ac5
AD		 3214 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3215 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3216}
3217
3218static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3219{
3220 u32 wptr, tmp;
3ce0a23d 3221
d8f60cfc
AD		 3222 /* XXX use writeback */
3223 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3224
d8f60cfc 3225 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3226 /* When a ring buffer overflow happen start parsing interrupt
3227 * from the last not overwritten vector (wptr + 16). Hopefully
3228 * this should allow us to catchup.
3229 */
3230 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3231 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3232 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3233 tmp = RREG32(IH_RB_CNTL);
3234 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3235 WREG32(IH_RB_CNTL, tmp);
3236 }
0c45249f 3237 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3238}
3ce0a23d 3239
d8f60cfc
AD		 3240/* r600 IV Ring
3241 * Each IV ring entry is 128 bits:
3242 * [7:0] - interrupt source id
3243 * [31:8] - reserved
3244 * [59:32] - interrupt source data
3245 * [127:60] - reserved
3246 *
3247 * The basic interrupt vector entries
3248 * are decoded as follows:
3249 * src_id src_data description
3250 * 1 0 D1 Vblank
3251 * 1 1 D1 Vline
3252 * 5 0 D2 Vblank
3253 * 5 1 D2 Vline
3254 * 19 0 FP Hot plug detection A
3255 * 19 1 FP Hot plug detection B
3256 * 19 2 DAC A auto-detection
3257 * 19 3 DAC B auto-detection
f2594933
CK		 3258 * 21 4 HDMI block A
3259 * 21 5 HDMI block B
d8f60cfc
AD		 3260 * 176 - CP_INT RB
3261 * 177 - CP_INT IB1
3262 * 178 - CP_INT IB2
3263 * 181 - EOP Interrupt
3264 * 233 - GUI Idle
3265 *
3266 * Note, these are based on r600 and may need to be
3267 * adjusted or added to on newer asics
3268 */
3269
3270int r600_irq_process(struct radeon_device *rdev)
3271{
3272 u32 wptr = r600_get_ih_wptr(rdev);
3273 u32 rptr = rdev->ih.rptr;
3274 u32 src_id, src_data;
e0df1ac5 3275 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
d8f60cfc 3276 unsigned long flags;
d4877cf2 3277 bool queue_hotplug = false;
d8f60cfc
AD		 3278
3279 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
79c2bbc5
JG		 3280 if (!rdev->ih.enabled)
3281 return IRQ_NONE;
d8f60cfc
AD		 3282
3283 spin_lock_irqsave(&rdev->ih.lock, flags);
3284
3285 if (rptr == wptr) {
3286 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3287 return IRQ_NONE;
3288 }
3289 if (rdev->shutdown) {
3290 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3291 return IRQ_NONE;
3292 }
3293
3294restart_ih:
3295 /* display interrupts */
e0df1ac5 3296 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
d8f60cfc
AD		 3297
3298 rdev->ih.wptr = wptr;
3299 while (rptr != wptr) {
3300 /* wptr/rptr are in bytes! */
3301 ring_index = rptr / 4;
3302 src_id = rdev->ih.ring[ring_index] & 0xff;
3303 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3304
3305 switch (src_id) {
3306 case 1: /* D1 vblank/vline */
3307 switch (src_data) {
3308 case 0: /* D1 vblank */
3309 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3310 drm_handle_vblank(rdev->ddev, 0);
839461d3 3311 rdev->pm.vblank_sync = true;
73a6d3fc 3312 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3313 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3314 DRM_DEBUG("IH: D1 vblank\n");
3315 }
3316 break;
3317 case 1: /* D1 vline */
3318 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3319 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3320 DRM_DEBUG("IH: D1 vline\n");
3321 }
3322 break;
3323 default:
b042589c 3324 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3325 break;
3326 }
3327 break;
3328 case 5: /* D2 vblank/vline */
3329 switch (src_data) {
3330 case 0: /* D2 vblank */
3331 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3332 drm_handle_vblank(rdev->ddev, 1);
839461d3 3333 rdev->pm.vblank_sync = true;
73a6d3fc 3334 wake_up(&rdev->irq.vblank_queue);
d8f60cfc
AD		 3335 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3336 DRM_DEBUG("IH: D2 vblank\n");
3337 }
3338 break;
3339 case 1: /* D1 vline */
3340 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3341 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3342 DRM_DEBUG("IH: D2 vline\n");
3343 }
3344 break;
3345 default:
b042589c 3346 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3347 break;
3348 }
3349 break;
e0df1ac5
AD		 3350 case 19: /* HPD/DAC hotplug */
3351 switch (src_data) {
3352 case 0:
3353 if (disp_int & DC_HPD1_INTERRUPT) {
3354 disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3355 queue_hotplug = true;
3356 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3357 }
3358 break;
3359 case 1:
3360 if (disp_int & DC_HPD2_INTERRUPT) {
3361 disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3362 queue_hotplug = true;
3363 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3364 }
3365 break;
3366 case 4:
3367 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3368 disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3369 queue_hotplug = true;
3370 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3371 }
3372 break;
3373 case 5:
3374 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3375 disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3376 queue_hotplug = true;
3377 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3378 }
3379 break;
3380 case 10:
3381 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
5898b1f3 3382 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3383 queue_hotplug = true;
3384 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3385 }
3386 break;
3387 case 12:
3388 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
5898b1f3 3389 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3390 queue_hotplug = true;
3391 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3392 }
3393 break;
3394 default:
b042589c 3395 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3396 break;
3397 }
3398 break;
f2594933
CK		 3399 case 21: /* HDMI */
3400 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3401 r600_audio_schedule_polling(rdev);
3402 break;
d8f60cfc
AD		 3403 case 176: /* CP_INT in ring buffer */
3404 case 177: /* CP_INT in IB1 */
3405 case 178: /* CP_INT in IB2 */
3406 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3407 radeon_fence_process(rdev);
3408 break;
3409 case 181: /* CP EOP event */
3410 DRM_DEBUG("IH: CP EOP\n");
3411 break;
2031f77c
AD		 3412 case 233: /* GUI IDLE */
3413 DRM_DEBUG("IH: CP EOP\n");
3414 rdev->pm.gui_idle = true;
3415 wake_up(&rdev->irq.idle_queue);
3416 break;
d8f60cfc 3417 default:
b042589c 3418 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3419 break;
3420 }
3421
3422 /* wptr/rptr are in bytes! */
0c45249f
JG		 3423 rptr += 16;
3424 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3425 }
3426 /* make sure wptr hasn't changed while processing */
3427 wptr = r600_get_ih_wptr(rdev);
3428 if (wptr != rdev->ih.wptr)
3429 goto restart_ih;
d4877cf2
AD		 3430 if (queue_hotplug)
3431 queue_work(rdev->wq, &rdev->hotplug_work);
d8f60cfc
AD		 3432 rdev->ih.rptr = rptr;
3433 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3434 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3435 return IRQ_HANDLED;
3436}
3ce0a23d
JG		 3437
3438/*
3439 * Debugfs info
3440 */
3441#if defined(CONFIG_DEBUG_FS)
3442
3443static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 3444{
3ce0a23d
JG		 3445 struct drm_info_node *node = (struct drm_info_node *) m->private;
3446 struct drm_device *dev = node->minor->dev;
3447 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 3448 unsigned count, i, j;
3449
3450 radeon_ring_free_size(rdev);
d6840766 3451 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 3452 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 3453 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3454 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3455 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3456 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 3457 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3458 seq_printf(m, "%u dwords in ring\n", count);
d6840766 3459 i = rdev->cp.rptr;
3ce0a23d 3460 for (j = 0; j <= count; j++) {
3ce0a23d 3461 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 3462 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 3463 }
3464 return 0;
3465}
3466
3467static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3468{
3469 struct drm_info_node *node = (struct drm_info_node *) m->private;
3470 struct drm_device *dev = node->minor->dev;
3471 struct radeon_device *rdev = dev->dev_private;
3472
3473 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3474 DREG32_SYS(m, rdev, VM_L2_STATUS);
3475 return 0;
3476}
3477
3478static struct drm_info_list r600_mc_info_list[] = {
3479 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3480 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3481};
3482#endif
3483
3484int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3485{
3486#if defined(CONFIG_DEBUG_FS)
3487 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3488#else
3489 return 0;
3490#endif
771fe6b9 3491}
062b389c
JG		 3492
3493/**
3494 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3495 * rdev: radeon device structure
3496 * bo: buffer object struct which userspace is waiting for idle
3497 *
3498 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3499 * through ring buffer, this leads to corruption in rendering, see
3500 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3501 * directly perform HDP flush by writing register through MMIO.
3502 */
3503void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3504{
3505 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3506}
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