[net-next-2.6.git] / drivers / gpu / drm / radeon / r420.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <linux/seq_file.h>
#include <linux/slab.h>
#include "drmP.h"
#include "radeon_reg.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "r100d.h"
#include "r420d.h"
#include "r420_reg_safe.h"

void r420_pm_init_profile(struct radeon_device *rdev)
{
	/* default */
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
	/* low sh */
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
	/* mid sh */
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
	/* high sh */
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
	/* low mh */
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
	/* mid mh */
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
	/* high mh */
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
}

static void r420_set_reg_safe(struct radeon_device *rdev)
{
	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
}

void r420_pipes_init(struct radeon_device *rdev)
{
	unsigned tmp;
	unsigned gb_pipe_select;
	unsigned num_pipes;

	/* GA_ENHANCE workaround TCL deadlock issue */
	WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
	       (1 << 2) | (1 << 3));
	/* add idle wait as per freedesktop.org bug 24041 */
	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "programming pipes. Bad things might happen.\n");
	}
	/* get max number of pipes */
	gb_pipe_select = RREG32(0x402C);
	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;

	/* SE chips have 1 pipe */
	if ((rdev->pdev->device == 0x5e4c) ||
	    (rdev->pdev->device == 0x5e4f))
		num_pipes = 1;

	rdev->num_gb_pipes = num_pipes;
	tmp = 0;
	switch (num_pipes) {
	default:
		/* force to 1 pipe */
		num_pipes = 1;
	case 1:
		tmp = (0 << 1);
		break;
	case 2:
		tmp = (3 << 1);
		break;
	case 3:
		tmp = (6 << 1);
		break;
	case 4:
		tmp = (7 << 1);
		break;
	}
	WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
	tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
	WREG32(R300_GB_TILE_CONFIG, tmp);
	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "programming pipes. Bad things might happen.\n");
	}

	tmp = RREG32(R300_DST_PIPE_CONFIG);
	WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);

	WREG32(R300_RB2D_DSTCACHE_MODE,
	       RREG32(R300_RB2D_DSTCACHE_MODE) |
	       R300_DC_AUTOFLUSH_ENABLE |
	       R300_DC_DC_DISABLE_IGNORE_PE);

	if (r100_gui_wait_for_idle(rdev)) {
		printk(KERN_WARNING "Failed to wait GUI idle while "
		       "programming pipes. Bad things might happen.\n");
	}

	if (rdev->family == CHIP_RV530) {
		tmp = RREG32(RV530_GB_PIPE_SELECT2);
		if ((tmp & 3) == 3)
			rdev->num_z_pipes = 2;
		else
			rdev->num_z_pipes = 1;
	} else
		rdev->num_z_pipes = 1;

	DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
		 rdev->num_gb_pipes, rdev->num_z_pipes);
}

u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
{
	u32 r;

	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
	r = RREG32(R_0001FC_MC_IND_DATA);
	return r;
}

void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
{
	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
		S_0001F8_MC_IND_WR_EN(1));
	WREG32(R_0001FC_MC_IND_DATA, v);
}

static void r420_debugfs(struct radeon_device *rdev)
{
	if (r100_debugfs_rbbm_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for RBBM !\n");
	}
	if (r420_debugfs_pipes_info_init(rdev)) {
		DRM_ERROR("Failed to register debugfs file for pipes !\n");
	}
}

static void r420_clock_resume(struct radeon_device *rdev)
{
	u32 sclk_cntl;

	if (radeon_dynclks != -1 && radeon_dynclks)
		radeon_atom_set_clock_gating(rdev, 1);
	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
	sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
	if (rdev->family == CHIP_R420)
		sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
}

static void r420_cp_errata_init(struct radeon_device *rdev)
{
	/* RV410 and R420 can lock up if CP DMA to host memory happens
	 * while the 2D engine is busy.
	 *
	 * The proper workaround is to queue a RESYNC at the beginning
	 * of the CP init, apparently.
	 */
	radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
	radeon_ring_lock(rdev, 8);
	radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
	radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
	radeon_ring_write(rdev, 0xDEADBEEF);
	radeon_ring_unlock_commit(rdev);
}

static void r420_cp_errata_fini(struct radeon_device *rdev)
{
	/* Catch the RESYNC we dispatched all the way back,
	 * at the very beginning of the CP init.
	 */
	radeon_ring_lock(rdev, 8);
	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
	radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
	radeon_ring_unlock_commit(rdev);
	radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
}

static int r420_startup(struct radeon_device *rdev)
{
	int r;

	/* set common regs */
	r100_set_common_regs(rdev);
	/* program mc */
	r300_mc_program(rdev);
	/* Resume clock */
	r420_clock_resume(rdev);
	/* Initialize GART (initialize after TTM so we can allocate
	 * memory through TTM but finalize after TTM) */
	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_enable(rdev);
		if (r)
			return r;
	}
	if (rdev->flags & RADEON_IS_PCI) {
		r = r100_pci_gart_enable(rdev);
		if (r)
			return r;
	}
	r420_pipes_init(rdev);
	/* Enable IRQ */
	r100_irq_set(rdev);
	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
	/* 1M ring buffer */
	r = r100_cp_init(rdev, 1024 * 1024);
	if (r) {
		dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
		return r;
	}
	r420_cp_errata_init(rdev);
	r = r100_wb_init(rdev);
	if (r) {
		dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
	}
	r = r100_ib_init(rdev);
	if (r) {
		dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
		return r;
	}
	return 0;
}

int r420_resume(struct radeon_device *rdev)
{
	/* Make sur GART are not working */
	if (rdev->flags & RADEON_IS_PCIE)
		rv370_pcie_gart_disable(rdev);
	if (rdev->flags & RADEON_IS_PCI)
		r100_pci_gart_disable(rdev);
	/* Resume clock before doing reset */
	r420_clock_resume(rdev);
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_asic_reset(rdev)) {
		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (rdev->is_atom_bios) {
		atom_asic_init(rdev->mode_info.atom_context);
	} else {
		radeon_combios_asic_init(rdev->ddev);
	}
	/* Resume clock after posting */
	r420_clock_resume(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	return r420_startup(rdev);
}

int r420_suspend(struct radeon_device *rdev)
{
	r420_cp_errata_fini(rdev);
	r100_cp_disable(rdev);
	r100_wb_disable(rdev);
	r100_irq_disable(rdev);
	if (rdev->flags & RADEON_IS_PCIE)
		rv370_pcie_gart_disable(rdev);
	if (rdev->flags & RADEON_IS_PCI)
		r100_pci_gart_disable(rdev);
	return 0;
}

void r420_fini(struct radeon_device *rdev)
{
	r100_cp_fini(rdev);
	r100_wb_fini(rdev);
	r100_ib_fini(rdev);
	radeon_gem_fini(rdev);
	if (rdev->flags & RADEON_IS_PCIE)
		rv370_pcie_gart_fini(rdev);
	if (rdev->flags & RADEON_IS_PCI)
		r100_pci_gart_fini(rdev);
	radeon_agp_fini(rdev);
	radeon_irq_kms_fini(rdev);
	radeon_fence_driver_fini(rdev);
	radeon_bo_fini(rdev);
	if (rdev->is_atom_bios) {
		radeon_atombios_fini(rdev);
	} else {
		radeon_combios_fini(rdev);
	}
	kfree(rdev->bios);
	rdev->bios = NULL;
}

int r420_init(struct radeon_device *rdev)
{
	int r;

	/* Initialize scratch registers */
	radeon_scratch_init(rdev);
	/* Initialize surface registers */
	radeon_surface_init(rdev);
	/* TODO: disable VGA need to use VGA request */
	/* BIOS*/
	if (!radeon_get_bios(rdev)) {
		if (ASIC_IS_AVIVO(rdev))
			return -EINVAL;
	}
	if (rdev->is_atom_bios) {
		r = radeon_atombios_init(rdev);
		if (r) {
			return r;
		}
	} else {
		r = radeon_combios_init(rdev);
		if (r) {
			return r;
		}
	}
	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
	if (radeon_asic_reset(rdev)) {
		dev_warn(rdev->dev,
			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
			RREG32(R_000E40_RBBM_STATUS),
			RREG32(R_0007C0_CP_STAT));
	}
	/* check if cards are posted or not */
	if (radeon_boot_test_post_card(rdev) == false)
		return -EINVAL;

	/* Initialize clocks */
	radeon_get_clock_info(rdev->ddev);
	/* initialize AGP */
	if (rdev->flags & RADEON_IS_AGP) {
		r = radeon_agp_init(rdev);
		if (r) {
			radeon_agp_disable(rdev);
		}
	}
	/* initialize memory controller */
	r300_mc_init(rdev);
	r420_debugfs(rdev);
	/* Fence driver */
	r = radeon_fence_driver_init(rdev);
	if (r) {
		return r;
	}
	r = radeon_irq_kms_init(rdev);
	if (r) {
		return r;
	}
	/* Memory manager */
	r = radeon_bo_init(rdev);
	if (r) {
		return r;
	}
	if (rdev->family == CHIP_R420)
		r100_enable_bm(rdev);

	if (rdev->flags & RADEON_IS_PCIE) {
		r = rv370_pcie_gart_init(rdev);
		if (r)
			return r;
	}
	if (rdev->flags & RADEON_IS_PCI) {
		r = r100_pci_gart_init(rdev);
		if (r)
			return r;
	}
	r420_set_reg_safe(rdev);
	rdev->accel_working = true;
	r = r420_startup(rdev);
	if (r) {
		/* Somethings want wront with the accel init stop accel */
		dev_err(rdev->dev, "Disabling GPU acceleration\n");
		r100_cp_fini(rdev);
		r100_wb_fini(rdev);
		r100_ib_fini(rdev);
		radeon_irq_kms_fini(rdev);
		if (rdev->flags & RADEON_IS_PCIE)
			rv370_pcie_gart_fini(rdev);
		if (rdev->flags & RADEON_IS_PCI)
			r100_pci_gart_fini(rdev);
		radeon_agp_fini(rdev);
		rdev->accel_working = false;
	}
	return 0;
}

/*
 * Debugfs info
 */
#if defined(CONFIG_DEBUG_FS)
static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
{
	struct drm_info_node *node = (struct drm_info_node *) m->private;
	struct drm_device *dev = node->minor->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t tmp;

	tmp = RREG32(R400_GB_PIPE_SELECT);
	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
	tmp = RREG32(R300_GB_TILE_CONFIG);
	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
	tmp = RREG32(R300_DST_PIPE_CONFIG);
	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
	return 0;
}

static struct drm_info_list r420_pipes_info_list[] = {
	{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
};
#endif

int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
#else
	return 0;
#endif
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include <linux/seq_file.h>
5a0e3ad6	29	#include <linux/slab.h>
771fe6b9 JG	30	#include "drmP.h"
	31	#include "radeon_reg.h"
	32	#include "radeon.h"
e6990375	33	#include "radeon_asic.h"
9f022ddf	34	#include "atom.h"
62cdc0c2	35	#include "r100d.h"
905b6822	36	#include "r420d.h"
804c7559 AD	37	#include "r420_reg_safe.h"
804c7559 AD	38
ce8f5370 AD	39	void r420_pm_init_profile(struct radeon_device *rdev)
	40	{
	41	/* default */
	42	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
	43	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	44	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
	45	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
	46	/* low sh */
	47	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
c9e75b21	48	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
ce8f5370 AD	49	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
ce8f5370 AD	50	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21 AD	51	/* mid sh */
	52	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
	53	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
	54	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
	55	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370 AD	56	/* high sh */
	57	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
	58	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	59	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
	60	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
	61	/* low mh */
	62	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
	63	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	64	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
	65	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21 AD	66	/* mid mh */
	67	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
	68	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	69	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
	70	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370 AD	71	/* high mh */
	72	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
	73	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
	74	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
	75	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
	76	}
	77
804c7559 AD	78	static void r420_set_reg_safe(struct radeon_device *rdev)
	79	{
	80	rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
	81	rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
	82	}
771fe6b9	83
771fe6b9 JG	84	void r420_pipes_init(struct radeon_device *rdev)
	85	{
	86	unsigned tmp;
	87	unsigned gb_pipe_select;
	88	unsigned num_pipes;
	89
	90	/* GA_ENHANCE workaround TCL deadlock issue */
4612dc97 AD	91	WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL \| R300_GA_FASTSYNC_CNTL \|
4612dc97 AD	92	(1 << 2) \| (1 << 3));
18a4cd2e DA	93	/* add idle wait as per freedesktop.org bug 24041 */
	94	if (r100_gui_wait_for_idle(rdev)) {
	95	printk(KERN_WARNING "Failed to wait GUI idle while "
	96	"programming pipes. Bad things might happen.\n");
	97	}
771fe6b9 JG	98	/* get max number of pipes */
	99	gb_pipe_select = RREG32(0x402C);
	100	num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
94f7bf64 TV	101
	102	/* SE chips have 1 pipe */
	103	if ((rdev->pdev->device == 0x5e4c) \|\|
	104	(rdev->pdev->device == 0x5e4f))
	105	num_pipes = 1;
	106
771fe6b9 JG	107	rdev->num_gb_pipes = num_pipes;
	108	tmp = 0;
	109	switch (num_pipes) {
	110	default:
	111	/* force to 1 pipe */
	112	num_pipes = 1;
	113	case 1:
	114	tmp = (0 << 1);
	115	break;
	116	case 2:
	117	tmp = (3 << 1);
	118	break;
	119	case 3:
	120	tmp = (6 << 1);
	121	break;
	122	case 4:
	123	tmp = (7 << 1);
	124	break;
	125	}
4612dc97	126	WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
771fe6b9	127	/* Sub pixel 1/12 so we can have 4K rendering according to doc */
4612dc97 AD	128	tmp \|= R300_TILE_SIZE_16 \| R300_ENABLE_TILING;
4612dc97 AD	129	WREG32(R300_GB_TILE_CONFIG, tmp);
771fe6b9 JG	130	if (r100_gui_wait_for_idle(rdev)) {
	131	printk(KERN_WARNING "Failed to wait GUI idle while "
	132	"programming pipes. Bad things might happen.\n");
	133	}
	134
4612dc97 AD	135	tmp = RREG32(R300_DST_PIPE_CONFIG);
4612dc97 AD	136	WREG32(R300_DST_PIPE_CONFIG, tmp \| R300_PIPE_AUTO_CONFIG);
771fe6b9 JG	137
	138	WREG32(R300_RB2D_DSTCACHE_MODE,
	139	RREG32(R300_RB2D_DSTCACHE_MODE) \|
	140	R300_DC_AUTOFLUSH_ENABLE \|
	141	R300_DC_DC_DISABLE_IGNORE_PE);
	142
	143	if (r100_gui_wait_for_idle(rdev)) {
	144	printk(KERN_WARNING "Failed to wait GUI idle while "
	145	"programming pipes. Bad things might happen.\n");
	146	}
f779b3e5 AD	147
	148	if (rdev->family == CHIP_RV530) {
	149	tmp = RREG32(RV530_GB_PIPE_SELECT2);
	150	if ((tmp & 3) == 3)
	151	rdev->num_z_pipes = 2;
	152	else
	153	rdev->num_z_pipes = 1;
	154	} else
	155	rdev->num_z_pipes = 1;
	156
	157	DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
	158	rdev->num_gb_pipes, rdev->num_z_pipes);
771fe6b9 JG	159	}
771fe6b9 JG	160
9f022ddf	161	u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
771fe6b9	162	{
9f022ddf JG	163	u32 r;
	164
	165	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
	166	r = RREG32(R_0001FC_MC_IND_DATA);
	167	return r;
	168	}
	169
	170	void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
	171	{
	172	WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) \|
	173	S_0001F8_MC_IND_WR_EN(1));
	174	WREG32(R_0001FC_MC_IND_DATA, v);
	175	}
	176
	177	static void r420_debugfs(struct radeon_device *rdev)
	178	{
	179	if (r100_debugfs_rbbm_init(rdev)) {
	180	DRM_ERROR("Failed to register debugfs file for RBBM !\n");
	181	}
	182	if (r420_debugfs_pipes_info_init(rdev)) {
	183	DRM_ERROR("Failed to register debugfs file for pipes !\n");
	184	}
	185	}
	186
	187	static void r420_clock_resume(struct radeon_device *rdev)
	188	{
	189	u32 sclk_cntl;
ca6ffc64 JG	190
	191	if (radeon_dynclks != -1 && radeon_dynclks)
	192	radeon_atom_set_clock_gating(rdev, 1);
9f022ddf JG	193	sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
	194	sclk_cntl \|= S_00000D_FORCE_CP(1) \| S_00000D_FORCE_VIP(1);
	195	if (rdev->family == CHIP_R420)
	196	sclk_cntl \|= S_00000D_FORCE_PX(1) \| S_00000D_FORCE_TX(1);
	197	WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
	198	}
	199
62cdc0c2 CS	200	static void r420_cp_errata_init(struct radeon_device *rdev)
	201	{
	202	/* RV410 and R420 can lock up if CP DMA to host memory happens
	203	* while the 2D engine is busy.
	204	*
	205	* The proper workaround is to queue a RESYNC at the beginning
	206	* of the CP init, apparently.
	207	*/
	208	radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
	209	radeon_ring_lock(rdev, 8);
	210	radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
	211	radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
	212	radeon_ring_write(rdev, 0xDEADBEEF);
	213	radeon_ring_unlock_commit(rdev);
	214	}
	215
	216	static void r420_cp_errata_fini(struct radeon_device *rdev)
	217	{
	218	/* Catch the RESYNC we dispatched all the way back,
	219	* at the very beginning of the CP init.
	220	*/
	221	radeon_ring_lock(rdev, 8);
	222	radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
	223	radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
	224	radeon_ring_unlock_commit(rdev);
	225	radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
	226	}
	227
fc30b8ef	228	static int r420_startup(struct radeon_device *rdev)
9f022ddf JG	229	{
	230	int r;
	231
92cde00c AD	232	/* set common regs */
	233	r100_set_common_regs(rdev);
	234	/* program mc */
9f022ddf	235	r300_mc_program(rdev);
ca6ffc64 JG	236	/* Resume clock */
ca6ffc64 JG	237	r420_clock_resume(rdev);
9f022ddf JG	238	/* Initialize GART (initialize after TTM so we can allocate
9f022ddf JG	239	* memory through TTM but finalize after TTM) */
4aac0473 JG	240	if (rdev->flags & RADEON_IS_PCIE) {
	241	r = rv370_pcie_gart_enable(rdev);
	242	if (r)
	243	return r;
	244	}
	245	if (rdev->flags & RADEON_IS_PCI) {
	246	r = r100_pci_gart_enable(rdev);
	247	if (r)
	248	return r;
9f022ddf	249	}
771fe6b9	250	r420_pipes_init(rdev);
9f022ddf	251	/* Enable IRQ */
9f022ddf	252	r100_irq_set(rdev);
cafe6609	253	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
9f022ddf JG	254	/* 1M ring buffer */
	255	r = r100_cp_init(rdev, 1024 * 1024);
	256	if (r) {
	257	dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
	258	return r;
	259	}
62cdc0c2	260	r420_cp_errata_init(rdev);
9f022ddf JG	261	r = r100_wb_init(rdev);
	262	if (r) {
	263	dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
771fe6b9	264	}
9f022ddf JG	265	r = r100_ib_init(rdev);
	266	if (r) {
	267	dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
	268	return r;
	269	}
	270	return 0;
771fe6b9 JG	271	}
771fe6b9 JG	272
fc30b8ef DA	273	int r420_resume(struct radeon_device *rdev)
	274	{
	275	/* Make sur GART are not working */
	276	if (rdev->flags & RADEON_IS_PCIE)
	277	rv370_pcie_gart_disable(rdev);
	278	if (rdev->flags & RADEON_IS_PCI)
	279	r100_pci_gart_disable(rdev);
	280	/* Resume clock before doing reset */
	281	r420_clock_resume(rdev);
	282	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74	283	if (radeon_asic_reset(rdev)) {
fc30b8ef DA	284	dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
	285	RREG32(R_000E40_RBBM_STATUS),
	286	RREG32(R_0007C0_CP_STAT));
	287	}
	288	/* check if cards are posted or not */
	289	if (rdev->is_atom_bios) {
	290	atom_asic_init(rdev->mode_info.atom_context);
	291	} else {
	292	radeon_combios_asic_init(rdev->ddev);
	293	}
	294	/* Resume clock after posting */
	295	r420_clock_resume(rdev);
550e2d92 DA	296	/* Initialize surface registers */
550e2d92 DA	297	radeon_surface_init(rdev);
fc30b8ef DA	298	return r420_startup(rdev);
	299	}
	300
9f022ddf JG	301	int r420_suspend(struct radeon_device *rdev)
9f022ddf JG	302	{
62cdc0c2	303	r420_cp_errata_fini(rdev);
9f022ddf JG	304	r100_cp_disable(rdev);
	305	r100_wb_disable(rdev);
	306	r100_irq_disable(rdev);
4aac0473 JG	307	if (rdev->flags & RADEON_IS_PCIE)
	308	rv370_pcie_gart_disable(rdev);
	309	if (rdev->flags & RADEON_IS_PCI)
	310	r100_pci_gart_disable(rdev);
9f022ddf JG	311	return 0;
9f022ddf JG	312	}
771fe6b9	313
9f022ddf	314	void r420_fini(struct radeon_device *rdev)
771fe6b9	315	{
9f022ddf JG	316	r100_cp_fini(rdev);
	317	r100_wb_fini(rdev);
	318	r100_ib_fini(rdev);
	319	radeon_gem_fini(rdev);
4aac0473 JG	320	if (rdev->flags & RADEON_IS_PCIE)
	321	rv370_pcie_gart_fini(rdev);
	322	if (rdev->flags & RADEON_IS_PCI)
	323	r100_pci_gart_fini(rdev);
9f022ddf JG	324	radeon_agp_fini(rdev);
	325	radeon_irq_kms_fini(rdev);
	326	radeon_fence_driver_fini(rdev);
4c788679	327	radeon_bo_fini(rdev);
9f022ddf JG	328	if (rdev->is_atom_bios) {
	329	radeon_atombios_fini(rdev);
	330	} else {
	331	radeon_combios_fini(rdev);
	332	}
	333	kfree(rdev->bios);
	334	rdev->bios = NULL;
771fe6b9 JG	335	}
771fe6b9 JG	336
9f022ddf JG	337	int r420_init(struct radeon_device *rdev)
	338	{
	339	int r;
	340
9f022ddf JG	341	/* Initialize scratch registers */
	342	radeon_scratch_init(rdev);
	343	/* Initialize surface registers */
	344	radeon_surface_init(rdev);
	345	/* TODO: disable VGA need to use VGA request */
	346	/* BIOS*/
	347	if (!radeon_get_bios(rdev)) {
	348	if (ASIC_IS_AVIVO(rdev))
	349	return -EINVAL;
	350	}
	351	if (rdev->is_atom_bios) {
	352	r = radeon_atombios_init(rdev);
	353	if (r) {
	354	return r;
	355	}
	356	} else {
	357	r = radeon_combios_init(rdev);
	358	if (r) {
	359	return r;
	360	}
	361	}
	362	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74	363	if (radeon_asic_reset(rdev)) {
9f022ddf JG	364	dev_warn(rdev->dev,
	365	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
	366	RREG32(R_000E40_RBBM_STATUS),
	367	RREG32(R_0007C0_CP_STAT));
	368	}
	369	/* check if cards are posted or not */
72542d77 DA	370	if (radeon_boot_test_post_card(rdev) == false)
	371	return -EINVAL;
	372
9f022ddf JG	373	/* Initialize clocks */
9f022ddf JG	374	radeon_get_clock_info(rdev->ddev);
d594e46a JG	375	/* initialize AGP */
	376	if (rdev->flags & RADEON_IS_AGP) {
	377	r = radeon_agp_init(rdev);
	378	if (r) {
	379	radeon_agp_disable(rdev);
	380	}
9f022ddf	381	}
d594e46a JG	382	/* initialize memory controller */
d594e46a JG	383	r300_mc_init(rdev);
9f022ddf JG	384	r420_debugfs(rdev);
	385	/* Fence driver */
	386	r = radeon_fence_driver_init(rdev);
	387	if (r) {
	388	return r;
	389	}
	390	r = radeon_irq_kms_init(rdev);
	391	if (r) {
	392	return r;
	393	}
	394	/* Memory manager */
4c788679	395	r = radeon_bo_init(rdev);
9f022ddf JG	396	if (r) {
	397	return r;
	398	}
17e15b0c DA	399	if (rdev->family == CHIP_R420)
	400	r100_enable_bm(rdev);
	401
4aac0473 JG	402	if (rdev->flags & RADEON_IS_PCIE) {
	403	r = rv370_pcie_gart_init(rdev);
	404	if (r)
	405	return r;
	406	}
	407	if (rdev->flags & RADEON_IS_PCI) {
	408	r = r100_pci_gart_init(rdev);
	409	if (r)
	410	return r;
	411	}
804c7559	412	r420_set_reg_safe(rdev);
733289c2	413	rdev->accel_working = true;
fc30b8ef	414	r = r420_startup(rdev);
9f022ddf JG	415	if (r) {
	416	/* Somethings want wront with the accel init stop accel */
	417	dev_err(rdev->dev, "Disabling GPU acceleration\n");
9f022ddf JG	418	r100_cp_fini(rdev);
	419	r100_wb_fini(rdev);
	420	r100_ib_fini(rdev);
655efd3d	421	radeon_irq_kms_fini(rdev);
4aac0473 JG	422	if (rdev->flags & RADEON_IS_PCIE)
	423	rv370_pcie_gart_fini(rdev);
	424	if (rdev->flags & RADEON_IS_PCI)
	425	r100_pci_gart_fini(rdev);
9f022ddf	426	radeon_agp_fini(rdev);
733289c2	427	rdev->accel_working = false;
9f022ddf JG	428	}
	429	return 0;
	430	}
771fe6b9 JG	431
	432	/*
	433	* Debugfs info
	434	*/
	435	#if defined(CONFIG_DEBUG_FS)
	436	static int r420_debugfs_pipes_info(struct seq_file m, void data)
	437	{
	438	struct drm_info_node node = (struct drm_info_node ) m->private;
	439	struct drm_device *dev = node->minor->dev;
	440	struct radeon_device *rdev = dev->dev_private;
	441	uint32_t tmp;
	442
	443	tmp = RREG32(R400_GB_PIPE_SELECT);
	444	seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
	445	tmp = RREG32(R300_GB_TILE_CONFIG);
	446	seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
	447	tmp = RREG32(R300_DST_PIPE_CONFIG);
	448	seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
	449	return 0;
	450	}
	451
	452	static struct drm_info_list r420_pipes_info_list[] = {
	453	{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
	454	};
	455	#endif
	456
	457	int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
	458	{
	459	#if defined(CONFIG_DEBUG_FS)
	460	return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
	461	#else
	462	return 0;
	463	#endif
	464	}