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drm/radeon/kms: simplify memory controller setup V2
[net-next-2.6.git] / drivers / gpu / drm / radeon / r300.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_reg.h"
32#include "radeon.h"
e024e110 33#include "radeon_drm.h"
551ebd83 34#include "r100_track.h"
3ce0a23d 35#include "r300d.h"
ca6ffc64 36#include "rv350d.h"
50f15303
DA		 37#include "r300_reg_safe.h"
38
cafe6609
JG		 39/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
40 *
41 * GPU Errata:
42 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
43 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
44 * However, scheduling such write to the ring seems harmless, i suspect
45 * the CP read collide with the flush somehow, or maybe the MC, hard to
46 * tell. (Jerome Glisse)
47 */
771fe6b9
JG		 48
49/*
50 * rv370,rv380 PCIE GART
51 */
207bf9e9
JG		 52static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
53
771fe6b9
JG		 54void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
55{
56 uint32_t tmp;
57 int i;
58
59 /* Workaround HW bug do flush 2 times */
60 for (i = 0; i < 2; i++) {
61 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
62 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
63 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
771fe6b9 65 }
de1b2898 66 mb();
771fe6b9
JG		 67}
68
4aac0473
JG		 69int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
70{
71 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
72
73 if (i < 0 || i > rdev->gart.num_gpu_pages) {
74 return -EINVAL;
75 }
76 addr = (lower_32_bits(addr) >> 8) |
77 ((upper_32_bits(addr) & 0xff) << 24) |
78 0xc;
79 /* on x86 we want this to be CPU endian, on powerpc
80 * on powerpc without HW swappers, it'll get swapped on way
81 * into VRAM - so no need for cpu_to_le32 on VRAM tables */
82 writel(addr, ((void __iomem *)ptr) + (i * 4));
83 return 0;
84}
85
86int rv370_pcie_gart_init(struct radeon_device *rdev)
771fe6b9 87{
771fe6b9
JG		 88 int r;
89
4aac0473
JG		 90 if (rdev->gart.table.vram.robj) {
91 WARN(1, "RV370 PCIE GART already initialized.\n");
92 return 0;
93 }
771fe6b9
JG		 94 /* Initialize common gart structure */
95 r = radeon_gart_init(rdev);
4aac0473 96 if (r)
771fe6b9 97 return r;
771fe6b9 98 r = rv370_debugfs_pcie_gart_info_init(rdev);
4aac0473 99 if (r)
771fe6b9 100 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
771fe6b9 101 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
4aac0473
JG		 102 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
103 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
104 return radeon_gart_table_vram_alloc(rdev);
105}
106
107int rv370_pcie_gart_enable(struct radeon_device *rdev)
108{
109 uint32_t table_addr;
110 uint32_t tmp;
111 int r;
112
113 if (rdev->gart.table.vram.robj == NULL) {
114 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
115 return -EINVAL;
771fe6b9 116 }
4aac0473
JG		 117 r = radeon_gart_table_vram_pin(rdev);
118 if (r)
119 return r;
82568565 120 radeon_gart_restore(rdev);
771fe6b9
JG		 121 /* discard memory request outside of configured range */
122 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
123 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
d594e46a
JG		 124 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
125 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
771fe6b9
JG		 126 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
127 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
128 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
129 table_addr = rdev->gart.table_addr;
130 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
131 /* FIXME: setup default page */
d594e46a 132 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
771fe6b9
JG		 133 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
134 /* Clear error */
135 WREG32_PCIE(0x18, 0);
136 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
137 tmp |= RADEON_PCIE_TX_GART_EN;
138 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
139 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
140 rv370_pcie_gart_tlb_flush(rdev);
141 DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
3ce0a23d 142 (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
771fe6b9
JG		 143 rdev->gart.ready = true;
144 return 0;
145}
146
147void rv370_pcie_gart_disable(struct radeon_device *rdev)
148{
4c788679
JG		 149 u32 tmp;
150 int r;
771fe6b9
JG		 151
152 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
153 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
154 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
155 if (rdev->gart.table.vram.robj) {
4c788679
JG		 156 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
157 if (likely(r == 0)) {
158 radeon_bo_kunmap(rdev->gart.table.vram.robj);
159 radeon_bo_unpin(rdev->gart.table.vram.robj);
160 radeon_bo_unreserve(rdev->gart.table.vram.robj);
161 }
771fe6b9
JG		 162 }
163}
164
4aac0473 165void rv370_pcie_gart_fini(struct radeon_device *rdev)
771fe6b9 166{
4aac0473
JG		 167 rv370_pcie_gart_disable(rdev);
168 radeon_gart_table_vram_free(rdev);
169 radeon_gart_fini(rdev);
771fe6b9
JG		 170}
171
771fe6b9
JG		 172void r300_fence_ring_emit(struct radeon_device *rdev,
173 struct radeon_fence *fence)
174{
175 /* Who ever call radeon_fence_emit should call ring_lock and ask
176 * for enough space (today caller are ib schedule and buffer move) */
177 /* Write SC register so SC & US assert idle */
4612dc97 178 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
771fe6b9 179 radeon_ring_write(rdev, 0);
4612dc97 180 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
771fe6b9
JG		 181 radeon_ring_write(rdev, 0);
182 /* Flush 3D cache */
4612dc97
AD		 183 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
184 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
185 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
186 radeon_ring_write(rdev, R300_ZC_FLUSH);
771fe6b9 187 /* Wait until IDLE & CLEAN */
4612dc97
AD		 188 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
189 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
190 RADEON_WAIT_2D_IDLECLEAN |
191 RADEON_WAIT_DMA_GUI_IDLE));
cafe6609
JG		 192 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
193 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
194 RADEON_HDP_READ_BUFFER_INVALIDATE);
195 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
196 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
771fe6b9
JG		 197 /* Emit fence sequence & fire IRQ */
198 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
199 radeon_ring_write(rdev, fence->seq);
200 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
201 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
202}
203
771fe6b9
JG		 204void r300_ring_start(struct radeon_device *rdev)
205{
206 unsigned gb_tile_config;
207 int r;
208
209 /* Sub pixel 1/12 so we can have 4K rendering according to doc */
210 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
068a117c 211 switch(rdev->num_gb_pipes) {
771fe6b9
JG		 212 case 2:
213 gb_tile_config |= R300_PIPE_COUNT_R300;
214 break;
215 case 3:
216 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
217 break;
218 case 4:
219 gb_tile_config |= R300_PIPE_COUNT_R420;
220 break;
221 case 1:
222 default:
223 gb_tile_config |= R300_PIPE_COUNT_RV350;
224 break;
225 }
226
227 r = radeon_ring_lock(rdev, 64);
228 if (r) {
229 return;
230 }
231 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
232 radeon_ring_write(rdev,
233 RADEON_ISYNC_ANY2D_IDLE3D |
234 RADEON_ISYNC_ANY3D_IDLE2D |
235 RADEON_ISYNC_WAIT_IDLEGUI |
236 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
237 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
238 radeon_ring_write(rdev, gb_tile_config);
239 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
240 radeon_ring_write(rdev,
241 RADEON_WAIT_2D_IDLECLEAN |
242 RADEON_WAIT_3D_IDLECLEAN);
4612dc97
AD		 243 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
244 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
771fe6b9
JG		 245 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
246 radeon_ring_write(rdev, 0);
247 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
248 radeon_ring_write(rdev, 0);
249 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
250 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
251 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
252 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
253 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
254 radeon_ring_write(rdev,
255 RADEON_WAIT_2D_IDLECLEAN |
256 RADEON_WAIT_3D_IDLECLEAN);
257 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
258 radeon_ring_write(rdev, 0);
259 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
260 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
261 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
262 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
263 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
264 radeon_ring_write(rdev,
265 ((6 << R300_MS_X0_SHIFT) |
266 (6 << R300_MS_Y0_SHIFT) |
267 (6 << R300_MS_X1_SHIFT) |
268 (6 << R300_MS_Y1_SHIFT) |
269 (6 << R300_MS_X2_SHIFT) |
270 (6 << R300_MS_Y2_SHIFT) |
271 (6 << R300_MSBD0_Y_SHIFT) |
272 (6 << R300_MSBD0_X_SHIFT)));
273 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
274 radeon_ring_write(rdev,
275 ((6 << R300_MS_X3_SHIFT) |
276 (6 << R300_MS_Y3_SHIFT) |
277 (6 << R300_MS_X4_SHIFT) |
278 (6 << R300_MS_Y4_SHIFT) |
279 (6 << R300_MS_X5_SHIFT) |
280 (6 << R300_MS_Y5_SHIFT) |
281 (6 << R300_MSBD1_SHIFT)));
282 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
283 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
284 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
285 radeon_ring_write(rdev,
286 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
287 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
288 radeon_ring_write(rdev,
289 R300_GEOMETRY_ROUND_NEAREST |
290 R300_COLOR_ROUND_NEAREST);
291 radeon_ring_unlock_commit(rdev);
292}
293
294void r300_errata(struct radeon_device *rdev)
295{
296 rdev->pll_errata = 0;
297
298 if (rdev->family == CHIP_R300 &&
299 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
300 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
301 }
302}
303
304int r300_mc_wait_for_idle(struct radeon_device *rdev)
305{
306 unsigned i;
307 uint32_t tmp;
308
309 for (i = 0; i < rdev->usec_timeout; i++) {
310 /* read MC_STATUS */
4612dc97
AD		 311 tmp = RREG32(RADEON_MC_STATUS);
312 if (tmp & R300_MC_IDLE) {
771fe6b9
JG		 313 return 0;
314 }
315 DRM_UDELAY(1);
316 }
317 return -1;
318}
319
320void r300_gpu_init(struct radeon_device *rdev)
321{
322 uint32_t gb_tile_config, tmp;
323
324 r100_hdp_reset(rdev);
325 /* FIXME: rv380 one pipes ? */
326 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
327 /* r300,r350 */
328 rdev->num_gb_pipes = 2;
329 } else {
330 /* rv350,rv370,rv380 */
331 rdev->num_gb_pipes = 1;
332 }
f779b3e5 333 rdev->num_z_pipes = 1;
771fe6b9
JG		 334 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
335 switch (rdev->num_gb_pipes) {
336 case 2:
337 gb_tile_config |= R300_PIPE_COUNT_R300;
338 break;
339 case 3:
340 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
341 break;
342 case 4:
343 gb_tile_config |= R300_PIPE_COUNT_R420;
344 break;
771fe6b9 345 default:
068a117c 346 case 1:
771fe6b9
JG		 347 gb_tile_config |= R300_PIPE_COUNT_RV350;
348 break;
349 }
350 WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
351
352 if (r100_gui_wait_for_idle(rdev)) {
353 printk(KERN_WARNING "Failed to wait GUI idle while "
354 "programming pipes. Bad things might happen.\n");
355 }
356
4612dc97
AD		 357 tmp = RREG32(R300_DST_PIPE_CONFIG);
358 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
771fe6b9
JG		 359
360 WREG32(R300_RB2D_DSTCACHE_MODE,
361 R300_DC_AUTOFLUSH_ENABLE |
362 R300_DC_DC_DISABLE_IGNORE_PE);
363
364 if (r100_gui_wait_for_idle(rdev)) {
365 printk(KERN_WARNING "Failed to wait GUI idle while "
366 "programming pipes. Bad things might happen.\n");
367 }
368 if (r300_mc_wait_for_idle(rdev)) {
369 printk(KERN_WARNING "Failed to wait MC idle while "
370 "programming pipes. Bad things might happen.\n");
371 }
f779b3e5
AD		 372 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
373 rdev->num_gb_pipes, rdev->num_z_pipes);
771fe6b9
JG		 374}
375
376int r300_ga_reset(struct radeon_device *rdev)
377{
378 uint32_t tmp;
379 bool reinit_cp;
380 int i;
381
382 reinit_cp = rdev->cp.ready;
383 rdev->cp.ready = false;
384 for (i = 0; i < rdev->usec_timeout; i++) {
385 WREG32(RADEON_CP_CSQ_MODE, 0);
386 WREG32(RADEON_CP_CSQ_CNTL, 0);
387 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
388 (void)RREG32(RADEON_RBBM_SOFT_RESET);
389 udelay(200);
390 WREG32(RADEON_RBBM_SOFT_RESET, 0);
391 /* Wait to prevent race in RBBM_STATUS */
392 mdelay(1);
393 tmp = RREG32(RADEON_RBBM_STATUS);
394 if (tmp & ((1 << 20) | (1 << 26))) {
395 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
396 /* GA still busy soft reset it */
397 WREG32(0x429C, 0x200);
398 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
4612dc97
AD		 399 WREG32(R300_RE_SCISSORS_TL, 0);
400 WREG32(R300_RE_SCISSORS_BR, 0);
771fe6b9
JG		 401 WREG32(0x24AC, 0);
402 }
403 /* Wait to prevent race in RBBM_STATUS */
404 mdelay(1);
405 tmp = RREG32(RADEON_RBBM_STATUS);
406 if (!(tmp & ((1 << 20) | (1 << 26)))) {
407 break;
408 }
409 }
410 for (i = 0; i < rdev->usec_timeout; i++) {
411 tmp = RREG32(RADEON_RBBM_STATUS);
412 if (!(tmp & ((1 << 20) | (1 << 26)))) {
413 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
414 tmp);
415 if (reinit_cp) {
416 return r100_cp_init(rdev, rdev->cp.ring_size);
417 }
418 return 0;
419 }
420 DRM_UDELAY(1);
421 }
422 tmp = RREG32(RADEON_RBBM_STATUS);
423 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
424 return -1;
425}
426
427int r300_gpu_reset(struct radeon_device *rdev)
428{
429 uint32_t status;
430
431 /* reset order likely matter */
432 status = RREG32(RADEON_RBBM_STATUS);
433 /* reset HDP */
434 r100_hdp_reset(rdev);
435 /* reset rb2d */
436 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
437 r100_rb2d_reset(rdev);
438 }
439 /* reset GA */
440 if (status & ((1 << 20) | (1 << 26))) {
441 r300_ga_reset(rdev);
442 }
443 /* reset CP */
444 status = RREG32(RADEON_RBBM_STATUS);
445 if (status & (1 << 16)) {
446 r100_cp_reset(rdev);
447 }
448 /* Check if GPU is idle */
449 status = RREG32(RADEON_RBBM_STATUS);
4612dc97 450 if (status & RADEON_RBBM_ACTIVE) {
771fe6b9
JG		 451 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
452 return -1;
453 }
454 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
455 return 0;
456}
457
458
459/*
460 * r300,r350,rv350,rv380 VRAM info
461 */
d594e46a 462void r300_mc_init(struct radeon_device *rdev)
771fe6b9
JG		 463{
464 uint32_t tmp;
465
466 /* DDR for all card after R300 & IGP */
467 rdev->mc.vram_is_ddr = true;
468 tmp = RREG32(RADEON_MEM_CNTL);
5ff55717
DA		 469 tmp &= R300_MEM_NUM_CHANNELS_MASK;
470 switch (tmp) {
471 case 0: rdev->mc.vram_width = 64; break;
472 case 1: rdev->mc.vram_width = 128; break;
473 case 2: rdev->mc.vram_width = 256; break;
474 default: rdev->mc.vram_width = 128; break;
771fe6b9 475 }
2a0f8918 476 r100_vram_init_sizes(rdev);
d594e46a
JG		 477 if (!(rdev->flags & RADEON_IS_AGP))
478 radeon_gtt_location(rdev, &rdev->mc);
771fe6b9
JG		 479}
480
771fe6b9
JG		 481void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
482{
483 uint32_t link_width_cntl, mask;
484
485 if (rdev->flags & RADEON_IS_IGP)
486 return;
487
488 if (!(rdev->flags & RADEON_IS_PCIE))
489 return;
490
491 /* FIXME wait for idle */
492
493 switch (lanes) {
494 case 0:
495 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
496 break;
497 case 1:
498 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
499 break;
500 case 2:
501 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
502 break;
503 case 4:
504 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
505 break;
506 case 8:
507 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
508 break;
509 case 12:
510 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
511 break;
512 case 16:
513 default:
514 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
515 break;
516 }
517
518 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
519
520 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
521 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
522 return;
523
524 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
525 RADEON_PCIE_LC_RECONFIG_NOW |
526 RADEON_PCIE_LC_RECONFIG_LATER |
527 RADEON_PCIE_LC_SHORT_RECONFIG_EN);
528 link_width_cntl |= mask;
529 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
530 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
531 RADEON_PCIE_LC_RECONFIG_NOW));
532
533 /* wait for lane set to complete */
534 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
535 while (link_width_cntl == 0xffffffff)
536 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
537
538}
539
c836a412
AD		 540int rv370_get_pcie_lanes(struct radeon_device *rdev)
541{
542 u32 link_width_cntl;
543
544 if (rdev->flags & RADEON_IS_IGP)
545 return 0;
546
547 if (!(rdev->flags & RADEON_IS_PCIE))
548 return 0;
549
550 /* FIXME wait for idle */
551
552 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
553
554 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
555 case RADEON_PCIE_LC_LINK_WIDTH_X0:
556 return 0;
557 case RADEON_PCIE_LC_LINK_WIDTH_X1:
558 return 1;
559 case RADEON_PCIE_LC_LINK_WIDTH_X2:
560 return 2;
561 case RADEON_PCIE_LC_LINK_WIDTH_X4:
562 return 4;
563 case RADEON_PCIE_LC_LINK_WIDTH_X8:
564 return 8;
565 case RADEON_PCIE_LC_LINK_WIDTH_X16:
566 default:
567 return 16;
568 }
569}
570
771fe6b9
JG		 571#if defined(CONFIG_DEBUG_FS)
572static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
573{
574 struct drm_info_node *node = (struct drm_info_node *) m->private;
575 struct drm_device *dev = node->minor->dev;
576 struct radeon_device *rdev = dev->dev_private;
577 uint32_t tmp;
578
579 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
580 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
581 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
582 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
583 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
584 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
585 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
586 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
587 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
588 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
589 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
590 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
591 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
592 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
593 return 0;
594}
595
596static struct drm_info_list rv370_pcie_gart_info_list[] = {
597 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
598};
599#endif
600
207bf9e9 601static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
771fe6b9
JG		 602{
603#if defined(CONFIG_DEBUG_FS)
604 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
605#else
606 return 0;
607#endif
608}
609
771fe6b9
JG		 610static int r300_packet0_check(struct radeon_cs_parser *p,
611 struct radeon_cs_packet *pkt,
612 unsigned idx, unsigned reg)
613{
771fe6b9 614 struct radeon_cs_reloc *reloc;
551ebd83 615 struct r100_cs_track *track;
771fe6b9 616 volatile uint32_t *ib;
e024e110 617 uint32_t tmp, tile_flags = 0;
771fe6b9
JG		 618 unsigned i;
619 int r;
513bcb46 620 u32 idx_value;
771fe6b9
JG		 621
622 ib = p->ib->ptr;
551ebd83 623 track = (struct r100_cs_track *)p->track;
513bcb46
DA		 624 idx_value = radeon_get_ib_value(p, idx);
625
068a117c 626 switch(reg) {
531369e6
DA		 627 case AVIVO_D1MODE_VLINE_START_END:
628 case RADEON_CRTC_GUI_TRIG_VLINE:
629 r = r100_cs_packet_parse_vline(p);
630 if (r) {
631 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
632 idx, reg);
633 r100_cs_dump_packet(p, pkt);
634 return r;
635 }
636 break;
771fe6b9
JG		 637 case RADEON_DST_PITCH_OFFSET:
638 case RADEON_SRC_PITCH_OFFSET:
551ebd83
DA		 639 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
640 if (r)
771fe6b9 641 return r;
771fe6b9
JG		 642 break;
643 case R300_RB3D_COLOROFFSET0:
644 case R300_RB3D_COLOROFFSET1:
645 case R300_RB3D_COLOROFFSET2:
646 case R300_RB3D_COLOROFFSET3:
647 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
648 r = r100_cs_packet_next_reloc(p, &reloc);
649 if (r) {
650 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
651 idx, reg);
652 r100_cs_dump_packet(p, pkt);
653 return r;
654 }
655 track->cb[i].robj = reloc->robj;
513bcb46
DA		 656 track->cb[i].offset = idx_value;
657 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
771fe6b9
JG		 658 break;
659 case R300_ZB_DEPTHOFFSET:
660 r = r100_cs_packet_next_reloc(p, &reloc);
661 if (r) {
662 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
663 idx, reg);
664 r100_cs_dump_packet(p, pkt);
665 return r;
666 }
667 track->zb.robj = reloc->robj;
513bcb46
DA		 668 track->zb.offset = idx_value;
669 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
771fe6b9
JG		 670 break;
671 case R300_TX_OFFSET_0:
672 case R300_TX_OFFSET_0+4:
673 case R300_TX_OFFSET_0+8:
674 case R300_TX_OFFSET_0+12:
675 case R300_TX_OFFSET_0+16:
676 case R300_TX_OFFSET_0+20:
677 case R300_TX_OFFSET_0+24:
678 case R300_TX_OFFSET_0+28:
679 case R300_TX_OFFSET_0+32:
680 case R300_TX_OFFSET_0+36:
681 case R300_TX_OFFSET_0+40:
682 case R300_TX_OFFSET_0+44:
683 case R300_TX_OFFSET_0+48:
684 case R300_TX_OFFSET_0+52:
685 case R300_TX_OFFSET_0+56:
686 case R300_TX_OFFSET_0+60:
068a117c 687 i = (reg - R300_TX_OFFSET_0) >> 2;
771fe6b9
JG		 688 r = r100_cs_packet_next_reloc(p, &reloc);
689 if (r) {
690 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
691 idx, reg);
692 r100_cs_dump_packet(p, pkt);
693 return r;
694 }
6e726772
MC		 695
696 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
697 tile_flags |= R300_TXO_MACRO_TILE;
698 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
699 tile_flags |= R300_TXO_MICRO_TILE;
700
701 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
702 tmp |= tile_flags;
703 ib[idx] = tmp;
068a117c 704 track->textures[i].robj = reloc->robj;
771fe6b9
JG		 705 break;
706 /* Tracked registers */
068a117c
JG		 707 case 0x2084:
708 /* VAP_VF_CNTL */
513bcb46 709 track->vap_vf_cntl = idx_value;
068a117c
JG		 710 break;
711 case 0x20B4:
712 /* VAP_VTX_SIZE */
513bcb46 713 track->vtx_size = idx_value & 0x7F;
068a117c
JG		 714 break;
715 case 0x2134:
716 /* VAP_VF_MAX_VTX_INDX */
513bcb46 717 track->max_indx = idx_value & 0x00FFFFFFUL;
068a117c 718 break;
771fe6b9
JG		 719 case 0x43E4:
720 /* SC_SCISSOR1 */
513bcb46 721 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
771fe6b9
JG		 722 if (p->rdev->family < CHIP_RV515) {
723 track->maxy -= 1440;
724 }
725 break;
726 case 0x4E00:
727 /* RB3D_CCTL */
513bcb46 728 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
771fe6b9
JG		 729 break;
730 case 0x4E38:
731 case 0x4E3C:
732 case 0x4E40:
733 case 0x4E44:
734 /* RB3D_COLORPITCH0 */
735 /* RB3D_COLORPITCH1 */
736 /* RB3D_COLORPITCH2 */
737 /* RB3D_COLORPITCH3 */
e024e110
DA		 738 r = r100_cs_packet_next_reloc(p, &reloc);
739 if (r) {
740 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
741 idx, reg);
742 r100_cs_dump_packet(p, pkt);
743 return r;
744 }
745
746 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
747 tile_flags |= R300_COLOR_TILE_ENABLE;
748 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
749 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
750
513bcb46 751 tmp = idx_value & ~(0x7 << 16);
e024e110
DA		 752 tmp |= tile_flags;
753 ib[idx] = tmp;
754
771fe6b9 755 i = (reg - 0x4E38) >> 2;
513bcb46
DA		 756 track->cb[i].pitch = idx_value & 0x3FFE;
757 switch (((idx_value >> 21) & 0xF)) {
771fe6b9
JG		 758 case 9:
759 case 11:
760 case 12:
761 track->cb[i].cpp = 1;
762 break;
763 case 3:
764 case 4:
765 case 13:
766 case 15:
767 track->cb[i].cpp = 2;
768 break;
769 case 6:
770 track->cb[i].cpp = 4;
771 break;
772 case 10:
773 track->cb[i].cpp = 8;
774 break;
775 case 7:
776 track->cb[i].cpp = 16;
777 break;
778 default:
779 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 780 ((idx_value >> 21) & 0xF));
771fe6b9
JG		 781 return -EINVAL;
782 }
783 break;
784 case 0x4F00:
785 /* ZB_CNTL */
513bcb46 786 if (idx_value & 2) {
771fe6b9
JG		 787 track->z_enabled = true;
788 } else {
789 track->z_enabled = false;
790 }
791 break;
792 case 0x4F10:
793 /* ZB_FORMAT */
513bcb46 794 switch ((idx_value & 0xF)) {
771fe6b9
JG		 795 case 0:
796 case 1:
797 track->zb.cpp = 2;
798 break;
799 case 2:
800 track->zb.cpp = 4;
801 break;
802 default:
803 DRM_ERROR("Invalid z buffer format (%d) !\n",
513bcb46 804 (idx_value & 0xF));
771fe6b9
JG		 805 return -EINVAL;
806 }
807 break;
808 case 0x4F24:
809 /* ZB_DEPTHPITCH */
e024e110
DA		 810 r = r100_cs_packet_next_reloc(p, &reloc);
811 if (r) {
812 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
813 idx, reg);
814 r100_cs_dump_packet(p, pkt);
815 return r;
816 }
817
818 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
819 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
820 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
821 tile_flags |= R300_DEPTHMICROTILE_TILED;;
822
513bcb46 823 tmp = idx_value & ~(0x7 << 16);
e024e110
DA		 824 tmp |= tile_flags;
825 ib[idx] = tmp;
826
513bcb46 827 track->zb.pitch = idx_value & 0x3FFC;
771fe6b9 828 break;
068a117c
JG		 829 case 0x4104:
830 for (i = 0; i < 16; i++) {
831 bool enabled;
832
513bcb46 833 enabled = !!(idx_value & (1 << i));
068a117c
JG		 834 track->textures[i].enabled = enabled;
835 }
836 break;
837 case 0x44C0:
838 case 0x44C4:
839 case 0x44C8:
840 case 0x44CC:
841 case 0x44D0:
842 case 0x44D4:
843 case 0x44D8:
844 case 0x44DC:
845 case 0x44E0:
846 case 0x44E4:
847 case 0x44E8:
848 case 0x44EC:
849 case 0x44F0:
850 case 0x44F4:
851 case 0x44F8:
852 case 0x44FC:
853 /* TX_FORMAT1_[0-15] */
854 i = (reg - 0x44C0) >> 2;
513bcb46 855 tmp = (idx_value >> 25) & 0x3;
068a117c 856 track->textures[i].tex_coord_type = tmp;
513bcb46 857 switch ((idx_value & 0x1F)) {
551ebd83
DA		 858 case R300_TX_FORMAT_X8:
859 case R300_TX_FORMAT_Y4X4:
860 case R300_TX_FORMAT_Z3Y3X2:
068a117c
JG		 861 track->textures[i].cpp = 1;
862 break;
551ebd83
DA		 863 case R300_TX_FORMAT_X16:
864 case R300_TX_FORMAT_Y8X8:
865 case R300_TX_FORMAT_Z5Y6X5:
866 case R300_TX_FORMAT_Z6Y5X5:
867 case R300_TX_FORMAT_W4Z4Y4X4:
868 case R300_TX_FORMAT_W1Z5Y5X5:
551ebd83
DA		 869 case R300_TX_FORMAT_D3DMFT_CxV8U8:
870 case R300_TX_FORMAT_B8G8_B8G8:
871 case R300_TX_FORMAT_G8R8_G8B8:
068a117c
JG		 872 track->textures[i].cpp = 2;
873 break;
551ebd83
DA		 874 case R300_TX_FORMAT_Y16X16:
875 case R300_TX_FORMAT_Z11Y11X10:
876 case R300_TX_FORMAT_Z10Y11X11:
877 case R300_TX_FORMAT_W8Z8Y8X8:
878 case R300_TX_FORMAT_W2Z10Y10X10:
879 case 0x17:
880 case R300_TX_FORMAT_FL_I32:
881 case 0x1e:
068a117c
JG		 882 track->textures[i].cpp = 4;
883 break;
551ebd83
DA		 884 case R300_TX_FORMAT_W16Z16Y16X16:
885 case R300_TX_FORMAT_FL_R16G16B16A16:
886 case R300_TX_FORMAT_FL_I32A32:
068a117c
JG		 887 track->textures[i].cpp = 8;
888 break;
551ebd83 889 case R300_TX_FORMAT_FL_R32G32B32A32:
068a117c
JG		 890 track->textures[i].cpp = 16;
891 break;
d785d78b
DA		 892 case R300_TX_FORMAT_DXT1:
893 track->textures[i].cpp = 1;
894 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
895 break;
512889f4
MO		 896 case R300_TX_FORMAT_ATI2N:
897 if (p->rdev->family < CHIP_R420) {
898 DRM_ERROR("Invalid texture format %u\n",
899 (idx_value & 0x1F));
900 return -EINVAL;
901 }
902 /* The same rules apply as for DXT3/5. */
903 /* Pass through. */
d785d78b
DA		 904 case R300_TX_FORMAT_DXT3:
905 case R300_TX_FORMAT_DXT5:
906 track->textures[i].cpp = 1;
907 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
908 break;
068a117c
JG		 909 default:
910 DRM_ERROR("Invalid texture format %u\n",
513bcb46 911 (idx_value & 0x1F));
068a117c
JG		 912 return -EINVAL;
913 break;
914 }
915 break;
916 case 0x4400:
917 case 0x4404:
918 case 0x4408:
919 case 0x440C:
920 case 0x4410:
921 case 0x4414:
922 case 0x4418:
923 case 0x441C:
924 case 0x4420:
925 case 0x4424:
926 case 0x4428:
927 case 0x442C:
928 case 0x4430:
929 case 0x4434:
930 case 0x4438:
931 case 0x443C:
932 /* TX_FILTER0_[0-15] */
933 i = (reg - 0x4400) >> 2;
513bcb46 934 tmp = idx_value & 0x7;
068a117c
JG		 935 if (tmp == 2 || tmp == 4 || tmp == 6) {
936 track->textures[i].roundup_w = false;
937 }
513bcb46 938 tmp = (idx_value >> 3) & 0x7;
068a117c
JG		 939 if (tmp == 2 || tmp == 4 || tmp == 6) {
940 track->textures[i].roundup_h = false;
941 }
942 break;
943 case 0x4500:
944 case 0x4504:
945 case 0x4508:
946 case 0x450C:
947 case 0x4510:
948 case 0x4514:
949 case 0x4518:
950 case 0x451C:
951 case 0x4520:
952 case 0x4524:
953 case 0x4528:
954 case 0x452C:
955 case 0x4530:
956 case 0x4534:
957 case 0x4538:
958 case 0x453C:
959 /* TX_FORMAT2_[0-15] */
960 i = (reg - 0x4500) >> 2;
513bcb46 961 tmp = idx_value & 0x3FFF;
068a117c
JG		 962 track->textures[i].pitch = tmp + 1;
963 if (p->rdev->family >= CHIP_RV515) {
513bcb46 964 tmp = ((idx_value >> 15) & 1) << 11;
068a117c 965 track->textures[i].width_11 = tmp;
513bcb46 966 tmp = ((idx_value >> 16) & 1) << 11;
068a117c 967 track->textures[i].height_11 = tmp;
512889f4
MO		 968
969 /* ATI1N */
970 if (idx_value & (1 << 14)) {
971 /* The same rules apply as for DXT1. */
972 track->textures[i].compress_format =
973 R100_TRACK_COMP_DXT1;
974 }
975 } else if (idx_value & (1 << 14)) {
976 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
977 return -EINVAL;
068a117c
JG		 978 }
979 break;
980 case 0x4480:
981 case 0x4484:
982 case 0x4488:
983 case 0x448C:
984 case 0x4490:
985 case 0x4494:
986 case 0x4498:
987 case 0x449C:
988 case 0x44A0:
989 case 0x44A4:
990 case 0x44A8:
991 case 0x44AC:
992 case 0x44B0:
993 case 0x44B4:
994 case 0x44B8:
995 case 0x44BC:
996 /* TX_FORMAT0_[0-15] */
997 i = (reg - 0x4480) >> 2;
513bcb46 998 tmp = idx_value & 0x7FF;
068a117c 999 track->textures[i].width = tmp + 1;
513bcb46 1000 tmp = (idx_value >> 11) & 0x7FF;
068a117c 1001 track->textures[i].height = tmp + 1;
513bcb46 1002 tmp = (idx_value >> 26) & 0xF;
068a117c 1003 track->textures[i].num_levels = tmp;
513bcb46 1004 tmp = idx_value & (1 << 31);
068a117c 1005 track->textures[i].use_pitch = !!tmp;
513bcb46 1006 tmp = (idx_value >> 22) & 0xF;
068a117c
JG		 1007 track->textures[i].txdepth = tmp;
1008 break;
3f8befec
DA		 1009 case R300_ZB_ZPASS_ADDR:
1010 r = r100_cs_packet_next_reloc(p, &reloc);
1011 if (r) {
1012 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1013 idx, reg);
1014 r100_cs_dump_packet(p, pkt);
1015 return r;
1016 }
513bcb46 1017 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
3f8befec 1018 break;
46c64d4b
MO		 1019 case 0x4e0c:
1020 /* RB3D_COLOR_CHANNEL_MASK */
1021 track->color_channel_mask = idx_value;
1022 break;
1023 case 0x4d1c:
1024 /* ZB_BW_CNTL */
1025 track->fastfill = !!(idx_value & (1 << 2));
1026 break;
1027 case 0x4e04:
1028 /* RB3D_BLENDCNTL */
1029 track->blend_read_enable = !!(idx_value & (1 << 2));
1030 break;
3f8befec
DA		 1031 case 0x4be8:
1032 /* valid register only on RV530 */
1033 if (p->rdev->family == CHIP_RV530)
1034 break;
1035 /* fallthrough do not move */
771fe6b9 1036 default:
068a117c
JG		 1037 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1038 reg, idx);
771fe6b9
JG		 1039 return -EINVAL;
1040 }
1041 return 0;
1042}
1043
1044static int r300_packet3_check(struct radeon_cs_parser *p,
1045 struct radeon_cs_packet *pkt)
1046{
771fe6b9 1047 struct radeon_cs_reloc *reloc;
551ebd83 1048 struct r100_cs_track *track;
771fe6b9
JG		 1049 volatile uint32_t *ib;
1050 unsigned idx;
771fe6b9
JG		 1051 int r;
1052
1053 ib = p->ib->ptr;
771fe6b9 1054 idx = pkt->idx + 1;
551ebd83 1055 track = (struct r100_cs_track *)p->track;
068a117c 1056 switch(pkt->opcode) {
771fe6b9 1057 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1058 r = r100_packet3_load_vbpntr(p, pkt, idx);
1059 if (r)
1060 return r;
771fe6b9
JG		 1061 break;
1062 case PACKET3_INDX_BUFFER:
1063 r = r100_cs_packet_next_reloc(p, &reloc);
1064 if (r) {
1065 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1066 r100_cs_dump_packet(p, pkt);
1067 return r;
1068 }
513bcb46 1069 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1070 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1071 if (r) {
1072 return r;
1073 }
771fe6b9
JG		 1074 break;
1075 /* Draw packet */
771fe6b9 1076 case PACKET3_3D_DRAW_IMMD:
068a117c
JG		 1077 /* Number of dwords is vtx_size * (num_vertices - 1)
1078 * PRIM_WALK must be equal to 3 vertex data in embedded
1079 * in cmd stream */
513bcb46 1080 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
068a117c
JG		 1081 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1082 return -EINVAL;
1083 }
513bcb46 1084 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
068a117c 1085 track->immd_dwords = pkt->count - 1;
551ebd83 1086 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1087 if (r) {
1088 return r;
1089 }
1090 break;
771fe6b9 1091 case PACKET3_3D_DRAW_IMMD_2:
068a117c
JG		 1092 /* Number of dwords is vtx_size * (num_vertices - 1)
1093 * PRIM_WALK must be equal to 3 vertex data in embedded
1094 * in cmd stream */
513bcb46 1095 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
068a117c
JG		 1096 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1097 return -EINVAL;
1098 }
513bcb46 1099 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
068a117c 1100 track->immd_dwords = pkt->count;
551ebd83 1101 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1102 if (r) {
1103 return r;
1104 }
1105 break;
1106 case PACKET3_3D_DRAW_VBUF:
513bcb46 1107 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83 1108 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1109 if (r) {
1110 return r;
1111 }
1112 break;
1113 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1114 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83 1115 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1116 if (r) {
1117 return r;
1118 }
1119 break;
1120 case PACKET3_3D_DRAW_INDX:
513bcb46 1121 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83 1122 r = r100_cs_track_check(p->rdev, track);
068a117c
JG		 1123 if (r) {
1124 return r;
1125 }
1126 break;
771fe6b9 1127 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1128 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83 1129 r = r100_cs_track_check(p->rdev, track);
771fe6b9
JG		 1130 if (r) {
1131 return r;
1132 }
1133 break;
1134 case PACKET3_NOP:
1135 break;
1136 default:
1137 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1138 return -EINVAL;
1139 }
1140 return 0;
1141}
1142
1143int r300_cs_parse(struct radeon_cs_parser *p)
1144{
1145 struct radeon_cs_packet pkt;
9f022ddf 1146 struct r100_cs_track *track;
771fe6b9
JG		 1147 int r;
1148
9f022ddf
JG		 1149 track = kzalloc(sizeof(*track), GFP_KERNEL);
1150 r100_cs_track_clear(p->rdev, track);
1151 p->track = track;
771fe6b9
JG		 1152 do {
1153 r = r100_cs_packet_parse(p, &pkt, p->idx);
1154 if (r) {
1155 return r;
1156 }
1157 p->idx += pkt.count + 2;
1158 switch (pkt.type) {
1159 case PACKET_TYPE0:
1160 r = r100_cs_parse_packet0(p, &pkt,
068a117c
JG		 1161 p->rdev->config.r300.reg_safe_bm,
1162 p->rdev->config.r300.reg_safe_bm_size,
771fe6b9
JG		 1163 &r300_packet0_check);
1164 break;
1165 case PACKET_TYPE2:
1166 break;
1167 case PACKET_TYPE3:
1168 r = r300_packet3_check(p, &pkt);
1169 break;
1170 default:
1171 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1172 return -EINVAL;
1173 }
1174 if (r) {
1175 return r;
1176 }
1177 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1178 return 0;
1179}
068a117c 1180
9f022ddf 1181void r300_set_reg_safe(struct radeon_device *rdev)
068a117c
JG		 1182{
1183 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1184 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
9f022ddf
JG		 1185}
1186
9f022ddf
JG		 1187void r300_mc_program(struct radeon_device *rdev)
1188{
1189 struct r100_mc_save save;
1190 int r;
1191
1192 r = r100_debugfs_mc_info_init(rdev);
1193 if (r) {
1194 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1195 }
1196
1197 /* Stops all mc clients */
1198 r100_mc_stop(rdev, &save);
9f022ddf
JG		 1199 if (rdev->flags & RADEON_IS_AGP) {
1200 WREG32(R_00014C_MC_AGP_LOCATION,
1201 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1202 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1203 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1204 WREG32(R_00015C_AGP_BASE_2,
1205 upper_32_bits(rdev->mc.agp_base) & 0xff);
1206 } else {
1207 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1208 WREG32(R_000170_AGP_BASE, 0);
1209 WREG32(R_00015C_AGP_BASE_2, 0);
1210 }
1211 /* Wait for mc idle */
1212 if (r300_mc_wait_for_idle(rdev))
1213 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1214 /* Program MC, should be a 32bits limited address space */
1215 WREG32(R_000148_MC_FB_LOCATION,
1216 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1217 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1218 r100_mc_resume(rdev, &save);
1219}
ca6ffc64
JG		 1220
1221void r300_clock_startup(struct radeon_device *rdev)
1222{
1223 u32 tmp;
1224
1225 if (radeon_dynclks != -1 && radeon_dynclks)
1226 radeon_legacy_set_clock_gating(rdev, 1);
1227 /* We need to force on some of the block */
1228 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1229 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1230 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1231 tmp |= S_00000D_FORCE_VAP(1);
1232 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1233}
207bf9e9
JG		 1234
1235static int r300_startup(struct radeon_device *rdev)
1236{
1237 int r;
1238
92cde00c
AD		 1239 /* set common regs */
1240 r100_set_common_regs(rdev);
1241 /* program mc */
207bf9e9
JG		 1242 r300_mc_program(rdev);
1243 /* Resume clock */
1244 r300_clock_startup(rdev);
1245 /* Initialize GPU configuration (# pipes, ...) */
1246 r300_gpu_init(rdev);
1247 /* Initialize GART (initialize after TTM so we can allocate
1248 * memory through TTM but finalize after TTM) */
1249 if (rdev->flags & RADEON_IS_PCIE) {
1250 r = rv370_pcie_gart_enable(rdev);
1251 if (r)
1252 return r;
1253 }
17e15b0c
DA		 1254
1255 if (rdev->family == CHIP_R300 ||
1256 rdev->family == CHIP_R350 ||
1257 rdev->family == CHIP_RV350)
1258 r100_enable_bm(rdev);
1259
207bf9e9
JG		 1260 if (rdev->flags & RADEON_IS_PCI) {
1261 r = r100_pci_gart_enable(rdev);
1262 if (r)
1263 return r;
1264 }
1265 /* Enable IRQ */
207bf9e9 1266 r100_irq_set(rdev);
cafe6609 1267 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
207bf9e9
JG		 1268 /* 1M ring buffer */
1269 r = r100_cp_init(rdev, 1024 * 1024);
1270 if (r) {
1271 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1272 return r;
1273 }
1274 r = r100_wb_init(rdev);
1275 if (r)
1276 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1277 r = r100_ib_init(rdev);
1278 if (r) {
1279 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1280 return r;
1281 }
1282 return 0;
1283}
1284
1285int r300_resume(struct radeon_device *rdev)
1286{
1287 /* Make sur GART are not working */
1288 if (rdev->flags & RADEON_IS_PCIE)
1289 rv370_pcie_gart_disable(rdev);
1290 if (rdev->flags & RADEON_IS_PCI)
1291 r100_pci_gart_disable(rdev);
1292 /* Resume clock before doing reset */
1293 r300_clock_startup(rdev);
1294 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1295 if (radeon_gpu_reset(rdev)) {
1296 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1297 RREG32(R_000E40_RBBM_STATUS),
1298 RREG32(R_0007C0_CP_STAT));
1299 }
1300 /* post */
1301 radeon_combios_asic_init(rdev->ddev);
1302 /* Resume clock after posting */
1303 r300_clock_startup(rdev);
550e2d92
DA		 1304 /* Initialize surface registers */
1305 radeon_surface_init(rdev);
207bf9e9
JG		 1306 return r300_startup(rdev);
1307}
1308
1309int r300_suspend(struct radeon_device *rdev)
1310{
1311 r100_cp_disable(rdev);
1312 r100_wb_disable(rdev);
1313 r100_irq_disable(rdev);
1314 if (rdev->flags & RADEON_IS_PCIE)
1315 rv370_pcie_gart_disable(rdev);
1316 if (rdev->flags & RADEON_IS_PCI)
1317 r100_pci_gart_disable(rdev);
1318 return 0;
1319}
1320
1321void r300_fini(struct radeon_device *rdev)
1322{
207bf9e9
JG		 1323 r100_cp_fini(rdev);
1324 r100_wb_fini(rdev);
1325 r100_ib_fini(rdev);
1326 radeon_gem_fini(rdev);
1327 if (rdev->flags & RADEON_IS_PCIE)
1328 rv370_pcie_gart_fini(rdev);
1329 if (rdev->flags & RADEON_IS_PCI)
1330 r100_pci_gart_fini(rdev);
d0269ed8 1331 radeon_agp_fini(rdev);
207bf9e9
JG		 1332 radeon_irq_kms_fini(rdev);
1333 radeon_fence_driver_fini(rdev);
4c788679 1334 radeon_bo_fini(rdev);
207bf9e9
JG		 1335 radeon_atombios_fini(rdev);
1336 kfree(rdev->bios);
1337 rdev->bios = NULL;
1338}
1339
1340int r300_init(struct radeon_device *rdev)
1341{
1342 int r;
1343
207bf9e9
JG		 1344 /* Disable VGA */
1345 r100_vga_render_disable(rdev);
1346 /* Initialize scratch registers */
1347 radeon_scratch_init(rdev);
1348 /* Initialize surface registers */
1349 radeon_surface_init(rdev);
1350 /* TODO: disable VGA need to use VGA request */
1351 /* BIOS*/
1352 if (!radeon_get_bios(rdev)) {
1353 if (ASIC_IS_AVIVO(rdev))
1354 return -EINVAL;
1355 }
1356 if (rdev->is_atom_bios) {
1357 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1358 return -EINVAL;
1359 } else {
1360 r = radeon_combios_init(rdev);
1361 if (r)
1362 return r;
1363 }
1364 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1365 if (radeon_gpu_reset(rdev)) {
1366 dev_warn(rdev->dev,
1367 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1368 RREG32(R_000E40_RBBM_STATUS),
1369 RREG32(R_0007C0_CP_STAT));
1370 }
1371 /* check if cards are posted or not */
72542d77
DA		 1372 if (radeon_boot_test_post_card(rdev) == false)
1373 return -EINVAL;
207bf9e9
JG		 1374 /* Set asic errata */
1375 r300_errata(rdev);
1376 /* Initialize clocks */
1377 radeon_get_clock_info(rdev->ddev);
6234077d
RM		 1378 /* Initialize power management */
1379 radeon_pm_init(rdev);
d594e46a
JG		 1380 /* initialize AGP */
1381 if (rdev->flags & RADEON_IS_AGP) {
1382 r = radeon_agp_init(rdev);
1383 if (r) {
1384 radeon_agp_disable(rdev);
1385 }
1386 }
1387 /* initialize memory controller */
1388 r300_mc_init(rdev);
207bf9e9
JG		 1389 /* Fence driver */
1390 r = radeon_fence_driver_init(rdev);
1391 if (r)
1392 return r;
1393 r = radeon_irq_kms_init(rdev);
1394 if (r)
1395 return r;
1396 /* Memory manager */
4c788679 1397 r = radeon_bo_init(rdev);
207bf9e9
JG		 1398 if (r)
1399 return r;
1400 if (rdev->flags & RADEON_IS_PCIE) {
1401 r = rv370_pcie_gart_init(rdev);
1402 if (r)
1403 return r;
1404 }
1405 if (rdev->flags & RADEON_IS_PCI) {
1406 r = r100_pci_gart_init(rdev);
1407 if (r)
1408 return r;
1409 }
1410 r300_set_reg_safe(rdev);
1411 rdev->accel_working = true;
1412 r = r300_startup(rdev);
1413 if (r) {
1414 /* Somethings want wront with the accel init stop accel */
1415 dev_err(rdev->dev, "Disabling GPU acceleration\n");
207bf9e9
JG		 1416 r100_cp_fini(rdev);
1417 r100_wb_fini(rdev);
1418 r100_ib_fini(rdev);
655efd3d 1419 radeon_irq_kms_fini(rdev);
207bf9e9
JG		 1420 if (rdev->flags & RADEON_IS_PCIE)
1421 rv370_pcie_gart_fini(rdev);
1422 if (rdev->flags & RADEON_IS_PCI)
1423 r100_pci_gart_fini(rdev);
655efd3d 1424 radeon_agp_fini(rdev);
207bf9e9
JG		 1425 rdev->accel_working = false;
1426 }
1427 return 0;
1428}
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