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[net-next-2.6.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
3ce0a23d 34#include "r100d.h"
d4550907
JG		 35#include "rs100d.h"
36#include "rv200d.h"
37#include "rv250d.h"
3ce0a23d 38
70967ab9
BH		 39#include <linux/firmware.h>
40#include <linux/platform_device.h>
41
551ebd83
DA		 42#include "r100_reg_safe.h"
43#include "rn50_reg_safe.h"
44
70967ab9
BH		 45/* Firmware Names */
46#define FIRMWARE_R100 "radeon/R100_cp.bin"
47#define FIRMWARE_R200 "radeon/R200_cp.bin"
48#define FIRMWARE_R300 "radeon/R300_cp.bin"
49#define FIRMWARE_R420 "radeon/R420_cp.bin"
50#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52#define FIRMWARE_R520 "radeon/R520_cp.bin"
53
54MODULE_FIRMWARE(FIRMWARE_R100);
55MODULE_FIRMWARE(FIRMWARE_R200);
56MODULE_FIRMWARE(FIRMWARE_R300);
57MODULE_FIRMWARE(FIRMWARE_R420);
58MODULE_FIRMWARE(FIRMWARE_RS690);
59MODULE_FIRMWARE(FIRMWARE_RS600);
60MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 61
551ebd83
DA		 62#include "r100_track.h"
63
771fe6b9
JG		 64/* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 66 */
771fe6b9 67
05a05c50
AD		 68/* hpd for digital panel detect/disconnect */
69bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
70{
71 bool connected = false;
72
73 switch (hpd) {
74 case RADEON_HPD_1:
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
76 connected = true;
77 break;
78 case RADEON_HPD_2:
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
80 connected = true;
81 break;
82 default:
83 break;
84 }
85 return connected;
86}
87
88void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
90{
91 u32 tmp;
92 bool connected = r100_hpd_sense(rdev, hpd);
93
94 switch (hpd) {
95 case RADEON_HPD_1:
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
97 if (connected)
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
99 else
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
102 break;
103 case RADEON_HPD_2:
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
105 if (connected)
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
107 else
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
110 break;
111 default:
112 break;
113 }
114}
115
116void r100_hpd_init(struct radeon_device *rdev)
117{
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
120
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
124 case RADEON_HPD_1:
125 rdev->irq.hpd[0] = true;
126 break;
127 case RADEON_HPD_2:
128 rdev->irq.hpd[1] = true;
129 break;
130 default:
131 break;
132 }
133 }
003e69f9
JG		 134 if (rdev->irq.installed)
135 r100_irq_set(rdev);
05a05c50
AD		 136}
137
138void r100_hpd_fini(struct radeon_device *rdev)
139{
140 struct drm_device *dev = rdev->ddev;
141 struct drm_connector *connector;
142
143 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
144 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
145 switch (radeon_connector->hpd.hpd) {
146 case RADEON_HPD_1:
147 rdev->irq.hpd[0] = false;
148 break;
149 case RADEON_HPD_2:
150 rdev->irq.hpd[1] = false;
151 break;
152 default:
153 break;
154 }
155 }
156}
157
771fe6b9
JG		 158/*
159 * PCI GART
160 */
161void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
162{
163 /* TODO: can we do somethings here ? */
164 /* It seems hw only cache one entry so we should discard this
165 * entry otherwise if first GPU GART read hit this entry it
166 * could end up in wrong address. */
167}
168
4aac0473 169int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 170{
771fe6b9
JG		 171 int r;
172
4aac0473
JG		 173 if (rdev->gart.table.ram.ptr) {
174 WARN(1, "R100 PCI GART already initialized.\n");
175 return 0;
176 }
771fe6b9
JG		 177 /* Initialize common gart structure */
178 r = radeon_gart_init(rdev);
4aac0473 179 if (r)
771fe6b9 180 return r;
4aac0473
JG		 181 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
182 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
183 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
184 return radeon_gart_table_ram_alloc(rdev);
185}
186
17e15b0c
DA		 187/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
188void r100_enable_bm(struct radeon_device *rdev)
189{
190 uint32_t tmp;
191 /* Enable bus mastering */
192 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
193 WREG32(RADEON_BUS_CNTL, tmp);
194}
195
4aac0473
JG		 196int r100_pci_gart_enable(struct radeon_device *rdev)
197{
198 uint32_t tmp;
199
82568565 200 radeon_gart_restore(rdev);
771fe6b9
JG		 201 /* discard memory request outside of configured range */
202 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
203 WREG32(RADEON_AIC_CNTL, tmp);
204 /* set address range for PCI address translate */
d594e46a
JG		 205 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
206 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 207 /* set PCI GART page-table base address */
208 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
209 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
210 WREG32(RADEON_AIC_CNTL, tmp);
211 r100_pci_gart_tlb_flush(rdev);
212 rdev->gart.ready = true;
213 return 0;
214}
215
216void r100_pci_gart_disable(struct radeon_device *rdev)
217{
218 uint32_t tmp;
219
220 /* discard memory request outside of configured range */
221 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
222 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
223 WREG32(RADEON_AIC_LO_ADDR, 0);
224 WREG32(RADEON_AIC_HI_ADDR, 0);
225}
226
227int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
228{
229 if (i < 0 || i > rdev->gart.num_gpu_pages) {
230 return -EINVAL;
231 }
ed10f95d 232 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 233 return 0;
234}
235
4aac0473 236void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 237{
4aac0473
JG		 238 r100_pci_gart_disable(rdev);
239 radeon_gart_table_ram_free(rdev);
240 radeon_gart_fini(rdev);
771fe6b9
JG		 241}
242
7ed220d7
MD		 243int r100_irq_set(struct radeon_device *rdev)
244{
245 uint32_t tmp = 0;
246
003e69f9
JG		 247 if (!rdev->irq.installed) {
248 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
249 WREG32(R_000040_GEN_INT_CNTL, 0);
250 return -EINVAL;
251 }
7ed220d7
MD		 252 if (rdev->irq.sw_int) {
253 tmp |= RADEON_SW_INT_ENABLE;
254 }
255 if (rdev->irq.crtc_vblank_int[0]) {
256 tmp |= RADEON_CRTC_VBLANK_MASK;
257 }
258 if (rdev->irq.crtc_vblank_int[1]) {
259 tmp |= RADEON_CRTC2_VBLANK_MASK;
260 }
05a05c50
AD		 261 if (rdev->irq.hpd[0]) {
262 tmp |= RADEON_FP_DETECT_MASK;
263 }
264 if (rdev->irq.hpd[1]) {
265 tmp |= RADEON_FP2_DETECT_MASK;
266 }
7ed220d7
MD		 267 WREG32(RADEON_GEN_INT_CNTL, tmp);
268 return 0;
269}
270
9f022ddf
JG		 271void r100_irq_disable(struct radeon_device *rdev)
272{
273 u32 tmp;
274
275 WREG32(R_000040_GEN_INT_CNTL, 0);
276 /* Wait and acknowledge irq */
277 mdelay(1);
278 tmp = RREG32(R_000044_GEN_INT_STATUS);
279 WREG32(R_000044_GEN_INT_STATUS, tmp);
280}
281
7ed220d7
MD		 282static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
283{
284 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 285 uint32_t irq_mask = RADEON_SW_INT_TEST |
286 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
287 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 288
289 if (irqs) {
290 WREG32(RADEON_GEN_INT_STATUS, irqs);
291 }
292 return irqs & irq_mask;
293}
294
295int r100_irq_process(struct radeon_device *rdev)
296{
3e5cb98d 297 uint32_t status, msi_rearm;
d4877cf2 298 bool queue_hotplug = false;
7ed220d7
MD		 299
300 status = r100_irq_ack(rdev);
301 if (!status) {
302 return IRQ_NONE;
303 }
a513c184
JG		 304 if (rdev->shutdown) {
305 return IRQ_NONE;
306 }
7ed220d7
MD		 307 while (status) {
308 /* SW interrupt */
309 if (status & RADEON_SW_INT_TEST) {
310 radeon_fence_process(rdev);
311 }
312 /* Vertical blank interrupts */
313 if (status & RADEON_CRTC_VBLANK_STAT) {
314 drm_handle_vblank(rdev->ddev, 0);
73a6d3fc 315 wake_up(&rdev->irq.vblank_queue);
7ed220d7
MD		 316 }
317 if (status & RADEON_CRTC2_VBLANK_STAT) {
318 drm_handle_vblank(rdev->ddev, 1);
73a6d3fc 319 wake_up(&rdev->irq.vblank_queue);
7ed220d7 320 }
05a05c50 321 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 322 queue_hotplug = true;
323 DRM_DEBUG("HPD1\n");
05a05c50
AD		 324 }
325 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 326 queue_hotplug = true;
327 DRM_DEBUG("HPD2\n");
05a05c50 328 }
7ed220d7
MD		 329 status = r100_irq_ack(rdev);
330 }
d4877cf2
AD		 331 if (queue_hotplug)
332 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 333 if (rdev->msi_enabled) {
334 switch (rdev->family) {
335 case CHIP_RS400:
336 case CHIP_RS480:
337 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
338 WREG32(RADEON_AIC_CNTL, msi_rearm);
339 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
340 break;
341 default:
342 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
343 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
344 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
345 break;
346 }
347 }
7ed220d7
MD		 348 return IRQ_HANDLED;
349}
350
351u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
352{
353 if (crtc == 0)
354 return RREG32(RADEON_CRTC_CRNT_FRAME);
355 else
356 return RREG32(RADEON_CRTC2_CRNT_FRAME);
357}
358
9e5b2af7
PN		 359/* Who ever call radeon_fence_emit should call ring_lock and ask
360 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 361void r100_fence_ring_emit(struct radeon_device *rdev,
362 struct radeon_fence *fence)
363{
9e5b2af7
PN		 364 /* We have to make sure that caches are flushed before
365 * CPU might read something from VRAM. */
366 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
367 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
368 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
369 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 370 /* Wait until IDLE & CLEAN */
4612dc97
AD		 371 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
372 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
cafe6609
JG		 373 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
374 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
375 RADEON_HDP_READ_BUFFER_INVALIDATE);
376 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
377 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 378 /* Emit fence sequence & fire IRQ */
379 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
380 radeon_ring_write(rdev, fence->seq);
381 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
382 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
383}
384
771fe6b9
JG		 385int r100_wb_init(struct radeon_device *rdev)
386{
387 int r;
388
389 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 390 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
391 RADEON_GEM_DOMAIN_GTT,
392 &rdev->wb.wb_obj);
771fe6b9 393 if (r) {
4c788679 394 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
771fe6b9
JG		 395 return r;
396 }
4c788679
JG		 397 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
398 if (unlikely(r != 0))
399 return r;
400 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
401 &rdev->wb.gpu_addr);
771fe6b9 402 if (r) {
4c788679
JG		 403 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
404 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9
JG		 405 return r;
406 }
4c788679
JG		 407 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
408 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9 409 if (r) {
4c788679 410 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
771fe6b9
JG		 411 return r;
412 }
413 }
9f022ddf
JG		 414 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
415 WREG32(R_00070C_CP_RB_RPTR_ADDR,
416 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
417 WREG32(R_000770_SCRATCH_UMSK, 0xff);
771fe6b9
JG		 418 return 0;
419}
420
9f022ddf
JG		 421void r100_wb_disable(struct radeon_device *rdev)
422{
423 WREG32(R_000770_SCRATCH_UMSK, 0);
424}
425
771fe6b9
JG		 426void r100_wb_fini(struct radeon_device *rdev)
427{
4c788679
JG		 428 int r;
429
9f022ddf 430 r100_wb_disable(rdev);
771fe6b9 431 if (rdev->wb.wb_obj) {
4c788679
JG		 432 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
433 if (unlikely(r != 0)) {
434 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
435 return;
436 }
437 radeon_bo_kunmap(rdev->wb.wb_obj);
438 radeon_bo_unpin(rdev->wb.wb_obj);
439 radeon_bo_unreserve(rdev->wb.wb_obj);
440 radeon_bo_unref(&rdev->wb.wb_obj);
771fe6b9
JG		 441 rdev->wb.wb = NULL;
442 rdev->wb.wb_obj = NULL;
443 }
444}
445
446int r100_copy_blit(struct radeon_device *rdev,
447 uint64_t src_offset,
448 uint64_t dst_offset,
449 unsigned num_pages,
450 struct radeon_fence *fence)
451{
452 uint32_t cur_pages;
453 uint32_t stride_bytes = PAGE_SIZE;
454 uint32_t pitch;
455 uint32_t stride_pixels;
456 unsigned ndw;
457 int num_loops;
458 int r = 0;
459
460 /* radeon limited to 16k stride */
461 stride_bytes &= 0x3fff;
462 /* radeon pitch is /64 */
463 pitch = stride_bytes / 64;
464 stride_pixels = stride_bytes / 4;
465 num_loops = DIV_ROUND_UP(num_pages, 8191);
466
467 /* Ask for enough room for blit + flush + fence */
468 ndw = 64 + (10 * num_loops);
469 r = radeon_ring_lock(rdev, ndw);
470 if (r) {
471 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
472 return -EINVAL;
473 }
474 while (num_pages > 0) {
475 cur_pages = num_pages;
476 if (cur_pages > 8191) {
477 cur_pages = 8191;
478 }
479 num_pages -= cur_pages;
480
481 /* pages are in Y direction - height
482 page width in X direction - width */
483 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
484 radeon_ring_write(rdev,
485 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
486 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
487 RADEON_GMC_SRC_CLIPPING |
488 RADEON_GMC_DST_CLIPPING |
489 RADEON_GMC_BRUSH_NONE |
490 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
491 RADEON_GMC_SRC_DATATYPE_COLOR |
492 RADEON_ROP3_S |
493 RADEON_DP_SRC_SOURCE_MEMORY |
494 RADEON_GMC_CLR_CMP_CNTL_DIS |
495 RADEON_GMC_WR_MSK_DIS);
496 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
497 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
498 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
499 radeon_ring_write(rdev, 0);
500 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
501 radeon_ring_write(rdev, num_pages);
502 radeon_ring_write(rdev, num_pages);
503 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
504 }
505 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
506 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
507 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
508 radeon_ring_write(rdev,
509 RADEON_WAIT_2D_IDLECLEAN |
510 RADEON_WAIT_HOST_IDLECLEAN |
511 RADEON_WAIT_DMA_GUI_IDLE);
512 if (fence) {
513 r = radeon_fence_emit(rdev, fence);
514 }
515 radeon_ring_unlock_commit(rdev);
516 return r;
517}
518
45600232
JG		 519static int r100_cp_wait_for_idle(struct radeon_device *rdev)
520{
521 unsigned i;
522 u32 tmp;
523
524 for (i = 0; i < rdev->usec_timeout; i++) {
525 tmp = RREG32(R_000E40_RBBM_STATUS);
526 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
527 return 0;
528 }
529 udelay(1);
530 }
531 return -1;
532}
533
771fe6b9
JG		 534void r100_ring_start(struct radeon_device *rdev)
535{
536 int r;
537
538 r = radeon_ring_lock(rdev, 2);
539 if (r) {
540 return;
541 }
542 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
543 radeon_ring_write(rdev,
544 RADEON_ISYNC_ANY2D_IDLE3D |
545 RADEON_ISYNC_ANY3D_IDLE2D |
546 RADEON_ISYNC_WAIT_IDLEGUI |
547 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
548 radeon_ring_unlock_commit(rdev);
549}
550
70967ab9
BH		 551
552/* Load the microcode for the CP */
553static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 554{
70967ab9
BH		 555 struct platform_device *pdev;
556 const char *fw_name = NULL;
557 int err;
771fe6b9 558
70967ab9 559 DRM_DEBUG("\n");
771fe6b9 560
70967ab9
BH		 561 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
562 err = IS_ERR(pdev);
563 if (err) {
564 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
565 return -EINVAL;
566 }
771fe6b9
JG		 567 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
568 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
569 (rdev->family == CHIP_RS200)) {
570 DRM_INFO("Loading R100 Microcode\n");
70967ab9 571 fw_name = FIRMWARE_R100;
771fe6b9
JG		 572 } else if ((rdev->family == CHIP_R200) ||
573 (rdev->family == CHIP_RV250) ||
574 (rdev->family == CHIP_RV280) ||
575 (rdev->family == CHIP_RS300)) {
576 DRM_INFO("Loading R200 Microcode\n");
70967ab9 577 fw_name = FIRMWARE_R200;
771fe6b9
JG		 578 } else if ((rdev->family == CHIP_R300) ||
579 (rdev->family == CHIP_R350) ||
580 (rdev->family == CHIP_RV350) ||
581 (rdev->family == CHIP_RV380) ||
582 (rdev->family == CHIP_RS400) ||
583 (rdev->family == CHIP_RS480)) {
584 DRM_INFO("Loading R300 Microcode\n");
70967ab9 585 fw_name = FIRMWARE_R300;
771fe6b9
JG		 586 } else if ((rdev->family == CHIP_R420) ||
587 (rdev->family == CHIP_R423) ||
588 (rdev->family == CHIP_RV410)) {
589 DRM_INFO("Loading R400 Microcode\n");
70967ab9 590 fw_name = FIRMWARE_R420;
771fe6b9
JG		 591 } else if ((rdev->family == CHIP_RS690) ||
592 (rdev->family == CHIP_RS740)) {
593 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 594 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 595 } else if (rdev->family == CHIP_RS600) {
596 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 597 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 598 } else if ((rdev->family == CHIP_RV515) ||
599 (rdev->family == CHIP_R520) ||
600 (rdev->family == CHIP_RV530) ||
601 (rdev->family == CHIP_R580) ||
602 (rdev->family == CHIP_RV560) ||
603 (rdev->family == CHIP_RV570)) {
604 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 605 fw_name = FIRMWARE_R520;
606 }
607
3ce0a23d 608 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 609 platform_device_unregister(pdev);
610 if (err) {
611 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
612 fw_name);
3ce0a23d 613 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 614 printk(KERN_ERR
615 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 616 rdev->me_fw->size, fw_name);
70967ab9 617 err = -EINVAL;
3ce0a23d
JG		 618 release_firmware(rdev->me_fw);
619 rdev->me_fw = NULL;
70967ab9
BH		 620 }
621 return err;
622}
d4550907 623
70967ab9
BH		 624static void r100_cp_load_microcode(struct radeon_device *rdev)
625{
626 const __be32 *fw_data;
627 int i, size;
628
629 if (r100_gui_wait_for_idle(rdev)) {
630 printk(KERN_WARNING "Failed to wait GUI idle while "
631 "programming pipes. Bad things might happen.\n");
632 }
633
3ce0a23d
JG		 634 if (rdev->me_fw) {
635 size = rdev->me_fw->size / 4;
636 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 637 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
638 for (i = 0; i < size; i += 2) {
639 WREG32(RADEON_CP_ME_RAM_DATAH,
640 be32_to_cpup(&fw_data[i]));
641 WREG32(RADEON_CP_ME_RAM_DATAL,
642 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 643 }
644 }
645}
646
647int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
648{
649 unsigned rb_bufsz;
650 unsigned rb_blksz;
651 unsigned max_fetch;
652 unsigned pre_write_timer;
653 unsigned pre_write_limit;
654 unsigned indirect2_start;
655 unsigned indirect1_start;
656 uint32_t tmp;
657 int r;
658
659 if (r100_debugfs_cp_init(rdev)) {
660 DRM_ERROR("Failed to register debugfs file for CP !\n");
661 }
662 /* Reset CP */
663 tmp = RREG32(RADEON_CP_CSQ_STAT);
664 if ((tmp & (1 << 31))) {
665 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
666 WREG32(RADEON_CP_CSQ_MODE, 0);
667 WREG32(RADEON_CP_CSQ_CNTL, 0);
668 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
669 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
670 mdelay(2);
671 WREG32(RADEON_RBBM_SOFT_RESET, 0);
672 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
673 mdelay(2);
674 tmp = RREG32(RADEON_CP_CSQ_STAT);
675 if ((tmp & (1 << 31))) {
676 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
677 }
678 } else {
679 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
680 }
70967ab9 681
3ce0a23d 682 if (!rdev->me_fw) {
70967ab9
BH		 683 r = r100_cp_init_microcode(rdev);
684 if (r) {
685 DRM_ERROR("Failed to load firmware!\n");
686 return r;
687 }
688 }
689
771fe6b9
JG		 690 /* Align ring size */
691 rb_bufsz = drm_order(ring_size / 8);
692 ring_size = (1 << (rb_bufsz + 1)) * 4;
693 r100_cp_load_microcode(rdev);
694 r = radeon_ring_init(rdev, ring_size);
695 if (r) {
696 return r;
697 }
698 /* Each time the cp read 1024 bytes (16 dword/quadword) update
699 * the rptr copy in system ram */
700 rb_blksz = 9;
701 /* cp will read 128bytes at a time (4 dwords) */
702 max_fetch = 1;
703 rdev->cp.align_mask = 16 - 1;
704 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
705 pre_write_timer = 64;
706 /* Force CP_RB_WPTR write if written more than one time before the
707 * delay expire
708 */
709 pre_write_limit = 0;
710 /* Setup the cp cache like this (cache size is 96 dwords) :
711 * RING 0 to 15
712 * INDIRECT1 16 to 79
713 * INDIRECT2 80 to 95
714 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
715 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
716 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
717 * Idea being that most of the gpu cmd will be through indirect1 buffer
718 * so it gets the bigger cache.
719 */
720 indirect2_start = 80;
721 indirect1_start = 16;
722 /* cp setup */
723 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 724 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9
JG		 725 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
726 REG_SET(RADEON_MAX_FETCH, max_fetch) |
727 RADEON_RB_NO_UPDATE);
d6f28938
AD		 728#ifdef __BIG_ENDIAN
729 tmp |= RADEON_BUF_SWAP_32BIT;
730#endif
731 WREG32(RADEON_CP_RB_CNTL, tmp);
732
771fe6b9
JG		 733 /* Set ring address */
734 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
735 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
736 /* Force read & write ptr to 0 */
771fe6b9
JG		 737 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
738 WREG32(RADEON_CP_RB_RPTR_WR, 0);
739 WREG32(RADEON_CP_RB_WPTR, 0);
740 WREG32(RADEON_CP_RB_CNTL, tmp);
741 udelay(10);
742 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
743 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
744 /* Set cp mode to bus mastering & enable cp*/
745 WREG32(RADEON_CP_CSQ_MODE,
746 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
747 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
748 WREG32(0x718, 0);
749 WREG32(0x744, 0x00004D4D);
750 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
751 radeon_ring_start(rdev);
752 r = radeon_ring_test(rdev);
753 if (r) {
754 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
755 return r;
756 }
757 rdev->cp.ready = true;
758 return 0;
759}
760
761void r100_cp_fini(struct radeon_device *rdev)
762{
45600232
JG		 763 if (r100_cp_wait_for_idle(rdev)) {
764 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
765 }
771fe6b9 766 /* Disable ring */
a18d7ea1 767 r100_cp_disable(rdev);
771fe6b9
JG		 768 radeon_ring_fini(rdev);
769 DRM_INFO("radeon: cp finalized\n");
770}
771
772void r100_cp_disable(struct radeon_device *rdev)
773{
774 /* Disable ring */
775 rdev->cp.ready = false;
776 WREG32(RADEON_CP_CSQ_MODE, 0);
777 WREG32(RADEON_CP_CSQ_CNTL, 0);
778 if (r100_gui_wait_for_idle(rdev)) {
779 printk(KERN_WARNING "Failed to wait GUI idle while "
780 "programming pipes. Bad things might happen.\n");
781 }
782}
783
784int r100_cp_reset(struct radeon_device *rdev)
785{
786 uint32_t tmp;
787 bool reinit_cp;
788 int i;
789
790 reinit_cp = rdev->cp.ready;
791 rdev->cp.ready = false;
792 WREG32(RADEON_CP_CSQ_MODE, 0);
793 WREG32(RADEON_CP_CSQ_CNTL, 0);
794 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
795 (void)RREG32(RADEON_RBBM_SOFT_RESET);
796 udelay(200);
797 WREG32(RADEON_RBBM_SOFT_RESET, 0);
798 /* Wait to prevent race in RBBM_STATUS */
799 mdelay(1);
800 for (i = 0; i < rdev->usec_timeout; i++) {
801 tmp = RREG32(RADEON_RBBM_STATUS);
802 if (!(tmp & (1 << 16))) {
803 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
804 tmp);
805 if (reinit_cp) {
806 return r100_cp_init(rdev, rdev->cp.ring_size);
807 }
808 return 0;
809 }
810 DRM_UDELAY(1);
811 }
812 tmp = RREG32(RADEON_RBBM_STATUS);
813 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
814 return -1;
815}
816
3ce0a23d
JG		 817void r100_cp_commit(struct radeon_device *rdev)
818{
819 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
820 (void)RREG32(RADEON_CP_RB_WPTR);
821}
822
771fe6b9
JG		 823
824/*
825 * CS functions
826 */
827int r100_cs_parse_packet0(struct radeon_cs_parser *p,
828 struct radeon_cs_packet *pkt,
068a117c 829 const unsigned *auth, unsigned n,
771fe6b9
JG		 830 radeon_packet0_check_t check)
831{
832 unsigned reg;
833 unsigned i, j, m;
834 unsigned idx;
835 int r;
836
837 idx = pkt->idx + 1;
838 reg = pkt->reg;
068a117c
JG		 839 /* Check that register fall into register range
840 * determined by the number of entry (n) in the
841 * safe register bitmap.
842 */
771fe6b9
JG		 843 if (pkt->one_reg_wr) {
844 if ((reg >> 7) > n) {
845 return -EINVAL;
846 }
847 } else {
848 if (((reg + (pkt->count << 2)) >> 7) > n) {
849 return -EINVAL;
850 }
851 }
852 for (i = 0; i <= pkt->count; i++, idx++) {
853 j = (reg >> 7);
854 m = 1 << ((reg >> 2) & 31);
855 if (auth[j] & m) {
856 r = check(p, pkt, idx, reg);
857 if (r) {
858 return r;
859 }
860 }
861 if (pkt->one_reg_wr) {
862 if (!(auth[j] & m)) {
863 break;
864 }
865 } else {
866 reg += 4;
867 }
868 }
869 return 0;
870}
871
771fe6b9
JG		 872void r100_cs_dump_packet(struct radeon_cs_parser *p,
873 struct radeon_cs_packet *pkt)
874{
771fe6b9
JG		 875 volatile uint32_t *ib;
876 unsigned i;
877 unsigned idx;
878
879 ib = p->ib->ptr;
771fe6b9
JG		 880 idx = pkt->idx;
881 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
882 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
883 }
884}
885
886/**
887 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
888 * @parser: parser structure holding parsing context.
889 * @pkt: where to store packet informations
890 *
891 * Assume that chunk_ib_index is properly set. Will return -EINVAL
892 * if packet is bigger than remaining ib size. or if packets is unknown.
893 **/
894int r100_cs_packet_parse(struct radeon_cs_parser *p,
895 struct radeon_cs_packet *pkt,
896 unsigned idx)
897{
898 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 899 uint32_t header;
771fe6b9
JG		 900
901 if (idx >= ib_chunk->length_dw) {
902 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
903 idx, ib_chunk->length_dw);
904 return -EINVAL;
905 }
513bcb46 906 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 907 pkt->idx = idx;
908 pkt->type = CP_PACKET_GET_TYPE(header);
909 pkt->count = CP_PACKET_GET_COUNT(header);
910 switch (pkt->type) {
911 case PACKET_TYPE0:
912 pkt->reg = CP_PACKET0_GET_REG(header);
913 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
914 break;
915 case PACKET_TYPE3:
916 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
917 break;
918 case PACKET_TYPE2:
919 pkt->count = -1;
920 break;
921 default:
922 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
923 return -EINVAL;
924 }
925 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
926 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
927 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
928 return -EINVAL;
929 }
930 return 0;
931}
932
531369e6
DA		 933/**
934 * r100_cs_packet_next_vline() - parse userspace VLINE packet
935 * @parser: parser structure holding parsing context.
936 *
937 * Userspace sends a special sequence for VLINE waits.
938 * PACKET0 - VLINE_START_END + value
939 * PACKET0 - WAIT_UNTIL +_value
940 * RELOC (P3) - crtc_id in reloc.
941 *
942 * This function parses this and relocates the VLINE START END
943 * and WAIT UNTIL packets to the correct crtc.
944 * It also detects a switched off crtc and nulls out the
945 * wait in that case.
946 */
947int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
948{
531369e6
DA		 949 struct drm_mode_object *obj;
950 struct drm_crtc *crtc;
951 struct radeon_crtc *radeon_crtc;
952 struct radeon_cs_packet p3reloc, waitreloc;
953 int crtc_id;
954 int r;
955 uint32_t header, h_idx, reg;
513bcb46 956 volatile uint32_t *ib;
531369e6 957
513bcb46 958 ib = p->ib->ptr;
531369e6
DA		 959
960 /* parse the wait until */
961 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
962 if (r)
963 return r;
964
965 /* check its a wait until and only 1 count */
966 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
967 waitreloc.count != 0) {
968 DRM_ERROR("vline wait had illegal wait until segment\n");
969 r = -EINVAL;
970 return r;
971 }
972
513bcb46 973 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 974 DRM_ERROR("vline wait had illegal wait until\n");
975 r = -EINVAL;
976 return r;
977 }
978
979 /* jump over the NOP */
90ebd065 980 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 981 if (r)
982 return r;
983
984 h_idx = p->idx - 2;
90ebd065
AD		 985 p->idx += waitreloc.count + 2;
986 p->idx += p3reloc.count + 2;
531369e6 987
513bcb46
DA		 988 header = radeon_get_ib_value(p, h_idx);
989 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 990 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 991 mutex_lock(&p->rdev->ddev->mode_config.mutex);
992 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
993 if (!obj) {
994 DRM_ERROR("cannot find crtc %d\n", crtc_id);
995 r = -EINVAL;
996 goto out;
997 }
998 crtc = obj_to_crtc(obj);
999 radeon_crtc = to_radeon_crtc(crtc);
1000 crtc_id = radeon_crtc->crtc_id;
1001
1002 if (!crtc->enabled) {
1003 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1004 ib[h_idx + 2] = PACKET2(0);
1005 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1006 } else if (crtc_id == 1) {
1007 switch (reg) {
1008 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1009 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1010 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1011 break;
1012 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1013 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1014 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1015 break;
1016 default:
1017 DRM_ERROR("unknown crtc reloc\n");
1018 r = -EINVAL;
1019 goto out;
1020 }
513bcb46
DA		 1021 ib[h_idx] = header;
1022 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1023 }
1024out:
1025 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1026 return r;
1027}
1028
771fe6b9
JG		 1029/**
1030 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1031 * @parser: parser structure holding parsing context.
1032 * @data: pointer to relocation data
1033 * @offset_start: starting offset
1034 * @offset_mask: offset mask (to align start offset on)
1035 * @reloc: reloc informations
1036 *
1037 * Check next packet is relocation packet3, do bo validation and compute
1038 * GPU offset using the provided start.
1039 **/
1040int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1041 struct radeon_cs_reloc **cs_reloc)
1042{
771fe6b9
JG		 1043 struct radeon_cs_chunk *relocs_chunk;
1044 struct radeon_cs_packet p3reloc;
1045 unsigned idx;
1046 int r;
1047
1048 if (p->chunk_relocs_idx == -1) {
1049 DRM_ERROR("No relocation chunk !\n");
1050 return -EINVAL;
1051 }
1052 *cs_reloc = NULL;
771fe6b9
JG		 1053 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1054 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1055 if (r) {
1056 return r;
1057 }
1058 p->idx += p3reloc.count + 2;
1059 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1060 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1061 p3reloc.idx);
1062 r100_cs_dump_packet(p, &p3reloc);
1063 return -EINVAL;
1064 }
513bcb46 1065 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1066 if (idx >= relocs_chunk->length_dw) {
1067 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1068 idx, relocs_chunk->length_dw);
1069 r100_cs_dump_packet(p, &p3reloc);
1070 return -EINVAL;
1071 }
1072 /* FIXME: we assume reloc size is 4 dwords */
1073 *cs_reloc = p->relocs_ptr[(idx / 4)];
1074 return 0;
1075}
1076
551ebd83
DA		 1077static int r100_get_vtx_size(uint32_t vtx_fmt)
1078{
1079 int vtx_size;
1080 vtx_size = 2;
1081 /* ordered according to bits in spec */
1082 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1083 vtx_size++;
1084 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1085 vtx_size += 3;
1086 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1087 vtx_size++;
1088 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1089 vtx_size++;
1090 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1091 vtx_size += 3;
1092 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1093 vtx_size++;
1094 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1095 vtx_size++;
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1097 vtx_size += 2;
1098 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1099 vtx_size += 2;
1100 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1101 vtx_size++;
1102 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1103 vtx_size += 2;
1104 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1105 vtx_size++;
1106 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1107 vtx_size += 2;
1108 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1109 vtx_size++;
1110 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1111 vtx_size++;
1112 /* blend weight */
1113 if (vtx_fmt & (0x7 << 15))
1114 vtx_size += (vtx_fmt >> 15) & 0x7;
1115 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1116 vtx_size += 3;
1117 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1118 vtx_size += 2;
1119 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1120 vtx_size++;
1121 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1122 vtx_size++;
1123 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1124 vtx_size++;
1125 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1126 vtx_size++;
1127 return vtx_size;
1128}
1129
771fe6b9 1130static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1131 struct radeon_cs_packet *pkt,
1132 unsigned idx, unsigned reg)
771fe6b9 1133{
771fe6b9 1134 struct radeon_cs_reloc *reloc;
551ebd83 1135 struct r100_cs_track *track;
771fe6b9
JG		 1136 volatile uint32_t *ib;
1137 uint32_t tmp;
771fe6b9 1138 int r;
551ebd83 1139 int i, face;
e024e110 1140 u32 tile_flags = 0;
513bcb46 1141 u32 idx_value;
771fe6b9
JG		 1142
1143 ib = p->ib->ptr;
551ebd83
DA		 1144 track = (struct r100_cs_track *)p->track;
1145
513bcb46
DA		 1146 idx_value = radeon_get_ib_value(p, idx);
1147
551ebd83
DA		 1148 switch (reg) {
1149 case RADEON_CRTC_GUI_TRIG_VLINE:
1150 r = r100_cs_packet_parse_vline(p);
1151 if (r) {
1152 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1153 idx, reg);
1154 r100_cs_dump_packet(p, pkt);
1155 return r;
1156 }
1157 break;
771fe6b9
JG		 1158 /* FIXME: only allow PACKET3 blit? easier to check for out of
1159 * range access */
551ebd83
DA		 1160 case RADEON_DST_PITCH_OFFSET:
1161 case RADEON_SRC_PITCH_OFFSET:
1162 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1163 if (r)
1164 return r;
1165 break;
1166 case RADEON_RB3D_DEPTHOFFSET:
1167 r = r100_cs_packet_next_reloc(p, &reloc);
1168 if (r) {
1169 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1170 idx, reg);
1171 r100_cs_dump_packet(p, pkt);
1172 return r;
1173 }
1174 track->zb.robj = reloc->robj;
513bcb46
DA		 1175 track->zb.offset = idx_value;
1176 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1177 break;
1178 case RADEON_RB3D_COLOROFFSET:
1179 r = r100_cs_packet_next_reloc(p, &reloc);
1180 if (r) {
1181 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1182 idx, reg);
1183 r100_cs_dump_packet(p, pkt);
1184 return r;
1185 }
1186 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1187 track->cb[0].offset = idx_value;
1188 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1189 break;
1190 case RADEON_PP_TXOFFSET_0:
1191 case RADEON_PP_TXOFFSET_1:
1192 case RADEON_PP_TXOFFSET_2:
1193 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1194 r = r100_cs_packet_next_reloc(p, &reloc);
1195 if (r) {
1196 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1197 idx, reg);
1198 r100_cs_dump_packet(p, pkt);
1199 return r;
1200 }
513bcb46 1201 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1202 track->textures[i].robj = reloc->robj;
1203 break;
1204 case RADEON_PP_CUBIC_OFFSET_T0_0:
1205 case RADEON_PP_CUBIC_OFFSET_T0_1:
1206 case RADEON_PP_CUBIC_OFFSET_T0_2:
1207 case RADEON_PP_CUBIC_OFFSET_T0_3:
1208 case RADEON_PP_CUBIC_OFFSET_T0_4:
1209 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1210 r = r100_cs_packet_next_reloc(p, &reloc);
1211 if (r) {
1212 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1213 idx, reg);
1214 r100_cs_dump_packet(p, pkt);
1215 return r;
1216 }
513bcb46
DA		 1217 track->textures[0].cube_info[i].offset = idx_value;
1218 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1219 track->textures[0].cube_info[i].robj = reloc->robj;
1220 break;
1221 case RADEON_PP_CUBIC_OFFSET_T1_0:
1222 case RADEON_PP_CUBIC_OFFSET_T1_1:
1223 case RADEON_PP_CUBIC_OFFSET_T1_2:
1224 case RADEON_PP_CUBIC_OFFSET_T1_3:
1225 case RADEON_PP_CUBIC_OFFSET_T1_4:
1226 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1227 r = r100_cs_packet_next_reloc(p, &reloc);
1228 if (r) {
1229 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1230 idx, reg);
1231 r100_cs_dump_packet(p, pkt);
1232 return r;
1233 }
513bcb46
DA		 1234 track->textures[1].cube_info[i].offset = idx_value;
1235 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1236 track->textures[1].cube_info[i].robj = reloc->robj;
1237 break;
1238 case RADEON_PP_CUBIC_OFFSET_T2_0:
1239 case RADEON_PP_CUBIC_OFFSET_T2_1:
1240 case RADEON_PP_CUBIC_OFFSET_T2_2:
1241 case RADEON_PP_CUBIC_OFFSET_T2_3:
1242 case RADEON_PP_CUBIC_OFFSET_T2_4:
1243 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1244 r = r100_cs_packet_next_reloc(p, &reloc);
1245 if (r) {
1246 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1247 idx, reg);
1248 r100_cs_dump_packet(p, pkt);
1249 return r;
1250 }
513bcb46
DA		 1251 track->textures[2].cube_info[i].offset = idx_value;
1252 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1253 track->textures[2].cube_info[i].robj = reloc->robj;
1254 break;
1255 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1256 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1257 break;
1258 case RADEON_RB3D_COLORPITCH:
1259 r = r100_cs_packet_next_reloc(p, &reloc);
1260 if (r) {
1261 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1262 idx, reg);
1263 r100_cs_dump_packet(p, pkt);
1264 return r;
1265 }
e024e110 1266
551ebd83
DA		 1267 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1268 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1269 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1270 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1271
513bcb46 1272 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1273 tmp |= tile_flags;
1274 ib[idx] = tmp;
e024e110 1275
513bcb46 1276 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1277 break;
1278 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1279 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1280 break;
1281 case RADEON_RB3D_CNTL:
513bcb46 1282 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1283 case 7:
1284 case 8:
1285 case 9:
1286 case 11:
1287 case 12:
1288 track->cb[0].cpp = 1;
e024e110 1289 break;
551ebd83
DA		 1290 case 3:
1291 case 4:
1292 case 15:
1293 track->cb[0].cpp = 2;
1294 break;
1295 case 6:
1296 track->cb[0].cpp = 4;
1297 break;
1298 default:
1299 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1300 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1301 return -EINVAL;
1302 }
513bcb46 1303 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1304 break;
1305 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1306 switch (idx_value & 0xf) {
551ebd83
DA		 1307 case 0:
1308 track->zb.cpp = 2;
1309 break;
1310 case 2:
1311 case 3:
1312 case 4:
1313 case 5:
1314 case 9:
1315 case 11:
1316 track->zb.cpp = 4;
17782d99 1317 break;
771fe6b9 1318 default:
771fe6b9
JG		 1319 break;
1320 }
551ebd83
DA		 1321 break;
1322 case RADEON_RB3D_ZPASS_ADDR:
1323 r = r100_cs_packet_next_reloc(p, &reloc);
1324 if (r) {
1325 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1326 idx, reg);
1327 r100_cs_dump_packet(p, pkt);
1328 return r;
1329 }
513bcb46 1330 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1331 break;
1332 case RADEON_PP_CNTL:
1333 {
513bcb46 1334 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1335 for (i = 0; i < track->num_texture; i++)
1336 track->textures[i].enabled = !!(temp & (1 << i));
1337 }
1338 break;
1339 case RADEON_SE_VF_CNTL:
513bcb46 1340 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1341 break;
1342 case RADEON_SE_VTX_FMT:
513bcb46 1343 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1344 break;
1345 case RADEON_PP_TEX_SIZE_0:
1346 case RADEON_PP_TEX_SIZE_1:
1347 case RADEON_PP_TEX_SIZE_2:
1348 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1349 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1350 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1351 break;
1352 case RADEON_PP_TEX_PITCH_0:
1353 case RADEON_PP_TEX_PITCH_1:
1354 case RADEON_PP_TEX_PITCH_2:
1355 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1356 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1357 break;
1358 case RADEON_PP_TXFILTER_0:
1359 case RADEON_PP_TXFILTER_1:
1360 case RADEON_PP_TXFILTER_2:
1361 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1362 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1363 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1364 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1365 if (tmp == 2 || tmp == 6)
1366 track->textures[i].roundup_w = false;
513bcb46 1367 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1368 if (tmp == 2 || tmp == 6)
1369 track->textures[i].roundup_h = false;
1370 break;
1371 case RADEON_PP_TXFORMAT_0:
1372 case RADEON_PP_TXFORMAT_1:
1373 case RADEON_PP_TXFORMAT_2:
1374 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1375 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1376 track->textures[i].use_pitch = 1;
1377 } else {
1378 track->textures[i].use_pitch = 0;
513bcb46
DA		 1379 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1380 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1381 }
513bcb46 1382 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1383 track->textures[i].tex_coord_type = 2;
513bcb46 1384 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1385 case RADEON_TXFORMAT_I8:
1386 case RADEON_TXFORMAT_RGB332:
1387 case RADEON_TXFORMAT_Y8:
1388 track->textures[i].cpp = 1;
1389 break;
1390 case RADEON_TXFORMAT_AI88:
1391 case RADEON_TXFORMAT_ARGB1555:
1392 case RADEON_TXFORMAT_RGB565:
1393 case RADEON_TXFORMAT_ARGB4444:
1394 case RADEON_TXFORMAT_VYUY422:
1395 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1396 case RADEON_TXFORMAT_SHADOW16:
1397 case RADEON_TXFORMAT_LDUDV655:
1398 case RADEON_TXFORMAT_DUDV88:
1399 track->textures[i].cpp = 2;
771fe6b9 1400 break;
551ebd83
DA		 1401 case RADEON_TXFORMAT_ARGB8888:
1402 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1403 case RADEON_TXFORMAT_SHADOW32:
1404 case RADEON_TXFORMAT_LDUDUV8888:
1405 track->textures[i].cpp = 4;
1406 break;
d785d78b
DA		 1407 case RADEON_TXFORMAT_DXT1:
1408 track->textures[i].cpp = 1;
1409 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1410 break;
1411 case RADEON_TXFORMAT_DXT23:
1412 case RADEON_TXFORMAT_DXT45:
1413 track->textures[i].cpp = 1;
1414 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1415 break;
551ebd83 1416 }
513bcb46
DA		 1417 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1418 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1419 break;
1420 case RADEON_PP_CUBIC_FACES_0:
1421 case RADEON_PP_CUBIC_FACES_1:
1422 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1423 tmp = idx_value;
551ebd83
DA		 1424 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1425 for (face = 0; face < 4; face++) {
1426 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1427 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1428 }
551ebd83
DA		 1429 break;
1430 default:
1431 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1432 reg, idx);
1433 return -EINVAL;
771fe6b9
JG		 1434 }
1435 return 0;
1436}
1437
068a117c
JG		 1438int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1439 struct radeon_cs_packet *pkt,
4c788679 1440 struct radeon_bo *robj)
068a117c 1441{
068a117c 1442 unsigned idx;
513bcb46 1443 u32 value;
068a117c 1444 idx = pkt->idx + 1;
513bcb46 1445 value = radeon_get_ib_value(p, idx + 2);
4c788679 1446 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1447 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1448 "(need %u have %lu) !\n",
513bcb46 1449 value + 1,
4c788679 1450 radeon_bo_size(robj));
068a117c
JG		 1451 return -EINVAL;
1452 }
1453 return 0;
1454}
1455
771fe6b9
JG		 1456static int r100_packet3_check(struct radeon_cs_parser *p,
1457 struct radeon_cs_packet *pkt)
1458{
771fe6b9 1459 struct radeon_cs_reloc *reloc;
551ebd83 1460 struct r100_cs_track *track;
771fe6b9 1461 unsigned idx;
771fe6b9
JG		 1462 volatile uint32_t *ib;
1463 int r;
1464
1465 ib = p->ib->ptr;
771fe6b9 1466 idx = pkt->idx + 1;
551ebd83 1467 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1468 switch (pkt->opcode) {
1469 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1470 r = r100_packet3_load_vbpntr(p, pkt, idx);
1471 if (r)
1472 return r;
771fe6b9
JG		 1473 break;
1474 case PACKET3_INDX_BUFFER:
1475 r = r100_cs_packet_next_reloc(p, &reloc);
1476 if (r) {
1477 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1478 r100_cs_dump_packet(p, pkt);
1479 return r;
1480 }
513bcb46 1481 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1482 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1483 if (r) {
1484 return r;
1485 }
771fe6b9
JG		 1486 break;
1487 case 0x23:
771fe6b9
JG		 1488 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1489 r = r100_cs_packet_next_reloc(p, &reloc);
1490 if (r) {
1491 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1492 r100_cs_dump_packet(p, pkt);
1493 return r;
1494 }
513bcb46 1495 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1496 track->num_arrays = 1;
513bcb46 1497 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1498
1499 track->arrays[0].robj = reloc->robj;
1500 track->arrays[0].esize = track->vtx_size;
1501
513bcb46 1502 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1503
513bcb46 1504 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1505 track->immd_dwords = pkt->count - 1;
1506 r = r100_cs_track_check(p->rdev, track);
1507 if (r)
1508 return r;
771fe6b9
JG		 1509 break;
1510 case PACKET3_3D_DRAW_IMMD:
513bcb46 1511 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1512 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1513 return -EINVAL;
1514 }
cf57fc7a 1515 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1516 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1517 track->immd_dwords = pkt->count - 1;
1518 r = r100_cs_track_check(p->rdev, track);
1519 if (r)
1520 return r;
1521 break;
771fe6b9
JG		 1522 /* triggers drawing using in-packet vertex data */
1523 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1524 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1525 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1526 return -EINVAL;
1527 }
513bcb46 1528 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1529 track->immd_dwords = pkt->count;
1530 r = r100_cs_track_check(p->rdev, track);
1531 if (r)
1532 return r;
1533 break;
771fe6b9
JG		 1534 /* triggers drawing using in-packet vertex data */
1535 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1536 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1537 r = r100_cs_track_check(p->rdev, track);
1538 if (r)
1539 return r;
1540 break;
771fe6b9
JG		 1541 /* triggers drawing of vertex buffers setup elsewhere */
1542 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1543 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1544 r = r100_cs_track_check(p->rdev, track);
1545 if (r)
1546 return r;
1547 break;
771fe6b9
JG		 1548 /* triggers drawing using indices to vertex buffer */
1549 case PACKET3_3D_DRAW_VBUF:
513bcb46 1550 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1551 r = r100_cs_track_check(p->rdev, track);
1552 if (r)
1553 return r;
1554 break;
771fe6b9
JG		 1555 /* triggers drawing of vertex buffers setup elsewhere */
1556 case PACKET3_3D_DRAW_INDX:
513bcb46 1557 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1558 r = r100_cs_track_check(p->rdev, track);
1559 if (r)
1560 return r;
1561 break;
771fe6b9
JG		 1562 /* triggers drawing using indices to vertex buffer */
1563 case PACKET3_NOP:
1564 break;
1565 default:
1566 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1567 return -EINVAL;
1568 }
1569 return 0;
1570}
1571
1572int r100_cs_parse(struct radeon_cs_parser *p)
1573{
1574 struct radeon_cs_packet pkt;
9f022ddf 1575 struct r100_cs_track *track;
771fe6b9
JG		 1576 int r;
1577
9f022ddf
JG		 1578 track = kzalloc(sizeof(*track), GFP_KERNEL);
1579 r100_cs_track_clear(p->rdev, track);
1580 p->track = track;
771fe6b9
JG		 1581 do {
1582 r = r100_cs_packet_parse(p, &pkt, p->idx);
1583 if (r) {
1584 return r;
1585 }
1586 p->idx += pkt.count + 2;
1587 switch (pkt.type) {
068a117c 1588 case PACKET_TYPE0:
551ebd83
DA		 1589 if (p->rdev->family >= CHIP_R200)
1590 r = r100_cs_parse_packet0(p, &pkt,
1591 p->rdev->config.r100.reg_safe_bm,
1592 p->rdev->config.r100.reg_safe_bm_size,
1593 &r200_packet0_check);
1594 else
1595 r = r100_cs_parse_packet0(p, &pkt,
1596 p->rdev->config.r100.reg_safe_bm,
1597 p->rdev->config.r100.reg_safe_bm_size,
1598 &r100_packet0_check);
068a117c
JG		 1599 break;
1600 case PACKET_TYPE2:
1601 break;
1602 case PACKET_TYPE3:
1603 r = r100_packet3_check(p, &pkt);
1604 break;
1605 default:
1606 DRM_ERROR("Unknown packet type %d !\n",
1607 pkt.type);
1608 return -EINVAL;
771fe6b9
JG		 1609 }
1610 if (r) {
1611 return r;
1612 }
1613 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1614 return 0;
1615}
1616
1617
1618/*
1619 * Global GPU functions
1620 */
1621void r100_errata(struct radeon_device *rdev)
1622{
1623 rdev->pll_errata = 0;
1624
1625 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1626 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1627 }
1628
1629 if (rdev->family == CHIP_RV100 ||
1630 rdev->family == CHIP_RS100 ||
1631 rdev->family == CHIP_RS200) {
1632 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1633 }
1634}
1635
1636/* Wait for vertical sync on primary CRTC */
1637void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1638{
1639 uint32_t crtc_gen_cntl, tmp;
1640 int i;
1641
1642 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1643 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1644 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1645 return;
1646 }
1647 /* Clear the CRTC_VBLANK_SAVE bit */
1648 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1649 for (i = 0; i < rdev->usec_timeout; i++) {
1650 tmp = RREG32(RADEON_CRTC_STATUS);
1651 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1652 return;
1653 }
1654 DRM_UDELAY(1);
1655 }
1656}
1657
1658/* Wait for vertical sync on secondary CRTC */
1659void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1660{
1661 uint32_t crtc2_gen_cntl, tmp;
1662 int i;
1663
1664 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1665 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1666 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1667 return;
1668
1669 /* Clear the CRTC_VBLANK_SAVE bit */
1670 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1671 for (i = 0; i < rdev->usec_timeout; i++) {
1672 tmp = RREG32(RADEON_CRTC2_STATUS);
1673 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1674 return;
1675 }
1676 DRM_UDELAY(1);
1677 }
1678}
1679
1680int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1681{
1682 unsigned i;
1683 uint32_t tmp;
1684
1685 for (i = 0; i < rdev->usec_timeout; i++) {
1686 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1687 if (tmp >= n) {
1688 return 0;
1689 }
1690 DRM_UDELAY(1);
1691 }
1692 return -1;
1693}
1694
1695int r100_gui_wait_for_idle(struct radeon_device *rdev)
1696{
1697 unsigned i;
1698 uint32_t tmp;
1699
1700 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1701 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1702 " Bad things might happen.\n");
1703 }
1704 for (i = 0; i < rdev->usec_timeout; i++) {
1705 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 1706 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 1707 return 0;
1708 }
1709 DRM_UDELAY(1);
1710 }
1711 return -1;
1712}
1713
1714int r100_mc_wait_for_idle(struct radeon_device *rdev)
1715{
1716 unsigned i;
1717 uint32_t tmp;
1718
1719 for (i = 0; i < rdev->usec_timeout; i++) {
1720 /* read MC_STATUS */
4612dc97
AD		 1721 tmp = RREG32(RADEON_MC_STATUS);
1722 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 1723 return 0;
1724 }
1725 DRM_UDELAY(1);
1726 }
1727 return -1;
1728}
1729
1730void r100_gpu_init(struct radeon_device *rdev)
1731{
1732 /* TODO: anythings to do here ? pipes ? */
1733 r100_hdp_reset(rdev);
1734}
1735
1736void r100_hdp_reset(struct radeon_device *rdev)
1737{
1738 uint32_t tmp;
1739
1740 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1741 tmp |= (7 << 28);
1742 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1743 (void)RREG32(RADEON_HOST_PATH_CNTL);
1744 udelay(200);
1745 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1746 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1747 (void)RREG32(RADEON_HOST_PATH_CNTL);
1748}
1749
1750int r100_rb2d_reset(struct radeon_device *rdev)
1751{
1752 uint32_t tmp;
1753 int i;
1754
1755 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1756 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1757 udelay(200);
1758 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1759 /* Wait to prevent race in RBBM_STATUS */
1760 mdelay(1);
1761 for (i = 0; i < rdev->usec_timeout; i++) {
1762 tmp = RREG32(RADEON_RBBM_STATUS);
1763 if (!(tmp & (1 << 26))) {
1764 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1765 tmp);
1766 return 0;
1767 }
1768 DRM_UDELAY(1);
1769 }
1770 tmp = RREG32(RADEON_RBBM_STATUS);
1771 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1772 return -1;
1773}
1774
1775int r100_gpu_reset(struct radeon_device *rdev)
1776{
1777 uint32_t status;
1778
1779 /* reset order likely matter */
1780 status = RREG32(RADEON_RBBM_STATUS);
1781 /* reset HDP */
1782 r100_hdp_reset(rdev);
1783 /* reset rb2d */
1784 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1785 r100_rb2d_reset(rdev);
1786 }
1787 /* TODO: reset 3D engine */
1788 /* reset CP */
1789 status = RREG32(RADEON_RBBM_STATUS);
1790 if (status & (1 << 16)) {
1791 r100_cp_reset(rdev);
1792 }
1793 /* Check if GPU is idle */
1794 status = RREG32(RADEON_RBBM_STATUS);
4612dc97 1795 if (status & RADEON_RBBM_ACTIVE) {
771fe6b9
JG		 1796 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1797 return -1;
1798 }
1799 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1800 return 0;
1801}
1802
92cde00c
AD		 1803void r100_set_common_regs(struct radeon_device *rdev)
1804{
2739d49c
AD		 1805 struct drm_device *dev = rdev->ddev;
1806 bool force_dac2 = false;
1807
92cde00c
AD		 1808 /* set these so they don't interfere with anything */
1809 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1810 WREG32(RADEON_SUBPIC_CNTL, 0);
1811 WREG32(RADEON_VIPH_CONTROL, 0);
1812 WREG32(RADEON_I2C_CNTL_1, 0);
1813 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1814 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1815 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 1816
1817 /* always set up dac2 on rn50 and some rv100 as lots
1818 * of servers seem to wire it up to a VGA port but
1819 * don't report it in the bios connector
1820 * table.
1821 */
1822 switch (dev->pdev->device) {
1823 /* RN50 */
1824 case 0x515e:
1825 case 0x5969:
1826 force_dac2 = true;
1827 break;
1828 /* RV100*/
1829 case 0x5159:
1830 case 0x515a:
1831 /* DELL triple head servers */
1832 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1833 ((dev->pdev->subsystem_device == 0x016c) ||
1834 (dev->pdev->subsystem_device == 0x016d) ||
1835 (dev->pdev->subsystem_device == 0x016e) ||
1836 (dev->pdev->subsystem_device == 0x016f) ||
1837 (dev->pdev->subsystem_device == 0x0170) ||
1838 (dev->pdev->subsystem_device == 0x017d) ||
1839 (dev->pdev->subsystem_device == 0x017e) ||
1840 (dev->pdev->subsystem_device == 0x0183) ||
1841 (dev->pdev->subsystem_device == 0x018a) ||
1842 (dev->pdev->subsystem_device == 0x019a)))
1843 force_dac2 = true;
1844 break;
1845 }
1846
1847 if (force_dac2) {
1848 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1849 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1850 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1851
1852 /* For CRT on DAC2, don't turn it on if BIOS didn't
1853 enable it, even it's detected.
1854 */
1855
1856 /* force it to crtc0 */
1857 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1858 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1859 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1860
1861 /* set up the TV DAC */
1862 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1863 RADEON_TV_DAC_STD_MASK |
1864 RADEON_TV_DAC_RDACPD |
1865 RADEON_TV_DAC_GDACPD |
1866 RADEON_TV_DAC_BDACPD |
1867 RADEON_TV_DAC_BGADJ_MASK |
1868 RADEON_TV_DAC_DACADJ_MASK);
1869 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1870 RADEON_TV_DAC_NHOLD |
1871 RADEON_TV_DAC_STD_PS2 |
1872 (0x58 << 16));
1873
1874 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1875 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1876 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1877 }
92cde00c 1878}
771fe6b9
JG		 1879
1880/*
1881 * VRAM info
1882 */
1883static void r100_vram_get_type(struct radeon_device *rdev)
1884{
1885 uint32_t tmp;
1886
1887 rdev->mc.vram_is_ddr = false;
1888 if (rdev->flags & RADEON_IS_IGP)
1889 rdev->mc.vram_is_ddr = true;
1890 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1891 rdev->mc.vram_is_ddr = true;
1892 if ((rdev->family == CHIP_RV100) ||
1893 (rdev->family == CHIP_RS100) ||
1894 (rdev->family == CHIP_RS200)) {
1895 tmp = RREG32(RADEON_MEM_CNTL);
1896 if (tmp & RV100_HALF_MODE) {
1897 rdev->mc.vram_width = 32;
1898 } else {
1899 rdev->mc.vram_width = 64;
1900 }
1901 if (rdev->flags & RADEON_SINGLE_CRTC) {
1902 rdev->mc.vram_width /= 4;
1903 rdev->mc.vram_is_ddr = true;
1904 }
1905 } else if (rdev->family <= CHIP_RV280) {
1906 tmp = RREG32(RADEON_MEM_CNTL);
1907 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1908 rdev->mc.vram_width = 128;
1909 } else {
1910 rdev->mc.vram_width = 64;
1911 }
1912 } else {
1913 /* newer IGPs */
1914 rdev->mc.vram_width = 128;
1915 }
1916}
1917
2a0f8918 1918static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1919{
2a0f8918
DA		 1920 u32 aper_size;
1921 u8 byte;
1922
1923 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1924
1925 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1926 * that is has the 2nd generation multifunction PCI interface
1927 */
1928 if (rdev->family == CHIP_RV280 ||
1929 rdev->family >= CHIP_RV350) {
1930 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1931 ~RADEON_HDP_APER_CNTL);
1932 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1933 return aper_size * 2;
1934 }
1935
1936 /* Older cards have all sorts of funny issues to deal with. First
1937 * check if it's a multifunction card by reading the PCI config
1938 * header type... Limit those to one aperture size
1939 */
1940 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1941 if (byte & 0x80) {
1942 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1943 DRM_INFO("Limiting VRAM to one aperture\n");
1944 return aper_size;
1945 }
1946
1947 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1948 * have set it up. We don't write this as it's broken on some ASICs but
1949 * we expect the BIOS to have done the right thing (might be too optimistic...)
1950 */
1951 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1952 return aper_size * 2;
1953 return aper_size;
1954}
1955
1956void r100_vram_init_sizes(struct radeon_device *rdev)
1957{
1958 u64 config_aper_size;
2a0f8918 1959
d594e46a 1960 /* work out accessible VRAM */
d594e46a
JG		 1961 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1962 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
51e5fcd3
JG		 1963 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1964 /* FIXME we don't use the second aperture yet when we could use it */
1965 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1966 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2a0f8918 1967 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1968 if (rdev->flags & RADEON_IS_IGP) {
1969 uint32_t tom;
1970 /* read NB_TOM to get the amount of ram stolen for the GPU */
1971 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1972 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 1973 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1974 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1975 } else {
7a50f01a 1976 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1977 /* Some production boards of m6 will report 0
1978 * if it's 8 MB
1979 */
7a50f01a
DA		 1980 if (rdev->mc.real_vram_size == 0) {
1981 rdev->mc.real_vram_size = 8192 * 1024;
1982 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1983 }
d594e46a
JG		 1984 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1985 * Novell bug 204882 + along with lots of ubuntu ones
1986 */
7a50f01a
DA		 1987 if (config_aper_size > rdev->mc.real_vram_size)
1988 rdev->mc.mc_vram_size = config_aper_size;
1989 else
1990 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1991 }
d594e46a
JG		 1992 /* FIXME remove this once we support unmappable VRAM */
1993 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
7a50f01a 1994 rdev->mc.mc_vram_size = rdev->mc.aper_size;
7a50f01a 1995 rdev->mc.real_vram_size = rdev->mc.aper_size;
d594e46a 1996 }
2a0f8918
DA		 1997}
1998
28d52043
DA		 1999void r100_vga_set_state(struct radeon_device *rdev, bool state)
2000{
2001 uint32_t temp;
2002
2003 temp = RREG32(RADEON_CONFIG_CNTL);
2004 if (state == false) {
2005 temp &= ~(1<<8);
2006 temp |= (1<<9);
2007 } else {
2008 temp &= ~(1<<9);
2009 }
2010 WREG32(RADEON_CONFIG_CNTL, temp);
2011}
2012
d594e46a 2013void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2014{
d594e46a 2015 u64 base;
2a0f8918 2016
d594e46a 2017 r100_vram_get_type(rdev);
2a0f8918 2018 r100_vram_init_sizes(rdev);
d594e46a
JG		 2019 base = rdev->mc.aper_base;
2020 if (rdev->flags & RADEON_IS_IGP)
2021 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2022 radeon_vram_location(rdev, &rdev->mc, base);
2023 if (!(rdev->flags & RADEON_IS_AGP))
2024 radeon_gtt_location(rdev, &rdev->mc);
771fe6b9
JG		 2025}
2026
2027
2028/*
2029 * Indirect registers accessor
2030 */
2031void r100_pll_errata_after_index(struct radeon_device *rdev)
2032{
2033 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2034 return;
2035 }
2036 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2037 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2038}
2039
2040static void r100_pll_errata_after_data(struct radeon_device *rdev)
2041{
2042 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2043 * or the chip could hang on a subsequent access
2044 */
2045 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2046 udelay(5000);
2047 }
2048
2049 /* This function is required to workaround a hardware bug in some (all?)
2050 * revisions of the R300. This workaround should be called after every
2051 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2052 * may not be correct.
2053 */
2054 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2055 uint32_t save, tmp;
2056
2057 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2058 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2059 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2060 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2061 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2062 }
2063}
2064
2065uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2066{
2067 uint32_t data;
2068
2069 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2070 r100_pll_errata_after_index(rdev);
2071 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2072 r100_pll_errata_after_data(rdev);
2073 return data;
2074}
2075
2076void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2077{
2078 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2079 r100_pll_errata_after_index(rdev);
2080 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2081 r100_pll_errata_after_data(rdev);
2082}
2083
d4550907 2084void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2085{
551ebd83
DA		 2086 if (ASIC_IS_RN50(rdev)) {
2087 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2088 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2089 } else if (rdev->family < CHIP_R200) {
2090 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2091 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2092 } else {
d4550907 2093 r200_set_safe_registers(rdev);
551ebd83 2094 }
068a117c
JG		 2095}
2096
771fe6b9
JG		 2097/*
2098 * Debugfs info
2099 */
2100#if defined(CONFIG_DEBUG_FS)
2101static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2102{
2103 struct drm_info_node *node = (struct drm_info_node *) m->private;
2104 struct drm_device *dev = node->minor->dev;
2105 struct radeon_device *rdev = dev->dev_private;
2106 uint32_t reg, value;
2107 unsigned i;
2108
2109 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2110 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2111 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2112 for (i = 0; i < 64; i++) {
2113 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2114 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2115 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2116 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2117 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2118 }
2119 return 0;
2120}
2121
2122static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2123{
2124 struct drm_info_node *node = (struct drm_info_node *) m->private;
2125 struct drm_device *dev = node->minor->dev;
2126 struct radeon_device *rdev = dev->dev_private;
2127 uint32_t rdp, wdp;
2128 unsigned count, i, j;
2129
2130 radeon_ring_free_size(rdev);
2131 rdp = RREG32(RADEON_CP_RB_RPTR);
2132 wdp = RREG32(RADEON_CP_RB_WPTR);
2133 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2134 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2135 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2136 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2137 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2138 seq_printf(m, "%u dwords in ring\n", count);
2139 for (j = 0; j <= count; j++) {
2140 i = (rdp + j) & rdev->cp.ptr_mask;
2141 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2142 }
2143 return 0;
2144}
2145
2146
2147static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2148{
2149 struct drm_info_node *node = (struct drm_info_node *) m->private;
2150 struct drm_device *dev = node->minor->dev;
2151 struct radeon_device *rdev = dev->dev_private;
2152 uint32_t csq_stat, csq2_stat, tmp;
2153 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2154 unsigned i;
2155
2156 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2157 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2158 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2159 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2160 r_rptr = (csq_stat >> 0) & 0x3ff;
2161 r_wptr = (csq_stat >> 10) & 0x3ff;
2162 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2163 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2164 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2165 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2166 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2167 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2168 seq_printf(m, "Ring rptr %u\n", r_rptr);
2169 seq_printf(m, "Ring wptr %u\n", r_wptr);
2170 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2171 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2172 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2173 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2174 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2175 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2176 seq_printf(m, "Ring fifo:\n");
2177 for (i = 0; i < 256; i++) {
2178 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2179 tmp = RREG32(RADEON_CP_CSQ_DATA);
2180 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2181 }
2182 seq_printf(m, "Indirect1 fifo:\n");
2183 for (i = 256; i <= 512; i++) {
2184 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2185 tmp = RREG32(RADEON_CP_CSQ_DATA);
2186 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2187 }
2188 seq_printf(m, "Indirect2 fifo:\n");
2189 for (i = 640; i < ib1_wptr; i++) {
2190 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2191 tmp = RREG32(RADEON_CP_CSQ_DATA);
2192 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2193 }
2194 return 0;
2195}
2196
2197static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2198{
2199 struct drm_info_node *node = (struct drm_info_node *) m->private;
2200 struct drm_device *dev = node->minor->dev;
2201 struct radeon_device *rdev = dev->dev_private;
2202 uint32_t tmp;
2203
2204 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2205 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2206 tmp = RREG32(RADEON_MC_FB_LOCATION);
2207 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2208 tmp = RREG32(RADEON_BUS_CNTL);
2209 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2210 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2211 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2212 tmp = RREG32(RADEON_AGP_BASE);
2213 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2214 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2215 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2216 tmp = RREG32(0x01D0);
2217 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2218 tmp = RREG32(RADEON_AIC_LO_ADDR);
2219 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2220 tmp = RREG32(RADEON_AIC_HI_ADDR);
2221 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2222 tmp = RREG32(0x01E4);
2223 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2224 return 0;
2225}
2226
2227static struct drm_info_list r100_debugfs_rbbm_list[] = {
2228 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2229};
2230
2231static struct drm_info_list r100_debugfs_cp_list[] = {
2232 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2233 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2234};
2235
2236static struct drm_info_list r100_debugfs_mc_info_list[] = {
2237 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2238};
2239#endif
2240
2241int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2242{
2243#if defined(CONFIG_DEBUG_FS)
2244 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2245#else
2246 return 0;
2247#endif
2248}
2249
2250int r100_debugfs_cp_init(struct radeon_device *rdev)
2251{
2252#if defined(CONFIG_DEBUG_FS)
2253 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2254#else
2255 return 0;
2256#endif
2257}
2258
2259int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2260{
2261#if defined(CONFIG_DEBUG_FS)
2262 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2263#else
2264 return 0;
2265#endif
2266}
e024e110
DA		 2267
2268int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2269 uint32_t tiling_flags, uint32_t pitch,
2270 uint32_t offset, uint32_t obj_size)
2271{
2272 int surf_index = reg * 16;
2273 int flags = 0;
2274
2275 /* r100/r200 divide by 16 */
2276 if (rdev->family < CHIP_R300)
2277 flags = pitch / 16;
2278 else
2279 flags = pitch / 8;
2280
2281 if (rdev->family <= CHIP_RS200) {
2282 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2283 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2284 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2285 if (tiling_flags & RADEON_TILING_MACRO)
2286 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2287 } else if (rdev->family <= CHIP_RV280) {
2288 if (tiling_flags & (RADEON_TILING_MACRO))
2289 flags |= R200_SURF_TILE_COLOR_MACRO;
2290 if (tiling_flags & RADEON_TILING_MICRO)
2291 flags |= R200_SURF_TILE_COLOR_MICRO;
2292 } else {
2293 if (tiling_flags & RADEON_TILING_MACRO)
2294 flags |= R300_SURF_TILE_MACRO;
2295 if (tiling_flags & RADEON_TILING_MICRO)
2296 flags |= R300_SURF_TILE_MICRO;
2297 }
2298
c88f9f0c
MD		 2299 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2300 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2301 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2302 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2303
e024e110
DA		 2304 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2305 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2306 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2307 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2308 return 0;
2309}
2310
2311void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2312{
2313 int surf_index = reg * 16;
2314 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2315}
c93bb85b
JG		 2316
2317void r100_bandwidth_update(struct radeon_device *rdev)
2318{
2319 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2320 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2321 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2322 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2323 fixed20_12 memtcas_ff[8] = {
2324 fixed_init(1),
2325 fixed_init(2),
2326 fixed_init(3),
2327 fixed_init(0),
2328 fixed_init_half(1),
2329 fixed_init_half(2),
2330 fixed_init(0),
2331 };
2332 fixed20_12 memtcas_rs480_ff[8] = {
2333 fixed_init(0),
2334 fixed_init(1),
2335 fixed_init(2),
2336 fixed_init(3),
2337 fixed_init(0),
2338 fixed_init_half(1),
2339 fixed_init_half(2),
2340 fixed_init_half(3),
2341 };
2342 fixed20_12 memtcas2_ff[8] = {
2343 fixed_init(0),
2344 fixed_init(1),
2345 fixed_init(2),
2346 fixed_init(3),
2347 fixed_init(4),
2348 fixed_init(5),
2349 fixed_init(6),
2350 fixed_init(7),
2351 };
2352 fixed20_12 memtrbs[8] = {
2353 fixed_init(1),
2354 fixed_init_half(1),
2355 fixed_init(2),
2356 fixed_init_half(2),
2357 fixed_init(3),
2358 fixed_init_half(3),
2359 fixed_init(4),
2360 fixed_init_half(4)
2361 };
2362 fixed20_12 memtrbs_r4xx[8] = {
2363 fixed_init(4),
2364 fixed_init(5),
2365 fixed_init(6),
2366 fixed_init(7),
2367 fixed_init(8),
2368 fixed_init(9),
2369 fixed_init(10),
2370 fixed_init(11)
2371 };
2372 fixed20_12 min_mem_eff;
2373 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2374 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2375 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2376 disp_drain_rate2, read_return_rate;
2377 fixed20_12 time_disp1_drop_priority;
2378 int c;
2379 int cur_size = 16; /* in octawords */
2380 int critical_point = 0, critical_point2;
2381/* uint32_t read_return_rate, time_disp1_drop_priority; */
2382 int stop_req, max_stop_req;
2383 struct drm_display_mode *mode1 = NULL;
2384 struct drm_display_mode *mode2 = NULL;
2385 uint32_t pixel_bytes1 = 0;
2386 uint32_t pixel_bytes2 = 0;
2387
2388 if (rdev->mode_info.crtcs[0]->base.enabled) {
2389 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2390 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2391 }
dfee5614
DA		 2392 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2393 if (rdev->mode_info.crtcs[1]->base.enabled) {
2394 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2395 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2396 }
c93bb85b
JG		 2397 }
2398
2399 min_mem_eff.full = rfixed_const_8(0);
2400 /* get modes */
2401 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2402 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2403 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2404 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2405 /* check crtc enables */
2406 if (mode2)
2407 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2408 if (mode1)
2409 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2410 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2411 }
2412
2413 /*
2414 * determine is there is enough bw for current mode
2415 */
2416 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2417 temp_ff.full = rfixed_const(100);
2418 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2419 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2420 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2421
2422 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2423 temp_ff.full = rfixed_const(temp);
2424 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2425
2426 pix_clk.full = 0;
2427 pix_clk2.full = 0;
2428 peak_disp_bw.full = 0;
2429 if (mode1) {
2430 temp_ff.full = rfixed_const(1000);
2431 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2432 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2433 temp_ff.full = rfixed_const(pixel_bytes1);
2434 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2435 }
2436 if (mode2) {
2437 temp_ff.full = rfixed_const(1000);
2438 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2439 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2440 temp_ff.full = rfixed_const(pixel_bytes2);
2441 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2442 }
2443
2444 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2445 if (peak_disp_bw.full >= mem_bw.full) {
2446 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2447 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2448 }
2449
2450 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2451 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2452 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2453 mem_trcd = ((temp >> 2) & 0x3) + 1;
2454 mem_trp = ((temp & 0x3)) + 1;
2455 mem_tras = ((temp & 0x70) >> 4) + 1;
2456 } else if (rdev->family == CHIP_R300 ||
2457 rdev->family == CHIP_R350) { /* r300, r350 */
2458 mem_trcd = (temp & 0x7) + 1;
2459 mem_trp = ((temp >> 8) & 0x7) + 1;
2460 mem_tras = ((temp >> 11) & 0xf) + 4;
2461 } else if (rdev->family == CHIP_RV350 ||
2462 rdev->family <= CHIP_RV380) {
2463 /* rv3x0 */
2464 mem_trcd = (temp & 0x7) + 3;
2465 mem_trp = ((temp >> 8) & 0x7) + 3;
2466 mem_tras = ((temp >> 11) & 0xf) + 6;
2467 } else if (rdev->family == CHIP_R420 ||
2468 rdev->family == CHIP_R423 ||
2469 rdev->family == CHIP_RV410) {
2470 /* r4xx */
2471 mem_trcd = (temp & 0xf) + 3;
2472 if (mem_trcd > 15)
2473 mem_trcd = 15;
2474 mem_trp = ((temp >> 8) & 0xf) + 3;
2475 if (mem_trp > 15)
2476 mem_trp = 15;
2477 mem_tras = ((temp >> 12) & 0x1f) + 6;
2478 if (mem_tras > 31)
2479 mem_tras = 31;
2480 } else { /* RV200, R200 */
2481 mem_trcd = (temp & 0x7) + 1;
2482 mem_trp = ((temp >> 8) & 0x7) + 1;
2483 mem_tras = ((temp >> 12) & 0xf) + 4;
2484 }
2485 /* convert to FF */
2486 trcd_ff.full = rfixed_const(mem_trcd);
2487 trp_ff.full = rfixed_const(mem_trp);
2488 tras_ff.full = rfixed_const(mem_tras);
2489
2490 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2491 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2492 data = (temp & (7 << 20)) >> 20;
2493 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2494 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2495 tcas_ff = memtcas_rs480_ff[data];
2496 else
2497 tcas_ff = memtcas_ff[data];
2498 } else
2499 tcas_ff = memtcas2_ff[data];
2500
2501 if (rdev->family == CHIP_RS400 ||
2502 rdev->family == CHIP_RS480) {
2503 /* extra cas latency stored in bits 23-25 0-4 clocks */
2504 data = (temp >> 23) & 0x7;
2505 if (data < 5)
2506 tcas_ff.full += rfixed_const(data);
2507 }
2508
2509 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2510 /* on the R300, Tcas is included in Trbs.
2511 */
2512 temp = RREG32(RADEON_MEM_CNTL);
2513 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2514 if (data == 1) {
2515 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2516 temp = RREG32(R300_MC_IND_INDEX);
2517 temp &= ~R300_MC_IND_ADDR_MASK;
2518 temp |= R300_MC_READ_CNTL_CD_mcind;
2519 WREG32(R300_MC_IND_INDEX, temp);
2520 temp = RREG32(R300_MC_IND_DATA);
2521 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2522 } else {
2523 temp = RREG32(R300_MC_READ_CNTL_AB);
2524 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2525 }
2526 } else {
2527 temp = RREG32(R300_MC_READ_CNTL_AB);
2528 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2529 }
2530 if (rdev->family == CHIP_RV410 ||
2531 rdev->family == CHIP_R420 ||
2532 rdev->family == CHIP_R423)
2533 trbs_ff = memtrbs_r4xx[data];
2534 else
2535 trbs_ff = memtrbs[data];
2536 tcas_ff.full += trbs_ff.full;
2537 }
2538
2539 sclk_eff_ff.full = sclk_ff.full;
2540
2541 if (rdev->flags & RADEON_IS_AGP) {
2542 fixed20_12 agpmode_ff;
2543 agpmode_ff.full = rfixed_const(radeon_agpmode);
2544 temp_ff.full = rfixed_const_666(16);
2545 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2546 }
2547 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2548
2549 if (ASIC_IS_R300(rdev)) {
2550 sclk_delay_ff.full = rfixed_const(250);
2551 } else {
2552 if ((rdev->family == CHIP_RV100) ||
2553 rdev->flags & RADEON_IS_IGP) {
2554 if (rdev->mc.vram_is_ddr)
2555 sclk_delay_ff.full = rfixed_const(41);
2556 else
2557 sclk_delay_ff.full = rfixed_const(33);
2558 } else {
2559 if (rdev->mc.vram_width == 128)
2560 sclk_delay_ff.full = rfixed_const(57);
2561 else
2562 sclk_delay_ff.full = rfixed_const(41);
2563 }
2564 }
2565
2566 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2567
2568 if (rdev->mc.vram_is_ddr) {
2569 if (rdev->mc.vram_width == 32) {
2570 k1.full = rfixed_const(40);
2571 c = 3;
2572 } else {
2573 k1.full = rfixed_const(20);
2574 c = 1;
2575 }
2576 } else {
2577 k1.full = rfixed_const(40);
2578 c = 3;
2579 }
2580
2581 temp_ff.full = rfixed_const(2);
2582 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2583 temp_ff.full = rfixed_const(c);
2584 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2585 temp_ff.full = rfixed_const(4);
2586 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2587 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2588 mc_latency_mclk.full += k1.full;
2589
2590 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2591 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2592
2593 /*
2594 HW cursor time assuming worst case of full size colour cursor.
2595 */
2596 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2597 temp_ff.full += trcd_ff.full;
2598 if (temp_ff.full < tras_ff.full)
2599 temp_ff.full = tras_ff.full;
2600 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2601
2602 temp_ff.full = rfixed_const(cur_size);
2603 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2604 /*
2605 Find the total latency for the display data.
2606 */
b5fc9010 2607 disp_latency_overhead.full = rfixed_const(8);
c93bb85b
JG		 2608 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2609 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2610 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2611
2612 if (mc_latency_mclk.full > mc_latency_sclk.full)
2613 disp_latency.full = mc_latency_mclk.full;
2614 else
2615 disp_latency.full = mc_latency_sclk.full;
2616
2617 /* setup Max GRPH_STOP_REQ default value */
2618 if (ASIC_IS_RV100(rdev))
2619 max_stop_req = 0x5c;
2620 else
2621 max_stop_req = 0x7c;
2622
2623 if (mode1) {
2624 /* CRTC1
2625 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2626 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2627 */
2628 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2629
2630 if (stop_req > max_stop_req)
2631 stop_req = max_stop_req;
2632
2633 /*
2634 Find the drain rate of the display buffer.
2635 */
2636 temp_ff.full = rfixed_const((16/pixel_bytes1));
2637 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2638
2639 /*
2640 Find the critical point of the display buffer.
2641 */
2642 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2643 crit_point_ff.full += rfixed_const_half(0);
2644
2645 critical_point = rfixed_trunc(crit_point_ff);
2646
2647 if (rdev->disp_priority == 2) {
2648 critical_point = 0;
2649 }
2650
2651 /*
2652 The critical point should never be above max_stop_req-4. Setting
2653 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2654 */
2655 if (max_stop_req - critical_point < 4)
2656 critical_point = 0;
2657
2658 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2659 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2660 critical_point = 0x10;
2661 }
2662
2663 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2664 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2665 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2666 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2667 if ((rdev->family == CHIP_R350) &&
2668 (stop_req > 0x15)) {
2669 stop_req -= 0x10;
2670 }
2671 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2672 temp |= RADEON_GRPH_BUFFER_SIZE;
2673 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2674 RADEON_GRPH_CRITICAL_AT_SOF |
2675 RADEON_GRPH_STOP_CNTL);
2676 /*
2677 Write the result into the register.
2678 */
2679 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2680 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2681
2682#if 0
2683 if ((rdev->family == CHIP_RS400) ||
2684 (rdev->family == CHIP_RS480)) {
2685 /* attempt to program RS400 disp regs correctly ??? */
2686 temp = RREG32(RS400_DISP1_REG_CNTL);
2687 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2688 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2689 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2690 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2691 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2692 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2693 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2694 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2695 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2696 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2697 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2698 }
2699#endif
2700
2701 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2702 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2703 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2704 }
2705
2706 if (mode2) {
2707 u32 grph2_cntl;
2708 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2709
2710 if (stop_req > max_stop_req)
2711 stop_req = max_stop_req;
2712
2713 /*
2714 Find the drain rate of the display buffer.
2715 */
2716 temp_ff.full = rfixed_const((16/pixel_bytes2));
2717 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2718
2719 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2720 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2721 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2722 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2723 if ((rdev->family == CHIP_R350) &&
2724 (stop_req > 0x15)) {
2725 stop_req -= 0x10;
2726 }
2727 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2728 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2729 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2730 RADEON_GRPH_CRITICAL_AT_SOF |
2731 RADEON_GRPH_STOP_CNTL);
2732
2733 if ((rdev->family == CHIP_RS100) ||
2734 (rdev->family == CHIP_RS200))
2735 critical_point2 = 0;
2736 else {
2737 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2738 temp_ff.full = rfixed_const(temp);
2739 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2740 if (sclk_ff.full < temp_ff.full)
2741 temp_ff.full = sclk_ff.full;
2742
2743 read_return_rate.full = temp_ff.full;
2744
2745 if (mode1) {
2746 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2747 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2748 } else {
2749 time_disp1_drop_priority.full = 0;
2750 }
2751 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2752 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2753 crit_point_ff.full += rfixed_const_half(0);
2754
2755 critical_point2 = rfixed_trunc(crit_point_ff);
2756
2757 if (rdev->disp_priority == 2) {
2758 critical_point2 = 0;
2759 }
2760
2761 if (max_stop_req - critical_point2 < 4)
2762 critical_point2 = 0;
2763
2764 }
2765
2766 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2767 /* some R300 cards have problem with this set to 0 */
2768 critical_point2 = 0x10;
2769 }
2770
2771 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2772 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2773
2774 if ((rdev->family == CHIP_RS400) ||
2775 (rdev->family == CHIP_RS480)) {
2776#if 0
2777 /* attempt to program RS400 disp2 regs correctly ??? */
2778 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2779 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2780 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2781 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2782 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2783 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2784 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2785 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2786 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2787 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2788 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2789 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2790#endif
2791 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2792 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2793 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2794 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2795 }
2796
2797 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2798 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2799 }
2800}
551ebd83
DA		 2801
2802static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2803{
2804 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 2805 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 2806 DRM_ERROR("width %d\n", t->width);
ceb776bc 2807 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 2808 DRM_ERROR("height %d\n", t->height);
ceb776bc 2809 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 2810 DRM_ERROR("num levels %d\n", t->num_levels);
2811 DRM_ERROR("depth %d\n", t->txdepth);
2812 DRM_ERROR("bpp %d\n", t->cpp);
2813 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2814 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2815 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 2816 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 2817}
2818
2819static int r100_cs_track_cube(struct radeon_device *rdev,
2820 struct r100_cs_track *track, unsigned idx)
2821{
2822 unsigned face, w, h;
4c788679 2823 struct radeon_bo *cube_robj;
551ebd83
DA		 2824 unsigned long size;
2825
2826 for (face = 0; face < 5; face++) {
2827 cube_robj = track->textures[idx].cube_info[face].robj;
2828 w = track->textures[idx].cube_info[face].width;
2829 h = track->textures[idx].cube_info[face].height;
2830
2831 size = w * h;
2832 size *= track->textures[idx].cpp;
2833
2834 size += track->textures[idx].cube_info[face].offset;
2835
4c788679 2836 if (size > radeon_bo_size(cube_robj)) {
551ebd83 2837 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
4c788679 2838 size, radeon_bo_size(cube_robj));
551ebd83
DA		 2839 r100_cs_track_texture_print(&track->textures[idx]);
2840 return -1;
2841 }
2842 }
2843 return 0;
2844}
2845
d785d78b
DA		 2846static int r100_track_compress_size(int compress_format, int w, int h)
2847{
2848 int block_width, block_height, block_bytes;
2849 int wblocks, hblocks;
2850 int min_wblocks;
2851 int sz;
2852
2853 block_width = 4;
2854 block_height = 4;
2855
2856 switch (compress_format) {
2857 case R100_TRACK_COMP_DXT1:
2858 block_bytes = 8;
2859 min_wblocks = 4;
2860 break;
2861 default:
2862 case R100_TRACK_COMP_DXT35:
2863 block_bytes = 16;
2864 min_wblocks = 2;
2865 break;
2866 }
2867
2868 hblocks = (h + block_height - 1) / block_height;
2869 wblocks = (w + block_width - 1) / block_width;
2870 if (wblocks < min_wblocks)
2871 wblocks = min_wblocks;
2872 sz = wblocks * hblocks * block_bytes;
2873 return sz;
2874}
2875
551ebd83
DA		 2876static int r100_cs_track_texture_check(struct radeon_device *rdev,
2877 struct r100_cs_track *track)
2878{
4c788679 2879 struct radeon_bo *robj;
551ebd83
DA		 2880 unsigned long size;
2881 unsigned u, i, w, h;
2882 int ret;
2883
2884 for (u = 0; u < track->num_texture; u++) {
2885 if (!track->textures[u].enabled)
2886 continue;
2887 robj = track->textures[u].robj;
2888 if (robj == NULL) {
2889 DRM_ERROR("No texture bound to unit %u\n", u);
2890 return -EINVAL;
2891 }
2892 size = 0;
2893 for (i = 0; i <= track->textures[u].num_levels; i++) {
2894 if (track->textures[u].use_pitch) {
2895 if (rdev->family < CHIP_R300)
2896 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2897 else
2898 w = track->textures[u].pitch / (1 << i);
2899 } else {
ceb776bc 2900 w = track->textures[u].width;
551ebd83
DA		 2901 if (rdev->family >= CHIP_RV515)
2902 w |= track->textures[u].width_11;
ceb776bc 2903 w = w / (1 << i);
551ebd83
DA		 2904 if (track->textures[u].roundup_w)
2905 w = roundup_pow_of_two(w);
2906 }
ceb776bc 2907 h = track->textures[u].height;
551ebd83
DA		 2908 if (rdev->family >= CHIP_RV515)
2909 h |= track->textures[u].height_11;
ceb776bc 2910 h = h / (1 << i);
551ebd83
DA		 2911 if (track->textures[u].roundup_h)
2912 h = roundup_pow_of_two(h);
d785d78b
DA		 2913 if (track->textures[u].compress_format) {
2914
2915 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2916 /* compressed textures are block based */
2917 } else
2918 size += w * h;
551ebd83
DA		 2919 }
2920 size *= track->textures[u].cpp;
d785d78b 2921
551ebd83
DA		 2922 switch (track->textures[u].tex_coord_type) {
2923 case 0:
2924 break;
2925 case 1:
2926 size *= (1 << track->textures[u].txdepth);
2927 break;
2928 case 2:
2929 if (track->separate_cube) {
2930 ret = r100_cs_track_cube(rdev, track, u);
2931 if (ret)
2932 return ret;
2933 } else
2934 size *= 6;
2935 break;
2936 default:
2937 DRM_ERROR("Invalid texture coordinate type %u for unit "
2938 "%u\n", track->textures[u].tex_coord_type, u);
2939 return -EINVAL;
2940 }
4c788679 2941 if (size > radeon_bo_size(robj)) {
551ebd83 2942 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 2943 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 2944 r100_cs_track_texture_print(&track->textures[u]);
2945 return -EINVAL;
2946 }
2947 }
2948 return 0;
2949}
2950
2951int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2952{
2953 unsigned i;
2954 unsigned long size;
2955 unsigned prim_walk;
2956 unsigned nverts;
2957
2958 for (i = 0; i < track->num_cb; i++) {
2959 if (track->cb[i].robj == NULL) {
46c64d4b
MO		 2960 if (!(track->fastfill || track->color_channel_mask ||
2961 track->blend_read_enable)) {
2962 continue;
2963 }
551ebd83
DA		 2964 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2965 return -EINVAL;
2966 }
2967 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2968 size += track->cb[i].offset;
4c788679 2969 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 2970 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2971 "(need %lu have %lu) !\n", i, size,
4c788679 2972 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 2973 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2974 i, track->cb[i].pitch, track->cb[i].cpp,
2975 track->cb[i].offset, track->maxy);
2976 return -EINVAL;
2977 }
2978 }
2979 if (track->z_enabled) {
2980 if (track->zb.robj == NULL) {
2981 DRM_ERROR("[drm] No buffer for z buffer !\n");
2982 return -EINVAL;
2983 }
2984 size = track->zb.pitch * track->zb.cpp * track->maxy;
2985 size += track->zb.offset;
4c788679 2986 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 2987 DRM_ERROR("[drm] Buffer too small for z buffer "
2988 "(need %lu have %lu) !\n", size,
4c788679 2989 radeon_bo_size(track->zb.robj));
551ebd83
DA		 2990 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2991 track->zb.pitch, track->zb.cpp,
2992 track->zb.offset, track->maxy);
2993 return -EINVAL;
2994 }
2995 }
2996 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2997 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2998 switch (prim_walk) {
2999 case 1:
3000 for (i = 0; i < track->num_arrays; i++) {
3001 size = track->arrays[i].esize * track->max_indx * 4;
3002 if (track->arrays[i].robj == NULL) {
3003 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3004 "bound\n", prim_walk, i);
3005 return -EINVAL;
3006 }
4c788679
JG		 3007 if (size > radeon_bo_size(track->arrays[i].robj)) {
3008 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3009 "need %lu dwords have %lu dwords\n",
3010 prim_walk, i, size >> 2,
3011 radeon_bo_size(track->arrays[i].robj)
3012 >> 2);
551ebd83
DA		 3013 DRM_ERROR("Max indices %u\n", track->max_indx);
3014 return -EINVAL;
3015 }
3016 }
3017 break;
3018 case 2:
3019 for (i = 0; i < track->num_arrays; i++) {
3020 size = track->arrays[i].esize * (nverts - 1) * 4;
3021 if (track->arrays[i].robj == NULL) {
3022 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3023 "bound\n", prim_walk, i);
3024 return -EINVAL;
3025 }
4c788679
JG		 3026 if (size > radeon_bo_size(track->arrays[i].robj)) {
3027 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3028 "need %lu dwords have %lu dwords\n",
3029 prim_walk, i, size >> 2,
3030 radeon_bo_size(track->arrays[i].robj)
3031 >> 2);
551ebd83
DA		 3032 return -EINVAL;
3033 }
3034 }
3035 break;
3036 case 3:
3037 size = track->vtx_size * nverts;
3038 if (size != track->immd_dwords) {
3039 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3040 track->immd_dwords, size);
3041 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3042 nverts, track->vtx_size);
3043 return -EINVAL;
3044 }
3045 break;
3046 default:
3047 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3048 prim_walk);
3049 return -EINVAL;
3050 }
3051 return r100_cs_track_texture_check(rdev, track);
3052}
3053
3054void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3055{
3056 unsigned i, face;
3057
3058 if (rdev->family < CHIP_R300) {
3059 track->num_cb = 1;
3060 if (rdev->family <= CHIP_RS200)
3061 track->num_texture = 3;
3062 else
3063 track->num_texture = 6;
3064 track->maxy = 2048;
3065 track->separate_cube = 1;
3066 } else {
3067 track->num_cb = 4;
3068 track->num_texture = 16;
3069 track->maxy = 4096;
3070 track->separate_cube = 0;
3071 }
3072
3073 for (i = 0; i < track->num_cb; i++) {
3074 track->cb[i].robj = NULL;
3075 track->cb[i].pitch = 8192;
3076 track->cb[i].cpp = 16;
3077 track->cb[i].offset = 0;
3078 }
3079 track->z_enabled = true;
3080 track->zb.robj = NULL;
3081 track->zb.pitch = 8192;
3082 track->zb.cpp = 4;
3083 track->zb.offset = 0;
3084 track->vtx_size = 0x7F;
3085 track->immd_dwords = 0xFFFFFFFFUL;
3086 track->num_arrays = 11;
3087 track->max_indx = 0x00FFFFFFUL;
3088 for (i = 0; i < track->num_arrays; i++) {
3089 track->arrays[i].robj = NULL;
3090 track->arrays[i].esize = 0x7F;
3091 }
3092 for (i = 0; i < track->num_texture; i++) {
d785d78b 3093 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3094 track->textures[i].pitch = 16536;
3095 track->textures[i].width = 16536;
3096 track->textures[i].height = 16536;
3097 track->textures[i].width_11 = 1 << 11;
3098 track->textures[i].height_11 = 1 << 11;
3099 track->textures[i].num_levels = 12;
3100 if (rdev->family <= CHIP_RS200) {
3101 track->textures[i].tex_coord_type = 0;
3102 track->textures[i].txdepth = 0;
3103 } else {
3104 track->textures[i].txdepth = 16;
3105 track->textures[i].tex_coord_type = 1;
3106 }
3107 track->textures[i].cpp = 64;
3108 track->textures[i].robj = NULL;
3109 /* CS IB emission code makes sure texture unit are disabled */
3110 track->textures[i].enabled = false;
3111 track->textures[i].roundup_w = true;
3112 track->textures[i].roundup_h = true;
3113 if (track->separate_cube)
3114 for (face = 0; face < 5; face++) {
3115 track->textures[i].cube_info[face].robj = NULL;
3116 track->textures[i].cube_info[face].width = 16536;
3117 track->textures[i].cube_info[face].height = 16536;
3118 track->textures[i].cube_info[face].offset = 0;
3119 }
3120 }
3121}
3ce0a23d
JG		 3122
3123int r100_ring_test(struct radeon_device *rdev)
3124{
3125 uint32_t scratch;
3126 uint32_t tmp = 0;
3127 unsigned i;
3128 int r;
3129
3130 r = radeon_scratch_get(rdev, &scratch);
3131 if (r) {
3132 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3133 return r;
3134 }
3135 WREG32(scratch, 0xCAFEDEAD);
3136 r = radeon_ring_lock(rdev, 2);
3137 if (r) {
3138 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3139 radeon_scratch_free(rdev, scratch);
3140 return r;
3141 }
3142 radeon_ring_write(rdev, PACKET0(scratch, 0));
3143 radeon_ring_write(rdev, 0xDEADBEEF);
3144 radeon_ring_unlock_commit(rdev);
3145 for (i = 0; i < rdev->usec_timeout; i++) {
3146 tmp = RREG32(scratch);
3147 if (tmp == 0xDEADBEEF) {
3148 break;
3149 }
3150 DRM_UDELAY(1);
3151 }
3152 if (i < rdev->usec_timeout) {
3153 DRM_INFO("ring test succeeded in %d usecs\n", i);
3154 } else {
3155 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3156 scratch, tmp);
3157 r = -EINVAL;
3158 }
3159 radeon_scratch_free(rdev, scratch);
3160 return r;
3161}
3162
3163void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3164{
3165 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3166 radeon_ring_write(rdev, ib->gpu_addr);
3167 radeon_ring_write(rdev, ib->length_dw);
3168}
3169
3170int r100_ib_test(struct radeon_device *rdev)
3171{
3172 struct radeon_ib *ib;
3173 uint32_t scratch;
3174 uint32_t tmp = 0;
3175 unsigned i;
3176 int r;
3177
3178 r = radeon_scratch_get(rdev, &scratch);
3179 if (r) {
3180 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3181 return r;
3182 }
3183 WREG32(scratch, 0xCAFEDEAD);
3184 r = radeon_ib_get(rdev, &ib);
3185 if (r) {
3186 return r;
3187 }
3188 ib->ptr[0] = PACKET0(scratch, 0);
3189 ib->ptr[1] = 0xDEADBEEF;
3190 ib->ptr[2] = PACKET2(0);
3191 ib->ptr[3] = PACKET2(0);
3192 ib->ptr[4] = PACKET2(0);
3193 ib->ptr[5] = PACKET2(0);
3194 ib->ptr[6] = PACKET2(0);
3195 ib->ptr[7] = PACKET2(0);
3196 ib->length_dw = 8;
3197 r = radeon_ib_schedule(rdev, ib);
3198 if (r) {
3199 radeon_scratch_free(rdev, scratch);
3200 radeon_ib_free(rdev, &ib);
3201 return r;
3202 }
3203 r = radeon_fence_wait(ib->fence, false);
3204 if (r) {
3205 return r;
3206 }
3207 for (i = 0; i < rdev->usec_timeout; i++) {
3208 tmp = RREG32(scratch);
3209 if (tmp == 0xDEADBEEF) {
3210 break;
3211 }
3212 DRM_UDELAY(1);
3213 }
3214 if (i < rdev->usec_timeout) {
3215 DRM_INFO("ib test succeeded in %u usecs\n", i);
3216 } else {
3217 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3218 scratch, tmp);
3219 r = -EINVAL;
3220 }
3221 radeon_scratch_free(rdev, scratch);
3222 radeon_ib_free(rdev, &ib);
3223 return r;
3224}
9f022ddf
JG		 3225
3226void r100_ib_fini(struct radeon_device *rdev)
3227{
3228 radeon_ib_pool_fini(rdev);
3229}
3230
3231int r100_ib_init(struct radeon_device *rdev)
3232{
3233 int r;
3234
3235 r = radeon_ib_pool_init(rdev);
3236 if (r) {
3237 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3238 r100_ib_fini(rdev);
3239 return r;
3240 }
3241 r = r100_ib_test(rdev);
3242 if (r) {
3243 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3244 r100_ib_fini(rdev);
3245 return r;
3246 }
3247 return 0;
3248}
3249
3250void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3251{
3252 /* Shutdown CP we shouldn't need to do that but better be safe than
3253 * sorry
3254 */
3255 rdev->cp.ready = false;
3256 WREG32(R_000740_CP_CSQ_CNTL, 0);
3257
3258 /* Save few CRTC registers */
ca6ffc64 3259 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3260 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3261 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3262 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3263 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3264 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3265 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3266 }
3267
3268 /* Disable VGA aperture access */
ca6ffc64 3269 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3270 /* Disable cursor, overlay, crtc */
3271 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3272 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3273 S_000054_CRTC_DISPLAY_DIS(1));
3274 WREG32(R_000050_CRTC_GEN_CNTL,
3275 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3276 S_000050_CRTC_DISP_REQ_EN_B(1));
3277 WREG32(R_000420_OV0_SCALE_CNTL,
3278 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3279 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3280 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3281 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3282 S_000360_CUR2_LOCK(1));
3283 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3284 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3285 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3286 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3287 WREG32(R_000360_CUR2_OFFSET,
3288 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3289 }
3290}
3291
3292void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3293{
3294 /* Update base address for crtc */
d594e46a 3295 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3296 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3297 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3298 }
3299 /* Restore CRTC registers */
ca6ffc64 3300 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3301 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3302 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3303 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3304 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3305 }
3306}
ca6ffc64
JG		 3307
3308void r100_vga_render_disable(struct radeon_device *rdev)
3309{
d4550907 3310 u32 tmp;
ca6ffc64 3311
d4550907 3312 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3313 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3314}
d4550907
JG		 3315
3316static void r100_debugfs(struct radeon_device *rdev)
3317{
3318 int r;
3319
3320 r = r100_debugfs_mc_info_init(rdev);
3321 if (r)
3322 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3323}
3324
3325static void r100_mc_program(struct radeon_device *rdev)
3326{
3327 struct r100_mc_save save;
3328
3329 /* Stops all mc clients */
3330 r100_mc_stop(rdev, &save);
3331 if (rdev->flags & RADEON_IS_AGP) {
3332 WREG32(R_00014C_MC_AGP_LOCATION,
3333 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3334 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3335 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3336 if (rdev->family > CHIP_RV200)
3337 WREG32(R_00015C_AGP_BASE_2,
3338 upper_32_bits(rdev->mc.agp_base) & 0xff);
3339 } else {
3340 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3341 WREG32(R_000170_AGP_BASE, 0);
3342 if (rdev->family > CHIP_RV200)
3343 WREG32(R_00015C_AGP_BASE_2, 0);
3344 }
3345 /* Wait for mc idle */
3346 if (r100_mc_wait_for_idle(rdev))
3347 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3348 /* Program MC, should be a 32bits limited address space */
3349 WREG32(R_000148_MC_FB_LOCATION,
3350 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3351 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3352 r100_mc_resume(rdev, &save);
3353}
3354
3355void r100_clock_startup(struct radeon_device *rdev)
3356{
3357 u32 tmp;
3358
3359 if (radeon_dynclks != -1 && radeon_dynclks)
3360 radeon_legacy_set_clock_gating(rdev, 1);
3361 /* We need to force on some of the block */
3362 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3363 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3364 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3365 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3366 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3367}
3368
3369static int r100_startup(struct radeon_device *rdev)
3370{
3371 int r;
3372
92cde00c
AD		 3373 /* set common regs */
3374 r100_set_common_regs(rdev);
3375 /* program mc */
d4550907
JG		 3376 r100_mc_program(rdev);
3377 /* Resume clock */
3378 r100_clock_startup(rdev);
3379 /* Initialize GPU configuration (# pipes, ...) */
3380 r100_gpu_init(rdev);
3381 /* Initialize GART (initialize after TTM so we can allocate
3382 * memory through TTM but finalize after TTM) */
17e15b0c 3383 r100_enable_bm(rdev);
d4550907
JG		 3384 if (rdev->flags & RADEON_IS_PCI) {
3385 r = r100_pci_gart_enable(rdev);
3386 if (r)
3387 return r;
3388 }
3389 /* Enable IRQ */
d4550907 3390 r100_irq_set(rdev);
cafe6609 3391 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3392 /* 1M ring buffer */
3393 r = r100_cp_init(rdev, 1024 * 1024);
3394 if (r) {
3395 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3396 return r;
3397 }
3398 r = r100_wb_init(rdev);
3399 if (r)
3400 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3401 r = r100_ib_init(rdev);
3402 if (r) {
3403 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3404 return r;
3405 }
3406 return 0;
3407}
3408
3409int r100_resume(struct radeon_device *rdev)
3410{
3411 /* Make sur GART are not working */
3412 if (rdev->flags & RADEON_IS_PCI)
3413 r100_pci_gart_disable(rdev);
3414 /* Resume clock before doing reset */
3415 r100_clock_startup(rdev);
3416 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3417 if (radeon_gpu_reset(rdev)) {
3418 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3419 RREG32(R_000E40_RBBM_STATUS),
3420 RREG32(R_0007C0_CP_STAT));
3421 }
3422 /* post */
3423 radeon_combios_asic_init(rdev->ddev);
3424 /* Resume clock after posting */
3425 r100_clock_startup(rdev);
550e2d92
DA		 3426 /* Initialize surface registers */
3427 radeon_surface_init(rdev);
d4550907
JG		 3428 return r100_startup(rdev);
3429}
3430
3431int r100_suspend(struct radeon_device *rdev)
3432{
3433 r100_cp_disable(rdev);
3434 r100_wb_disable(rdev);
3435 r100_irq_disable(rdev);
3436 if (rdev->flags & RADEON_IS_PCI)
3437 r100_pci_gart_disable(rdev);
3438 return 0;
3439}
3440
3441void r100_fini(struct radeon_device *rdev)
3442{
d4550907
JG		 3443 r100_cp_fini(rdev);
3444 r100_wb_fini(rdev);
3445 r100_ib_fini(rdev);
3446 radeon_gem_fini(rdev);
3447 if (rdev->flags & RADEON_IS_PCI)
3448 r100_pci_gart_fini(rdev);
d0269ed8 3449 radeon_agp_fini(rdev);
d4550907
JG		 3450 radeon_irq_kms_fini(rdev);
3451 radeon_fence_driver_fini(rdev);
4c788679 3452 radeon_bo_fini(rdev);
d4550907
JG		 3453 radeon_atombios_fini(rdev);
3454 kfree(rdev->bios);
3455 rdev->bios = NULL;
3456}
3457
d4550907
JG		 3458int r100_init(struct radeon_device *rdev)
3459{
3460 int r;
3461
d4550907
JG		 3462 /* Register debugfs file specific to this group of asics */
3463 r100_debugfs(rdev);
3464 /* Disable VGA */
3465 r100_vga_render_disable(rdev);
3466 /* Initialize scratch registers */
3467 radeon_scratch_init(rdev);
3468 /* Initialize surface registers */
3469 radeon_surface_init(rdev);
3470 /* TODO: disable VGA need to use VGA request */
3471 /* BIOS*/
3472 if (!radeon_get_bios(rdev)) {
3473 if (ASIC_IS_AVIVO(rdev))
3474 return -EINVAL;
3475 }
3476 if (rdev->is_atom_bios) {
3477 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3478 return -EINVAL;
3479 } else {
3480 r = radeon_combios_init(rdev);
3481 if (r)
3482 return r;
3483 }
3484 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3485 if (radeon_gpu_reset(rdev)) {
3486 dev_warn(rdev->dev,
3487 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3488 RREG32(R_000E40_RBBM_STATUS),
3489 RREG32(R_0007C0_CP_STAT));
3490 }
3491 /* check if cards are posted or not */
72542d77
DA		 3492 if (radeon_boot_test_post_card(rdev) == false)
3493 return -EINVAL;
d4550907
JG		 3494 /* Set asic errata */
3495 r100_errata(rdev);
3496 /* Initialize clocks */
3497 radeon_get_clock_info(rdev->ddev);
6234077d
RM		 3498 /* Initialize power management */
3499 radeon_pm_init(rdev);
d594e46a
JG		 3500 /* initialize AGP */
3501 if (rdev->flags & RADEON_IS_AGP) {
3502 r = radeon_agp_init(rdev);
3503 if (r) {
3504 radeon_agp_disable(rdev);
3505 }
3506 }
3507 /* initialize VRAM */
3508 r100_mc_init(rdev);
d4550907
JG		 3509 /* Fence driver */
3510 r = radeon_fence_driver_init(rdev);
3511 if (r)
3512 return r;
3513 r = radeon_irq_kms_init(rdev);
3514 if (r)
3515 return r;
3516 /* Memory manager */
4c788679 3517 r = radeon_bo_init(rdev);
d4550907
JG		 3518 if (r)
3519 return r;
3520 if (rdev->flags & RADEON_IS_PCI) {
3521 r = r100_pci_gart_init(rdev);
3522 if (r)
3523 return r;
3524 }
3525 r100_set_safe_registers(rdev);
3526 rdev->accel_working = true;
3527 r = r100_startup(rdev);
3528 if (r) {
3529 /* Somethings want wront with the accel init stop accel */
3530 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907
JG		 3531 r100_cp_fini(rdev);
3532 r100_wb_fini(rdev);
3533 r100_ib_fini(rdev);
655efd3d 3534 radeon_irq_kms_fini(rdev);
d4550907
JG		 3535 if (rdev->flags & RADEON_IS_PCI)
3536 r100_pci_gart_fini(rdev);
d4550907
JG		 3537 rdev->accel_working = false;
3538 }
3539 return 0;
3540}
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