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drm/radeon/kms/atom: fix gpio i2c table overrun (v2)
[net-next-2.6.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
e6990375 34#include "radeon_asic.h"
3ce0a23d 35#include "r100d.h"
d4550907
JG		 36#include "rs100d.h"
37#include "rv200d.h"
38#include "rv250d.h"
3ce0a23d 39
70967ab9
BH		 40#include <linux/firmware.h>
41#include <linux/platform_device.h>
42
551ebd83
DA		 43#include "r100_reg_safe.h"
44#include "rn50_reg_safe.h"
45
70967ab9
BH		 46/* Firmware Names */
47#define FIRMWARE_R100 "radeon/R100_cp.bin"
48#define FIRMWARE_R200 "radeon/R200_cp.bin"
49#define FIRMWARE_R300 "radeon/R300_cp.bin"
50#define FIRMWARE_R420 "radeon/R420_cp.bin"
51#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
52#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
53#define FIRMWARE_R520 "radeon/R520_cp.bin"
54
55MODULE_FIRMWARE(FIRMWARE_R100);
56MODULE_FIRMWARE(FIRMWARE_R200);
57MODULE_FIRMWARE(FIRMWARE_R300);
58MODULE_FIRMWARE(FIRMWARE_R420);
59MODULE_FIRMWARE(FIRMWARE_RS690);
60MODULE_FIRMWARE(FIRMWARE_RS600);
61MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 62
551ebd83
DA		 63#include "r100_track.h"
64
771fe6b9
JG		 65/* This files gather functions specifics to:
66 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 67 */
771fe6b9 68
05a05c50
AD		 69/* hpd for digital panel detect/disconnect */
70bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
71{
72 bool connected = false;
73
74 switch (hpd) {
75 case RADEON_HPD_1:
76 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
77 connected = true;
78 break;
79 case RADEON_HPD_2:
80 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
81 connected = true;
82 break;
83 default:
84 break;
85 }
86 return connected;
87}
88
89void r100_hpd_set_polarity(struct radeon_device *rdev,
90 enum radeon_hpd_id hpd)
91{
92 u32 tmp;
93 bool connected = r100_hpd_sense(rdev, hpd);
94
95 switch (hpd) {
96 case RADEON_HPD_1:
97 tmp = RREG32(RADEON_FP_GEN_CNTL);
98 if (connected)
99 tmp &= ~RADEON_FP_DETECT_INT_POL;
100 else
101 tmp |= RADEON_FP_DETECT_INT_POL;
102 WREG32(RADEON_FP_GEN_CNTL, tmp);
103 break;
104 case RADEON_HPD_2:
105 tmp = RREG32(RADEON_FP2_GEN_CNTL);
106 if (connected)
107 tmp &= ~RADEON_FP2_DETECT_INT_POL;
108 else
109 tmp |= RADEON_FP2_DETECT_INT_POL;
110 WREG32(RADEON_FP2_GEN_CNTL, tmp);
111 break;
112 default:
113 break;
114 }
115}
116
117void r100_hpd_init(struct radeon_device *rdev)
118{
119 struct drm_device *dev = rdev->ddev;
120 struct drm_connector *connector;
121
122 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
123 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
124 switch (radeon_connector->hpd.hpd) {
125 case RADEON_HPD_1:
126 rdev->irq.hpd[0] = true;
127 break;
128 case RADEON_HPD_2:
129 rdev->irq.hpd[1] = true;
130 break;
131 default:
132 break;
133 }
134 }
003e69f9
JG		 135 if (rdev->irq.installed)
136 r100_irq_set(rdev);
05a05c50
AD		 137}
138
139void r100_hpd_fini(struct radeon_device *rdev)
140{
141 struct drm_device *dev = rdev->ddev;
142 struct drm_connector *connector;
143
144 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
145 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
146 switch (radeon_connector->hpd.hpd) {
147 case RADEON_HPD_1:
148 rdev->irq.hpd[0] = false;
149 break;
150 case RADEON_HPD_2:
151 rdev->irq.hpd[1] = false;
152 break;
153 default:
154 break;
155 }
156 }
157}
158
771fe6b9
JG		 159/*
160 * PCI GART
161 */
162void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
163{
164 /* TODO: can we do somethings here ? */
165 /* It seems hw only cache one entry so we should discard this
166 * entry otherwise if first GPU GART read hit this entry it
167 * could end up in wrong address. */
168}
169
4aac0473 170int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 171{
771fe6b9
JG		 172 int r;
173
4aac0473
JG		 174 if (rdev->gart.table.ram.ptr) {
175 WARN(1, "R100 PCI GART already initialized.\n");
176 return 0;
177 }
771fe6b9
JG		 178 /* Initialize common gart structure */
179 r = radeon_gart_init(rdev);
4aac0473 180 if (r)
771fe6b9 181 return r;
4aac0473
JG		 182 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
183 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
184 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
185 return radeon_gart_table_ram_alloc(rdev);
186}
187
17e15b0c
DA		 188/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
189void r100_enable_bm(struct radeon_device *rdev)
190{
191 uint32_t tmp;
192 /* Enable bus mastering */
193 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
194 WREG32(RADEON_BUS_CNTL, tmp);
195}
196
4aac0473
JG		 197int r100_pci_gart_enable(struct radeon_device *rdev)
198{
199 uint32_t tmp;
200
82568565 201 radeon_gart_restore(rdev);
771fe6b9
JG		 202 /* discard memory request outside of configured range */
203 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
204 WREG32(RADEON_AIC_CNTL, tmp);
205 /* set address range for PCI address translate */
d594e46a
JG		 206 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
207 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 208 /* set PCI GART page-table base address */
209 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
210 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
211 WREG32(RADEON_AIC_CNTL, tmp);
212 r100_pci_gart_tlb_flush(rdev);
213 rdev->gart.ready = true;
214 return 0;
215}
216
217void r100_pci_gart_disable(struct radeon_device *rdev)
218{
219 uint32_t tmp;
220
221 /* discard memory request outside of configured range */
222 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
223 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
224 WREG32(RADEON_AIC_LO_ADDR, 0);
225 WREG32(RADEON_AIC_HI_ADDR, 0);
226}
227
228int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
229{
230 if (i < 0 || i > rdev->gart.num_gpu_pages) {
231 return -EINVAL;
232 }
ed10f95d 233 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 234 return 0;
235}
236
4aac0473 237void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 238{
f9274562 239 radeon_gart_fini(rdev);
4aac0473
JG		 240 r100_pci_gart_disable(rdev);
241 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 242}
243
7ed220d7
MD		 244int r100_irq_set(struct radeon_device *rdev)
245{
246 uint32_t tmp = 0;
247
003e69f9
JG		 248 if (!rdev->irq.installed) {
249 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
250 WREG32(R_000040_GEN_INT_CNTL, 0);
251 return -EINVAL;
252 }
7ed220d7
MD		 253 if (rdev->irq.sw_int) {
254 tmp |= RADEON_SW_INT_ENABLE;
255 }
256 if (rdev->irq.crtc_vblank_int[0]) {
257 tmp |= RADEON_CRTC_VBLANK_MASK;
258 }
259 if (rdev->irq.crtc_vblank_int[1]) {
260 tmp |= RADEON_CRTC2_VBLANK_MASK;
261 }
05a05c50
AD		 262 if (rdev->irq.hpd[0]) {
263 tmp |= RADEON_FP_DETECT_MASK;
264 }
265 if (rdev->irq.hpd[1]) {
266 tmp |= RADEON_FP2_DETECT_MASK;
267 }
7ed220d7
MD		 268 WREG32(RADEON_GEN_INT_CNTL, tmp);
269 return 0;
270}
271
9f022ddf
JG		 272void r100_irq_disable(struct radeon_device *rdev)
273{
274 u32 tmp;
275
276 WREG32(R_000040_GEN_INT_CNTL, 0);
277 /* Wait and acknowledge irq */
278 mdelay(1);
279 tmp = RREG32(R_000044_GEN_INT_STATUS);
280 WREG32(R_000044_GEN_INT_STATUS, tmp);
281}
282
7ed220d7
MD		 283static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
284{
285 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 286 uint32_t irq_mask = RADEON_SW_INT_TEST |
287 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
288 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 289
290 if (irqs) {
291 WREG32(RADEON_GEN_INT_STATUS, irqs);
292 }
293 return irqs & irq_mask;
294}
295
296int r100_irq_process(struct radeon_device *rdev)
297{
3e5cb98d 298 uint32_t status, msi_rearm;
d4877cf2 299 bool queue_hotplug = false;
7ed220d7
MD		 300
301 status = r100_irq_ack(rdev);
302 if (!status) {
303 return IRQ_NONE;
304 }
a513c184
JG		 305 if (rdev->shutdown) {
306 return IRQ_NONE;
307 }
7ed220d7
MD		 308 while (status) {
309 /* SW interrupt */
310 if (status & RADEON_SW_INT_TEST) {
311 radeon_fence_process(rdev);
312 }
313 /* Vertical blank interrupts */
314 if (status & RADEON_CRTC_VBLANK_STAT) {
315 drm_handle_vblank(rdev->ddev, 0);
839461d3 316 rdev->pm.vblank_sync = true;
73a6d3fc 317 wake_up(&rdev->irq.vblank_queue);
7ed220d7
MD		 318 }
319 if (status & RADEON_CRTC2_VBLANK_STAT) {
320 drm_handle_vblank(rdev->ddev, 1);
839461d3 321 rdev->pm.vblank_sync = true;
73a6d3fc 322 wake_up(&rdev->irq.vblank_queue);
7ed220d7 323 }
05a05c50 324 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 325 queue_hotplug = true;
326 DRM_DEBUG("HPD1\n");
05a05c50
AD		 327 }
328 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 329 queue_hotplug = true;
330 DRM_DEBUG("HPD2\n");
05a05c50 331 }
7ed220d7
MD		 332 status = r100_irq_ack(rdev);
333 }
d4877cf2
AD		 334 if (queue_hotplug)
335 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 336 if (rdev->msi_enabled) {
337 switch (rdev->family) {
338 case CHIP_RS400:
339 case CHIP_RS480:
340 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
341 WREG32(RADEON_AIC_CNTL, msi_rearm);
342 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
343 break;
344 default:
345 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
346 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
347 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
348 break;
349 }
350 }
7ed220d7
MD		 351 return IRQ_HANDLED;
352}
353
354u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
355{
356 if (crtc == 0)
357 return RREG32(RADEON_CRTC_CRNT_FRAME);
358 else
359 return RREG32(RADEON_CRTC2_CRNT_FRAME);
360}
361
9e5b2af7
PN		 362/* Who ever call radeon_fence_emit should call ring_lock and ask
363 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 364void r100_fence_ring_emit(struct radeon_device *rdev,
365 struct radeon_fence *fence)
366{
9e5b2af7
PN		 367 /* We have to make sure that caches are flushed before
368 * CPU might read something from VRAM. */
369 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
370 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
371 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
372 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 373 /* Wait until IDLE & CLEAN */
4612dc97
AD		 374 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
375 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
cafe6609
JG		 376 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
377 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
378 RADEON_HDP_READ_BUFFER_INVALIDATE);
379 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
380 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 381 /* Emit fence sequence & fire IRQ */
382 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
383 radeon_ring_write(rdev, fence->seq);
384 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
385 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
386}
387
771fe6b9
JG		 388int r100_wb_init(struct radeon_device *rdev)
389{
390 int r;
391
392 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 393 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
394 RADEON_GEM_DOMAIN_GTT,
395 &rdev->wb.wb_obj);
771fe6b9 396 if (r) {
4c788679 397 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
771fe6b9
JG		 398 return r;
399 }
4c788679
JG		 400 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
401 if (unlikely(r != 0))
402 return r;
403 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
404 &rdev->wb.gpu_addr);
771fe6b9 405 if (r) {
4c788679
JG		 406 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
407 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9
JG		 408 return r;
409 }
4c788679
JG		 410 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
411 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9 412 if (r) {
4c788679 413 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
771fe6b9
JG		 414 return r;
415 }
416 }
9f022ddf
JG		 417 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
418 WREG32(R_00070C_CP_RB_RPTR_ADDR,
419 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
420 WREG32(R_000770_SCRATCH_UMSK, 0xff);
771fe6b9
JG		 421 return 0;
422}
423
9f022ddf
JG		 424void r100_wb_disable(struct radeon_device *rdev)
425{
426 WREG32(R_000770_SCRATCH_UMSK, 0);
427}
428
771fe6b9
JG		 429void r100_wb_fini(struct radeon_device *rdev)
430{
4c788679
JG		 431 int r;
432
9f022ddf 433 r100_wb_disable(rdev);
771fe6b9 434 if (rdev->wb.wb_obj) {
4c788679
JG		 435 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
436 if (unlikely(r != 0)) {
437 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
438 return;
439 }
440 radeon_bo_kunmap(rdev->wb.wb_obj);
441 radeon_bo_unpin(rdev->wb.wb_obj);
442 radeon_bo_unreserve(rdev->wb.wb_obj);
443 radeon_bo_unref(&rdev->wb.wb_obj);
771fe6b9
JG		 444 rdev->wb.wb = NULL;
445 rdev->wb.wb_obj = NULL;
446 }
447}
448
449int r100_copy_blit(struct radeon_device *rdev,
450 uint64_t src_offset,
451 uint64_t dst_offset,
452 unsigned num_pages,
453 struct radeon_fence *fence)
454{
455 uint32_t cur_pages;
456 uint32_t stride_bytes = PAGE_SIZE;
457 uint32_t pitch;
458 uint32_t stride_pixels;
459 unsigned ndw;
460 int num_loops;
461 int r = 0;
462
463 /* radeon limited to 16k stride */
464 stride_bytes &= 0x3fff;
465 /* radeon pitch is /64 */
466 pitch = stride_bytes / 64;
467 stride_pixels = stride_bytes / 4;
468 num_loops = DIV_ROUND_UP(num_pages, 8191);
469
470 /* Ask for enough room for blit + flush + fence */
471 ndw = 64 + (10 * num_loops);
472 r = radeon_ring_lock(rdev, ndw);
473 if (r) {
474 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
475 return -EINVAL;
476 }
477 while (num_pages > 0) {
478 cur_pages = num_pages;
479 if (cur_pages > 8191) {
480 cur_pages = 8191;
481 }
482 num_pages -= cur_pages;
483
484 /* pages are in Y direction - height
485 page width in X direction - width */
486 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
487 radeon_ring_write(rdev,
488 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
489 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
490 RADEON_GMC_SRC_CLIPPING |
491 RADEON_GMC_DST_CLIPPING |
492 RADEON_GMC_BRUSH_NONE |
493 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
494 RADEON_GMC_SRC_DATATYPE_COLOR |
495 RADEON_ROP3_S |
496 RADEON_DP_SRC_SOURCE_MEMORY |
497 RADEON_GMC_CLR_CMP_CNTL_DIS |
498 RADEON_GMC_WR_MSK_DIS);
499 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
500 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
501 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
502 radeon_ring_write(rdev, 0);
503 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
504 radeon_ring_write(rdev, num_pages);
505 radeon_ring_write(rdev, num_pages);
506 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
507 }
508 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
509 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
510 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
511 radeon_ring_write(rdev,
512 RADEON_WAIT_2D_IDLECLEAN |
513 RADEON_WAIT_HOST_IDLECLEAN |
514 RADEON_WAIT_DMA_GUI_IDLE);
515 if (fence) {
516 r = radeon_fence_emit(rdev, fence);
517 }
518 radeon_ring_unlock_commit(rdev);
519 return r;
520}
521
45600232
JG		 522static int r100_cp_wait_for_idle(struct radeon_device *rdev)
523{
524 unsigned i;
525 u32 tmp;
526
527 for (i = 0; i < rdev->usec_timeout; i++) {
528 tmp = RREG32(R_000E40_RBBM_STATUS);
529 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
530 return 0;
531 }
532 udelay(1);
533 }
534 return -1;
535}
536
771fe6b9
JG		 537void r100_ring_start(struct radeon_device *rdev)
538{
539 int r;
540
541 r = radeon_ring_lock(rdev, 2);
542 if (r) {
543 return;
544 }
545 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
546 radeon_ring_write(rdev,
547 RADEON_ISYNC_ANY2D_IDLE3D |
548 RADEON_ISYNC_ANY3D_IDLE2D |
549 RADEON_ISYNC_WAIT_IDLEGUI |
550 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
551 radeon_ring_unlock_commit(rdev);
552}
553
70967ab9
BH		 554
555/* Load the microcode for the CP */
556static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 557{
70967ab9
BH		 558 struct platform_device *pdev;
559 const char *fw_name = NULL;
560 int err;
771fe6b9 561
70967ab9 562 DRM_DEBUG("\n");
771fe6b9 563
70967ab9
BH		 564 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
565 err = IS_ERR(pdev);
566 if (err) {
567 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
568 return -EINVAL;
569 }
771fe6b9
JG		 570 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
571 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
572 (rdev->family == CHIP_RS200)) {
573 DRM_INFO("Loading R100 Microcode\n");
70967ab9 574 fw_name = FIRMWARE_R100;
771fe6b9
JG		 575 } else if ((rdev->family == CHIP_R200) ||
576 (rdev->family == CHIP_RV250) ||
577 (rdev->family == CHIP_RV280) ||
578 (rdev->family == CHIP_RS300)) {
579 DRM_INFO("Loading R200 Microcode\n");
70967ab9 580 fw_name = FIRMWARE_R200;
771fe6b9
JG		 581 } else if ((rdev->family == CHIP_R300) ||
582 (rdev->family == CHIP_R350) ||
583 (rdev->family == CHIP_RV350) ||
584 (rdev->family == CHIP_RV380) ||
585 (rdev->family == CHIP_RS400) ||
586 (rdev->family == CHIP_RS480)) {
587 DRM_INFO("Loading R300 Microcode\n");
70967ab9 588 fw_name = FIRMWARE_R300;
771fe6b9
JG		 589 } else if ((rdev->family == CHIP_R420) ||
590 (rdev->family == CHIP_R423) ||
591 (rdev->family == CHIP_RV410)) {
592 DRM_INFO("Loading R400 Microcode\n");
70967ab9 593 fw_name = FIRMWARE_R420;
771fe6b9
JG		 594 } else if ((rdev->family == CHIP_RS690) ||
595 (rdev->family == CHIP_RS740)) {
596 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 597 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 598 } else if (rdev->family == CHIP_RS600) {
599 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 600 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 601 } else if ((rdev->family == CHIP_RV515) ||
602 (rdev->family == CHIP_R520) ||
603 (rdev->family == CHIP_RV530) ||
604 (rdev->family == CHIP_R580) ||
605 (rdev->family == CHIP_RV560) ||
606 (rdev->family == CHIP_RV570)) {
607 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 608 fw_name = FIRMWARE_R520;
609 }
610
3ce0a23d 611 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 612 platform_device_unregister(pdev);
613 if (err) {
614 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
615 fw_name);
3ce0a23d 616 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 617 printk(KERN_ERR
618 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 619 rdev->me_fw->size, fw_name);
70967ab9 620 err = -EINVAL;
3ce0a23d
JG		 621 release_firmware(rdev->me_fw);
622 rdev->me_fw = NULL;
70967ab9
BH		 623 }
624 return err;
625}
d4550907 626
70967ab9
BH		 627static void r100_cp_load_microcode(struct radeon_device *rdev)
628{
629 const __be32 *fw_data;
630 int i, size;
631
632 if (r100_gui_wait_for_idle(rdev)) {
633 printk(KERN_WARNING "Failed to wait GUI idle while "
634 "programming pipes. Bad things might happen.\n");
635 }
636
3ce0a23d
JG		 637 if (rdev->me_fw) {
638 size = rdev->me_fw->size / 4;
639 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 640 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
641 for (i = 0; i < size; i += 2) {
642 WREG32(RADEON_CP_ME_RAM_DATAH,
643 be32_to_cpup(&fw_data[i]));
644 WREG32(RADEON_CP_ME_RAM_DATAL,
645 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 646 }
647 }
648}
649
650int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
651{
652 unsigned rb_bufsz;
653 unsigned rb_blksz;
654 unsigned max_fetch;
655 unsigned pre_write_timer;
656 unsigned pre_write_limit;
657 unsigned indirect2_start;
658 unsigned indirect1_start;
659 uint32_t tmp;
660 int r;
661
662 if (r100_debugfs_cp_init(rdev)) {
663 DRM_ERROR("Failed to register debugfs file for CP !\n");
664 }
665 /* Reset CP */
666 tmp = RREG32(RADEON_CP_CSQ_STAT);
667 if ((tmp & (1 << 31))) {
668 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
669 WREG32(RADEON_CP_CSQ_MODE, 0);
670 WREG32(RADEON_CP_CSQ_CNTL, 0);
671 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
672 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
673 mdelay(2);
674 WREG32(RADEON_RBBM_SOFT_RESET, 0);
675 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
676 mdelay(2);
677 tmp = RREG32(RADEON_CP_CSQ_STAT);
678 if ((tmp & (1 << 31))) {
679 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
680 }
681 } else {
682 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
683 }
70967ab9 684
3ce0a23d 685 if (!rdev->me_fw) {
70967ab9
BH		 686 r = r100_cp_init_microcode(rdev);
687 if (r) {
688 DRM_ERROR("Failed to load firmware!\n");
689 return r;
690 }
691 }
692
771fe6b9
JG		 693 /* Align ring size */
694 rb_bufsz = drm_order(ring_size / 8);
695 ring_size = (1 << (rb_bufsz + 1)) * 4;
696 r100_cp_load_microcode(rdev);
697 r = radeon_ring_init(rdev, ring_size);
698 if (r) {
699 return r;
700 }
701 /* Each time the cp read 1024 bytes (16 dword/quadword) update
702 * the rptr copy in system ram */
703 rb_blksz = 9;
704 /* cp will read 128bytes at a time (4 dwords) */
705 max_fetch = 1;
706 rdev->cp.align_mask = 16 - 1;
707 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
708 pre_write_timer = 64;
709 /* Force CP_RB_WPTR write if written more than one time before the
710 * delay expire
711 */
712 pre_write_limit = 0;
713 /* Setup the cp cache like this (cache size is 96 dwords) :
714 * RING 0 to 15
715 * INDIRECT1 16 to 79
716 * INDIRECT2 80 to 95
717 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
718 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
719 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
720 * Idea being that most of the gpu cmd will be through indirect1 buffer
721 * so it gets the bigger cache.
722 */
723 indirect2_start = 80;
724 indirect1_start = 16;
725 /* cp setup */
726 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 727 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9
JG		 728 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
729 REG_SET(RADEON_MAX_FETCH, max_fetch) |
730 RADEON_RB_NO_UPDATE);
d6f28938
AD		 731#ifdef __BIG_ENDIAN
732 tmp |= RADEON_BUF_SWAP_32BIT;
733#endif
734 WREG32(RADEON_CP_RB_CNTL, tmp);
735
771fe6b9
JG		 736 /* Set ring address */
737 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
738 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
739 /* Force read & write ptr to 0 */
771fe6b9
JG		 740 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
741 WREG32(RADEON_CP_RB_RPTR_WR, 0);
742 WREG32(RADEON_CP_RB_WPTR, 0);
743 WREG32(RADEON_CP_RB_CNTL, tmp);
744 udelay(10);
745 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
746 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
9e5786bd
DA		 747 /* protect against crazy HW on resume */
748 rdev->cp.wptr &= rdev->cp.ptr_mask;
771fe6b9
JG		 749 /* Set cp mode to bus mastering & enable cp*/
750 WREG32(RADEON_CP_CSQ_MODE,
751 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
752 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
753 WREG32(0x718, 0);
754 WREG32(0x744, 0x00004D4D);
755 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
756 radeon_ring_start(rdev);
757 r = radeon_ring_test(rdev);
758 if (r) {
759 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
760 return r;
761 }
762 rdev->cp.ready = true;
763 return 0;
764}
765
766void r100_cp_fini(struct radeon_device *rdev)
767{
45600232
JG		 768 if (r100_cp_wait_for_idle(rdev)) {
769 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
770 }
771fe6b9 771 /* Disable ring */
a18d7ea1 772 r100_cp_disable(rdev);
771fe6b9
JG		 773 radeon_ring_fini(rdev);
774 DRM_INFO("radeon: cp finalized\n");
775}
776
777void r100_cp_disable(struct radeon_device *rdev)
778{
779 /* Disable ring */
780 rdev->cp.ready = false;
781 WREG32(RADEON_CP_CSQ_MODE, 0);
782 WREG32(RADEON_CP_CSQ_CNTL, 0);
783 if (r100_gui_wait_for_idle(rdev)) {
784 printk(KERN_WARNING "Failed to wait GUI idle while "
785 "programming pipes. Bad things might happen.\n");
786 }
787}
788
789int r100_cp_reset(struct radeon_device *rdev)
790{
791 uint32_t tmp;
792 bool reinit_cp;
793 int i;
794
795 reinit_cp = rdev->cp.ready;
796 rdev->cp.ready = false;
797 WREG32(RADEON_CP_CSQ_MODE, 0);
798 WREG32(RADEON_CP_CSQ_CNTL, 0);
799 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
800 (void)RREG32(RADEON_RBBM_SOFT_RESET);
801 udelay(200);
802 WREG32(RADEON_RBBM_SOFT_RESET, 0);
803 /* Wait to prevent race in RBBM_STATUS */
804 mdelay(1);
805 for (i = 0; i < rdev->usec_timeout; i++) {
806 tmp = RREG32(RADEON_RBBM_STATUS);
807 if (!(tmp & (1 << 16))) {
808 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
809 tmp);
810 if (reinit_cp) {
811 return r100_cp_init(rdev, rdev->cp.ring_size);
812 }
813 return 0;
814 }
815 DRM_UDELAY(1);
816 }
817 tmp = RREG32(RADEON_RBBM_STATUS);
818 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
819 return -1;
820}
821
3ce0a23d
JG		 822void r100_cp_commit(struct radeon_device *rdev)
823{
824 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
825 (void)RREG32(RADEON_CP_RB_WPTR);
826}
827
771fe6b9
JG		 828
829/*
830 * CS functions
831 */
832int r100_cs_parse_packet0(struct radeon_cs_parser *p,
833 struct radeon_cs_packet *pkt,
068a117c 834 const unsigned *auth, unsigned n,
771fe6b9
JG		 835 radeon_packet0_check_t check)
836{
837 unsigned reg;
838 unsigned i, j, m;
839 unsigned idx;
840 int r;
841
842 idx = pkt->idx + 1;
843 reg = pkt->reg;
068a117c
JG		 844 /* Check that register fall into register range
845 * determined by the number of entry (n) in the
846 * safe register bitmap.
847 */
771fe6b9
JG		 848 if (pkt->one_reg_wr) {
849 if ((reg >> 7) > n) {
850 return -EINVAL;
851 }
852 } else {
853 if (((reg + (pkt->count << 2)) >> 7) > n) {
854 return -EINVAL;
855 }
856 }
857 for (i = 0; i <= pkt->count; i++, idx++) {
858 j = (reg >> 7);
859 m = 1 << ((reg >> 2) & 31);
860 if (auth[j] & m) {
861 r = check(p, pkt, idx, reg);
862 if (r) {
863 return r;
864 }
865 }
866 if (pkt->one_reg_wr) {
867 if (!(auth[j] & m)) {
868 break;
869 }
870 } else {
871 reg += 4;
872 }
873 }
874 return 0;
875}
876
771fe6b9
JG		 877void r100_cs_dump_packet(struct radeon_cs_parser *p,
878 struct radeon_cs_packet *pkt)
879{
771fe6b9
JG		 880 volatile uint32_t *ib;
881 unsigned i;
882 unsigned idx;
883
884 ib = p->ib->ptr;
771fe6b9
JG		 885 idx = pkt->idx;
886 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
887 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
888 }
889}
890
891/**
892 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
893 * @parser: parser structure holding parsing context.
894 * @pkt: where to store packet informations
895 *
896 * Assume that chunk_ib_index is properly set. Will return -EINVAL
897 * if packet is bigger than remaining ib size. or if packets is unknown.
898 **/
899int r100_cs_packet_parse(struct radeon_cs_parser *p,
900 struct radeon_cs_packet *pkt,
901 unsigned idx)
902{
903 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 904 uint32_t header;
771fe6b9
JG		 905
906 if (idx >= ib_chunk->length_dw) {
907 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
908 idx, ib_chunk->length_dw);
909 return -EINVAL;
910 }
513bcb46 911 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 912 pkt->idx = idx;
913 pkt->type = CP_PACKET_GET_TYPE(header);
914 pkt->count = CP_PACKET_GET_COUNT(header);
915 switch (pkt->type) {
916 case PACKET_TYPE0:
917 pkt->reg = CP_PACKET0_GET_REG(header);
918 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
919 break;
920 case PACKET_TYPE3:
921 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
922 break;
923 case PACKET_TYPE2:
924 pkt->count = -1;
925 break;
926 default:
927 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
928 return -EINVAL;
929 }
930 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
931 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
932 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
933 return -EINVAL;
934 }
935 return 0;
936}
937
531369e6
DA		 938/**
939 * r100_cs_packet_next_vline() - parse userspace VLINE packet
940 * @parser: parser structure holding parsing context.
941 *
942 * Userspace sends a special sequence for VLINE waits.
943 * PACKET0 - VLINE_START_END + value
944 * PACKET0 - WAIT_UNTIL +_value
945 * RELOC (P3) - crtc_id in reloc.
946 *
947 * This function parses this and relocates the VLINE START END
948 * and WAIT UNTIL packets to the correct crtc.
949 * It also detects a switched off crtc and nulls out the
950 * wait in that case.
951 */
952int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
953{
531369e6
DA		 954 struct drm_mode_object *obj;
955 struct drm_crtc *crtc;
956 struct radeon_crtc *radeon_crtc;
957 struct radeon_cs_packet p3reloc, waitreloc;
958 int crtc_id;
959 int r;
960 uint32_t header, h_idx, reg;
513bcb46 961 volatile uint32_t *ib;
531369e6 962
513bcb46 963 ib = p->ib->ptr;
531369e6
DA		 964
965 /* parse the wait until */
966 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
967 if (r)
968 return r;
969
970 /* check its a wait until and only 1 count */
971 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
972 waitreloc.count != 0) {
973 DRM_ERROR("vline wait had illegal wait until segment\n");
974 r = -EINVAL;
975 return r;
976 }
977
513bcb46 978 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 979 DRM_ERROR("vline wait had illegal wait until\n");
980 r = -EINVAL;
981 return r;
982 }
983
984 /* jump over the NOP */
90ebd065 985 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 986 if (r)
987 return r;
988
989 h_idx = p->idx - 2;
90ebd065
AD		 990 p->idx += waitreloc.count + 2;
991 p->idx += p3reloc.count + 2;
531369e6 992
513bcb46
DA		 993 header = radeon_get_ib_value(p, h_idx);
994 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 995 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 996 mutex_lock(&p->rdev->ddev->mode_config.mutex);
997 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
998 if (!obj) {
999 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1000 r = -EINVAL;
1001 goto out;
1002 }
1003 crtc = obj_to_crtc(obj);
1004 radeon_crtc = to_radeon_crtc(crtc);
1005 crtc_id = radeon_crtc->crtc_id;
1006
1007 if (!crtc->enabled) {
1008 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1009 ib[h_idx + 2] = PACKET2(0);
1010 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1011 } else if (crtc_id == 1) {
1012 switch (reg) {
1013 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1014 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1015 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1016 break;
1017 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1018 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1019 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1020 break;
1021 default:
1022 DRM_ERROR("unknown crtc reloc\n");
1023 r = -EINVAL;
1024 goto out;
1025 }
513bcb46
DA		 1026 ib[h_idx] = header;
1027 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1028 }
1029out:
1030 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1031 return r;
1032}
1033
771fe6b9
JG		 1034/**
1035 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1036 * @parser: parser structure holding parsing context.
1037 * @data: pointer to relocation data
1038 * @offset_start: starting offset
1039 * @offset_mask: offset mask (to align start offset on)
1040 * @reloc: reloc informations
1041 *
1042 * Check next packet is relocation packet3, do bo validation and compute
1043 * GPU offset using the provided start.
1044 **/
1045int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1046 struct radeon_cs_reloc **cs_reloc)
1047{
771fe6b9
JG		 1048 struct radeon_cs_chunk *relocs_chunk;
1049 struct radeon_cs_packet p3reloc;
1050 unsigned idx;
1051 int r;
1052
1053 if (p->chunk_relocs_idx == -1) {
1054 DRM_ERROR("No relocation chunk !\n");
1055 return -EINVAL;
1056 }
1057 *cs_reloc = NULL;
771fe6b9
JG		 1058 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1059 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1060 if (r) {
1061 return r;
1062 }
1063 p->idx += p3reloc.count + 2;
1064 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1065 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1066 p3reloc.idx);
1067 r100_cs_dump_packet(p, &p3reloc);
1068 return -EINVAL;
1069 }
513bcb46 1070 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1071 if (idx >= relocs_chunk->length_dw) {
1072 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1073 idx, relocs_chunk->length_dw);
1074 r100_cs_dump_packet(p, &p3reloc);
1075 return -EINVAL;
1076 }
1077 /* FIXME: we assume reloc size is 4 dwords */
1078 *cs_reloc = p->relocs_ptr[(idx / 4)];
1079 return 0;
1080}
1081
551ebd83
DA		 1082static int r100_get_vtx_size(uint32_t vtx_fmt)
1083{
1084 int vtx_size;
1085 vtx_size = 2;
1086 /* ordered according to bits in spec */
1087 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1088 vtx_size++;
1089 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1090 vtx_size += 3;
1091 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1092 vtx_size++;
1093 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1094 vtx_size++;
1095 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1096 vtx_size += 3;
1097 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1098 vtx_size++;
1099 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1100 vtx_size++;
1101 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1102 vtx_size += 2;
1103 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1104 vtx_size += 2;
1105 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1106 vtx_size++;
1107 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1108 vtx_size += 2;
1109 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1110 vtx_size++;
1111 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1112 vtx_size += 2;
1113 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1114 vtx_size++;
1115 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1116 vtx_size++;
1117 /* blend weight */
1118 if (vtx_fmt & (0x7 << 15))
1119 vtx_size += (vtx_fmt >> 15) & 0x7;
1120 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1121 vtx_size += 3;
1122 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1123 vtx_size += 2;
1124 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1125 vtx_size++;
1126 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1127 vtx_size++;
1128 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1129 vtx_size++;
1130 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1131 vtx_size++;
1132 return vtx_size;
1133}
1134
771fe6b9 1135static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1136 struct radeon_cs_packet *pkt,
1137 unsigned idx, unsigned reg)
771fe6b9 1138{
771fe6b9 1139 struct radeon_cs_reloc *reloc;
551ebd83 1140 struct r100_cs_track *track;
771fe6b9
JG		 1141 volatile uint32_t *ib;
1142 uint32_t tmp;
771fe6b9 1143 int r;
551ebd83 1144 int i, face;
e024e110 1145 u32 tile_flags = 0;
513bcb46 1146 u32 idx_value;
771fe6b9
JG		 1147
1148 ib = p->ib->ptr;
551ebd83
DA		 1149 track = (struct r100_cs_track *)p->track;
1150
513bcb46
DA		 1151 idx_value = radeon_get_ib_value(p, idx);
1152
551ebd83
DA		 1153 switch (reg) {
1154 case RADEON_CRTC_GUI_TRIG_VLINE:
1155 r = r100_cs_packet_parse_vline(p);
1156 if (r) {
1157 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1158 idx, reg);
1159 r100_cs_dump_packet(p, pkt);
1160 return r;
1161 }
1162 break;
771fe6b9
JG		 1163 /* FIXME: only allow PACKET3 blit? easier to check for out of
1164 * range access */
551ebd83
DA		 1165 case RADEON_DST_PITCH_OFFSET:
1166 case RADEON_SRC_PITCH_OFFSET:
1167 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1168 if (r)
1169 return r;
1170 break;
1171 case RADEON_RB3D_DEPTHOFFSET:
1172 r = r100_cs_packet_next_reloc(p, &reloc);
1173 if (r) {
1174 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1175 idx, reg);
1176 r100_cs_dump_packet(p, pkt);
1177 return r;
1178 }
1179 track->zb.robj = reloc->robj;
513bcb46
DA		 1180 track->zb.offset = idx_value;
1181 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1182 break;
1183 case RADEON_RB3D_COLOROFFSET:
1184 r = r100_cs_packet_next_reloc(p, &reloc);
1185 if (r) {
1186 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1187 idx, reg);
1188 r100_cs_dump_packet(p, pkt);
1189 return r;
1190 }
1191 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1192 track->cb[0].offset = idx_value;
1193 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1194 break;
1195 case RADEON_PP_TXOFFSET_0:
1196 case RADEON_PP_TXOFFSET_1:
1197 case RADEON_PP_TXOFFSET_2:
1198 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1199 r = r100_cs_packet_next_reloc(p, &reloc);
1200 if (r) {
1201 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1202 idx, reg);
1203 r100_cs_dump_packet(p, pkt);
1204 return r;
1205 }
513bcb46 1206 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1207 track->textures[i].robj = reloc->robj;
1208 break;
1209 case RADEON_PP_CUBIC_OFFSET_T0_0:
1210 case RADEON_PP_CUBIC_OFFSET_T0_1:
1211 case RADEON_PP_CUBIC_OFFSET_T0_2:
1212 case RADEON_PP_CUBIC_OFFSET_T0_3:
1213 case RADEON_PP_CUBIC_OFFSET_T0_4:
1214 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1215 r = r100_cs_packet_next_reloc(p, &reloc);
1216 if (r) {
1217 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1218 idx, reg);
1219 r100_cs_dump_packet(p, pkt);
1220 return r;
1221 }
513bcb46
DA		 1222 track->textures[0].cube_info[i].offset = idx_value;
1223 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1224 track->textures[0].cube_info[i].robj = reloc->robj;
1225 break;
1226 case RADEON_PP_CUBIC_OFFSET_T1_0:
1227 case RADEON_PP_CUBIC_OFFSET_T1_1:
1228 case RADEON_PP_CUBIC_OFFSET_T1_2:
1229 case RADEON_PP_CUBIC_OFFSET_T1_3:
1230 case RADEON_PP_CUBIC_OFFSET_T1_4:
1231 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1232 r = r100_cs_packet_next_reloc(p, &reloc);
1233 if (r) {
1234 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1235 idx, reg);
1236 r100_cs_dump_packet(p, pkt);
1237 return r;
1238 }
513bcb46
DA		 1239 track->textures[1].cube_info[i].offset = idx_value;
1240 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1241 track->textures[1].cube_info[i].robj = reloc->robj;
1242 break;
1243 case RADEON_PP_CUBIC_OFFSET_T2_0:
1244 case RADEON_PP_CUBIC_OFFSET_T2_1:
1245 case RADEON_PP_CUBIC_OFFSET_T2_2:
1246 case RADEON_PP_CUBIC_OFFSET_T2_3:
1247 case RADEON_PP_CUBIC_OFFSET_T2_4:
1248 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1249 r = r100_cs_packet_next_reloc(p, &reloc);
1250 if (r) {
1251 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1252 idx, reg);
1253 r100_cs_dump_packet(p, pkt);
1254 return r;
1255 }
513bcb46
DA		 1256 track->textures[2].cube_info[i].offset = idx_value;
1257 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1258 track->textures[2].cube_info[i].robj = reloc->robj;
1259 break;
1260 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1261 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1262 break;
1263 case RADEON_RB3D_COLORPITCH:
1264 r = r100_cs_packet_next_reloc(p, &reloc);
1265 if (r) {
1266 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1267 idx, reg);
1268 r100_cs_dump_packet(p, pkt);
1269 return r;
1270 }
e024e110 1271
551ebd83
DA		 1272 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1273 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1274 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1275 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1276
513bcb46 1277 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1278 tmp |= tile_flags;
1279 ib[idx] = tmp;
e024e110 1280
513bcb46 1281 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1282 break;
1283 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1284 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1285 break;
1286 case RADEON_RB3D_CNTL:
513bcb46 1287 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1288 case 7:
1289 case 8:
1290 case 9:
1291 case 11:
1292 case 12:
1293 track->cb[0].cpp = 1;
e024e110 1294 break;
551ebd83
DA		 1295 case 3:
1296 case 4:
1297 case 15:
1298 track->cb[0].cpp = 2;
1299 break;
1300 case 6:
1301 track->cb[0].cpp = 4;
1302 break;
1303 default:
1304 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1305 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1306 return -EINVAL;
1307 }
513bcb46 1308 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1309 break;
1310 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1311 switch (idx_value & 0xf) {
551ebd83
DA		 1312 case 0:
1313 track->zb.cpp = 2;
1314 break;
1315 case 2:
1316 case 3:
1317 case 4:
1318 case 5:
1319 case 9:
1320 case 11:
1321 track->zb.cpp = 4;
17782d99 1322 break;
771fe6b9 1323 default:
771fe6b9
JG		 1324 break;
1325 }
551ebd83
DA		 1326 break;
1327 case RADEON_RB3D_ZPASS_ADDR:
1328 r = r100_cs_packet_next_reloc(p, &reloc);
1329 if (r) {
1330 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1331 idx, reg);
1332 r100_cs_dump_packet(p, pkt);
1333 return r;
1334 }
513bcb46 1335 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1336 break;
1337 case RADEON_PP_CNTL:
1338 {
513bcb46 1339 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1340 for (i = 0; i < track->num_texture; i++)
1341 track->textures[i].enabled = !!(temp & (1 << i));
1342 }
1343 break;
1344 case RADEON_SE_VF_CNTL:
513bcb46 1345 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1346 break;
1347 case RADEON_SE_VTX_FMT:
513bcb46 1348 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1349 break;
1350 case RADEON_PP_TEX_SIZE_0:
1351 case RADEON_PP_TEX_SIZE_1:
1352 case RADEON_PP_TEX_SIZE_2:
1353 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1354 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1355 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1356 break;
1357 case RADEON_PP_TEX_PITCH_0:
1358 case RADEON_PP_TEX_PITCH_1:
1359 case RADEON_PP_TEX_PITCH_2:
1360 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1361 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1362 break;
1363 case RADEON_PP_TXFILTER_0:
1364 case RADEON_PP_TXFILTER_1:
1365 case RADEON_PP_TXFILTER_2:
1366 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1367 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1368 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1369 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1370 if (tmp == 2 || tmp == 6)
1371 track->textures[i].roundup_w = false;
513bcb46 1372 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1373 if (tmp == 2 || tmp == 6)
1374 track->textures[i].roundup_h = false;
1375 break;
1376 case RADEON_PP_TXFORMAT_0:
1377 case RADEON_PP_TXFORMAT_1:
1378 case RADEON_PP_TXFORMAT_2:
1379 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1380 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1381 track->textures[i].use_pitch = 1;
1382 } else {
1383 track->textures[i].use_pitch = 0;
513bcb46
DA		 1384 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1385 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1386 }
513bcb46 1387 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1388 track->textures[i].tex_coord_type = 2;
513bcb46 1389 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1390 case RADEON_TXFORMAT_I8:
1391 case RADEON_TXFORMAT_RGB332:
1392 case RADEON_TXFORMAT_Y8:
1393 track->textures[i].cpp = 1;
1394 break;
1395 case RADEON_TXFORMAT_AI88:
1396 case RADEON_TXFORMAT_ARGB1555:
1397 case RADEON_TXFORMAT_RGB565:
1398 case RADEON_TXFORMAT_ARGB4444:
1399 case RADEON_TXFORMAT_VYUY422:
1400 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1401 case RADEON_TXFORMAT_SHADOW16:
1402 case RADEON_TXFORMAT_LDUDV655:
1403 case RADEON_TXFORMAT_DUDV88:
1404 track->textures[i].cpp = 2;
771fe6b9 1405 break;
551ebd83
DA		 1406 case RADEON_TXFORMAT_ARGB8888:
1407 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1408 case RADEON_TXFORMAT_SHADOW32:
1409 case RADEON_TXFORMAT_LDUDUV8888:
1410 track->textures[i].cpp = 4;
1411 break;
d785d78b
DA		 1412 case RADEON_TXFORMAT_DXT1:
1413 track->textures[i].cpp = 1;
1414 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1415 break;
1416 case RADEON_TXFORMAT_DXT23:
1417 case RADEON_TXFORMAT_DXT45:
1418 track->textures[i].cpp = 1;
1419 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1420 break;
551ebd83 1421 }
513bcb46
DA		 1422 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1423 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1424 break;
1425 case RADEON_PP_CUBIC_FACES_0:
1426 case RADEON_PP_CUBIC_FACES_1:
1427 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1428 tmp = idx_value;
551ebd83
DA		 1429 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1430 for (face = 0; face < 4; face++) {
1431 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1432 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1433 }
551ebd83
DA		 1434 break;
1435 default:
1436 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1437 reg, idx);
1438 return -EINVAL;
771fe6b9
JG		 1439 }
1440 return 0;
1441}
1442
068a117c
JG		 1443int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1444 struct radeon_cs_packet *pkt,
4c788679 1445 struct radeon_bo *robj)
068a117c 1446{
068a117c 1447 unsigned idx;
513bcb46 1448 u32 value;
068a117c 1449 idx = pkt->idx + 1;
513bcb46 1450 value = radeon_get_ib_value(p, idx + 2);
4c788679 1451 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1452 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1453 "(need %u have %lu) !\n",
513bcb46 1454 value + 1,
4c788679 1455 radeon_bo_size(robj));
068a117c
JG		 1456 return -EINVAL;
1457 }
1458 return 0;
1459}
1460
771fe6b9
JG		 1461static int r100_packet3_check(struct radeon_cs_parser *p,
1462 struct radeon_cs_packet *pkt)
1463{
771fe6b9 1464 struct radeon_cs_reloc *reloc;
551ebd83 1465 struct r100_cs_track *track;
771fe6b9 1466 unsigned idx;
771fe6b9
JG		 1467 volatile uint32_t *ib;
1468 int r;
1469
1470 ib = p->ib->ptr;
771fe6b9 1471 idx = pkt->idx + 1;
551ebd83 1472 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1473 switch (pkt->opcode) {
1474 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1475 r = r100_packet3_load_vbpntr(p, pkt, idx);
1476 if (r)
1477 return r;
771fe6b9
JG		 1478 break;
1479 case PACKET3_INDX_BUFFER:
1480 r = r100_cs_packet_next_reloc(p, &reloc);
1481 if (r) {
1482 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1483 r100_cs_dump_packet(p, pkt);
1484 return r;
1485 }
513bcb46 1486 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1487 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1488 if (r) {
1489 return r;
1490 }
771fe6b9
JG		 1491 break;
1492 case 0x23:
771fe6b9
JG		 1493 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1494 r = r100_cs_packet_next_reloc(p, &reloc);
1495 if (r) {
1496 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1497 r100_cs_dump_packet(p, pkt);
1498 return r;
1499 }
513bcb46 1500 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1501 track->num_arrays = 1;
513bcb46 1502 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1503
1504 track->arrays[0].robj = reloc->robj;
1505 track->arrays[0].esize = track->vtx_size;
1506
513bcb46 1507 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1508
513bcb46 1509 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1510 track->immd_dwords = pkt->count - 1;
1511 r = r100_cs_track_check(p->rdev, track);
1512 if (r)
1513 return r;
771fe6b9
JG		 1514 break;
1515 case PACKET3_3D_DRAW_IMMD:
513bcb46 1516 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1517 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1518 return -EINVAL;
1519 }
cf57fc7a 1520 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1521 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1522 track->immd_dwords = pkt->count - 1;
1523 r = r100_cs_track_check(p->rdev, track);
1524 if (r)
1525 return r;
1526 break;
771fe6b9
JG		 1527 /* triggers drawing using in-packet vertex data */
1528 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1529 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1530 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1531 return -EINVAL;
1532 }
513bcb46 1533 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1534 track->immd_dwords = pkt->count;
1535 r = r100_cs_track_check(p->rdev, track);
1536 if (r)
1537 return r;
1538 break;
771fe6b9
JG		 1539 /* triggers drawing using in-packet vertex data */
1540 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1541 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1542 r = r100_cs_track_check(p->rdev, track);
1543 if (r)
1544 return r;
1545 break;
771fe6b9
JG		 1546 /* triggers drawing of vertex buffers setup elsewhere */
1547 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1548 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1549 r = r100_cs_track_check(p->rdev, track);
1550 if (r)
1551 return r;
1552 break;
771fe6b9
JG		 1553 /* triggers drawing using indices to vertex buffer */
1554 case PACKET3_3D_DRAW_VBUF:
513bcb46 1555 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1556 r = r100_cs_track_check(p->rdev, track);
1557 if (r)
1558 return r;
1559 break;
771fe6b9
JG		 1560 /* triggers drawing of vertex buffers setup elsewhere */
1561 case PACKET3_3D_DRAW_INDX:
513bcb46 1562 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1563 r = r100_cs_track_check(p->rdev, track);
1564 if (r)
1565 return r;
1566 break;
771fe6b9
JG		 1567 /* triggers drawing using indices to vertex buffer */
1568 case PACKET3_NOP:
1569 break;
1570 default:
1571 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1572 return -EINVAL;
1573 }
1574 return 0;
1575}
1576
1577int r100_cs_parse(struct radeon_cs_parser *p)
1578{
1579 struct radeon_cs_packet pkt;
9f022ddf 1580 struct r100_cs_track *track;
771fe6b9
JG		 1581 int r;
1582
9f022ddf
JG		 1583 track = kzalloc(sizeof(*track), GFP_KERNEL);
1584 r100_cs_track_clear(p->rdev, track);
1585 p->track = track;
771fe6b9
JG		 1586 do {
1587 r = r100_cs_packet_parse(p, &pkt, p->idx);
1588 if (r) {
1589 return r;
1590 }
1591 p->idx += pkt.count + 2;
1592 switch (pkt.type) {
068a117c 1593 case PACKET_TYPE0:
551ebd83
DA		 1594 if (p->rdev->family >= CHIP_R200)
1595 r = r100_cs_parse_packet0(p, &pkt,
1596 p->rdev->config.r100.reg_safe_bm,
1597 p->rdev->config.r100.reg_safe_bm_size,
1598 &r200_packet0_check);
1599 else
1600 r = r100_cs_parse_packet0(p, &pkt,
1601 p->rdev->config.r100.reg_safe_bm,
1602 p->rdev->config.r100.reg_safe_bm_size,
1603 &r100_packet0_check);
068a117c
JG		 1604 break;
1605 case PACKET_TYPE2:
1606 break;
1607 case PACKET_TYPE3:
1608 r = r100_packet3_check(p, &pkt);
1609 break;
1610 default:
1611 DRM_ERROR("Unknown packet type %d !\n",
1612 pkt.type);
1613 return -EINVAL;
771fe6b9
JG		 1614 }
1615 if (r) {
1616 return r;
1617 }
1618 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1619 return 0;
1620}
1621
1622
1623/*
1624 * Global GPU functions
1625 */
1626void r100_errata(struct radeon_device *rdev)
1627{
1628 rdev->pll_errata = 0;
1629
1630 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1631 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1632 }
1633
1634 if (rdev->family == CHIP_RV100 ||
1635 rdev->family == CHIP_RS100 ||
1636 rdev->family == CHIP_RS200) {
1637 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1638 }
1639}
1640
1641/* Wait for vertical sync on primary CRTC */
1642void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1643{
1644 uint32_t crtc_gen_cntl, tmp;
1645 int i;
1646
1647 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1648 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1649 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1650 return;
1651 }
1652 /* Clear the CRTC_VBLANK_SAVE bit */
1653 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1654 for (i = 0; i < rdev->usec_timeout; i++) {
1655 tmp = RREG32(RADEON_CRTC_STATUS);
1656 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1657 return;
1658 }
1659 DRM_UDELAY(1);
1660 }
1661}
1662
1663/* Wait for vertical sync on secondary CRTC */
1664void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1665{
1666 uint32_t crtc2_gen_cntl, tmp;
1667 int i;
1668
1669 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1670 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1671 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1672 return;
1673
1674 /* Clear the CRTC_VBLANK_SAVE bit */
1675 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1676 for (i = 0; i < rdev->usec_timeout; i++) {
1677 tmp = RREG32(RADEON_CRTC2_STATUS);
1678 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1679 return;
1680 }
1681 DRM_UDELAY(1);
1682 }
1683}
1684
1685int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1686{
1687 unsigned i;
1688 uint32_t tmp;
1689
1690 for (i = 0; i < rdev->usec_timeout; i++) {
1691 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1692 if (tmp >= n) {
1693 return 0;
1694 }
1695 DRM_UDELAY(1);
1696 }
1697 return -1;
1698}
1699
1700int r100_gui_wait_for_idle(struct radeon_device *rdev)
1701{
1702 unsigned i;
1703 uint32_t tmp;
1704
1705 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1706 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1707 " Bad things might happen.\n");
1708 }
1709 for (i = 0; i < rdev->usec_timeout; i++) {
1710 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 1711 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 1712 return 0;
1713 }
1714 DRM_UDELAY(1);
1715 }
1716 return -1;
1717}
1718
1719int r100_mc_wait_for_idle(struct radeon_device *rdev)
1720{
1721 unsigned i;
1722 uint32_t tmp;
1723
1724 for (i = 0; i < rdev->usec_timeout; i++) {
1725 /* read MC_STATUS */
4612dc97
AD		 1726 tmp = RREG32(RADEON_MC_STATUS);
1727 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 1728 return 0;
1729 }
1730 DRM_UDELAY(1);
1731 }
1732 return -1;
1733}
1734
1735void r100_gpu_init(struct radeon_device *rdev)
1736{
1737 /* TODO: anythings to do here ? pipes ? */
1738 r100_hdp_reset(rdev);
1739}
1740
1741void r100_hdp_reset(struct radeon_device *rdev)
1742{
1743 uint32_t tmp;
1744
1745 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1746 tmp |= (7 << 28);
1747 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1748 (void)RREG32(RADEON_HOST_PATH_CNTL);
1749 udelay(200);
1750 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1751 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1752 (void)RREG32(RADEON_HOST_PATH_CNTL);
1753}
1754
1755int r100_rb2d_reset(struct radeon_device *rdev)
1756{
1757 uint32_t tmp;
1758 int i;
1759
1760 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1761 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1762 udelay(200);
1763 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1764 /* Wait to prevent race in RBBM_STATUS */
1765 mdelay(1);
1766 for (i = 0; i < rdev->usec_timeout; i++) {
1767 tmp = RREG32(RADEON_RBBM_STATUS);
1768 if (!(tmp & (1 << 26))) {
1769 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1770 tmp);
1771 return 0;
1772 }
1773 DRM_UDELAY(1);
1774 }
1775 tmp = RREG32(RADEON_RBBM_STATUS);
1776 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1777 return -1;
1778}
1779
1780int r100_gpu_reset(struct radeon_device *rdev)
1781{
1782 uint32_t status;
1783
1784 /* reset order likely matter */
1785 status = RREG32(RADEON_RBBM_STATUS);
1786 /* reset HDP */
1787 r100_hdp_reset(rdev);
1788 /* reset rb2d */
1789 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1790 r100_rb2d_reset(rdev);
1791 }
1792 /* TODO: reset 3D engine */
1793 /* reset CP */
1794 status = RREG32(RADEON_RBBM_STATUS);
1795 if (status & (1 << 16)) {
1796 r100_cp_reset(rdev);
1797 }
1798 /* Check if GPU is idle */
1799 status = RREG32(RADEON_RBBM_STATUS);
4612dc97 1800 if (status & RADEON_RBBM_ACTIVE) {
771fe6b9
JG		 1801 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1802 return -1;
1803 }
1804 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1805 return 0;
1806}
1807
92cde00c
AD		 1808void r100_set_common_regs(struct radeon_device *rdev)
1809{
2739d49c
AD		 1810 struct drm_device *dev = rdev->ddev;
1811 bool force_dac2 = false;
d668046c 1812 u32 tmp;
2739d49c 1813
92cde00c
AD		 1814 /* set these so they don't interfere with anything */
1815 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1816 WREG32(RADEON_SUBPIC_CNTL, 0);
1817 WREG32(RADEON_VIPH_CONTROL, 0);
1818 WREG32(RADEON_I2C_CNTL_1, 0);
1819 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1820 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1821 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 1822
1823 /* always set up dac2 on rn50 and some rv100 as lots
1824 * of servers seem to wire it up to a VGA port but
1825 * don't report it in the bios connector
1826 * table.
1827 */
1828 switch (dev->pdev->device) {
1829 /* RN50 */
1830 case 0x515e:
1831 case 0x5969:
1832 force_dac2 = true;
1833 break;
1834 /* RV100*/
1835 case 0x5159:
1836 case 0x515a:
1837 /* DELL triple head servers */
1838 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1839 ((dev->pdev->subsystem_device == 0x016c) ||
1840 (dev->pdev->subsystem_device == 0x016d) ||
1841 (dev->pdev->subsystem_device == 0x016e) ||
1842 (dev->pdev->subsystem_device == 0x016f) ||
1843 (dev->pdev->subsystem_device == 0x0170) ||
1844 (dev->pdev->subsystem_device == 0x017d) ||
1845 (dev->pdev->subsystem_device == 0x017e) ||
1846 (dev->pdev->subsystem_device == 0x0183) ||
1847 (dev->pdev->subsystem_device == 0x018a) ||
1848 (dev->pdev->subsystem_device == 0x019a)))
1849 force_dac2 = true;
1850 break;
1851 }
1852
1853 if (force_dac2) {
1854 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1855 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1856 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1857
1858 /* For CRT on DAC2, don't turn it on if BIOS didn't
1859 enable it, even it's detected.
1860 */
1861
1862 /* force it to crtc0 */
1863 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1864 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1865 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1866
1867 /* set up the TV DAC */
1868 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1869 RADEON_TV_DAC_STD_MASK |
1870 RADEON_TV_DAC_RDACPD |
1871 RADEON_TV_DAC_GDACPD |
1872 RADEON_TV_DAC_BDACPD |
1873 RADEON_TV_DAC_BGADJ_MASK |
1874 RADEON_TV_DAC_DACADJ_MASK);
1875 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1876 RADEON_TV_DAC_NHOLD |
1877 RADEON_TV_DAC_STD_PS2 |
1878 (0x58 << 16));
1879
1880 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1881 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1882 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1883 }
d668046c
DA		 1884
1885 /* switch PM block to ACPI mode */
1886 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
1887 tmp &= ~RADEON_PM_MODE_SEL;
1888 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
1889
92cde00c 1890}
771fe6b9
JG		 1891
1892/*
1893 * VRAM info
1894 */
1895static void r100_vram_get_type(struct radeon_device *rdev)
1896{
1897 uint32_t tmp;
1898
1899 rdev->mc.vram_is_ddr = false;
1900 if (rdev->flags & RADEON_IS_IGP)
1901 rdev->mc.vram_is_ddr = true;
1902 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1903 rdev->mc.vram_is_ddr = true;
1904 if ((rdev->family == CHIP_RV100) ||
1905 (rdev->family == CHIP_RS100) ||
1906 (rdev->family == CHIP_RS200)) {
1907 tmp = RREG32(RADEON_MEM_CNTL);
1908 if (tmp & RV100_HALF_MODE) {
1909 rdev->mc.vram_width = 32;
1910 } else {
1911 rdev->mc.vram_width = 64;
1912 }
1913 if (rdev->flags & RADEON_SINGLE_CRTC) {
1914 rdev->mc.vram_width /= 4;
1915 rdev->mc.vram_is_ddr = true;
1916 }
1917 } else if (rdev->family <= CHIP_RV280) {
1918 tmp = RREG32(RADEON_MEM_CNTL);
1919 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1920 rdev->mc.vram_width = 128;
1921 } else {
1922 rdev->mc.vram_width = 64;
1923 }
1924 } else {
1925 /* newer IGPs */
1926 rdev->mc.vram_width = 128;
1927 }
1928}
1929
2a0f8918 1930static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1931{
2a0f8918
DA		 1932 u32 aper_size;
1933 u8 byte;
1934
1935 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1936
1937 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1938 * that is has the 2nd generation multifunction PCI interface
1939 */
1940 if (rdev->family == CHIP_RV280 ||
1941 rdev->family >= CHIP_RV350) {
1942 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1943 ~RADEON_HDP_APER_CNTL);
1944 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1945 return aper_size * 2;
1946 }
1947
1948 /* Older cards have all sorts of funny issues to deal with. First
1949 * check if it's a multifunction card by reading the PCI config
1950 * header type... Limit those to one aperture size
1951 */
1952 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1953 if (byte & 0x80) {
1954 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1955 DRM_INFO("Limiting VRAM to one aperture\n");
1956 return aper_size;
1957 }
1958
1959 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1960 * have set it up. We don't write this as it's broken on some ASICs but
1961 * we expect the BIOS to have done the right thing (might be too optimistic...)
1962 */
1963 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1964 return aper_size * 2;
1965 return aper_size;
1966}
1967
1968void r100_vram_init_sizes(struct radeon_device *rdev)
1969{
1970 u64 config_aper_size;
2a0f8918 1971
d594e46a 1972 /* work out accessible VRAM */
d594e46a
JG		 1973 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1974 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
51e5fcd3
JG		 1975 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1976 /* FIXME we don't use the second aperture yet when we could use it */
1977 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1978 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2a0f8918 1979 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1980 if (rdev->flags & RADEON_IS_IGP) {
1981 uint32_t tom;
1982 /* read NB_TOM to get the amount of ram stolen for the GPU */
1983 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1984 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 1985 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1986 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1987 } else {
7a50f01a 1988 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1989 /* Some production boards of m6 will report 0
1990 * if it's 8 MB
1991 */
7a50f01a
DA		 1992 if (rdev->mc.real_vram_size == 0) {
1993 rdev->mc.real_vram_size = 8192 * 1024;
1994 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1995 }
d594e46a
JG		 1996 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1997 * Novell bug 204882 + along with lots of ubuntu ones
1998 */
7a50f01a
DA		 1999 if (config_aper_size > rdev->mc.real_vram_size)
2000 rdev->mc.mc_vram_size = config_aper_size;
2001 else
2002 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2003 }
d594e46a
JG		 2004 /* FIXME remove this once we support unmappable VRAM */
2005 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
7a50f01a 2006 rdev->mc.mc_vram_size = rdev->mc.aper_size;
7a50f01a 2007 rdev->mc.real_vram_size = rdev->mc.aper_size;
d594e46a 2008 }
2a0f8918
DA		 2009}
2010
28d52043
DA		 2011void r100_vga_set_state(struct radeon_device *rdev, bool state)
2012{
2013 uint32_t temp;
2014
2015 temp = RREG32(RADEON_CONFIG_CNTL);
2016 if (state == false) {
2017 temp &= ~(1<<8);
2018 temp |= (1<<9);
2019 } else {
2020 temp &= ~(1<<9);
2021 }
2022 WREG32(RADEON_CONFIG_CNTL, temp);
2023}
2024
d594e46a 2025void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2026{
d594e46a 2027 u64 base;
2a0f8918 2028
d594e46a 2029 r100_vram_get_type(rdev);
2a0f8918 2030 r100_vram_init_sizes(rdev);
d594e46a
JG		 2031 base = rdev->mc.aper_base;
2032 if (rdev->flags & RADEON_IS_IGP)
2033 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2034 radeon_vram_location(rdev, &rdev->mc, base);
2035 if (!(rdev->flags & RADEON_IS_AGP))
2036 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 2037 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 2038}
2039
2040
2041/*
2042 * Indirect registers accessor
2043 */
2044void r100_pll_errata_after_index(struct radeon_device *rdev)
2045{
2046 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2047 return;
2048 }
2049 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2050 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2051}
2052
2053static void r100_pll_errata_after_data(struct radeon_device *rdev)
2054{
2055 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2056 * or the chip could hang on a subsequent access
2057 */
2058 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2059 udelay(5000);
2060 }
2061
2062 /* This function is required to workaround a hardware bug in some (all?)
2063 * revisions of the R300. This workaround should be called after every
2064 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2065 * may not be correct.
2066 */
2067 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2068 uint32_t save, tmp;
2069
2070 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2071 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2072 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2073 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2074 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2075 }
2076}
2077
2078uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2079{
2080 uint32_t data;
2081
2082 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2083 r100_pll_errata_after_index(rdev);
2084 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2085 r100_pll_errata_after_data(rdev);
2086 return data;
2087}
2088
2089void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2090{
2091 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2092 r100_pll_errata_after_index(rdev);
2093 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2094 r100_pll_errata_after_data(rdev);
2095}
2096
d4550907 2097void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2098{
551ebd83
DA		 2099 if (ASIC_IS_RN50(rdev)) {
2100 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2101 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2102 } else if (rdev->family < CHIP_R200) {
2103 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2104 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2105 } else {
d4550907 2106 r200_set_safe_registers(rdev);
551ebd83 2107 }
068a117c
JG		 2108}
2109
771fe6b9
JG		 2110/*
2111 * Debugfs info
2112 */
2113#if defined(CONFIG_DEBUG_FS)
2114static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2115{
2116 struct drm_info_node *node = (struct drm_info_node *) m->private;
2117 struct drm_device *dev = node->minor->dev;
2118 struct radeon_device *rdev = dev->dev_private;
2119 uint32_t reg, value;
2120 unsigned i;
2121
2122 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2123 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2124 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2125 for (i = 0; i < 64; i++) {
2126 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2127 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2128 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2129 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2130 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2131 }
2132 return 0;
2133}
2134
2135static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2136{
2137 struct drm_info_node *node = (struct drm_info_node *) m->private;
2138 struct drm_device *dev = node->minor->dev;
2139 struct radeon_device *rdev = dev->dev_private;
2140 uint32_t rdp, wdp;
2141 unsigned count, i, j;
2142
2143 radeon_ring_free_size(rdev);
2144 rdp = RREG32(RADEON_CP_RB_RPTR);
2145 wdp = RREG32(RADEON_CP_RB_WPTR);
2146 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2147 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2148 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2149 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2150 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2151 seq_printf(m, "%u dwords in ring\n", count);
2152 for (j = 0; j <= count; j++) {
2153 i = (rdp + j) & rdev->cp.ptr_mask;
2154 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2155 }
2156 return 0;
2157}
2158
2159
2160static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2161{
2162 struct drm_info_node *node = (struct drm_info_node *) m->private;
2163 struct drm_device *dev = node->minor->dev;
2164 struct radeon_device *rdev = dev->dev_private;
2165 uint32_t csq_stat, csq2_stat, tmp;
2166 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2167 unsigned i;
2168
2169 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2170 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2171 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2172 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2173 r_rptr = (csq_stat >> 0) & 0x3ff;
2174 r_wptr = (csq_stat >> 10) & 0x3ff;
2175 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2176 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2177 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2178 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2179 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2180 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2181 seq_printf(m, "Ring rptr %u\n", r_rptr);
2182 seq_printf(m, "Ring wptr %u\n", r_wptr);
2183 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2184 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2185 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2186 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2187 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2188 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2189 seq_printf(m, "Ring fifo:\n");
2190 for (i = 0; i < 256; i++) {
2191 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2192 tmp = RREG32(RADEON_CP_CSQ_DATA);
2193 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2194 }
2195 seq_printf(m, "Indirect1 fifo:\n");
2196 for (i = 256; i <= 512; i++) {
2197 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2198 tmp = RREG32(RADEON_CP_CSQ_DATA);
2199 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2200 }
2201 seq_printf(m, "Indirect2 fifo:\n");
2202 for (i = 640; i < ib1_wptr; i++) {
2203 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2204 tmp = RREG32(RADEON_CP_CSQ_DATA);
2205 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2206 }
2207 return 0;
2208}
2209
2210static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2211{
2212 struct drm_info_node *node = (struct drm_info_node *) m->private;
2213 struct drm_device *dev = node->minor->dev;
2214 struct radeon_device *rdev = dev->dev_private;
2215 uint32_t tmp;
2216
2217 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2218 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2219 tmp = RREG32(RADEON_MC_FB_LOCATION);
2220 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2221 tmp = RREG32(RADEON_BUS_CNTL);
2222 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2223 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2224 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2225 tmp = RREG32(RADEON_AGP_BASE);
2226 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2227 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2228 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2229 tmp = RREG32(0x01D0);
2230 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2231 tmp = RREG32(RADEON_AIC_LO_ADDR);
2232 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2233 tmp = RREG32(RADEON_AIC_HI_ADDR);
2234 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2235 tmp = RREG32(0x01E4);
2236 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2237 return 0;
2238}
2239
2240static struct drm_info_list r100_debugfs_rbbm_list[] = {
2241 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2242};
2243
2244static struct drm_info_list r100_debugfs_cp_list[] = {
2245 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2246 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2247};
2248
2249static struct drm_info_list r100_debugfs_mc_info_list[] = {
2250 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2251};
2252#endif
2253
2254int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2255{
2256#if defined(CONFIG_DEBUG_FS)
2257 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2258#else
2259 return 0;
2260#endif
2261}
2262
2263int r100_debugfs_cp_init(struct radeon_device *rdev)
2264{
2265#if defined(CONFIG_DEBUG_FS)
2266 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2267#else
2268 return 0;
2269#endif
2270}
2271
2272int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2273{
2274#if defined(CONFIG_DEBUG_FS)
2275 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2276#else
2277 return 0;
2278#endif
2279}
e024e110
DA		 2280
2281int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2282 uint32_t tiling_flags, uint32_t pitch,
2283 uint32_t offset, uint32_t obj_size)
2284{
2285 int surf_index = reg * 16;
2286 int flags = 0;
2287
2288 /* r100/r200 divide by 16 */
2289 if (rdev->family < CHIP_R300)
2290 flags = pitch / 16;
2291 else
2292 flags = pitch / 8;
2293
2294 if (rdev->family <= CHIP_RS200) {
2295 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2296 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2297 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2298 if (tiling_flags & RADEON_TILING_MACRO)
2299 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2300 } else if (rdev->family <= CHIP_RV280) {
2301 if (tiling_flags & (RADEON_TILING_MACRO))
2302 flags |= R200_SURF_TILE_COLOR_MACRO;
2303 if (tiling_flags & RADEON_TILING_MICRO)
2304 flags |= R200_SURF_TILE_COLOR_MICRO;
2305 } else {
2306 if (tiling_flags & RADEON_TILING_MACRO)
2307 flags |= R300_SURF_TILE_MACRO;
2308 if (tiling_flags & RADEON_TILING_MICRO)
2309 flags |= R300_SURF_TILE_MICRO;
2310 }
2311
c88f9f0c
MD		 2312 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2313 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2314 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2315 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2316
e024e110
DA		 2317 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2318 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2319 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2320 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2321 return 0;
2322}
2323
2324void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2325{
2326 int surf_index = reg * 16;
2327 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2328}
c93bb85b
JG		 2329
2330void r100_bandwidth_update(struct radeon_device *rdev)
2331{
2332 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2333 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2334 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2335 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2336 fixed20_12 memtcas_ff[8] = {
2337 fixed_init(1),
2338 fixed_init(2),
2339 fixed_init(3),
2340 fixed_init(0),
2341 fixed_init_half(1),
2342 fixed_init_half(2),
2343 fixed_init(0),
2344 };
2345 fixed20_12 memtcas_rs480_ff[8] = {
2346 fixed_init(0),
2347 fixed_init(1),
2348 fixed_init(2),
2349 fixed_init(3),
2350 fixed_init(0),
2351 fixed_init_half(1),
2352 fixed_init_half(2),
2353 fixed_init_half(3),
2354 };
2355 fixed20_12 memtcas2_ff[8] = {
2356 fixed_init(0),
2357 fixed_init(1),
2358 fixed_init(2),
2359 fixed_init(3),
2360 fixed_init(4),
2361 fixed_init(5),
2362 fixed_init(6),
2363 fixed_init(7),
2364 };
2365 fixed20_12 memtrbs[8] = {
2366 fixed_init(1),
2367 fixed_init_half(1),
2368 fixed_init(2),
2369 fixed_init_half(2),
2370 fixed_init(3),
2371 fixed_init_half(3),
2372 fixed_init(4),
2373 fixed_init_half(4)
2374 };
2375 fixed20_12 memtrbs_r4xx[8] = {
2376 fixed_init(4),
2377 fixed_init(5),
2378 fixed_init(6),
2379 fixed_init(7),
2380 fixed_init(8),
2381 fixed_init(9),
2382 fixed_init(10),
2383 fixed_init(11)
2384 };
2385 fixed20_12 min_mem_eff;
2386 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2387 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2388 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2389 disp_drain_rate2, read_return_rate;
2390 fixed20_12 time_disp1_drop_priority;
2391 int c;
2392 int cur_size = 16; /* in octawords */
2393 int critical_point = 0, critical_point2;
2394/* uint32_t read_return_rate, time_disp1_drop_priority; */
2395 int stop_req, max_stop_req;
2396 struct drm_display_mode *mode1 = NULL;
2397 struct drm_display_mode *mode2 = NULL;
2398 uint32_t pixel_bytes1 = 0;
2399 uint32_t pixel_bytes2 = 0;
2400
f46c0120
AD		 2401 radeon_update_display_priority(rdev);
2402
c93bb85b
JG		 2403 if (rdev->mode_info.crtcs[0]->base.enabled) {
2404 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2405 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2406 }
dfee5614
DA		 2407 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2408 if (rdev->mode_info.crtcs[1]->base.enabled) {
2409 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2410 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2411 }
c93bb85b
JG		 2412 }
2413
2414 min_mem_eff.full = rfixed_const_8(0);
2415 /* get modes */
2416 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2417 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2418 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2419 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2420 /* check crtc enables */
2421 if (mode2)
2422 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2423 if (mode1)
2424 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2425 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2426 }
2427
2428 /*
2429 * determine is there is enough bw for current mode
2430 */
f47299c5
AD		 2431 sclk_ff = rdev->pm.sclk;
2432 mclk_ff = rdev->pm.mclk;
c93bb85b
JG		 2433
2434 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2435 temp_ff.full = rfixed_const(temp);
2436 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2437
2438 pix_clk.full = 0;
2439 pix_clk2.full = 0;
2440 peak_disp_bw.full = 0;
2441 if (mode1) {
2442 temp_ff.full = rfixed_const(1000);
2443 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2444 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2445 temp_ff.full = rfixed_const(pixel_bytes1);
2446 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2447 }
2448 if (mode2) {
2449 temp_ff.full = rfixed_const(1000);
2450 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2451 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2452 temp_ff.full = rfixed_const(pixel_bytes2);
2453 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2454 }
2455
2456 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2457 if (peak_disp_bw.full >= mem_bw.full) {
2458 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2459 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2460 }
2461
2462 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2463 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2464 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2465 mem_trcd = ((temp >> 2) & 0x3) + 1;
2466 mem_trp = ((temp & 0x3)) + 1;
2467 mem_tras = ((temp & 0x70) >> 4) + 1;
2468 } else if (rdev->family == CHIP_R300 ||
2469 rdev->family == CHIP_R350) { /* r300, r350 */
2470 mem_trcd = (temp & 0x7) + 1;
2471 mem_trp = ((temp >> 8) & 0x7) + 1;
2472 mem_tras = ((temp >> 11) & 0xf) + 4;
2473 } else if (rdev->family == CHIP_RV350 ||
2474 rdev->family <= CHIP_RV380) {
2475 /* rv3x0 */
2476 mem_trcd = (temp & 0x7) + 3;
2477 mem_trp = ((temp >> 8) & 0x7) + 3;
2478 mem_tras = ((temp >> 11) & 0xf) + 6;
2479 } else if (rdev->family == CHIP_R420 ||
2480 rdev->family == CHIP_R423 ||
2481 rdev->family == CHIP_RV410) {
2482 /* r4xx */
2483 mem_trcd = (temp & 0xf) + 3;
2484 if (mem_trcd > 15)
2485 mem_trcd = 15;
2486 mem_trp = ((temp >> 8) & 0xf) + 3;
2487 if (mem_trp > 15)
2488 mem_trp = 15;
2489 mem_tras = ((temp >> 12) & 0x1f) + 6;
2490 if (mem_tras > 31)
2491 mem_tras = 31;
2492 } else { /* RV200, R200 */
2493 mem_trcd = (temp & 0x7) + 1;
2494 mem_trp = ((temp >> 8) & 0x7) + 1;
2495 mem_tras = ((temp >> 12) & 0xf) + 4;
2496 }
2497 /* convert to FF */
2498 trcd_ff.full = rfixed_const(mem_trcd);
2499 trp_ff.full = rfixed_const(mem_trp);
2500 tras_ff.full = rfixed_const(mem_tras);
2501
2502 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2503 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2504 data = (temp & (7 << 20)) >> 20;
2505 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2506 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2507 tcas_ff = memtcas_rs480_ff[data];
2508 else
2509 tcas_ff = memtcas_ff[data];
2510 } else
2511 tcas_ff = memtcas2_ff[data];
2512
2513 if (rdev->family == CHIP_RS400 ||
2514 rdev->family == CHIP_RS480) {
2515 /* extra cas latency stored in bits 23-25 0-4 clocks */
2516 data = (temp >> 23) & 0x7;
2517 if (data < 5)
2518 tcas_ff.full += rfixed_const(data);
2519 }
2520
2521 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2522 /* on the R300, Tcas is included in Trbs.
2523 */
2524 temp = RREG32(RADEON_MEM_CNTL);
2525 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2526 if (data == 1) {
2527 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2528 temp = RREG32(R300_MC_IND_INDEX);
2529 temp &= ~R300_MC_IND_ADDR_MASK;
2530 temp |= R300_MC_READ_CNTL_CD_mcind;
2531 WREG32(R300_MC_IND_INDEX, temp);
2532 temp = RREG32(R300_MC_IND_DATA);
2533 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2534 } else {
2535 temp = RREG32(R300_MC_READ_CNTL_AB);
2536 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2537 }
2538 } else {
2539 temp = RREG32(R300_MC_READ_CNTL_AB);
2540 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2541 }
2542 if (rdev->family == CHIP_RV410 ||
2543 rdev->family == CHIP_R420 ||
2544 rdev->family == CHIP_R423)
2545 trbs_ff = memtrbs_r4xx[data];
2546 else
2547 trbs_ff = memtrbs[data];
2548 tcas_ff.full += trbs_ff.full;
2549 }
2550
2551 sclk_eff_ff.full = sclk_ff.full;
2552
2553 if (rdev->flags & RADEON_IS_AGP) {
2554 fixed20_12 agpmode_ff;
2555 agpmode_ff.full = rfixed_const(radeon_agpmode);
2556 temp_ff.full = rfixed_const_666(16);
2557 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2558 }
2559 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2560
2561 if (ASIC_IS_R300(rdev)) {
2562 sclk_delay_ff.full = rfixed_const(250);
2563 } else {
2564 if ((rdev->family == CHIP_RV100) ||
2565 rdev->flags & RADEON_IS_IGP) {
2566 if (rdev->mc.vram_is_ddr)
2567 sclk_delay_ff.full = rfixed_const(41);
2568 else
2569 sclk_delay_ff.full = rfixed_const(33);
2570 } else {
2571 if (rdev->mc.vram_width == 128)
2572 sclk_delay_ff.full = rfixed_const(57);
2573 else
2574 sclk_delay_ff.full = rfixed_const(41);
2575 }
2576 }
2577
2578 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2579
2580 if (rdev->mc.vram_is_ddr) {
2581 if (rdev->mc.vram_width == 32) {
2582 k1.full = rfixed_const(40);
2583 c = 3;
2584 } else {
2585 k1.full = rfixed_const(20);
2586 c = 1;
2587 }
2588 } else {
2589 k1.full = rfixed_const(40);
2590 c = 3;
2591 }
2592
2593 temp_ff.full = rfixed_const(2);
2594 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2595 temp_ff.full = rfixed_const(c);
2596 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2597 temp_ff.full = rfixed_const(4);
2598 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2599 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2600 mc_latency_mclk.full += k1.full;
2601
2602 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2603 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2604
2605 /*
2606 HW cursor time assuming worst case of full size colour cursor.
2607 */
2608 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2609 temp_ff.full += trcd_ff.full;
2610 if (temp_ff.full < tras_ff.full)
2611 temp_ff.full = tras_ff.full;
2612 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2613
2614 temp_ff.full = rfixed_const(cur_size);
2615 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2616 /*
2617 Find the total latency for the display data.
2618 */
b5fc9010 2619 disp_latency_overhead.full = rfixed_const(8);
c93bb85b
JG		 2620 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2621 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2622 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2623
2624 if (mc_latency_mclk.full > mc_latency_sclk.full)
2625 disp_latency.full = mc_latency_mclk.full;
2626 else
2627 disp_latency.full = mc_latency_sclk.full;
2628
2629 /* setup Max GRPH_STOP_REQ default value */
2630 if (ASIC_IS_RV100(rdev))
2631 max_stop_req = 0x5c;
2632 else
2633 max_stop_req = 0x7c;
2634
2635 if (mode1) {
2636 /* CRTC1
2637 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2638 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2639 */
2640 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2641
2642 if (stop_req > max_stop_req)
2643 stop_req = max_stop_req;
2644
2645 /*
2646 Find the drain rate of the display buffer.
2647 */
2648 temp_ff.full = rfixed_const((16/pixel_bytes1));
2649 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2650
2651 /*
2652 Find the critical point of the display buffer.
2653 */
2654 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2655 crit_point_ff.full += rfixed_const_half(0);
2656
2657 critical_point = rfixed_trunc(crit_point_ff);
2658
2659 if (rdev->disp_priority == 2) {
2660 critical_point = 0;
2661 }
2662
2663 /*
2664 The critical point should never be above max_stop_req-4. Setting
2665 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2666 */
2667 if (max_stop_req - critical_point < 4)
2668 critical_point = 0;
2669
2670 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2671 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2672 critical_point = 0x10;
2673 }
2674
2675 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2676 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2677 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2678 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2679 if ((rdev->family == CHIP_R350) &&
2680 (stop_req > 0x15)) {
2681 stop_req -= 0x10;
2682 }
2683 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2684 temp |= RADEON_GRPH_BUFFER_SIZE;
2685 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2686 RADEON_GRPH_CRITICAL_AT_SOF |
2687 RADEON_GRPH_STOP_CNTL);
2688 /*
2689 Write the result into the register.
2690 */
2691 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2692 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2693
2694#if 0
2695 if ((rdev->family == CHIP_RS400) ||
2696 (rdev->family == CHIP_RS480)) {
2697 /* attempt to program RS400 disp regs correctly ??? */
2698 temp = RREG32(RS400_DISP1_REG_CNTL);
2699 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2700 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2701 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2702 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2703 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2704 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2705 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2706 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2707 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2708 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2709 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2710 }
2711#endif
2712
2713 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2714 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2715 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2716 }
2717
2718 if (mode2) {
2719 u32 grph2_cntl;
2720 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2721
2722 if (stop_req > max_stop_req)
2723 stop_req = max_stop_req;
2724
2725 /*
2726 Find the drain rate of the display buffer.
2727 */
2728 temp_ff.full = rfixed_const((16/pixel_bytes2));
2729 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2730
2731 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2732 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2733 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2734 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2735 if ((rdev->family == CHIP_R350) &&
2736 (stop_req > 0x15)) {
2737 stop_req -= 0x10;
2738 }
2739 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2740 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2741 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2742 RADEON_GRPH_CRITICAL_AT_SOF |
2743 RADEON_GRPH_STOP_CNTL);
2744
2745 if ((rdev->family == CHIP_RS100) ||
2746 (rdev->family == CHIP_RS200))
2747 critical_point2 = 0;
2748 else {
2749 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2750 temp_ff.full = rfixed_const(temp);
2751 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2752 if (sclk_ff.full < temp_ff.full)
2753 temp_ff.full = sclk_ff.full;
2754
2755 read_return_rate.full = temp_ff.full;
2756
2757 if (mode1) {
2758 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2759 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2760 } else {
2761 time_disp1_drop_priority.full = 0;
2762 }
2763 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2764 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2765 crit_point_ff.full += rfixed_const_half(0);
2766
2767 critical_point2 = rfixed_trunc(crit_point_ff);
2768
2769 if (rdev->disp_priority == 2) {
2770 critical_point2 = 0;
2771 }
2772
2773 if (max_stop_req - critical_point2 < 4)
2774 critical_point2 = 0;
2775
2776 }
2777
2778 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2779 /* some R300 cards have problem with this set to 0 */
2780 critical_point2 = 0x10;
2781 }
2782
2783 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2784 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2785
2786 if ((rdev->family == CHIP_RS400) ||
2787 (rdev->family == CHIP_RS480)) {
2788#if 0
2789 /* attempt to program RS400 disp2 regs correctly ??? */
2790 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2791 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2792 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2793 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2794 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2795 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2796 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2797 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2798 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2799 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2800 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2801 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2802#endif
2803 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2804 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2805 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2806 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2807 }
2808
2809 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2810 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2811 }
2812}
551ebd83
DA		 2813
2814static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2815{
2816 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 2817 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 2818 DRM_ERROR("width %d\n", t->width);
ceb776bc 2819 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 2820 DRM_ERROR("height %d\n", t->height);
ceb776bc 2821 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 2822 DRM_ERROR("num levels %d\n", t->num_levels);
2823 DRM_ERROR("depth %d\n", t->txdepth);
2824 DRM_ERROR("bpp %d\n", t->cpp);
2825 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2826 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2827 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 2828 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 2829}
2830
2831static int r100_cs_track_cube(struct radeon_device *rdev,
2832 struct r100_cs_track *track, unsigned idx)
2833{
2834 unsigned face, w, h;
4c788679 2835 struct radeon_bo *cube_robj;
551ebd83
DA		 2836 unsigned long size;
2837
2838 for (face = 0; face < 5; face++) {
2839 cube_robj = track->textures[idx].cube_info[face].robj;
2840 w = track->textures[idx].cube_info[face].width;
2841 h = track->textures[idx].cube_info[face].height;
2842
2843 size = w * h;
2844 size *= track->textures[idx].cpp;
2845
2846 size += track->textures[idx].cube_info[face].offset;
2847
4c788679 2848 if (size > radeon_bo_size(cube_robj)) {
551ebd83 2849 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
4c788679 2850 size, radeon_bo_size(cube_robj));
551ebd83
DA		 2851 r100_cs_track_texture_print(&track->textures[idx]);
2852 return -1;
2853 }
2854 }
2855 return 0;
2856}
2857
d785d78b
DA		 2858static int r100_track_compress_size(int compress_format, int w, int h)
2859{
2860 int block_width, block_height, block_bytes;
2861 int wblocks, hblocks;
2862 int min_wblocks;
2863 int sz;
2864
2865 block_width = 4;
2866 block_height = 4;
2867
2868 switch (compress_format) {
2869 case R100_TRACK_COMP_DXT1:
2870 block_bytes = 8;
2871 min_wblocks = 4;
2872 break;
2873 default:
2874 case R100_TRACK_COMP_DXT35:
2875 block_bytes = 16;
2876 min_wblocks = 2;
2877 break;
2878 }
2879
2880 hblocks = (h + block_height - 1) / block_height;
2881 wblocks = (w + block_width - 1) / block_width;
2882 if (wblocks < min_wblocks)
2883 wblocks = min_wblocks;
2884 sz = wblocks * hblocks * block_bytes;
2885 return sz;
2886}
2887
551ebd83
DA		 2888static int r100_cs_track_texture_check(struct radeon_device *rdev,
2889 struct r100_cs_track *track)
2890{
4c788679 2891 struct radeon_bo *robj;
551ebd83
DA		 2892 unsigned long size;
2893 unsigned u, i, w, h;
2894 int ret;
2895
2896 for (u = 0; u < track->num_texture; u++) {
2897 if (!track->textures[u].enabled)
2898 continue;
2899 robj = track->textures[u].robj;
2900 if (robj == NULL) {
2901 DRM_ERROR("No texture bound to unit %u\n", u);
2902 return -EINVAL;
2903 }
2904 size = 0;
2905 for (i = 0; i <= track->textures[u].num_levels; i++) {
2906 if (track->textures[u].use_pitch) {
2907 if (rdev->family < CHIP_R300)
2908 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2909 else
2910 w = track->textures[u].pitch / (1 << i);
2911 } else {
ceb776bc 2912 w = track->textures[u].width;
551ebd83
DA		 2913 if (rdev->family >= CHIP_RV515)
2914 w |= track->textures[u].width_11;
ceb776bc 2915 w = w / (1 << i);
551ebd83
DA		 2916 if (track->textures[u].roundup_w)
2917 w = roundup_pow_of_two(w);
2918 }
ceb776bc 2919 h = track->textures[u].height;
551ebd83
DA		 2920 if (rdev->family >= CHIP_RV515)
2921 h |= track->textures[u].height_11;
ceb776bc 2922 h = h / (1 << i);
551ebd83
DA		 2923 if (track->textures[u].roundup_h)
2924 h = roundup_pow_of_two(h);
d785d78b
DA		 2925 if (track->textures[u].compress_format) {
2926
2927 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2928 /* compressed textures are block based */
2929 } else
2930 size += w * h;
551ebd83
DA		 2931 }
2932 size *= track->textures[u].cpp;
d785d78b 2933
551ebd83
DA		 2934 switch (track->textures[u].tex_coord_type) {
2935 case 0:
2936 break;
2937 case 1:
2938 size *= (1 << track->textures[u].txdepth);
2939 break;
2940 case 2:
2941 if (track->separate_cube) {
2942 ret = r100_cs_track_cube(rdev, track, u);
2943 if (ret)
2944 return ret;
2945 } else
2946 size *= 6;
2947 break;
2948 default:
2949 DRM_ERROR("Invalid texture coordinate type %u for unit "
2950 "%u\n", track->textures[u].tex_coord_type, u);
2951 return -EINVAL;
2952 }
4c788679 2953 if (size > radeon_bo_size(robj)) {
551ebd83 2954 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 2955 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 2956 r100_cs_track_texture_print(&track->textures[u]);
2957 return -EINVAL;
2958 }
2959 }
2960 return 0;
2961}
2962
2963int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2964{
2965 unsigned i;
2966 unsigned long size;
2967 unsigned prim_walk;
2968 unsigned nverts;
2969
2970 for (i = 0; i < track->num_cb; i++) {
2971 if (track->cb[i].robj == NULL) {
46c64d4b
MO		 2972 if (!(track->fastfill || track->color_channel_mask ||
2973 track->blend_read_enable)) {
2974 continue;
2975 }
551ebd83
DA		 2976 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2977 return -EINVAL;
2978 }
2979 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2980 size += track->cb[i].offset;
4c788679 2981 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 2982 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2983 "(need %lu have %lu) !\n", i, size,
4c788679 2984 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 2985 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2986 i, track->cb[i].pitch, track->cb[i].cpp,
2987 track->cb[i].offset, track->maxy);
2988 return -EINVAL;
2989 }
2990 }
2991 if (track->z_enabled) {
2992 if (track->zb.robj == NULL) {
2993 DRM_ERROR("[drm] No buffer for z buffer !\n");
2994 return -EINVAL;
2995 }
2996 size = track->zb.pitch * track->zb.cpp * track->maxy;
2997 size += track->zb.offset;
4c788679 2998 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 2999 DRM_ERROR("[drm] Buffer too small for z buffer "
3000 "(need %lu have %lu) !\n", size,
4c788679 3001 radeon_bo_size(track->zb.robj));
551ebd83
DA		 3002 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3003 track->zb.pitch, track->zb.cpp,
3004 track->zb.offset, track->maxy);
3005 return -EINVAL;
3006 }
3007 }
3008 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3009 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3010 switch (prim_walk) {
3011 case 1:
3012 for (i = 0; i < track->num_arrays; i++) {
3013 size = track->arrays[i].esize * track->max_indx * 4;
3014 if (track->arrays[i].robj == NULL) {
3015 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3016 "bound\n", prim_walk, i);
3017 return -EINVAL;
3018 }
4c788679
JG		 3019 if (size > radeon_bo_size(track->arrays[i].robj)) {
3020 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3021 "need %lu dwords have %lu dwords\n",
3022 prim_walk, i, size >> 2,
3023 radeon_bo_size(track->arrays[i].robj)
3024 >> 2);
551ebd83
DA		 3025 DRM_ERROR("Max indices %u\n", track->max_indx);
3026 return -EINVAL;
3027 }
3028 }
3029 break;
3030 case 2:
3031 for (i = 0; i < track->num_arrays; i++) {
3032 size = track->arrays[i].esize * (nverts - 1) * 4;
3033 if (track->arrays[i].robj == NULL) {
3034 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3035 "bound\n", prim_walk, i);
3036 return -EINVAL;
3037 }
4c788679
JG		 3038 if (size > radeon_bo_size(track->arrays[i].robj)) {
3039 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3040 "need %lu dwords have %lu dwords\n",
3041 prim_walk, i, size >> 2,
3042 radeon_bo_size(track->arrays[i].robj)
3043 >> 2);
551ebd83
DA		 3044 return -EINVAL;
3045 }
3046 }
3047 break;
3048 case 3:
3049 size = track->vtx_size * nverts;
3050 if (size != track->immd_dwords) {
3051 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3052 track->immd_dwords, size);
3053 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3054 nverts, track->vtx_size);
3055 return -EINVAL;
3056 }
3057 break;
3058 default:
3059 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3060 prim_walk);
3061 return -EINVAL;
3062 }
3063 return r100_cs_track_texture_check(rdev, track);
3064}
3065
3066void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3067{
3068 unsigned i, face;
3069
3070 if (rdev->family < CHIP_R300) {
3071 track->num_cb = 1;
3072 if (rdev->family <= CHIP_RS200)
3073 track->num_texture = 3;
3074 else
3075 track->num_texture = 6;
3076 track->maxy = 2048;
3077 track->separate_cube = 1;
3078 } else {
3079 track->num_cb = 4;
3080 track->num_texture = 16;
3081 track->maxy = 4096;
3082 track->separate_cube = 0;
3083 }
3084
3085 for (i = 0; i < track->num_cb; i++) {
3086 track->cb[i].robj = NULL;
3087 track->cb[i].pitch = 8192;
3088 track->cb[i].cpp = 16;
3089 track->cb[i].offset = 0;
3090 }
3091 track->z_enabled = true;
3092 track->zb.robj = NULL;
3093 track->zb.pitch = 8192;
3094 track->zb.cpp = 4;
3095 track->zb.offset = 0;
3096 track->vtx_size = 0x7F;
3097 track->immd_dwords = 0xFFFFFFFFUL;
3098 track->num_arrays = 11;
3099 track->max_indx = 0x00FFFFFFUL;
3100 for (i = 0; i < track->num_arrays; i++) {
3101 track->arrays[i].robj = NULL;
3102 track->arrays[i].esize = 0x7F;
3103 }
3104 for (i = 0; i < track->num_texture; i++) {
d785d78b 3105 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3106 track->textures[i].pitch = 16536;
3107 track->textures[i].width = 16536;
3108 track->textures[i].height = 16536;
3109 track->textures[i].width_11 = 1 << 11;
3110 track->textures[i].height_11 = 1 << 11;
3111 track->textures[i].num_levels = 12;
3112 if (rdev->family <= CHIP_RS200) {
3113 track->textures[i].tex_coord_type = 0;
3114 track->textures[i].txdepth = 0;
3115 } else {
3116 track->textures[i].txdepth = 16;
3117 track->textures[i].tex_coord_type = 1;
3118 }
3119 track->textures[i].cpp = 64;
3120 track->textures[i].robj = NULL;
3121 /* CS IB emission code makes sure texture unit are disabled */
3122 track->textures[i].enabled = false;
3123 track->textures[i].roundup_w = true;
3124 track->textures[i].roundup_h = true;
3125 if (track->separate_cube)
3126 for (face = 0; face < 5; face++) {
3127 track->textures[i].cube_info[face].robj = NULL;
3128 track->textures[i].cube_info[face].width = 16536;
3129 track->textures[i].cube_info[face].height = 16536;
3130 track->textures[i].cube_info[face].offset = 0;
3131 }
3132 }
3133}
3ce0a23d
JG		 3134
3135int r100_ring_test(struct radeon_device *rdev)
3136{
3137 uint32_t scratch;
3138 uint32_t tmp = 0;
3139 unsigned i;
3140 int r;
3141
3142 r = radeon_scratch_get(rdev, &scratch);
3143 if (r) {
3144 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3145 return r;
3146 }
3147 WREG32(scratch, 0xCAFEDEAD);
3148 r = radeon_ring_lock(rdev, 2);
3149 if (r) {
3150 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3151 radeon_scratch_free(rdev, scratch);
3152 return r;
3153 }
3154 radeon_ring_write(rdev, PACKET0(scratch, 0));
3155 radeon_ring_write(rdev, 0xDEADBEEF);
3156 radeon_ring_unlock_commit(rdev);
3157 for (i = 0; i < rdev->usec_timeout; i++) {
3158 tmp = RREG32(scratch);
3159 if (tmp == 0xDEADBEEF) {
3160 break;
3161 }
3162 DRM_UDELAY(1);
3163 }
3164 if (i < rdev->usec_timeout) {
3165 DRM_INFO("ring test succeeded in %d usecs\n", i);
3166 } else {
3167 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3168 scratch, tmp);
3169 r = -EINVAL;
3170 }
3171 radeon_scratch_free(rdev, scratch);
3172 return r;
3173}
3174
3175void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3176{
3177 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3178 radeon_ring_write(rdev, ib->gpu_addr);
3179 radeon_ring_write(rdev, ib->length_dw);
3180}
3181
3182int r100_ib_test(struct radeon_device *rdev)
3183{
3184 struct radeon_ib *ib;
3185 uint32_t scratch;
3186 uint32_t tmp = 0;
3187 unsigned i;
3188 int r;
3189
3190 r = radeon_scratch_get(rdev, &scratch);
3191 if (r) {
3192 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3193 return r;
3194 }
3195 WREG32(scratch, 0xCAFEDEAD);
3196 r = radeon_ib_get(rdev, &ib);
3197 if (r) {
3198 return r;
3199 }
3200 ib->ptr[0] = PACKET0(scratch, 0);
3201 ib->ptr[1] = 0xDEADBEEF;
3202 ib->ptr[2] = PACKET2(0);
3203 ib->ptr[3] = PACKET2(0);
3204 ib->ptr[4] = PACKET2(0);
3205 ib->ptr[5] = PACKET2(0);
3206 ib->ptr[6] = PACKET2(0);
3207 ib->ptr[7] = PACKET2(0);
3208 ib->length_dw = 8;
3209 r = radeon_ib_schedule(rdev, ib);
3210 if (r) {
3211 radeon_scratch_free(rdev, scratch);
3212 radeon_ib_free(rdev, &ib);
3213 return r;
3214 }
3215 r = radeon_fence_wait(ib->fence, false);
3216 if (r) {
3217 return r;
3218 }
3219 for (i = 0; i < rdev->usec_timeout; i++) {
3220 tmp = RREG32(scratch);
3221 if (tmp == 0xDEADBEEF) {
3222 break;
3223 }
3224 DRM_UDELAY(1);
3225 }
3226 if (i < rdev->usec_timeout) {
3227 DRM_INFO("ib test succeeded in %u usecs\n", i);
3228 } else {
3229 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3230 scratch, tmp);
3231 r = -EINVAL;
3232 }
3233 radeon_scratch_free(rdev, scratch);
3234 radeon_ib_free(rdev, &ib);
3235 return r;
3236}
9f022ddf
JG		 3237
3238void r100_ib_fini(struct radeon_device *rdev)
3239{
3240 radeon_ib_pool_fini(rdev);
3241}
3242
3243int r100_ib_init(struct radeon_device *rdev)
3244{
3245 int r;
3246
3247 r = radeon_ib_pool_init(rdev);
3248 if (r) {
3249 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3250 r100_ib_fini(rdev);
3251 return r;
3252 }
3253 r = r100_ib_test(rdev);
3254 if (r) {
3255 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3256 r100_ib_fini(rdev);
3257 return r;
3258 }
3259 return 0;
3260}
3261
3262void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3263{
3264 /* Shutdown CP we shouldn't need to do that but better be safe than
3265 * sorry
3266 */
3267 rdev->cp.ready = false;
3268 WREG32(R_000740_CP_CSQ_CNTL, 0);
3269
3270 /* Save few CRTC registers */
ca6ffc64 3271 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3272 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3273 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3274 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3275 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3276 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3277 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3278 }
3279
3280 /* Disable VGA aperture access */
ca6ffc64 3281 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3282 /* Disable cursor, overlay, crtc */
3283 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3284 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3285 S_000054_CRTC_DISPLAY_DIS(1));
3286 WREG32(R_000050_CRTC_GEN_CNTL,
3287 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3288 S_000050_CRTC_DISP_REQ_EN_B(1));
3289 WREG32(R_000420_OV0_SCALE_CNTL,
3290 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3291 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3292 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3293 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3294 S_000360_CUR2_LOCK(1));
3295 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3296 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3297 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3298 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3299 WREG32(R_000360_CUR2_OFFSET,
3300 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3301 }
3302}
3303
3304void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3305{
3306 /* Update base address for crtc */
d594e46a 3307 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3308 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3309 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3310 }
3311 /* Restore CRTC registers */
ca6ffc64 3312 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3313 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3314 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3315 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3316 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3317 }
3318}
ca6ffc64
JG		 3319
3320void r100_vga_render_disable(struct radeon_device *rdev)
3321{
d4550907 3322 u32 tmp;
ca6ffc64 3323
d4550907 3324 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3325 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3326}
d4550907
JG		 3327
3328static void r100_debugfs(struct radeon_device *rdev)
3329{
3330 int r;
3331
3332 r = r100_debugfs_mc_info_init(rdev);
3333 if (r)
3334 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3335}
3336
3337static void r100_mc_program(struct radeon_device *rdev)
3338{
3339 struct r100_mc_save save;
3340
3341 /* Stops all mc clients */
3342 r100_mc_stop(rdev, &save);
3343 if (rdev->flags & RADEON_IS_AGP) {
3344 WREG32(R_00014C_MC_AGP_LOCATION,
3345 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3346 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3347 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3348 if (rdev->family > CHIP_RV200)
3349 WREG32(R_00015C_AGP_BASE_2,
3350 upper_32_bits(rdev->mc.agp_base) & 0xff);
3351 } else {
3352 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3353 WREG32(R_000170_AGP_BASE, 0);
3354 if (rdev->family > CHIP_RV200)
3355 WREG32(R_00015C_AGP_BASE_2, 0);
3356 }
3357 /* Wait for mc idle */
3358 if (r100_mc_wait_for_idle(rdev))
3359 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3360 /* Program MC, should be a 32bits limited address space */
3361 WREG32(R_000148_MC_FB_LOCATION,
3362 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3363 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3364 r100_mc_resume(rdev, &save);
3365}
3366
3367void r100_clock_startup(struct radeon_device *rdev)
3368{
3369 u32 tmp;
3370
3371 if (radeon_dynclks != -1 && radeon_dynclks)
3372 radeon_legacy_set_clock_gating(rdev, 1);
3373 /* We need to force on some of the block */
3374 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3375 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3376 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3377 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3378 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3379}
3380
3381static int r100_startup(struct radeon_device *rdev)
3382{
3383 int r;
3384
92cde00c
AD		 3385 /* set common regs */
3386 r100_set_common_regs(rdev);
3387 /* program mc */
d4550907
JG		 3388 r100_mc_program(rdev);
3389 /* Resume clock */
3390 r100_clock_startup(rdev);
3391 /* Initialize GPU configuration (# pipes, ...) */
3392 r100_gpu_init(rdev);
3393 /* Initialize GART (initialize after TTM so we can allocate
3394 * memory through TTM but finalize after TTM) */
17e15b0c 3395 r100_enable_bm(rdev);
d4550907
JG		 3396 if (rdev->flags & RADEON_IS_PCI) {
3397 r = r100_pci_gart_enable(rdev);
3398 if (r)
3399 return r;
3400 }
3401 /* Enable IRQ */
d4550907 3402 r100_irq_set(rdev);
cafe6609 3403 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3404 /* 1M ring buffer */
3405 r = r100_cp_init(rdev, 1024 * 1024);
3406 if (r) {
3407 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3408 return r;
3409 }
3410 r = r100_wb_init(rdev);
3411 if (r)
3412 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3413 r = r100_ib_init(rdev);
3414 if (r) {
3415 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3416 return r;
3417 }
3418 return 0;
3419}
3420
3421int r100_resume(struct radeon_device *rdev)
3422{
3423 /* Make sur GART are not working */
3424 if (rdev->flags & RADEON_IS_PCI)
3425 r100_pci_gart_disable(rdev);
3426 /* Resume clock before doing reset */
3427 r100_clock_startup(rdev);
3428 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3429 if (radeon_gpu_reset(rdev)) {
3430 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3431 RREG32(R_000E40_RBBM_STATUS),
3432 RREG32(R_0007C0_CP_STAT));
3433 }
3434 /* post */
3435 radeon_combios_asic_init(rdev->ddev);
3436 /* Resume clock after posting */
3437 r100_clock_startup(rdev);
550e2d92
DA		 3438 /* Initialize surface registers */
3439 radeon_surface_init(rdev);
d4550907
JG		 3440 return r100_startup(rdev);
3441}
3442
3443int r100_suspend(struct radeon_device *rdev)
3444{
3445 r100_cp_disable(rdev);
3446 r100_wb_disable(rdev);
3447 r100_irq_disable(rdev);
3448 if (rdev->flags & RADEON_IS_PCI)
3449 r100_pci_gart_disable(rdev);
3450 return 0;
3451}
3452
3453void r100_fini(struct radeon_device *rdev)
3454{
29fb52ca 3455 radeon_pm_fini(rdev);
d4550907
JG		 3456 r100_cp_fini(rdev);
3457 r100_wb_fini(rdev);
3458 r100_ib_fini(rdev);
3459 radeon_gem_fini(rdev);
3460 if (rdev->flags & RADEON_IS_PCI)
3461 r100_pci_gart_fini(rdev);
d0269ed8 3462 radeon_agp_fini(rdev);
d4550907
JG		 3463 radeon_irq_kms_fini(rdev);
3464 radeon_fence_driver_fini(rdev);
4c788679 3465 radeon_bo_fini(rdev);
d4550907
JG		 3466 radeon_atombios_fini(rdev);
3467 kfree(rdev->bios);
3468 rdev->bios = NULL;
3469}
3470
d4550907
JG		 3471int r100_init(struct radeon_device *rdev)
3472{
3473 int r;
3474
d4550907
JG		 3475 /* Register debugfs file specific to this group of asics */
3476 r100_debugfs(rdev);
3477 /* Disable VGA */
3478 r100_vga_render_disable(rdev);
3479 /* Initialize scratch registers */
3480 radeon_scratch_init(rdev);
3481 /* Initialize surface registers */
3482 radeon_surface_init(rdev);
3483 /* TODO: disable VGA need to use VGA request */
3484 /* BIOS*/
3485 if (!radeon_get_bios(rdev)) {
3486 if (ASIC_IS_AVIVO(rdev))
3487 return -EINVAL;
3488 }
3489 if (rdev->is_atom_bios) {
3490 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3491 return -EINVAL;
3492 } else {
3493 r = radeon_combios_init(rdev);
3494 if (r)
3495 return r;
3496 }
3497 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3498 if (radeon_gpu_reset(rdev)) {
3499 dev_warn(rdev->dev,
3500 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3501 RREG32(R_000E40_RBBM_STATUS),
3502 RREG32(R_0007C0_CP_STAT));
3503 }
3504 /* check if cards are posted or not */
72542d77
DA		 3505 if (radeon_boot_test_post_card(rdev) == false)
3506 return -EINVAL;
d4550907
JG		 3507 /* Set asic errata */
3508 r100_errata(rdev);
3509 /* Initialize clocks */
3510 radeon_get_clock_info(rdev->ddev);
6234077d
RM		 3511 /* Initialize power management */
3512 radeon_pm_init(rdev);
d594e46a
JG		 3513 /* initialize AGP */
3514 if (rdev->flags & RADEON_IS_AGP) {
3515 r = radeon_agp_init(rdev);
3516 if (r) {
3517 radeon_agp_disable(rdev);
3518 }
3519 }
3520 /* initialize VRAM */
3521 r100_mc_init(rdev);
d4550907
JG		 3522 /* Fence driver */
3523 r = radeon_fence_driver_init(rdev);
3524 if (r)
3525 return r;
3526 r = radeon_irq_kms_init(rdev);
3527 if (r)
3528 return r;
3529 /* Memory manager */
4c788679 3530 r = radeon_bo_init(rdev);
d4550907
JG		 3531 if (r)
3532 return r;
3533 if (rdev->flags & RADEON_IS_PCI) {
3534 r = r100_pci_gart_init(rdev);
3535 if (r)
3536 return r;
3537 }
3538 r100_set_safe_registers(rdev);
3539 rdev->accel_working = true;
3540 r = r100_startup(rdev);
3541 if (r) {
3542 /* Somethings want wront with the accel init stop accel */
3543 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907
JG		 3544 r100_cp_fini(rdev);
3545 r100_wb_fini(rdev);
3546 r100_ib_fini(rdev);
655efd3d 3547 radeon_irq_kms_fini(rdev);
d4550907
JG		 3548 if (rdev->flags & RADEON_IS_PCI)
3549 r100_pci_gart_fini(rdev);
d4550907
JG		 3550 rdev->accel_working = false;
3551 }
3552 return 0;
3553}
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