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drm/radeon/kms: enable memory clock reading on legacy (V2)
[net-next-2.6.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
3ce0a23d 34#include "r100d.h"
d4550907
JG		 35#include "rs100d.h"
36#include "rv200d.h"
37#include "rv250d.h"
3ce0a23d 38
70967ab9
BH		 39#include <linux/firmware.h>
40#include <linux/platform_device.h>
41
551ebd83
DA		 42#include "r100_reg_safe.h"
43#include "rn50_reg_safe.h"
44
70967ab9
BH		 45/* Firmware Names */
46#define FIRMWARE_R100 "radeon/R100_cp.bin"
47#define FIRMWARE_R200 "radeon/R200_cp.bin"
48#define FIRMWARE_R300 "radeon/R300_cp.bin"
49#define FIRMWARE_R420 "radeon/R420_cp.bin"
50#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52#define FIRMWARE_R520 "radeon/R520_cp.bin"
53
54MODULE_FIRMWARE(FIRMWARE_R100);
55MODULE_FIRMWARE(FIRMWARE_R200);
56MODULE_FIRMWARE(FIRMWARE_R300);
57MODULE_FIRMWARE(FIRMWARE_R420);
58MODULE_FIRMWARE(FIRMWARE_RS690);
59MODULE_FIRMWARE(FIRMWARE_RS600);
60MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 61
551ebd83
DA		 62#include "r100_track.h"
63
771fe6b9
JG		 64/* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 66 */
771fe6b9 67
05a05c50
AD		 68/* hpd for digital panel detect/disconnect */
69bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
70{
71 bool connected = false;
72
73 switch (hpd) {
74 case RADEON_HPD_1:
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
76 connected = true;
77 break;
78 case RADEON_HPD_2:
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
80 connected = true;
81 break;
82 default:
83 break;
84 }
85 return connected;
86}
87
88void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
90{
91 u32 tmp;
92 bool connected = r100_hpd_sense(rdev, hpd);
93
94 switch (hpd) {
95 case RADEON_HPD_1:
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
97 if (connected)
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
99 else
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
102 break;
103 case RADEON_HPD_2:
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
105 if (connected)
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
107 else
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
110 break;
111 default:
112 break;
113 }
114}
115
116void r100_hpd_init(struct radeon_device *rdev)
117{
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
120
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
124 case RADEON_HPD_1:
125 rdev->irq.hpd[0] = true;
126 break;
127 case RADEON_HPD_2:
128 rdev->irq.hpd[1] = true;
129 break;
130 default:
131 break;
132 }
133 }
134 r100_irq_set(rdev);
135}
136
137void r100_hpd_fini(struct radeon_device *rdev)
138{
139 struct drm_device *dev = rdev->ddev;
140 struct drm_connector *connector;
141
142 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
143 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
144 switch (radeon_connector->hpd.hpd) {
145 case RADEON_HPD_1:
146 rdev->irq.hpd[0] = false;
147 break;
148 case RADEON_HPD_2:
149 rdev->irq.hpd[1] = false;
150 break;
151 default:
152 break;
153 }
154 }
155}
156
771fe6b9
JG		 157/*
158 * PCI GART
159 */
160void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
161{
162 /* TODO: can we do somethings here ? */
163 /* It seems hw only cache one entry so we should discard this
164 * entry otherwise if first GPU GART read hit this entry it
165 * could end up in wrong address. */
166}
167
4aac0473 168int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 169{
771fe6b9
JG		 170 int r;
171
4aac0473
JG		 172 if (rdev->gart.table.ram.ptr) {
173 WARN(1, "R100 PCI GART already initialized.\n");
174 return 0;
175 }
771fe6b9
JG		 176 /* Initialize common gart structure */
177 r = radeon_gart_init(rdev);
4aac0473 178 if (r)
771fe6b9 179 return r;
4aac0473
JG		 180 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
181 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
182 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
183 return radeon_gart_table_ram_alloc(rdev);
184}
185
17e15b0c
DA		 186/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
187void r100_enable_bm(struct radeon_device *rdev)
188{
189 uint32_t tmp;
190 /* Enable bus mastering */
191 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
192 WREG32(RADEON_BUS_CNTL, tmp);
193}
194
4aac0473
JG		 195int r100_pci_gart_enable(struct radeon_device *rdev)
196{
197 uint32_t tmp;
198
771fe6b9
JG		 199 /* discard memory request outside of configured range */
200 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
201 WREG32(RADEON_AIC_CNTL, tmp);
202 /* set address range for PCI address translate */
203 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
204 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
205 WREG32(RADEON_AIC_HI_ADDR, tmp);
771fe6b9
JG		 206 /* set PCI GART page-table base address */
207 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
208 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
209 WREG32(RADEON_AIC_CNTL, tmp);
210 r100_pci_gart_tlb_flush(rdev);
211 rdev->gart.ready = true;
212 return 0;
213}
214
215void r100_pci_gart_disable(struct radeon_device *rdev)
216{
217 uint32_t tmp;
218
219 /* discard memory request outside of configured range */
220 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
221 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
222 WREG32(RADEON_AIC_LO_ADDR, 0);
223 WREG32(RADEON_AIC_HI_ADDR, 0);
224}
225
226int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
227{
228 if (i < 0 || i > rdev->gart.num_gpu_pages) {
229 return -EINVAL;
230 }
ed10f95d 231 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 232 return 0;
233}
234
4aac0473 235void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 236{
4aac0473
JG		 237 r100_pci_gart_disable(rdev);
238 radeon_gart_table_ram_free(rdev);
239 radeon_gart_fini(rdev);
771fe6b9
JG		 240}
241
7ed220d7
MD		 242int r100_irq_set(struct radeon_device *rdev)
243{
244 uint32_t tmp = 0;
245
246 if (rdev->irq.sw_int) {
247 tmp |= RADEON_SW_INT_ENABLE;
248 }
249 if (rdev->irq.crtc_vblank_int[0]) {
250 tmp |= RADEON_CRTC_VBLANK_MASK;
251 }
252 if (rdev->irq.crtc_vblank_int[1]) {
253 tmp |= RADEON_CRTC2_VBLANK_MASK;
254 }
05a05c50
AD		 255 if (rdev->irq.hpd[0]) {
256 tmp |= RADEON_FP_DETECT_MASK;
257 }
258 if (rdev->irq.hpd[1]) {
259 tmp |= RADEON_FP2_DETECT_MASK;
260 }
7ed220d7
MD		 261 WREG32(RADEON_GEN_INT_CNTL, tmp);
262 return 0;
263}
264
9f022ddf
JG		 265void r100_irq_disable(struct radeon_device *rdev)
266{
267 u32 tmp;
268
269 WREG32(R_000040_GEN_INT_CNTL, 0);
270 /* Wait and acknowledge irq */
271 mdelay(1);
272 tmp = RREG32(R_000044_GEN_INT_STATUS);
273 WREG32(R_000044_GEN_INT_STATUS, tmp);
274}
275
7ed220d7
MD		 276static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
277{
278 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 279 uint32_t irq_mask = RADEON_SW_INT_TEST |
280 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
281 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 282
283 if (irqs) {
284 WREG32(RADEON_GEN_INT_STATUS, irqs);
285 }
286 return irqs & irq_mask;
287}
288
289int r100_irq_process(struct radeon_device *rdev)
290{
3e5cb98d 291 uint32_t status, msi_rearm;
d4877cf2 292 bool queue_hotplug = false;
7ed220d7
MD		 293
294 status = r100_irq_ack(rdev);
295 if (!status) {
296 return IRQ_NONE;
297 }
a513c184
JG		 298 if (rdev->shutdown) {
299 return IRQ_NONE;
300 }
7ed220d7
MD		 301 while (status) {
302 /* SW interrupt */
303 if (status & RADEON_SW_INT_TEST) {
304 radeon_fence_process(rdev);
305 }
306 /* Vertical blank interrupts */
307 if (status & RADEON_CRTC_VBLANK_STAT) {
308 drm_handle_vblank(rdev->ddev, 0);
309 }
310 if (status & RADEON_CRTC2_VBLANK_STAT) {
311 drm_handle_vblank(rdev->ddev, 1);
312 }
05a05c50 313 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 314 queue_hotplug = true;
315 DRM_DEBUG("HPD1\n");
05a05c50
AD		 316 }
317 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 318 queue_hotplug = true;
319 DRM_DEBUG("HPD2\n");
05a05c50 320 }
7ed220d7
MD		 321 status = r100_irq_ack(rdev);
322 }
d4877cf2
AD		 323 if (queue_hotplug)
324 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 325 if (rdev->msi_enabled) {
326 switch (rdev->family) {
327 case CHIP_RS400:
328 case CHIP_RS480:
329 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
330 WREG32(RADEON_AIC_CNTL, msi_rearm);
331 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
332 break;
333 default:
334 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
335 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
336 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
337 break;
338 }
339 }
7ed220d7
MD		 340 return IRQ_HANDLED;
341}
342
343u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
344{
345 if (crtc == 0)
346 return RREG32(RADEON_CRTC_CRNT_FRAME);
347 else
348 return RREG32(RADEON_CRTC2_CRNT_FRAME);
349}
350
771fe6b9
JG		 351void r100_fence_ring_emit(struct radeon_device *rdev,
352 struct radeon_fence *fence)
353{
354 /* Who ever call radeon_fence_emit should call ring_lock and ask
355 * for enough space (today caller are ib schedule and buffer move) */
356 /* Wait until IDLE & CLEAN */
357 radeon_ring_write(rdev, PACKET0(0x1720, 0));
358 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
359 /* Emit fence sequence & fire IRQ */
360 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
361 radeon_ring_write(rdev, fence->seq);
362 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
363 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
364}
365
771fe6b9
JG		 366int r100_wb_init(struct radeon_device *rdev)
367{
368 int r;
369
370 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 371 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
372 RADEON_GEM_DOMAIN_GTT,
373 &rdev->wb.wb_obj);
771fe6b9 374 if (r) {
4c788679 375 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
771fe6b9
JG		 376 return r;
377 }
4c788679
JG		 378 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
379 if (unlikely(r != 0))
380 return r;
381 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
382 &rdev->wb.gpu_addr);
771fe6b9 383 if (r) {
4c788679
JG		 384 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
385 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9
JG		 386 return r;
387 }
4c788679
JG		 388 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
389 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9 390 if (r) {
4c788679 391 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
771fe6b9
JG		 392 return r;
393 }
394 }
9f022ddf
JG		 395 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
396 WREG32(R_00070C_CP_RB_RPTR_ADDR,
397 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
398 WREG32(R_000770_SCRATCH_UMSK, 0xff);
771fe6b9
JG		 399 return 0;
400}
401
9f022ddf
JG		 402void r100_wb_disable(struct radeon_device *rdev)
403{
404 WREG32(R_000770_SCRATCH_UMSK, 0);
405}
406
771fe6b9
JG		 407void r100_wb_fini(struct radeon_device *rdev)
408{
4c788679
JG		 409 int r;
410
9f022ddf 411 r100_wb_disable(rdev);
771fe6b9 412 if (rdev->wb.wb_obj) {
4c788679
JG		 413 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
414 if (unlikely(r != 0)) {
415 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
416 return;
417 }
418 radeon_bo_kunmap(rdev->wb.wb_obj);
419 radeon_bo_unpin(rdev->wb.wb_obj);
420 radeon_bo_unreserve(rdev->wb.wb_obj);
421 radeon_bo_unref(&rdev->wb.wb_obj);
771fe6b9
JG		 422 rdev->wb.wb = NULL;
423 rdev->wb.wb_obj = NULL;
424 }
425}
426
427int r100_copy_blit(struct radeon_device *rdev,
428 uint64_t src_offset,
429 uint64_t dst_offset,
430 unsigned num_pages,
431 struct radeon_fence *fence)
432{
433 uint32_t cur_pages;
434 uint32_t stride_bytes = PAGE_SIZE;
435 uint32_t pitch;
436 uint32_t stride_pixels;
437 unsigned ndw;
438 int num_loops;
439 int r = 0;
440
441 /* radeon limited to 16k stride */
442 stride_bytes &= 0x3fff;
443 /* radeon pitch is /64 */
444 pitch = stride_bytes / 64;
445 stride_pixels = stride_bytes / 4;
446 num_loops = DIV_ROUND_UP(num_pages, 8191);
447
448 /* Ask for enough room for blit + flush + fence */
449 ndw = 64 + (10 * num_loops);
450 r = radeon_ring_lock(rdev, ndw);
451 if (r) {
452 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
453 return -EINVAL;
454 }
455 while (num_pages > 0) {
456 cur_pages = num_pages;
457 if (cur_pages > 8191) {
458 cur_pages = 8191;
459 }
460 num_pages -= cur_pages;
461
462 /* pages are in Y direction - height
463 page width in X direction - width */
464 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
465 radeon_ring_write(rdev,
466 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
467 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
468 RADEON_GMC_SRC_CLIPPING |
469 RADEON_GMC_DST_CLIPPING |
470 RADEON_GMC_BRUSH_NONE |
471 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
472 RADEON_GMC_SRC_DATATYPE_COLOR |
473 RADEON_ROP3_S |
474 RADEON_DP_SRC_SOURCE_MEMORY |
475 RADEON_GMC_CLR_CMP_CNTL_DIS |
476 RADEON_GMC_WR_MSK_DIS);
477 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
478 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
479 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
480 radeon_ring_write(rdev, 0);
481 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
482 radeon_ring_write(rdev, num_pages);
483 radeon_ring_write(rdev, num_pages);
484 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
485 }
486 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
487 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
488 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
489 radeon_ring_write(rdev,
490 RADEON_WAIT_2D_IDLECLEAN |
491 RADEON_WAIT_HOST_IDLECLEAN |
492 RADEON_WAIT_DMA_GUI_IDLE);
493 if (fence) {
494 r = radeon_fence_emit(rdev, fence);
495 }
496 radeon_ring_unlock_commit(rdev);
497 return r;
498}
499
45600232
JG		 500static int r100_cp_wait_for_idle(struct radeon_device *rdev)
501{
502 unsigned i;
503 u32 tmp;
504
505 for (i = 0; i < rdev->usec_timeout; i++) {
506 tmp = RREG32(R_000E40_RBBM_STATUS);
507 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
508 return 0;
509 }
510 udelay(1);
511 }
512 return -1;
513}
514
771fe6b9
JG		 515void r100_ring_start(struct radeon_device *rdev)
516{
517 int r;
518
519 r = radeon_ring_lock(rdev, 2);
520 if (r) {
521 return;
522 }
523 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
524 radeon_ring_write(rdev,
525 RADEON_ISYNC_ANY2D_IDLE3D |
526 RADEON_ISYNC_ANY3D_IDLE2D |
527 RADEON_ISYNC_WAIT_IDLEGUI |
528 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
529 radeon_ring_unlock_commit(rdev);
530}
531
70967ab9
BH		 532
533/* Load the microcode for the CP */
534static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 535{
70967ab9
BH		 536 struct platform_device *pdev;
537 const char *fw_name = NULL;
538 int err;
771fe6b9 539
70967ab9 540 DRM_DEBUG("\n");
771fe6b9 541
70967ab9
BH		 542 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
543 err = IS_ERR(pdev);
544 if (err) {
545 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
546 return -EINVAL;
547 }
771fe6b9
JG		 548 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
549 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
550 (rdev->family == CHIP_RS200)) {
551 DRM_INFO("Loading R100 Microcode\n");
70967ab9 552 fw_name = FIRMWARE_R100;
771fe6b9
JG		 553 } else if ((rdev->family == CHIP_R200) ||
554 (rdev->family == CHIP_RV250) ||
555 (rdev->family == CHIP_RV280) ||
556 (rdev->family == CHIP_RS300)) {
557 DRM_INFO("Loading R200 Microcode\n");
70967ab9 558 fw_name = FIRMWARE_R200;
771fe6b9
JG		 559 } else if ((rdev->family == CHIP_R300) ||
560 (rdev->family == CHIP_R350) ||
561 (rdev->family == CHIP_RV350) ||
562 (rdev->family == CHIP_RV380) ||
563 (rdev->family == CHIP_RS400) ||
564 (rdev->family == CHIP_RS480)) {
565 DRM_INFO("Loading R300 Microcode\n");
70967ab9 566 fw_name = FIRMWARE_R300;
771fe6b9
JG		 567 } else if ((rdev->family == CHIP_R420) ||
568 (rdev->family == CHIP_R423) ||
569 (rdev->family == CHIP_RV410)) {
570 DRM_INFO("Loading R400 Microcode\n");
70967ab9 571 fw_name = FIRMWARE_R420;
771fe6b9
JG		 572 } else if ((rdev->family == CHIP_RS690) ||
573 (rdev->family == CHIP_RS740)) {
574 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 575 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 576 } else if (rdev->family == CHIP_RS600) {
577 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 578 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 579 } else if ((rdev->family == CHIP_RV515) ||
580 (rdev->family == CHIP_R520) ||
581 (rdev->family == CHIP_RV530) ||
582 (rdev->family == CHIP_R580) ||
583 (rdev->family == CHIP_RV560) ||
584 (rdev->family == CHIP_RV570)) {
585 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 586 fw_name = FIRMWARE_R520;
587 }
588
3ce0a23d 589 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 590 platform_device_unregister(pdev);
591 if (err) {
592 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
593 fw_name);
3ce0a23d 594 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 595 printk(KERN_ERR
596 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 597 rdev->me_fw->size, fw_name);
70967ab9 598 err = -EINVAL;
3ce0a23d
JG		 599 release_firmware(rdev->me_fw);
600 rdev->me_fw = NULL;
70967ab9
BH		 601 }
602 return err;
603}
d4550907 604
70967ab9
BH		 605static void r100_cp_load_microcode(struct radeon_device *rdev)
606{
607 const __be32 *fw_data;
608 int i, size;
609
610 if (r100_gui_wait_for_idle(rdev)) {
611 printk(KERN_WARNING "Failed to wait GUI idle while "
612 "programming pipes. Bad things might happen.\n");
613 }
614
3ce0a23d
JG		 615 if (rdev->me_fw) {
616 size = rdev->me_fw->size / 4;
617 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 618 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
619 for (i = 0; i < size; i += 2) {
620 WREG32(RADEON_CP_ME_RAM_DATAH,
621 be32_to_cpup(&fw_data[i]));
622 WREG32(RADEON_CP_ME_RAM_DATAL,
623 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 624 }
625 }
626}
627
628int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
629{
630 unsigned rb_bufsz;
631 unsigned rb_blksz;
632 unsigned max_fetch;
633 unsigned pre_write_timer;
634 unsigned pre_write_limit;
635 unsigned indirect2_start;
636 unsigned indirect1_start;
637 uint32_t tmp;
638 int r;
639
640 if (r100_debugfs_cp_init(rdev)) {
641 DRM_ERROR("Failed to register debugfs file for CP !\n");
642 }
643 /* Reset CP */
644 tmp = RREG32(RADEON_CP_CSQ_STAT);
645 if ((tmp & (1 << 31))) {
646 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
647 WREG32(RADEON_CP_CSQ_MODE, 0);
648 WREG32(RADEON_CP_CSQ_CNTL, 0);
649 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
650 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
651 mdelay(2);
652 WREG32(RADEON_RBBM_SOFT_RESET, 0);
653 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
654 mdelay(2);
655 tmp = RREG32(RADEON_CP_CSQ_STAT);
656 if ((tmp & (1 << 31))) {
657 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
658 }
659 } else {
660 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
661 }
70967ab9 662
3ce0a23d 663 if (!rdev->me_fw) {
70967ab9
BH		 664 r = r100_cp_init_microcode(rdev);
665 if (r) {
666 DRM_ERROR("Failed to load firmware!\n");
667 return r;
668 }
669 }
670
771fe6b9
JG		 671 /* Align ring size */
672 rb_bufsz = drm_order(ring_size / 8);
673 ring_size = (1 << (rb_bufsz + 1)) * 4;
674 r100_cp_load_microcode(rdev);
675 r = radeon_ring_init(rdev, ring_size);
676 if (r) {
677 return r;
678 }
679 /* Each time the cp read 1024 bytes (16 dword/quadword) update
680 * the rptr copy in system ram */
681 rb_blksz = 9;
682 /* cp will read 128bytes at a time (4 dwords) */
683 max_fetch = 1;
684 rdev->cp.align_mask = 16 - 1;
685 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
686 pre_write_timer = 64;
687 /* Force CP_RB_WPTR write if written more than one time before the
688 * delay expire
689 */
690 pre_write_limit = 0;
691 /* Setup the cp cache like this (cache size is 96 dwords) :
692 * RING 0 to 15
693 * INDIRECT1 16 to 79
694 * INDIRECT2 80 to 95
695 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
696 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
697 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
698 * Idea being that most of the gpu cmd will be through indirect1 buffer
699 * so it gets the bigger cache.
700 */
701 indirect2_start = 80;
702 indirect1_start = 16;
703 /* cp setup */
704 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 705 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9
JG		 706 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
707 REG_SET(RADEON_MAX_FETCH, max_fetch) |
708 RADEON_RB_NO_UPDATE);
d6f28938
AD		 709#ifdef __BIG_ENDIAN
710 tmp |= RADEON_BUF_SWAP_32BIT;
711#endif
712 WREG32(RADEON_CP_RB_CNTL, tmp);
713
771fe6b9
JG		 714 /* Set ring address */
715 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
716 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
717 /* Force read & write ptr to 0 */
771fe6b9
JG		 718 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
719 WREG32(RADEON_CP_RB_RPTR_WR, 0);
720 WREG32(RADEON_CP_RB_WPTR, 0);
721 WREG32(RADEON_CP_RB_CNTL, tmp);
722 udelay(10);
723 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
724 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
725 /* Set cp mode to bus mastering & enable cp*/
726 WREG32(RADEON_CP_CSQ_MODE,
727 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
728 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
729 WREG32(0x718, 0);
730 WREG32(0x744, 0x00004D4D);
731 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
732 radeon_ring_start(rdev);
733 r = radeon_ring_test(rdev);
734 if (r) {
735 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
736 return r;
737 }
738 rdev->cp.ready = true;
739 return 0;
740}
741
742void r100_cp_fini(struct radeon_device *rdev)
743{
45600232
JG		 744 if (r100_cp_wait_for_idle(rdev)) {
745 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
746 }
771fe6b9 747 /* Disable ring */
a18d7ea1 748 r100_cp_disable(rdev);
771fe6b9
JG		 749 radeon_ring_fini(rdev);
750 DRM_INFO("radeon: cp finalized\n");
751}
752
753void r100_cp_disable(struct radeon_device *rdev)
754{
755 /* Disable ring */
756 rdev->cp.ready = false;
757 WREG32(RADEON_CP_CSQ_MODE, 0);
758 WREG32(RADEON_CP_CSQ_CNTL, 0);
759 if (r100_gui_wait_for_idle(rdev)) {
760 printk(KERN_WARNING "Failed to wait GUI idle while "
761 "programming pipes. Bad things might happen.\n");
762 }
763}
764
765int r100_cp_reset(struct radeon_device *rdev)
766{
767 uint32_t tmp;
768 bool reinit_cp;
769 int i;
770
771 reinit_cp = rdev->cp.ready;
772 rdev->cp.ready = false;
773 WREG32(RADEON_CP_CSQ_MODE, 0);
774 WREG32(RADEON_CP_CSQ_CNTL, 0);
775 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
776 (void)RREG32(RADEON_RBBM_SOFT_RESET);
777 udelay(200);
778 WREG32(RADEON_RBBM_SOFT_RESET, 0);
779 /* Wait to prevent race in RBBM_STATUS */
780 mdelay(1);
781 for (i = 0; i < rdev->usec_timeout; i++) {
782 tmp = RREG32(RADEON_RBBM_STATUS);
783 if (!(tmp & (1 << 16))) {
784 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
785 tmp);
786 if (reinit_cp) {
787 return r100_cp_init(rdev, rdev->cp.ring_size);
788 }
789 return 0;
790 }
791 DRM_UDELAY(1);
792 }
793 tmp = RREG32(RADEON_RBBM_STATUS);
794 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
795 return -1;
796}
797
3ce0a23d
JG		 798void r100_cp_commit(struct radeon_device *rdev)
799{
800 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
801 (void)RREG32(RADEON_CP_RB_WPTR);
802}
803
771fe6b9
JG		 804
805/*
806 * CS functions
807 */
808int r100_cs_parse_packet0(struct radeon_cs_parser *p,
809 struct radeon_cs_packet *pkt,
068a117c 810 const unsigned *auth, unsigned n,
771fe6b9
JG		 811 radeon_packet0_check_t check)
812{
813 unsigned reg;
814 unsigned i, j, m;
815 unsigned idx;
816 int r;
817
818 idx = pkt->idx + 1;
819 reg = pkt->reg;
068a117c
JG		 820 /* Check that register fall into register range
821 * determined by the number of entry (n) in the
822 * safe register bitmap.
823 */
771fe6b9
JG		 824 if (pkt->one_reg_wr) {
825 if ((reg >> 7) > n) {
826 return -EINVAL;
827 }
828 } else {
829 if (((reg + (pkt->count << 2)) >> 7) > n) {
830 return -EINVAL;
831 }
832 }
833 for (i = 0; i <= pkt->count; i++, idx++) {
834 j = (reg >> 7);
835 m = 1 << ((reg >> 2) & 31);
836 if (auth[j] & m) {
837 r = check(p, pkt, idx, reg);
838 if (r) {
839 return r;
840 }
841 }
842 if (pkt->one_reg_wr) {
843 if (!(auth[j] & m)) {
844 break;
845 }
846 } else {
847 reg += 4;
848 }
849 }
850 return 0;
851}
852
771fe6b9
JG		 853void r100_cs_dump_packet(struct radeon_cs_parser *p,
854 struct radeon_cs_packet *pkt)
855{
771fe6b9
JG		 856 volatile uint32_t *ib;
857 unsigned i;
858 unsigned idx;
859
860 ib = p->ib->ptr;
771fe6b9
JG		 861 idx = pkt->idx;
862 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
863 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
864 }
865}
866
867/**
868 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
869 * @parser: parser structure holding parsing context.
870 * @pkt: where to store packet informations
871 *
872 * Assume that chunk_ib_index is properly set. Will return -EINVAL
873 * if packet is bigger than remaining ib size. or if packets is unknown.
874 **/
875int r100_cs_packet_parse(struct radeon_cs_parser *p,
876 struct radeon_cs_packet *pkt,
877 unsigned idx)
878{
879 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 880 uint32_t header;
771fe6b9
JG		 881
882 if (idx >= ib_chunk->length_dw) {
883 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
884 idx, ib_chunk->length_dw);
885 return -EINVAL;
886 }
513bcb46 887 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 888 pkt->idx = idx;
889 pkt->type = CP_PACKET_GET_TYPE(header);
890 pkt->count = CP_PACKET_GET_COUNT(header);
891 switch (pkt->type) {
892 case PACKET_TYPE0:
893 pkt->reg = CP_PACKET0_GET_REG(header);
894 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
895 break;
896 case PACKET_TYPE3:
897 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
898 break;
899 case PACKET_TYPE2:
900 pkt->count = -1;
901 break;
902 default:
903 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
904 return -EINVAL;
905 }
906 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
907 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
908 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
909 return -EINVAL;
910 }
911 return 0;
912}
913
531369e6
DA		 914/**
915 * r100_cs_packet_next_vline() - parse userspace VLINE packet
916 * @parser: parser structure holding parsing context.
917 *
918 * Userspace sends a special sequence for VLINE waits.
919 * PACKET0 - VLINE_START_END + value
920 * PACKET0 - WAIT_UNTIL +_value
921 * RELOC (P3) - crtc_id in reloc.
922 *
923 * This function parses this and relocates the VLINE START END
924 * and WAIT UNTIL packets to the correct crtc.
925 * It also detects a switched off crtc and nulls out the
926 * wait in that case.
927 */
928int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
929{
531369e6
DA		 930 struct drm_mode_object *obj;
931 struct drm_crtc *crtc;
932 struct radeon_crtc *radeon_crtc;
933 struct radeon_cs_packet p3reloc, waitreloc;
934 int crtc_id;
935 int r;
936 uint32_t header, h_idx, reg;
513bcb46 937 volatile uint32_t *ib;
531369e6 938
513bcb46 939 ib = p->ib->ptr;
531369e6
DA		 940
941 /* parse the wait until */
942 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
943 if (r)
944 return r;
945
946 /* check its a wait until and only 1 count */
947 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
948 waitreloc.count != 0) {
949 DRM_ERROR("vline wait had illegal wait until segment\n");
950 r = -EINVAL;
951 return r;
952 }
953
513bcb46 954 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 955 DRM_ERROR("vline wait had illegal wait until\n");
956 r = -EINVAL;
957 return r;
958 }
959
960 /* jump over the NOP */
90ebd065 961 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 962 if (r)
963 return r;
964
965 h_idx = p->idx - 2;
90ebd065
AD		 966 p->idx += waitreloc.count + 2;
967 p->idx += p3reloc.count + 2;
531369e6 968
513bcb46
DA		 969 header = radeon_get_ib_value(p, h_idx);
970 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 971 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 972 mutex_lock(&p->rdev->ddev->mode_config.mutex);
973 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
974 if (!obj) {
975 DRM_ERROR("cannot find crtc %d\n", crtc_id);
976 r = -EINVAL;
977 goto out;
978 }
979 crtc = obj_to_crtc(obj);
980 radeon_crtc = to_radeon_crtc(crtc);
981 crtc_id = radeon_crtc->crtc_id;
982
983 if (!crtc->enabled) {
984 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 985 ib[h_idx + 2] = PACKET2(0);
986 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 987 } else if (crtc_id == 1) {
988 switch (reg) {
989 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 990 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 991 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
992 break;
993 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 994 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 995 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
996 break;
997 default:
998 DRM_ERROR("unknown crtc reloc\n");
999 r = -EINVAL;
1000 goto out;
1001 }
513bcb46
DA		 1002 ib[h_idx] = header;
1003 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1004 }
1005out:
1006 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1007 return r;
1008}
1009
771fe6b9
JG		 1010/**
1011 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1012 * @parser: parser structure holding parsing context.
1013 * @data: pointer to relocation data
1014 * @offset_start: starting offset
1015 * @offset_mask: offset mask (to align start offset on)
1016 * @reloc: reloc informations
1017 *
1018 * Check next packet is relocation packet3, do bo validation and compute
1019 * GPU offset using the provided start.
1020 **/
1021int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1022 struct radeon_cs_reloc **cs_reloc)
1023{
771fe6b9
JG		 1024 struct radeon_cs_chunk *relocs_chunk;
1025 struct radeon_cs_packet p3reloc;
1026 unsigned idx;
1027 int r;
1028
1029 if (p->chunk_relocs_idx == -1) {
1030 DRM_ERROR("No relocation chunk !\n");
1031 return -EINVAL;
1032 }
1033 *cs_reloc = NULL;
771fe6b9
JG		 1034 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1035 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1036 if (r) {
1037 return r;
1038 }
1039 p->idx += p3reloc.count + 2;
1040 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1041 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1042 p3reloc.idx);
1043 r100_cs_dump_packet(p, &p3reloc);
1044 return -EINVAL;
1045 }
513bcb46 1046 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1047 if (idx >= relocs_chunk->length_dw) {
1048 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1049 idx, relocs_chunk->length_dw);
1050 r100_cs_dump_packet(p, &p3reloc);
1051 return -EINVAL;
1052 }
1053 /* FIXME: we assume reloc size is 4 dwords */
1054 *cs_reloc = p->relocs_ptr[(idx / 4)];
1055 return 0;
1056}
1057
551ebd83
DA		 1058static int r100_get_vtx_size(uint32_t vtx_fmt)
1059{
1060 int vtx_size;
1061 vtx_size = 2;
1062 /* ordered according to bits in spec */
1063 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1064 vtx_size++;
1065 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1066 vtx_size += 3;
1067 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1068 vtx_size++;
1069 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1070 vtx_size++;
1071 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1072 vtx_size += 3;
1073 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1074 vtx_size++;
1075 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1076 vtx_size++;
1077 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1078 vtx_size += 2;
1079 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1080 vtx_size += 2;
1081 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1082 vtx_size++;
1083 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1084 vtx_size += 2;
1085 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1086 vtx_size++;
1087 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1088 vtx_size += 2;
1089 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1090 vtx_size++;
1091 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1092 vtx_size++;
1093 /* blend weight */
1094 if (vtx_fmt & (0x7 << 15))
1095 vtx_size += (vtx_fmt >> 15) & 0x7;
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1097 vtx_size += 3;
1098 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1099 vtx_size += 2;
1100 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1101 vtx_size++;
1102 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1103 vtx_size++;
1104 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1105 vtx_size++;
1106 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1107 vtx_size++;
1108 return vtx_size;
1109}
1110
771fe6b9 1111static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1112 struct radeon_cs_packet *pkt,
1113 unsigned idx, unsigned reg)
771fe6b9 1114{
771fe6b9 1115 struct radeon_cs_reloc *reloc;
551ebd83 1116 struct r100_cs_track *track;
771fe6b9
JG		 1117 volatile uint32_t *ib;
1118 uint32_t tmp;
771fe6b9 1119 int r;
551ebd83 1120 int i, face;
e024e110 1121 u32 tile_flags = 0;
513bcb46 1122 u32 idx_value;
771fe6b9
JG		 1123
1124 ib = p->ib->ptr;
551ebd83
DA		 1125 track = (struct r100_cs_track *)p->track;
1126
513bcb46
DA		 1127 idx_value = radeon_get_ib_value(p, idx);
1128
551ebd83
DA		 1129 switch (reg) {
1130 case RADEON_CRTC_GUI_TRIG_VLINE:
1131 r = r100_cs_packet_parse_vline(p);
1132 if (r) {
1133 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1134 idx, reg);
1135 r100_cs_dump_packet(p, pkt);
1136 return r;
1137 }
1138 break;
771fe6b9
JG		 1139 /* FIXME: only allow PACKET3 blit? easier to check for out of
1140 * range access */
551ebd83
DA		 1141 case RADEON_DST_PITCH_OFFSET:
1142 case RADEON_SRC_PITCH_OFFSET:
1143 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1144 if (r)
1145 return r;
1146 break;
1147 case RADEON_RB3D_DEPTHOFFSET:
1148 r = r100_cs_packet_next_reloc(p, &reloc);
1149 if (r) {
1150 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1151 idx, reg);
1152 r100_cs_dump_packet(p, pkt);
1153 return r;
1154 }
1155 track->zb.robj = reloc->robj;
513bcb46
DA		 1156 track->zb.offset = idx_value;
1157 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1158 break;
1159 case RADEON_RB3D_COLOROFFSET:
1160 r = r100_cs_packet_next_reloc(p, &reloc);
1161 if (r) {
1162 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1163 idx, reg);
1164 r100_cs_dump_packet(p, pkt);
1165 return r;
1166 }
1167 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1168 track->cb[0].offset = idx_value;
1169 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1170 break;
1171 case RADEON_PP_TXOFFSET_0:
1172 case RADEON_PP_TXOFFSET_1:
1173 case RADEON_PP_TXOFFSET_2:
1174 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1175 r = r100_cs_packet_next_reloc(p, &reloc);
1176 if (r) {
1177 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1178 idx, reg);
1179 r100_cs_dump_packet(p, pkt);
1180 return r;
1181 }
513bcb46 1182 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1183 track->textures[i].robj = reloc->robj;
1184 break;
1185 case RADEON_PP_CUBIC_OFFSET_T0_0:
1186 case RADEON_PP_CUBIC_OFFSET_T0_1:
1187 case RADEON_PP_CUBIC_OFFSET_T0_2:
1188 case RADEON_PP_CUBIC_OFFSET_T0_3:
1189 case RADEON_PP_CUBIC_OFFSET_T0_4:
1190 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1191 r = r100_cs_packet_next_reloc(p, &reloc);
1192 if (r) {
1193 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1194 idx, reg);
1195 r100_cs_dump_packet(p, pkt);
1196 return r;
1197 }
513bcb46
DA		 1198 track->textures[0].cube_info[i].offset = idx_value;
1199 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1200 track->textures[0].cube_info[i].robj = reloc->robj;
1201 break;
1202 case RADEON_PP_CUBIC_OFFSET_T1_0:
1203 case RADEON_PP_CUBIC_OFFSET_T1_1:
1204 case RADEON_PP_CUBIC_OFFSET_T1_2:
1205 case RADEON_PP_CUBIC_OFFSET_T1_3:
1206 case RADEON_PP_CUBIC_OFFSET_T1_4:
1207 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1208 r = r100_cs_packet_next_reloc(p, &reloc);
1209 if (r) {
1210 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1211 idx, reg);
1212 r100_cs_dump_packet(p, pkt);
1213 return r;
1214 }
513bcb46
DA		 1215 track->textures[1].cube_info[i].offset = idx_value;
1216 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1217 track->textures[1].cube_info[i].robj = reloc->robj;
1218 break;
1219 case RADEON_PP_CUBIC_OFFSET_T2_0:
1220 case RADEON_PP_CUBIC_OFFSET_T2_1:
1221 case RADEON_PP_CUBIC_OFFSET_T2_2:
1222 case RADEON_PP_CUBIC_OFFSET_T2_3:
1223 case RADEON_PP_CUBIC_OFFSET_T2_4:
1224 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1225 r = r100_cs_packet_next_reloc(p, &reloc);
1226 if (r) {
1227 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1228 idx, reg);
1229 r100_cs_dump_packet(p, pkt);
1230 return r;
1231 }
513bcb46
DA		 1232 track->textures[2].cube_info[i].offset = idx_value;
1233 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1234 track->textures[2].cube_info[i].robj = reloc->robj;
1235 break;
1236 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1237 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1238 break;
1239 case RADEON_RB3D_COLORPITCH:
1240 r = r100_cs_packet_next_reloc(p, &reloc);
1241 if (r) {
1242 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1243 idx, reg);
1244 r100_cs_dump_packet(p, pkt);
1245 return r;
1246 }
e024e110 1247
551ebd83
DA		 1248 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1249 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1250 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1251 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1252
513bcb46 1253 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1254 tmp |= tile_flags;
1255 ib[idx] = tmp;
e024e110 1256
513bcb46 1257 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1258 break;
1259 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1260 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1261 break;
1262 case RADEON_RB3D_CNTL:
513bcb46 1263 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1264 case 7:
1265 case 8:
1266 case 9:
1267 case 11:
1268 case 12:
1269 track->cb[0].cpp = 1;
e024e110 1270 break;
551ebd83
DA		 1271 case 3:
1272 case 4:
1273 case 15:
1274 track->cb[0].cpp = 2;
1275 break;
1276 case 6:
1277 track->cb[0].cpp = 4;
1278 break;
1279 default:
1280 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1281 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1282 return -EINVAL;
1283 }
513bcb46 1284 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1285 break;
1286 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1287 switch (idx_value & 0xf) {
551ebd83
DA		 1288 case 0:
1289 track->zb.cpp = 2;
1290 break;
1291 case 2:
1292 case 3:
1293 case 4:
1294 case 5:
1295 case 9:
1296 case 11:
1297 track->zb.cpp = 4;
17782d99 1298 break;
771fe6b9 1299 default:
771fe6b9
JG		 1300 break;
1301 }
551ebd83
DA		 1302 break;
1303 case RADEON_RB3D_ZPASS_ADDR:
1304 r = r100_cs_packet_next_reloc(p, &reloc);
1305 if (r) {
1306 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1307 idx, reg);
1308 r100_cs_dump_packet(p, pkt);
1309 return r;
1310 }
513bcb46 1311 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1312 break;
1313 case RADEON_PP_CNTL:
1314 {
513bcb46 1315 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1316 for (i = 0; i < track->num_texture; i++)
1317 track->textures[i].enabled = !!(temp & (1 << i));
1318 }
1319 break;
1320 case RADEON_SE_VF_CNTL:
513bcb46 1321 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1322 break;
1323 case RADEON_SE_VTX_FMT:
513bcb46 1324 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1325 break;
1326 case RADEON_PP_TEX_SIZE_0:
1327 case RADEON_PP_TEX_SIZE_1:
1328 case RADEON_PP_TEX_SIZE_2:
1329 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1330 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1331 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1332 break;
1333 case RADEON_PP_TEX_PITCH_0:
1334 case RADEON_PP_TEX_PITCH_1:
1335 case RADEON_PP_TEX_PITCH_2:
1336 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1337 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1338 break;
1339 case RADEON_PP_TXFILTER_0:
1340 case RADEON_PP_TXFILTER_1:
1341 case RADEON_PP_TXFILTER_2:
1342 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1343 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1344 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1345 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1346 if (tmp == 2 || tmp == 6)
1347 track->textures[i].roundup_w = false;
513bcb46 1348 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1349 if (tmp == 2 || tmp == 6)
1350 track->textures[i].roundup_h = false;
1351 break;
1352 case RADEON_PP_TXFORMAT_0:
1353 case RADEON_PP_TXFORMAT_1:
1354 case RADEON_PP_TXFORMAT_2:
1355 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1356 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1357 track->textures[i].use_pitch = 1;
1358 } else {
1359 track->textures[i].use_pitch = 0;
513bcb46
DA		 1360 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1361 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1362 }
513bcb46 1363 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1364 track->textures[i].tex_coord_type = 2;
513bcb46 1365 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1366 case RADEON_TXFORMAT_I8:
1367 case RADEON_TXFORMAT_RGB332:
1368 case RADEON_TXFORMAT_Y8:
1369 track->textures[i].cpp = 1;
1370 break;
1371 case RADEON_TXFORMAT_AI88:
1372 case RADEON_TXFORMAT_ARGB1555:
1373 case RADEON_TXFORMAT_RGB565:
1374 case RADEON_TXFORMAT_ARGB4444:
1375 case RADEON_TXFORMAT_VYUY422:
1376 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1377 case RADEON_TXFORMAT_SHADOW16:
1378 case RADEON_TXFORMAT_LDUDV655:
1379 case RADEON_TXFORMAT_DUDV88:
1380 track->textures[i].cpp = 2;
771fe6b9 1381 break;
551ebd83
DA		 1382 case RADEON_TXFORMAT_ARGB8888:
1383 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1384 case RADEON_TXFORMAT_SHADOW32:
1385 case RADEON_TXFORMAT_LDUDUV8888:
1386 track->textures[i].cpp = 4;
1387 break;
d785d78b
DA		 1388 case RADEON_TXFORMAT_DXT1:
1389 track->textures[i].cpp = 1;
1390 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1391 break;
1392 case RADEON_TXFORMAT_DXT23:
1393 case RADEON_TXFORMAT_DXT45:
1394 track->textures[i].cpp = 1;
1395 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1396 break;
551ebd83 1397 }
513bcb46
DA		 1398 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1399 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1400 break;
1401 case RADEON_PP_CUBIC_FACES_0:
1402 case RADEON_PP_CUBIC_FACES_1:
1403 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1404 tmp = idx_value;
551ebd83
DA		 1405 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1406 for (face = 0; face < 4; face++) {
1407 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1408 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1409 }
551ebd83
DA		 1410 break;
1411 default:
1412 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1413 reg, idx);
1414 return -EINVAL;
771fe6b9
JG		 1415 }
1416 return 0;
1417}
1418
068a117c
JG		 1419int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1420 struct radeon_cs_packet *pkt,
4c788679 1421 struct radeon_bo *robj)
068a117c 1422{
068a117c 1423 unsigned idx;
513bcb46 1424 u32 value;
068a117c 1425 idx = pkt->idx + 1;
513bcb46 1426 value = radeon_get_ib_value(p, idx + 2);
4c788679 1427 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1428 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1429 "(need %u have %lu) !\n",
513bcb46 1430 value + 1,
4c788679 1431 radeon_bo_size(robj));
068a117c
JG		 1432 return -EINVAL;
1433 }
1434 return 0;
1435}
1436
771fe6b9
JG		 1437static int r100_packet3_check(struct radeon_cs_parser *p,
1438 struct radeon_cs_packet *pkt)
1439{
771fe6b9 1440 struct radeon_cs_reloc *reloc;
551ebd83 1441 struct r100_cs_track *track;
771fe6b9 1442 unsigned idx;
771fe6b9
JG		 1443 volatile uint32_t *ib;
1444 int r;
1445
1446 ib = p->ib->ptr;
771fe6b9 1447 idx = pkt->idx + 1;
551ebd83 1448 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1449 switch (pkt->opcode) {
1450 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1451 r = r100_packet3_load_vbpntr(p, pkt, idx);
1452 if (r)
1453 return r;
771fe6b9
JG		 1454 break;
1455 case PACKET3_INDX_BUFFER:
1456 r = r100_cs_packet_next_reloc(p, &reloc);
1457 if (r) {
1458 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1459 r100_cs_dump_packet(p, pkt);
1460 return r;
1461 }
513bcb46 1462 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1463 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1464 if (r) {
1465 return r;
1466 }
771fe6b9
JG		 1467 break;
1468 case 0x23:
771fe6b9
JG		 1469 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1470 r = r100_cs_packet_next_reloc(p, &reloc);
1471 if (r) {
1472 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1473 r100_cs_dump_packet(p, pkt);
1474 return r;
1475 }
513bcb46 1476 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1477 track->num_arrays = 1;
513bcb46 1478 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1479
1480 track->arrays[0].robj = reloc->robj;
1481 track->arrays[0].esize = track->vtx_size;
1482
513bcb46 1483 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1484
513bcb46 1485 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1486 track->immd_dwords = pkt->count - 1;
1487 r = r100_cs_track_check(p->rdev, track);
1488 if (r)
1489 return r;
771fe6b9
JG		 1490 break;
1491 case PACKET3_3D_DRAW_IMMD:
513bcb46 1492 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1493 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1494 return -EINVAL;
1495 }
513bcb46 1496 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1497 track->immd_dwords = pkt->count - 1;
1498 r = r100_cs_track_check(p->rdev, track);
1499 if (r)
1500 return r;
1501 break;
771fe6b9
JG		 1502 /* triggers drawing using in-packet vertex data */
1503 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1504 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1505 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1506 return -EINVAL;
1507 }
513bcb46 1508 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1509 track->immd_dwords = pkt->count;
1510 r = r100_cs_track_check(p->rdev, track);
1511 if (r)
1512 return r;
1513 break;
771fe6b9
JG		 1514 /* triggers drawing using in-packet vertex data */
1515 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1516 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1517 r = r100_cs_track_check(p->rdev, track);
1518 if (r)
1519 return r;
1520 break;
771fe6b9
JG		 1521 /* triggers drawing of vertex buffers setup elsewhere */
1522 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1523 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1524 r = r100_cs_track_check(p->rdev, track);
1525 if (r)
1526 return r;
1527 break;
771fe6b9
JG		 1528 /* triggers drawing using indices to vertex buffer */
1529 case PACKET3_3D_DRAW_VBUF:
513bcb46 1530 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1531 r = r100_cs_track_check(p->rdev, track);
1532 if (r)
1533 return r;
1534 break;
771fe6b9
JG		 1535 /* triggers drawing of vertex buffers setup elsewhere */
1536 case PACKET3_3D_DRAW_INDX:
513bcb46 1537 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1538 r = r100_cs_track_check(p->rdev, track);
1539 if (r)
1540 return r;
1541 break;
771fe6b9
JG		 1542 /* triggers drawing using indices to vertex buffer */
1543 case PACKET3_NOP:
1544 break;
1545 default:
1546 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1547 return -EINVAL;
1548 }
1549 return 0;
1550}
1551
1552int r100_cs_parse(struct radeon_cs_parser *p)
1553{
1554 struct radeon_cs_packet pkt;
9f022ddf 1555 struct r100_cs_track *track;
771fe6b9
JG		 1556 int r;
1557
9f022ddf
JG		 1558 track = kzalloc(sizeof(*track), GFP_KERNEL);
1559 r100_cs_track_clear(p->rdev, track);
1560 p->track = track;
771fe6b9
JG		 1561 do {
1562 r = r100_cs_packet_parse(p, &pkt, p->idx);
1563 if (r) {
1564 return r;
1565 }
1566 p->idx += pkt.count + 2;
1567 switch (pkt.type) {
068a117c 1568 case PACKET_TYPE0:
551ebd83
DA		 1569 if (p->rdev->family >= CHIP_R200)
1570 r = r100_cs_parse_packet0(p, &pkt,
1571 p->rdev->config.r100.reg_safe_bm,
1572 p->rdev->config.r100.reg_safe_bm_size,
1573 &r200_packet0_check);
1574 else
1575 r = r100_cs_parse_packet0(p, &pkt,
1576 p->rdev->config.r100.reg_safe_bm,
1577 p->rdev->config.r100.reg_safe_bm_size,
1578 &r100_packet0_check);
068a117c
JG		 1579 break;
1580 case PACKET_TYPE2:
1581 break;
1582 case PACKET_TYPE3:
1583 r = r100_packet3_check(p, &pkt);
1584 break;
1585 default:
1586 DRM_ERROR("Unknown packet type %d !\n",
1587 pkt.type);
1588 return -EINVAL;
771fe6b9
JG		 1589 }
1590 if (r) {
1591 return r;
1592 }
1593 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1594 return 0;
1595}
1596
1597
1598/*
1599 * Global GPU functions
1600 */
1601void r100_errata(struct radeon_device *rdev)
1602{
1603 rdev->pll_errata = 0;
1604
1605 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1606 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1607 }
1608
1609 if (rdev->family == CHIP_RV100 ||
1610 rdev->family == CHIP_RS100 ||
1611 rdev->family == CHIP_RS200) {
1612 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1613 }
1614}
1615
1616/* Wait for vertical sync on primary CRTC */
1617void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1618{
1619 uint32_t crtc_gen_cntl, tmp;
1620 int i;
1621
1622 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1623 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1624 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1625 return;
1626 }
1627 /* Clear the CRTC_VBLANK_SAVE bit */
1628 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1629 for (i = 0; i < rdev->usec_timeout; i++) {
1630 tmp = RREG32(RADEON_CRTC_STATUS);
1631 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1632 return;
1633 }
1634 DRM_UDELAY(1);
1635 }
1636}
1637
1638/* Wait for vertical sync on secondary CRTC */
1639void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1640{
1641 uint32_t crtc2_gen_cntl, tmp;
1642 int i;
1643
1644 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1645 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1646 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1647 return;
1648
1649 /* Clear the CRTC_VBLANK_SAVE bit */
1650 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1651 for (i = 0; i < rdev->usec_timeout; i++) {
1652 tmp = RREG32(RADEON_CRTC2_STATUS);
1653 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1654 return;
1655 }
1656 DRM_UDELAY(1);
1657 }
1658}
1659
1660int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1661{
1662 unsigned i;
1663 uint32_t tmp;
1664
1665 for (i = 0; i < rdev->usec_timeout; i++) {
1666 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1667 if (tmp >= n) {
1668 return 0;
1669 }
1670 DRM_UDELAY(1);
1671 }
1672 return -1;
1673}
1674
1675int r100_gui_wait_for_idle(struct radeon_device *rdev)
1676{
1677 unsigned i;
1678 uint32_t tmp;
1679
1680 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1681 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1682 " Bad things might happen.\n");
1683 }
1684 for (i = 0; i < rdev->usec_timeout; i++) {
1685 tmp = RREG32(RADEON_RBBM_STATUS);
1686 if (!(tmp & (1 << 31))) {
1687 return 0;
1688 }
1689 DRM_UDELAY(1);
1690 }
1691 return -1;
1692}
1693
1694int r100_mc_wait_for_idle(struct radeon_device *rdev)
1695{
1696 unsigned i;
1697 uint32_t tmp;
1698
1699 for (i = 0; i < rdev->usec_timeout; i++) {
1700 /* read MC_STATUS */
1701 tmp = RREG32(0x0150);
1702 if (tmp & (1 << 2)) {
1703 return 0;
1704 }
1705 DRM_UDELAY(1);
1706 }
1707 return -1;
1708}
1709
1710void r100_gpu_init(struct radeon_device *rdev)
1711{
1712 /* TODO: anythings to do here ? pipes ? */
1713 r100_hdp_reset(rdev);
1714}
1715
23956dfa
DA		 1716void r100_hdp_flush(struct radeon_device *rdev)
1717{
1718 u32 tmp;
1719 tmp = RREG32(RADEON_HOST_PATH_CNTL);
1720 tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
1721 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1722}
1723
771fe6b9
JG		 1724void r100_hdp_reset(struct radeon_device *rdev)
1725{
1726 uint32_t tmp;
1727
1728 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1729 tmp |= (7 << 28);
1730 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1731 (void)RREG32(RADEON_HOST_PATH_CNTL);
1732 udelay(200);
1733 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1734 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1735 (void)RREG32(RADEON_HOST_PATH_CNTL);
1736}
1737
1738int r100_rb2d_reset(struct radeon_device *rdev)
1739{
1740 uint32_t tmp;
1741 int i;
1742
1743 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1744 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1745 udelay(200);
1746 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1747 /* Wait to prevent race in RBBM_STATUS */
1748 mdelay(1);
1749 for (i = 0; i < rdev->usec_timeout; i++) {
1750 tmp = RREG32(RADEON_RBBM_STATUS);
1751 if (!(tmp & (1 << 26))) {
1752 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1753 tmp);
1754 return 0;
1755 }
1756 DRM_UDELAY(1);
1757 }
1758 tmp = RREG32(RADEON_RBBM_STATUS);
1759 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1760 return -1;
1761}
1762
1763int r100_gpu_reset(struct radeon_device *rdev)
1764{
1765 uint32_t status;
1766
1767 /* reset order likely matter */
1768 status = RREG32(RADEON_RBBM_STATUS);
1769 /* reset HDP */
1770 r100_hdp_reset(rdev);
1771 /* reset rb2d */
1772 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1773 r100_rb2d_reset(rdev);
1774 }
1775 /* TODO: reset 3D engine */
1776 /* reset CP */
1777 status = RREG32(RADEON_RBBM_STATUS);
1778 if (status & (1 << 16)) {
1779 r100_cp_reset(rdev);
1780 }
1781 /* Check if GPU is idle */
1782 status = RREG32(RADEON_RBBM_STATUS);
1783 if (status & (1 << 31)) {
1784 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1785 return -1;
1786 }
1787 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1788 return 0;
1789}
1790
92cde00c
AD		 1791void r100_set_common_regs(struct radeon_device *rdev)
1792{
1793 /* set these so they don't interfere with anything */
1794 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1795 WREG32(RADEON_SUBPIC_CNTL, 0);
1796 WREG32(RADEON_VIPH_CONTROL, 0);
1797 WREG32(RADEON_I2C_CNTL_1, 0);
1798 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1799 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1800 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1801}
771fe6b9
JG		 1802
1803/*
1804 * VRAM info
1805 */
1806static void r100_vram_get_type(struct radeon_device *rdev)
1807{
1808 uint32_t tmp;
1809
1810 rdev->mc.vram_is_ddr = false;
1811 if (rdev->flags & RADEON_IS_IGP)
1812 rdev->mc.vram_is_ddr = true;
1813 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1814 rdev->mc.vram_is_ddr = true;
1815 if ((rdev->family == CHIP_RV100) ||
1816 (rdev->family == CHIP_RS100) ||
1817 (rdev->family == CHIP_RS200)) {
1818 tmp = RREG32(RADEON_MEM_CNTL);
1819 if (tmp & RV100_HALF_MODE) {
1820 rdev->mc.vram_width = 32;
1821 } else {
1822 rdev->mc.vram_width = 64;
1823 }
1824 if (rdev->flags & RADEON_SINGLE_CRTC) {
1825 rdev->mc.vram_width /= 4;
1826 rdev->mc.vram_is_ddr = true;
1827 }
1828 } else if (rdev->family <= CHIP_RV280) {
1829 tmp = RREG32(RADEON_MEM_CNTL);
1830 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1831 rdev->mc.vram_width = 128;
1832 } else {
1833 rdev->mc.vram_width = 64;
1834 }
1835 } else {
1836 /* newer IGPs */
1837 rdev->mc.vram_width = 128;
1838 }
1839}
1840
2a0f8918 1841static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1842{
2a0f8918
DA		 1843 u32 aper_size;
1844 u8 byte;
1845
1846 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1847
1848 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1849 * that is has the 2nd generation multifunction PCI interface
1850 */
1851 if (rdev->family == CHIP_RV280 ||
1852 rdev->family >= CHIP_RV350) {
1853 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1854 ~RADEON_HDP_APER_CNTL);
1855 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1856 return aper_size * 2;
1857 }
1858
1859 /* Older cards have all sorts of funny issues to deal with. First
1860 * check if it's a multifunction card by reading the PCI config
1861 * header type... Limit those to one aperture size
1862 */
1863 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1864 if (byte & 0x80) {
1865 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1866 DRM_INFO("Limiting VRAM to one aperture\n");
1867 return aper_size;
1868 }
1869
1870 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1871 * have set it up. We don't write this as it's broken on some ASICs but
1872 * we expect the BIOS to have done the right thing (might be too optimistic...)
1873 */
1874 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1875 return aper_size * 2;
1876 return aper_size;
1877}
1878
1879void r100_vram_init_sizes(struct radeon_device *rdev)
1880{
1881 u64 config_aper_size;
1882 u32 accessible;
1883
1884 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1885
1886 if (rdev->flags & RADEON_IS_IGP) {
1887 uint32_t tom;
1888 /* read NB_TOM to get the amount of ram stolen for the GPU */
1889 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1890 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
3e43d821
DA		 1891 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1892 rdev->mc.vram_location = (tom & 0xffff) << 16;
7a50f01a
DA		 1893 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1894 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1895 } else {
7a50f01a 1896 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1897 /* Some production boards of m6 will report 0
1898 * if it's 8 MB
1899 */
7a50f01a
DA		 1900 if (rdev->mc.real_vram_size == 0) {
1901 rdev->mc.real_vram_size = 8192 * 1024;
1902 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1903 }
3e43d821
DA		 1904 /* let driver place VRAM */
1905 rdev->mc.vram_location = 0xFFFFFFFFUL;
2a0f8918
DA		 1906 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1907 * Novell bug 204882 + along with lots of ubuntu ones */
7a50f01a
DA		 1908 if (config_aper_size > rdev->mc.real_vram_size)
1909 rdev->mc.mc_vram_size = config_aper_size;
1910 else
1911 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 1912 }
1913
2a0f8918
DA		 1914 /* work out accessible VRAM */
1915 accessible = r100_get_accessible_vram(rdev);
1916
771fe6b9
JG		 1917 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1918 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2a0f8918
DA		 1919
1920 if (accessible > rdev->mc.aper_size)
1921 accessible = rdev->mc.aper_size;
1922
7a50f01a
DA		 1923 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1924 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1925
1926 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1927 rdev->mc.real_vram_size = rdev->mc.aper_size;
2a0f8918
DA		 1928}
1929
28d52043
DA		 1930void r100_vga_set_state(struct radeon_device *rdev, bool state)
1931{
1932 uint32_t temp;
1933
1934 temp = RREG32(RADEON_CONFIG_CNTL);
1935 if (state == false) {
1936 temp &= ~(1<<8);
1937 temp |= (1<<9);
1938 } else {
1939 temp &= ~(1<<9);
1940 }
1941 WREG32(RADEON_CONFIG_CNTL, temp);
1942}
1943
2a0f8918
DA		 1944void r100_vram_info(struct radeon_device *rdev)
1945{
1946 r100_vram_get_type(rdev);
1947
1948 r100_vram_init_sizes(rdev);
771fe6b9
JG		 1949}
1950
1951
1952/*
1953 * Indirect registers accessor
1954 */
1955void r100_pll_errata_after_index(struct radeon_device *rdev)
1956{
1957 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1958 return;
1959 }
1960 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1961 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1962}
1963
1964static void r100_pll_errata_after_data(struct radeon_device *rdev)
1965{
1966 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1967 * or the chip could hang on a subsequent access
1968 */
1969 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1970 udelay(5000);
1971 }
1972
1973 /* This function is required to workaround a hardware bug in some (all?)
1974 * revisions of the R300. This workaround should be called after every
1975 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1976 * may not be correct.
1977 */
1978 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1979 uint32_t save, tmp;
1980
1981 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1982 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1983 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1984 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1985 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1986 }
1987}
1988
1989uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1990{
1991 uint32_t data;
1992
1993 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1994 r100_pll_errata_after_index(rdev);
1995 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1996 r100_pll_errata_after_data(rdev);
1997 return data;
1998}
1999
2000void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2001{
2002 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2003 r100_pll_errata_after_index(rdev);
2004 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2005 r100_pll_errata_after_data(rdev);
2006}
2007
d4550907 2008void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2009{
551ebd83
DA		 2010 if (ASIC_IS_RN50(rdev)) {
2011 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2012 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2013 } else if (rdev->family < CHIP_R200) {
2014 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2015 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2016 } else {
d4550907 2017 r200_set_safe_registers(rdev);
551ebd83 2018 }
068a117c
JG		 2019}
2020
771fe6b9
JG		 2021/*
2022 * Debugfs info
2023 */
2024#if defined(CONFIG_DEBUG_FS)
2025static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2026{
2027 struct drm_info_node *node = (struct drm_info_node *) m->private;
2028 struct drm_device *dev = node->minor->dev;
2029 struct radeon_device *rdev = dev->dev_private;
2030 uint32_t reg, value;
2031 unsigned i;
2032
2033 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2034 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2035 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2036 for (i = 0; i < 64; i++) {
2037 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2038 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2039 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2040 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2041 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2042 }
2043 return 0;
2044}
2045
2046static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2047{
2048 struct drm_info_node *node = (struct drm_info_node *) m->private;
2049 struct drm_device *dev = node->minor->dev;
2050 struct radeon_device *rdev = dev->dev_private;
2051 uint32_t rdp, wdp;
2052 unsigned count, i, j;
2053
2054 radeon_ring_free_size(rdev);
2055 rdp = RREG32(RADEON_CP_RB_RPTR);
2056 wdp = RREG32(RADEON_CP_RB_WPTR);
2057 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2058 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2059 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2060 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2061 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2062 seq_printf(m, "%u dwords in ring\n", count);
2063 for (j = 0; j <= count; j++) {
2064 i = (rdp + j) & rdev->cp.ptr_mask;
2065 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2066 }
2067 return 0;
2068}
2069
2070
2071static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2072{
2073 struct drm_info_node *node = (struct drm_info_node *) m->private;
2074 struct drm_device *dev = node->minor->dev;
2075 struct radeon_device *rdev = dev->dev_private;
2076 uint32_t csq_stat, csq2_stat, tmp;
2077 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2078 unsigned i;
2079
2080 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2081 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2082 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2083 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2084 r_rptr = (csq_stat >> 0) & 0x3ff;
2085 r_wptr = (csq_stat >> 10) & 0x3ff;
2086 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2087 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2088 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2089 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2090 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2091 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2092 seq_printf(m, "Ring rptr %u\n", r_rptr);
2093 seq_printf(m, "Ring wptr %u\n", r_wptr);
2094 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2095 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2096 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2097 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2098 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2099 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2100 seq_printf(m, "Ring fifo:\n");
2101 for (i = 0; i < 256; i++) {
2102 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2103 tmp = RREG32(RADEON_CP_CSQ_DATA);
2104 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2105 }
2106 seq_printf(m, "Indirect1 fifo:\n");
2107 for (i = 256; i <= 512; i++) {
2108 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2109 tmp = RREG32(RADEON_CP_CSQ_DATA);
2110 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2111 }
2112 seq_printf(m, "Indirect2 fifo:\n");
2113 for (i = 640; i < ib1_wptr; i++) {
2114 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2115 tmp = RREG32(RADEON_CP_CSQ_DATA);
2116 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2117 }
2118 return 0;
2119}
2120
2121static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2122{
2123 struct drm_info_node *node = (struct drm_info_node *) m->private;
2124 struct drm_device *dev = node->minor->dev;
2125 struct radeon_device *rdev = dev->dev_private;
2126 uint32_t tmp;
2127
2128 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2129 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2130 tmp = RREG32(RADEON_MC_FB_LOCATION);
2131 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2132 tmp = RREG32(RADEON_BUS_CNTL);
2133 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2134 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2135 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2136 tmp = RREG32(RADEON_AGP_BASE);
2137 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2138 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2139 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2140 tmp = RREG32(0x01D0);
2141 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2142 tmp = RREG32(RADEON_AIC_LO_ADDR);
2143 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2144 tmp = RREG32(RADEON_AIC_HI_ADDR);
2145 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2146 tmp = RREG32(0x01E4);
2147 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2148 return 0;
2149}
2150
2151static struct drm_info_list r100_debugfs_rbbm_list[] = {
2152 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2153};
2154
2155static struct drm_info_list r100_debugfs_cp_list[] = {
2156 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2157 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2158};
2159
2160static struct drm_info_list r100_debugfs_mc_info_list[] = {
2161 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2162};
2163#endif
2164
2165int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2166{
2167#if defined(CONFIG_DEBUG_FS)
2168 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2169#else
2170 return 0;
2171#endif
2172}
2173
2174int r100_debugfs_cp_init(struct radeon_device *rdev)
2175{
2176#if defined(CONFIG_DEBUG_FS)
2177 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2178#else
2179 return 0;
2180#endif
2181}
2182
2183int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2184{
2185#if defined(CONFIG_DEBUG_FS)
2186 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2187#else
2188 return 0;
2189#endif
2190}
e024e110
DA		 2191
2192int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2193 uint32_t tiling_flags, uint32_t pitch,
2194 uint32_t offset, uint32_t obj_size)
2195{
2196 int surf_index = reg * 16;
2197 int flags = 0;
2198
2199 /* r100/r200 divide by 16 */
2200 if (rdev->family < CHIP_R300)
2201 flags = pitch / 16;
2202 else
2203 flags = pitch / 8;
2204
2205 if (rdev->family <= CHIP_RS200) {
2206 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2207 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2208 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2209 if (tiling_flags & RADEON_TILING_MACRO)
2210 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2211 } else if (rdev->family <= CHIP_RV280) {
2212 if (tiling_flags & (RADEON_TILING_MACRO))
2213 flags |= R200_SURF_TILE_COLOR_MACRO;
2214 if (tiling_flags & RADEON_TILING_MICRO)
2215 flags |= R200_SURF_TILE_COLOR_MICRO;
2216 } else {
2217 if (tiling_flags & RADEON_TILING_MACRO)
2218 flags |= R300_SURF_TILE_MACRO;
2219 if (tiling_flags & RADEON_TILING_MICRO)
2220 flags |= R300_SURF_TILE_MICRO;
2221 }
2222
c88f9f0c
MD		 2223 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2224 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2225 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2226 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2227
e024e110
DA		 2228 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2229 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2230 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2231 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2232 return 0;
2233}
2234
2235void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2236{
2237 int surf_index = reg * 16;
2238 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2239}
c93bb85b
JG		 2240
2241void r100_bandwidth_update(struct radeon_device *rdev)
2242{
2243 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2244 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2245 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2246 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2247 fixed20_12 memtcas_ff[8] = {
2248 fixed_init(1),
2249 fixed_init(2),
2250 fixed_init(3),
2251 fixed_init(0),
2252 fixed_init_half(1),
2253 fixed_init_half(2),
2254 fixed_init(0),
2255 };
2256 fixed20_12 memtcas_rs480_ff[8] = {
2257 fixed_init(0),
2258 fixed_init(1),
2259 fixed_init(2),
2260 fixed_init(3),
2261 fixed_init(0),
2262 fixed_init_half(1),
2263 fixed_init_half(2),
2264 fixed_init_half(3),
2265 };
2266 fixed20_12 memtcas2_ff[8] = {
2267 fixed_init(0),
2268 fixed_init(1),
2269 fixed_init(2),
2270 fixed_init(3),
2271 fixed_init(4),
2272 fixed_init(5),
2273 fixed_init(6),
2274 fixed_init(7),
2275 };
2276 fixed20_12 memtrbs[8] = {
2277 fixed_init(1),
2278 fixed_init_half(1),
2279 fixed_init(2),
2280 fixed_init_half(2),
2281 fixed_init(3),
2282 fixed_init_half(3),
2283 fixed_init(4),
2284 fixed_init_half(4)
2285 };
2286 fixed20_12 memtrbs_r4xx[8] = {
2287 fixed_init(4),
2288 fixed_init(5),
2289 fixed_init(6),
2290 fixed_init(7),
2291 fixed_init(8),
2292 fixed_init(9),
2293 fixed_init(10),
2294 fixed_init(11)
2295 };
2296 fixed20_12 min_mem_eff;
2297 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2298 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2299 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2300 disp_drain_rate2, read_return_rate;
2301 fixed20_12 time_disp1_drop_priority;
2302 int c;
2303 int cur_size = 16; /* in octawords */
2304 int critical_point = 0, critical_point2;
2305/* uint32_t read_return_rate, time_disp1_drop_priority; */
2306 int stop_req, max_stop_req;
2307 struct drm_display_mode *mode1 = NULL;
2308 struct drm_display_mode *mode2 = NULL;
2309 uint32_t pixel_bytes1 = 0;
2310 uint32_t pixel_bytes2 = 0;
2311
2312 if (rdev->mode_info.crtcs[0]->base.enabled) {
2313 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2314 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2315 }
dfee5614
DA		 2316 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2317 if (rdev->mode_info.crtcs[1]->base.enabled) {
2318 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2319 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2320 }
c93bb85b
JG		 2321 }
2322
2323 min_mem_eff.full = rfixed_const_8(0);
2324 /* get modes */
2325 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2326 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2327 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2328 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2329 /* check crtc enables */
2330 if (mode2)
2331 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2332 if (mode1)
2333 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2334 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2335 }
2336
2337 /*
2338 * determine is there is enough bw for current mode
2339 */
2340 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2341 temp_ff.full = rfixed_const(100);
2342 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2343 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2344 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2345
2346 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2347 temp_ff.full = rfixed_const(temp);
2348 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2349
2350 pix_clk.full = 0;
2351 pix_clk2.full = 0;
2352 peak_disp_bw.full = 0;
2353 if (mode1) {
2354 temp_ff.full = rfixed_const(1000);
2355 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2356 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2357 temp_ff.full = rfixed_const(pixel_bytes1);
2358 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2359 }
2360 if (mode2) {
2361 temp_ff.full = rfixed_const(1000);
2362 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2363 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2364 temp_ff.full = rfixed_const(pixel_bytes2);
2365 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2366 }
2367
2368 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2369 if (peak_disp_bw.full >= mem_bw.full) {
2370 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2371 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2372 }
2373
2374 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2375 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2376 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2377 mem_trcd = ((temp >> 2) & 0x3) + 1;
2378 mem_trp = ((temp & 0x3)) + 1;
2379 mem_tras = ((temp & 0x70) >> 4) + 1;
2380 } else if (rdev->family == CHIP_R300 ||
2381 rdev->family == CHIP_R350) { /* r300, r350 */
2382 mem_trcd = (temp & 0x7) + 1;
2383 mem_trp = ((temp >> 8) & 0x7) + 1;
2384 mem_tras = ((temp >> 11) & 0xf) + 4;
2385 } else if (rdev->family == CHIP_RV350 ||
2386 rdev->family <= CHIP_RV380) {
2387 /* rv3x0 */
2388 mem_trcd = (temp & 0x7) + 3;
2389 mem_trp = ((temp >> 8) & 0x7) + 3;
2390 mem_tras = ((temp >> 11) & 0xf) + 6;
2391 } else if (rdev->family == CHIP_R420 ||
2392 rdev->family == CHIP_R423 ||
2393 rdev->family == CHIP_RV410) {
2394 /* r4xx */
2395 mem_trcd = (temp & 0xf) + 3;
2396 if (mem_trcd > 15)
2397 mem_trcd = 15;
2398 mem_trp = ((temp >> 8) & 0xf) + 3;
2399 if (mem_trp > 15)
2400 mem_trp = 15;
2401 mem_tras = ((temp >> 12) & 0x1f) + 6;
2402 if (mem_tras > 31)
2403 mem_tras = 31;
2404 } else { /* RV200, R200 */
2405 mem_trcd = (temp & 0x7) + 1;
2406 mem_trp = ((temp >> 8) & 0x7) + 1;
2407 mem_tras = ((temp >> 12) & 0xf) + 4;
2408 }
2409 /* convert to FF */
2410 trcd_ff.full = rfixed_const(mem_trcd);
2411 trp_ff.full = rfixed_const(mem_trp);
2412 tras_ff.full = rfixed_const(mem_tras);
2413
2414 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2415 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2416 data = (temp & (7 << 20)) >> 20;
2417 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2418 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2419 tcas_ff = memtcas_rs480_ff[data];
2420 else
2421 tcas_ff = memtcas_ff[data];
2422 } else
2423 tcas_ff = memtcas2_ff[data];
2424
2425 if (rdev->family == CHIP_RS400 ||
2426 rdev->family == CHIP_RS480) {
2427 /* extra cas latency stored in bits 23-25 0-4 clocks */
2428 data = (temp >> 23) & 0x7;
2429 if (data < 5)
2430 tcas_ff.full += rfixed_const(data);
2431 }
2432
2433 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2434 /* on the R300, Tcas is included in Trbs.
2435 */
2436 temp = RREG32(RADEON_MEM_CNTL);
2437 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2438 if (data == 1) {
2439 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2440 temp = RREG32(R300_MC_IND_INDEX);
2441 temp &= ~R300_MC_IND_ADDR_MASK;
2442 temp |= R300_MC_READ_CNTL_CD_mcind;
2443 WREG32(R300_MC_IND_INDEX, temp);
2444 temp = RREG32(R300_MC_IND_DATA);
2445 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2446 } else {
2447 temp = RREG32(R300_MC_READ_CNTL_AB);
2448 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2449 }
2450 } else {
2451 temp = RREG32(R300_MC_READ_CNTL_AB);
2452 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2453 }
2454 if (rdev->family == CHIP_RV410 ||
2455 rdev->family == CHIP_R420 ||
2456 rdev->family == CHIP_R423)
2457 trbs_ff = memtrbs_r4xx[data];
2458 else
2459 trbs_ff = memtrbs[data];
2460 tcas_ff.full += trbs_ff.full;
2461 }
2462
2463 sclk_eff_ff.full = sclk_ff.full;
2464
2465 if (rdev->flags & RADEON_IS_AGP) {
2466 fixed20_12 agpmode_ff;
2467 agpmode_ff.full = rfixed_const(radeon_agpmode);
2468 temp_ff.full = rfixed_const_666(16);
2469 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2470 }
2471 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2472
2473 if (ASIC_IS_R300(rdev)) {
2474 sclk_delay_ff.full = rfixed_const(250);
2475 } else {
2476 if ((rdev->family == CHIP_RV100) ||
2477 rdev->flags & RADEON_IS_IGP) {
2478 if (rdev->mc.vram_is_ddr)
2479 sclk_delay_ff.full = rfixed_const(41);
2480 else
2481 sclk_delay_ff.full = rfixed_const(33);
2482 } else {
2483 if (rdev->mc.vram_width == 128)
2484 sclk_delay_ff.full = rfixed_const(57);
2485 else
2486 sclk_delay_ff.full = rfixed_const(41);
2487 }
2488 }
2489
2490 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2491
2492 if (rdev->mc.vram_is_ddr) {
2493 if (rdev->mc.vram_width == 32) {
2494 k1.full = rfixed_const(40);
2495 c = 3;
2496 } else {
2497 k1.full = rfixed_const(20);
2498 c = 1;
2499 }
2500 } else {
2501 k1.full = rfixed_const(40);
2502 c = 3;
2503 }
2504
2505 temp_ff.full = rfixed_const(2);
2506 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2507 temp_ff.full = rfixed_const(c);
2508 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2509 temp_ff.full = rfixed_const(4);
2510 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2511 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2512 mc_latency_mclk.full += k1.full;
2513
2514 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2515 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2516
2517 /*
2518 HW cursor time assuming worst case of full size colour cursor.
2519 */
2520 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2521 temp_ff.full += trcd_ff.full;
2522 if (temp_ff.full < tras_ff.full)
2523 temp_ff.full = tras_ff.full;
2524 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2525
2526 temp_ff.full = rfixed_const(cur_size);
2527 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2528 /*
2529 Find the total latency for the display data.
2530 */
b5fc9010 2531 disp_latency_overhead.full = rfixed_const(8);
c93bb85b
JG		 2532 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2533 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2534 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2535
2536 if (mc_latency_mclk.full > mc_latency_sclk.full)
2537 disp_latency.full = mc_latency_mclk.full;
2538 else
2539 disp_latency.full = mc_latency_sclk.full;
2540
2541 /* setup Max GRPH_STOP_REQ default value */
2542 if (ASIC_IS_RV100(rdev))
2543 max_stop_req = 0x5c;
2544 else
2545 max_stop_req = 0x7c;
2546
2547 if (mode1) {
2548 /* CRTC1
2549 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2550 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2551 */
2552 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2553
2554 if (stop_req > max_stop_req)
2555 stop_req = max_stop_req;
2556
2557 /*
2558 Find the drain rate of the display buffer.
2559 */
2560 temp_ff.full = rfixed_const((16/pixel_bytes1));
2561 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2562
2563 /*
2564 Find the critical point of the display buffer.
2565 */
2566 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2567 crit_point_ff.full += rfixed_const_half(0);
2568
2569 critical_point = rfixed_trunc(crit_point_ff);
2570
2571 if (rdev->disp_priority == 2) {
2572 critical_point = 0;
2573 }
2574
2575 /*
2576 The critical point should never be above max_stop_req-4. Setting
2577 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2578 */
2579 if (max_stop_req - critical_point < 4)
2580 critical_point = 0;
2581
2582 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2583 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2584 critical_point = 0x10;
2585 }
2586
2587 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2588 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2589 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2590 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2591 if ((rdev->family == CHIP_R350) &&
2592 (stop_req > 0x15)) {
2593 stop_req -= 0x10;
2594 }
2595 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2596 temp |= RADEON_GRPH_BUFFER_SIZE;
2597 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2598 RADEON_GRPH_CRITICAL_AT_SOF |
2599 RADEON_GRPH_STOP_CNTL);
2600 /*
2601 Write the result into the register.
2602 */
2603 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2604 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2605
2606#if 0
2607 if ((rdev->family == CHIP_RS400) ||
2608 (rdev->family == CHIP_RS480)) {
2609 /* attempt to program RS400 disp regs correctly ??? */
2610 temp = RREG32(RS400_DISP1_REG_CNTL);
2611 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2612 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2613 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2614 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2615 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2616 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2617 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2618 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2619 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2620 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2621 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2622 }
2623#endif
2624
2625 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2626 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2627 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2628 }
2629
2630 if (mode2) {
2631 u32 grph2_cntl;
2632 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2633
2634 if (stop_req > max_stop_req)
2635 stop_req = max_stop_req;
2636
2637 /*
2638 Find the drain rate of the display buffer.
2639 */
2640 temp_ff.full = rfixed_const((16/pixel_bytes2));
2641 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2642
2643 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2644 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2645 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2646 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2647 if ((rdev->family == CHIP_R350) &&
2648 (stop_req > 0x15)) {
2649 stop_req -= 0x10;
2650 }
2651 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2652 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2653 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2654 RADEON_GRPH_CRITICAL_AT_SOF |
2655 RADEON_GRPH_STOP_CNTL);
2656
2657 if ((rdev->family == CHIP_RS100) ||
2658 (rdev->family == CHIP_RS200))
2659 critical_point2 = 0;
2660 else {
2661 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2662 temp_ff.full = rfixed_const(temp);
2663 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2664 if (sclk_ff.full < temp_ff.full)
2665 temp_ff.full = sclk_ff.full;
2666
2667 read_return_rate.full = temp_ff.full;
2668
2669 if (mode1) {
2670 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2671 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2672 } else {
2673 time_disp1_drop_priority.full = 0;
2674 }
2675 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2676 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2677 crit_point_ff.full += rfixed_const_half(0);
2678
2679 critical_point2 = rfixed_trunc(crit_point_ff);
2680
2681 if (rdev->disp_priority == 2) {
2682 critical_point2 = 0;
2683 }
2684
2685 if (max_stop_req - critical_point2 < 4)
2686 critical_point2 = 0;
2687
2688 }
2689
2690 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2691 /* some R300 cards have problem with this set to 0 */
2692 critical_point2 = 0x10;
2693 }
2694
2695 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2696 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2697
2698 if ((rdev->family == CHIP_RS400) ||
2699 (rdev->family == CHIP_RS480)) {
2700#if 0
2701 /* attempt to program RS400 disp2 regs correctly ??? */
2702 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2703 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2704 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2705 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2706 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2707 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2708 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2709 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2710 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2711 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2712 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2713 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2714#endif
2715 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2716 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2717 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2718 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2719 }
2720
2721 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2722 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2723 }
2724}
551ebd83
DA		 2725
2726static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2727{
2728 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 2729 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 2730 DRM_ERROR("width %d\n", t->width);
ceb776bc 2731 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 2732 DRM_ERROR("height %d\n", t->height);
ceb776bc 2733 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 2734 DRM_ERROR("num levels %d\n", t->num_levels);
2735 DRM_ERROR("depth %d\n", t->txdepth);
2736 DRM_ERROR("bpp %d\n", t->cpp);
2737 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2738 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2739 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 2740 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 2741}
2742
2743static int r100_cs_track_cube(struct radeon_device *rdev,
2744 struct r100_cs_track *track, unsigned idx)
2745{
2746 unsigned face, w, h;
4c788679 2747 struct radeon_bo *cube_robj;
551ebd83
DA		 2748 unsigned long size;
2749
2750 for (face = 0; face < 5; face++) {
2751 cube_robj = track->textures[idx].cube_info[face].robj;
2752 w = track->textures[idx].cube_info[face].width;
2753 h = track->textures[idx].cube_info[face].height;
2754
2755 size = w * h;
2756 size *= track->textures[idx].cpp;
2757
2758 size += track->textures[idx].cube_info[face].offset;
2759
4c788679 2760 if (size > radeon_bo_size(cube_robj)) {
551ebd83 2761 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
4c788679 2762 size, radeon_bo_size(cube_robj));
551ebd83
DA		 2763 r100_cs_track_texture_print(&track->textures[idx]);
2764 return -1;
2765 }
2766 }
2767 return 0;
2768}
2769
d785d78b
DA		 2770static int r100_track_compress_size(int compress_format, int w, int h)
2771{
2772 int block_width, block_height, block_bytes;
2773 int wblocks, hblocks;
2774 int min_wblocks;
2775 int sz;
2776
2777 block_width = 4;
2778 block_height = 4;
2779
2780 switch (compress_format) {
2781 case R100_TRACK_COMP_DXT1:
2782 block_bytes = 8;
2783 min_wblocks = 4;
2784 break;
2785 default:
2786 case R100_TRACK_COMP_DXT35:
2787 block_bytes = 16;
2788 min_wblocks = 2;
2789 break;
2790 }
2791
2792 hblocks = (h + block_height - 1) / block_height;
2793 wblocks = (w + block_width - 1) / block_width;
2794 if (wblocks < min_wblocks)
2795 wblocks = min_wblocks;
2796 sz = wblocks * hblocks * block_bytes;
2797 return sz;
2798}
2799
551ebd83
DA		 2800static int r100_cs_track_texture_check(struct radeon_device *rdev,
2801 struct r100_cs_track *track)
2802{
4c788679 2803 struct radeon_bo *robj;
551ebd83
DA		 2804 unsigned long size;
2805 unsigned u, i, w, h;
2806 int ret;
2807
2808 for (u = 0; u < track->num_texture; u++) {
2809 if (!track->textures[u].enabled)
2810 continue;
2811 robj = track->textures[u].robj;
2812 if (robj == NULL) {
2813 DRM_ERROR("No texture bound to unit %u\n", u);
2814 return -EINVAL;
2815 }
2816 size = 0;
2817 for (i = 0; i <= track->textures[u].num_levels; i++) {
2818 if (track->textures[u].use_pitch) {
2819 if (rdev->family < CHIP_R300)
2820 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2821 else
2822 w = track->textures[u].pitch / (1 << i);
2823 } else {
ceb776bc 2824 w = track->textures[u].width;
551ebd83
DA		 2825 if (rdev->family >= CHIP_RV515)
2826 w |= track->textures[u].width_11;
ceb776bc 2827 w = w / (1 << i);
551ebd83
DA		 2828 if (track->textures[u].roundup_w)
2829 w = roundup_pow_of_two(w);
2830 }
ceb776bc 2831 h = track->textures[u].height;
551ebd83
DA		 2832 if (rdev->family >= CHIP_RV515)
2833 h |= track->textures[u].height_11;
ceb776bc 2834 h = h / (1 << i);
551ebd83
DA		 2835 if (track->textures[u].roundup_h)
2836 h = roundup_pow_of_two(h);
d785d78b
DA		 2837 if (track->textures[u].compress_format) {
2838
2839 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2840 /* compressed textures are block based */
2841 } else
2842 size += w * h;
551ebd83
DA		 2843 }
2844 size *= track->textures[u].cpp;
d785d78b 2845
551ebd83
DA		 2846 switch (track->textures[u].tex_coord_type) {
2847 case 0:
2848 break;
2849 case 1:
2850 size *= (1 << track->textures[u].txdepth);
2851 break;
2852 case 2:
2853 if (track->separate_cube) {
2854 ret = r100_cs_track_cube(rdev, track, u);
2855 if (ret)
2856 return ret;
2857 } else
2858 size *= 6;
2859 break;
2860 default:
2861 DRM_ERROR("Invalid texture coordinate type %u for unit "
2862 "%u\n", track->textures[u].tex_coord_type, u);
2863 return -EINVAL;
2864 }
4c788679 2865 if (size > radeon_bo_size(robj)) {
551ebd83 2866 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 2867 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 2868 r100_cs_track_texture_print(&track->textures[u]);
2869 return -EINVAL;
2870 }
2871 }
2872 return 0;
2873}
2874
2875int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2876{
2877 unsigned i;
2878 unsigned long size;
2879 unsigned prim_walk;
2880 unsigned nverts;
2881
2882 for (i = 0; i < track->num_cb; i++) {
2883 if (track->cb[i].robj == NULL) {
2884 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2885 return -EINVAL;
2886 }
2887 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2888 size += track->cb[i].offset;
4c788679 2889 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 2890 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2891 "(need %lu have %lu) !\n", i, size,
4c788679 2892 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 2893 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2894 i, track->cb[i].pitch, track->cb[i].cpp,
2895 track->cb[i].offset, track->maxy);
2896 return -EINVAL;
2897 }
2898 }
2899 if (track->z_enabled) {
2900 if (track->zb.robj == NULL) {
2901 DRM_ERROR("[drm] No buffer for z buffer !\n");
2902 return -EINVAL;
2903 }
2904 size = track->zb.pitch * track->zb.cpp * track->maxy;
2905 size += track->zb.offset;
4c788679 2906 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 2907 DRM_ERROR("[drm] Buffer too small for z buffer "
2908 "(need %lu have %lu) !\n", size,
4c788679 2909 radeon_bo_size(track->zb.robj));
551ebd83
DA		 2910 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2911 track->zb.pitch, track->zb.cpp,
2912 track->zb.offset, track->maxy);
2913 return -EINVAL;
2914 }
2915 }
2916 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2917 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2918 switch (prim_walk) {
2919 case 1:
2920 for (i = 0; i < track->num_arrays; i++) {
2921 size = track->arrays[i].esize * track->max_indx * 4;
2922 if (track->arrays[i].robj == NULL) {
2923 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2924 "bound\n", prim_walk, i);
2925 return -EINVAL;
2926 }
4c788679
JG		 2927 if (size > radeon_bo_size(track->arrays[i].robj)) {
2928 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2929 "need %lu dwords have %lu dwords\n",
2930 prim_walk, i, size >> 2,
2931 radeon_bo_size(track->arrays[i].robj)
2932 >> 2);
551ebd83
DA		 2933 DRM_ERROR("Max indices %u\n", track->max_indx);
2934 return -EINVAL;
2935 }
2936 }
2937 break;
2938 case 2:
2939 for (i = 0; i < track->num_arrays; i++) {
2940 size = track->arrays[i].esize * (nverts - 1) * 4;
2941 if (track->arrays[i].robj == NULL) {
2942 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2943 "bound\n", prim_walk, i);
2944 return -EINVAL;
2945 }
4c788679
JG		 2946 if (size > radeon_bo_size(track->arrays[i].robj)) {
2947 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2948 "need %lu dwords have %lu dwords\n",
2949 prim_walk, i, size >> 2,
2950 radeon_bo_size(track->arrays[i].robj)
2951 >> 2);
551ebd83
DA		 2952 return -EINVAL;
2953 }
2954 }
2955 break;
2956 case 3:
2957 size = track->vtx_size * nverts;
2958 if (size != track->immd_dwords) {
2959 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2960 track->immd_dwords, size);
2961 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2962 nverts, track->vtx_size);
2963 return -EINVAL;
2964 }
2965 break;
2966 default:
2967 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2968 prim_walk);
2969 return -EINVAL;
2970 }
2971 return r100_cs_track_texture_check(rdev, track);
2972}
2973
2974void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2975{
2976 unsigned i, face;
2977
2978 if (rdev->family < CHIP_R300) {
2979 track->num_cb = 1;
2980 if (rdev->family <= CHIP_RS200)
2981 track->num_texture = 3;
2982 else
2983 track->num_texture = 6;
2984 track->maxy = 2048;
2985 track->separate_cube = 1;
2986 } else {
2987 track->num_cb = 4;
2988 track->num_texture = 16;
2989 track->maxy = 4096;
2990 track->separate_cube = 0;
2991 }
2992
2993 for (i = 0; i < track->num_cb; i++) {
2994 track->cb[i].robj = NULL;
2995 track->cb[i].pitch = 8192;
2996 track->cb[i].cpp = 16;
2997 track->cb[i].offset = 0;
2998 }
2999 track->z_enabled = true;
3000 track->zb.robj = NULL;
3001 track->zb.pitch = 8192;
3002 track->zb.cpp = 4;
3003 track->zb.offset = 0;
3004 track->vtx_size = 0x7F;
3005 track->immd_dwords = 0xFFFFFFFFUL;
3006 track->num_arrays = 11;
3007 track->max_indx = 0x00FFFFFFUL;
3008 for (i = 0; i < track->num_arrays; i++) {
3009 track->arrays[i].robj = NULL;
3010 track->arrays[i].esize = 0x7F;
3011 }
3012 for (i = 0; i < track->num_texture; i++) {
d785d78b 3013 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3014 track->textures[i].pitch = 16536;
3015 track->textures[i].width = 16536;
3016 track->textures[i].height = 16536;
3017 track->textures[i].width_11 = 1 << 11;
3018 track->textures[i].height_11 = 1 << 11;
3019 track->textures[i].num_levels = 12;
3020 if (rdev->family <= CHIP_RS200) {
3021 track->textures[i].tex_coord_type = 0;
3022 track->textures[i].txdepth = 0;
3023 } else {
3024 track->textures[i].txdepth = 16;
3025 track->textures[i].tex_coord_type = 1;
3026 }
3027 track->textures[i].cpp = 64;
3028 track->textures[i].robj = NULL;
3029 /* CS IB emission code makes sure texture unit are disabled */
3030 track->textures[i].enabled = false;
3031 track->textures[i].roundup_w = true;
3032 track->textures[i].roundup_h = true;
3033 if (track->separate_cube)
3034 for (face = 0; face < 5; face++) {
3035 track->textures[i].cube_info[face].robj = NULL;
3036 track->textures[i].cube_info[face].width = 16536;
3037 track->textures[i].cube_info[face].height = 16536;
3038 track->textures[i].cube_info[face].offset = 0;
3039 }
3040 }
3041}
3ce0a23d
JG		 3042
3043int r100_ring_test(struct radeon_device *rdev)
3044{
3045 uint32_t scratch;
3046 uint32_t tmp = 0;
3047 unsigned i;
3048 int r;
3049
3050 r = radeon_scratch_get(rdev, &scratch);
3051 if (r) {
3052 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3053 return r;
3054 }
3055 WREG32(scratch, 0xCAFEDEAD);
3056 r = radeon_ring_lock(rdev, 2);
3057 if (r) {
3058 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3059 radeon_scratch_free(rdev, scratch);
3060 return r;
3061 }
3062 radeon_ring_write(rdev, PACKET0(scratch, 0));
3063 radeon_ring_write(rdev, 0xDEADBEEF);
3064 radeon_ring_unlock_commit(rdev);
3065 for (i = 0; i < rdev->usec_timeout; i++) {
3066 tmp = RREG32(scratch);
3067 if (tmp == 0xDEADBEEF) {
3068 break;
3069 }
3070 DRM_UDELAY(1);
3071 }
3072 if (i < rdev->usec_timeout) {
3073 DRM_INFO("ring test succeeded in %d usecs\n", i);
3074 } else {
3075 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3076 scratch, tmp);
3077 r = -EINVAL;
3078 }
3079 radeon_scratch_free(rdev, scratch);
3080 return r;
3081}
3082
3083void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3084{
3085 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3086 radeon_ring_write(rdev, ib->gpu_addr);
3087 radeon_ring_write(rdev, ib->length_dw);
3088}
3089
3090int r100_ib_test(struct radeon_device *rdev)
3091{
3092 struct radeon_ib *ib;
3093 uint32_t scratch;
3094 uint32_t tmp = 0;
3095 unsigned i;
3096 int r;
3097
3098 r = radeon_scratch_get(rdev, &scratch);
3099 if (r) {
3100 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3101 return r;
3102 }
3103 WREG32(scratch, 0xCAFEDEAD);
3104 r = radeon_ib_get(rdev, &ib);
3105 if (r) {
3106 return r;
3107 }
3108 ib->ptr[0] = PACKET0(scratch, 0);
3109 ib->ptr[1] = 0xDEADBEEF;
3110 ib->ptr[2] = PACKET2(0);
3111 ib->ptr[3] = PACKET2(0);
3112 ib->ptr[4] = PACKET2(0);
3113 ib->ptr[5] = PACKET2(0);
3114 ib->ptr[6] = PACKET2(0);
3115 ib->ptr[7] = PACKET2(0);
3116 ib->length_dw = 8;
3117 r = radeon_ib_schedule(rdev, ib);
3118 if (r) {
3119 radeon_scratch_free(rdev, scratch);
3120 radeon_ib_free(rdev, &ib);
3121 return r;
3122 }
3123 r = radeon_fence_wait(ib->fence, false);
3124 if (r) {
3125 return r;
3126 }
3127 for (i = 0; i < rdev->usec_timeout; i++) {
3128 tmp = RREG32(scratch);
3129 if (tmp == 0xDEADBEEF) {
3130 break;
3131 }
3132 DRM_UDELAY(1);
3133 }
3134 if (i < rdev->usec_timeout) {
3135 DRM_INFO("ib test succeeded in %u usecs\n", i);
3136 } else {
3137 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3138 scratch, tmp);
3139 r = -EINVAL;
3140 }
3141 radeon_scratch_free(rdev, scratch);
3142 radeon_ib_free(rdev, &ib);
3143 return r;
3144}
9f022ddf
JG		 3145
3146void r100_ib_fini(struct radeon_device *rdev)
3147{
3148 radeon_ib_pool_fini(rdev);
3149}
3150
3151int r100_ib_init(struct radeon_device *rdev)
3152{
3153 int r;
3154
3155 r = radeon_ib_pool_init(rdev);
3156 if (r) {
3157 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3158 r100_ib_fini(rdev);
3159 return r;
3160 }
3161 r = r100_ib_test(rdev);
3162 if (r) {
3163 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3164 r100_ib_fini(rdev);
3165 return r;
3166 }
3167 return 0;
3168}
3169
3170void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3171{
3172 /* Shutdown CP we shouldn't need to do that but better be safe than
3173 * sorry
3174 */
3175 rdev->cp.ready = false;
3176 WREG32(R_000740_CP_CSQ_CNTL, 0);
3177
3178 /* Save few CRTC registers */
ca6ffc64 3179 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3180 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3181 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3182 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3183 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3184 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3185 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3186 }
3187
3188 /* Disable VGA aperture access */
ca6ffc64 3189 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3190 /* Disable cursor, overlay, crtc */
3191 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3192 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3193 S_000054_CRTC_DISPLAY_DIS(1));
3194 WREG32(R_000050_CRTC_GEN_CNTL,
3195 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3196 S_000050_CRTC_DISP_REQ_EN_B(1));
3197 WREG32(R_000420_OV0_SCALE_CNTL,
3198 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3199 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3200 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3201 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3202 S_000360_CUR2_LOCK(1));
3203 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3204 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3205 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3206 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3207 WREG32(R_000360_CUR2_OFFSET,
3208 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3209 }
3210}
3211
3212void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3213{
3214 /* Update base address for crtc */
3215 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3216 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3217 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3218 rdev->mc.vram_location);
3219 }
3220 /* Restore CRTC registers */
ca6ffc64 3221 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3222 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3223 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3224 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3225 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3226 }
3227}
ca6ffc64
JG		 3228
3229void r100_vga_render_disable(struct radeon_device *rdev)
3230{
d4550907 3231 u32 tmp;
ca6ffc64 3232
d4550907 3233 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3234 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3235}
d4550907
JG		 3236
3237static void r100_debugfs(struct radeon_device *rdev)
3238{
3239 int r;
3240
3241 r = r100_debugfs_mc_info_init(rdev);
3242 if (r)
3243 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3244}
3245
3246static void r100_mc_program(struct radeon_device *rdev)
3247{
3248 struct r100_mc_save save;
3249
3250 /* Stops all mc clients */
3251 r100_mc_stop(rdev, &save);
3252 if (rdev->flags & RADEON_IS_AGP) {
3253 WREG32(R_00014C_MC_AGP_LOCATION,
3254 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3255 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3256 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3257 if (rdev->family > CHIP_RV200)
3258 WREG32(R_00015C_AGP_BASE_2,
3259 upper_32_bits(rdev->mc.agp_base) & 0xff);
3260 } else {
3261 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3262 WREG32(R_000170_AGP_BASE, 0);
3263 if (rdev->family > CHIP_RV200)
3264 WREG32(R_00015C_AGP_BASE_2, 0);
3265 }
3266 /* Wait for mc idle */
3267 if (r100_mc_wait_for_idle(rdev))
3268 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3269 /* Program MC, should be a 32bits limited address space */
3270 WREG32(R_000148_MC_FB_LOCATION,
3271 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3272 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3273 r100_mc_resume(rdev, &save);
3274}
3275
3276void r100_clock_startup(struct radeon_device *rdev)
3277{
3278 u32 tmp;
3279
3280 if (radeon_dynclks != -1 && radeon_dynclks)
3281 radeon_legacy_set_clock_gating(rdev, 1);
3282 /* We need to force on some of the block */
3283 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3284 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3285 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3286 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3287 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3288}
3289
3290static int r100_startup(struct radeon_device *rdev)
3291{
3292 int r;
3293
92cde00c
AD		 3294 /* set common regs */
3295 r100_set_common_regs(rdev);
3296 /* program mc */
d4550907
JG		 3297 r100_mc_program(rdev);
3298 /* Resume clock */
3299 r100_clock_startup(rdev);
3300 /* Initialize GPU configuration (# pipes, ...) */
3301 r100_gpu_init(rdev);
3302 /* Initialize GART (initialize after TTM so we can allocate
3303 * memory through TTM but finalize after TTM) */
17e15b0c 3304 r100_enable_bm(rdev);
d4550907
JG		 3305 if (rdev->flags & RADEON_IS_PCI) {
3306 r = r100_pci_gart_enable(rdev);
3307 if (r)
3308 return r;
3309 }
3310 /* Enable IRQ */
d4550907
JG		 3311 r100_irq_set(rdev);
3312 /* 1M ring buffer */
3313 r = r100_cp_init(rdev, 1024 * 1024);
3314 if (r) {
3315 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3316 return r;
3317 }
3318 r = r100_wb_init(rdev);
3319 if (r)
3320 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3321 r = r100_ib_init(rdev);
3322 if (r) {
3323 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3324 return r;
3325 }
3326 return 0;
3327}
3328
3329int r100_resume(struct radeon_device *rdev)
3330{
3331 /* Make sur GART are not working */
3332 if (rdev->flags & RADEON_IS_PCI)
3333 r100_pci_gart_disable(rdev);
3334 /* Resume clock before doing reset */
3335 r100_clock_startup(rdev);
3336 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3337 if (radeon_gpu_reset(rdev)) {
3338 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3339 RREG32(R_000E40_RBBM_STATUS),
3340 RREG32(R_0007C0_CP_STAT));
3341 }
3342 /* post */
3343 radeon_combios_asic_init(rdev->ddev);
3344 /* Resume clock after posting */
3345 r100_clock_startup(rdev);
550e2d92
DA		 3346 /* Initialize surface registers */
3347 radeon_surface_init(rdev);
d4550907
JG		 3348 return r100_startup(rdev);
3349}
3350
3351int r100_suspend(struct radeon_device *rdev)
3352{
3353 r100_cp_disable(rdev);
3354 r100_wb_disable(rdev);
3355 r100_irq_disable(rdev);
3356 if (rdev->flags & RADEON_IS_PCI)
3357 r100_pci_gart_disable(rdev);
3358 return 0;
3359}
3360
3361void r100_fini(struct radeon_device *rdev)
3362{
3363 r100_suspend(rdev);
3364 r100_cp_fini(rdev);
3365 r100_wb_fini(rdev);
3366 r100_ib_fini(rdev);
3367 radeon_gem_fini(rdev);
3368 if (rdev->flags & RADEON_IS_PCI)
3369 r100_pci_gart_fini(rdev);
3370 radeon_irq_kms_fini(rdev);
3371 radeon_fence_driver_fini(rdev);
4c788679 3372 radeon_bo_fini(rdev);
d4550907
JG		 3373 radeon_atombios_fini(rdev);
3374 kfree(rdev->bios);
3375 rdev->bios = NULL;
3376}
3377
3378int r100_mc_init(struct radeon_device *rdev)
3379{
3380 int r;
3381 u32 tmp;
3382
3383 /* Setup GPU memory space */
3384 rdev->mc.vram_location = 0xFFFFFFFFUL;
3385 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3386 if (rdev->flags & RADEON_IS_IGP) {
3387 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3388 rdev->mc.vram_location = tmp << 16;
3389 }
3390 if (rdev->flags & RADEON_IS_AGP) {
3391 r = radeon_agp_init(rdev);
3392 if (r) {
3393 printk(KERN_WARNING "[drm] Disabling AGP\n");
3394 rdev->flags &= ~RADEON_IS_AGP;
3395 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3396 } else {
3397 rdev->mc.gtt_location = rdev->mc.agp_base;
3398 }
3399 }
3400 r = radeon_mc_setup(rdev);
3401 if (r)
3402 return r;
3403 return 0;
3404}
3405
3406int r100_init(struct radeon_device *rdev)
3407{
3408 int r;
3409
d4550907
JG		 3410 /* Register debugfs file specific to this group of asics */
3411 r100_debugfs(rdev);
3412 /* Disable VGA */
3413 r100_vga_render_disable(rdev);
3414 /* Initialize scratch registers */
3415 radeon_scratch_init(rdev);
3416 /* Initialize surface registers */
3417 radeon_surface_init(rdev);
3418 /* TODO: disable VGA need to use VGA request */
3419 /* BIOS*/
3420 if (!radeon_get_bios(rdev)) {
3421 if (ASIC_IS_AVIVO(rdev))
3422 return -EINVAL;
3423 }
3424 if (rdev->is_atom_bios) {
3425 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3426 return -EINVAL;
3427 } else {
3428 r = radeon_combios_init(rdev);
3429 if (r)
3430 return r;
3431 }
3432 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3433 if (radeon_gpu_reset(rdev)) {
3434 dev_warn(rdev->dev,
3435 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3436 RREG32(R_000E40_RBBM_STATUS),
3437 RREG32(R_0007C0_CP_STAT));
3438 }
3439 /* check if cards are posted or not */
72542d77
DA		 3440 if (radeon_boot_test_post_card(rdev) == false)
3441 return -EINVAL;
d4550907
JG		 3442 /* Set asic errata */
3443 r100_errata(rdev);
3444 /* Initialize clocks */
3445 radeon_get_clock_info(rdev->ddev);
6234077d
RM		 3446 /* Initialize power management */
3447 radeon_pm_init(rdev);
d4550907
JG		 3448 /* Get vram informations */
3449 r100_vram_info(rdev);
3450 /* Initialize memory controller (also test AGP) */
3451 r = r100_mc_init(rdev);
3452 if (r)
3453 return r;
3454 /* Fence driver */
3455 r = radeon_fence_driver_init(rdev);
3456 if (r)
3457 return r;
3458 r = radeon_irq_kms_init(rdev);
3459 if (r)
3460 return r;
3461 /* Memory manager */
4c788679 3462 r = radeon_bo_init(rdev);
d4550907
JG		 3463 if (r)
3464 return r;
3465 if (rdev->flags & RADEON_IS_PCI) {
3466 r = r100_pci_gart_init(rdev);
3467 if (r)
3468 return r;
3469 }
3470 r100_set_safe_registers(rdev);
3471 rdev->accel_working = true;
3472 r = r100_startup(rdev);
3473 if (r) {
3474 /* Somethings want wront with the accel init stop accel */
3475 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3476 r100_suspend(rdev);
3477 r100_cp_fini(rdev);
3478 r100_wb_fini(rdev);
3479 r100_ib_fini(rdev);
3480 if (rdev->flags & RADEON_IS_PCI)
3481 r100_pci_gart_fini(rdev);
3482 radeon_irq_kms_fini(rdev);
3483 rdev->accel_working = false;
3484 }
3485 return 0;
3486}
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