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drm/radeon/kms: use udelay for short delays
[net-next-2.6.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
3ce0a23d 34#include "r100d.h"
d4550907
JG		 35#include "rs100d.h"
36#include "rv200d.h"
37#include "rv250d.h"
3ce0a23d 38
70967ab9
BH		 39#include <linux/firmware.h>
40#include <linux/platform_device.h>
41
551ebd83
DA		 42#include "r100_reg_safe.h"
43#include "rn50_reg_safe.h"
44
70967ab9
BH		 45/* Firmware Names */
46#define FIRMWARE_R100 "radeon/R100_cp.bin"
47#define FIRMWARE_R200 "radeon/R200_cp.bin"
48#define FIRMWARE_R300 "radeon/R300_cp.bin"
49#define FIRMWARE_R420 "radeon/R420_cp.bin"
50#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
51#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
52#define FIRMWARE_R520 "radeon/R520_cp.bin"
53
54MODULE_FIRMWARE(FIRMWARE_R100);
55MODULE_FIRMWARE(FIRMWARE_R200);
56MODULE_FIRMWARE(FIRMWARE_R300);
57MODULE_FIRMWARE(FIRMWARE_R420);
58MODULE_FIRMWARE(FIRMWARE_RS690);
59MODULE_FIRMWARE(FIRMWARE_RS600);
60MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 61
551ebd83
DA		 62#include "r100_track.h"
63
771fe6b9
JG		 64/* This files gather functions specifics to:
65 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 66 */
771fe6b9 67
05a05c50
AD		 68/* hpd for digital panel detect/disconnect */
69bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
70{
71 bool connected = false;
72
73 switch (hpd) {
74 case RADEON_HPD_1:
75 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
76 connected = true;
77 break;
78 case RADEON_HPD_2:
79 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
80 connected = true;
81 break;
82 default:
83 break;
84 }
85 return connected;
86}
87
88void r100_hpd_set_polarity(struct radeon_device *rdev,
89 enum radeon_hpd_id hpd)
90{
91 u32 tmp;
92 bool connected = r100_hpd_sense(rdev, hpd);
93
94 switch (hpd) {
95 case RADEON_HPD_1:
96 tmp = RREG32(RADEON_FP_GEN_CNTL);
97 if (connected)
98 tmp &= ~RADEON_FP_DETECT_INT_POL;
99 else
100 tmp |= RADEON_FP_DETECT_INT_POL;
101 WREG32(RADEON_FP_GEN_CNTL, tmp);
102 break;
103 case RADEON_HPD_2:
104 tmp = RREG32(RADEON_FP2_GEN_CNTL);
105 if (connected)
106 tmp &= ~RADEON_FP2_DETECT_INT_POL;
107 else
108 tmp |= RADEON_FP2_DETECT_INT_POL;
109 WREG32(RADEON_FP2_GEN_CNTL, tmp);
110 break;
111 default:
112 break;
113 }
114}
115
116void r100_hpd_init(struct radeon_device *rdev)
117{
118 struct drm_device *dev = rdev->ddev;
119 struct drm_connector *connector;
120
121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
122 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
123 switch (radeon_connector->hpd.hpd) {
124 case RADEON_HPD_1:
125 rdev->irq.hpd[0] = true;
126 break;
127 case RADEON_HPD_2:
128 rdev->irq.hpd[1] = true;
129 break;
130 default:
131 break;
132 }
133 }
003e69f9
JG		 134 if (rdev->irq.installed)
135 r100_irq_set(rdev);
05a05c50
AD		 136}
137
138void r100_hpd_fini(struct radeon_device *rdev)
139{
140 struct drm_device *dev = rdev->ddev;
141 struct drm_connector *connector;
142
143 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
144 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
145 switch (radeon_connector->hpd.hpd) {
146 case RADEON_HPD_1:
147 rdev->irq.hpd[0] = false;
148 break;
149 case RADEON_HPD_2:
150 rdev->irq.hpd[1] = false;
151 break;
152 default:
153 break;
154 }
155 }
156}
157
771fe6b9
JG		 158/*
159 * PCI GART
160 */
161void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
162{
163 /* TODO: can we do somethings here ? */
164 /* It seems hw only cache one entry so we should discard this
165 * entry otherwise if first GPU GART read hit this entry it
166 * could end up in wrong address. */
167}
168
4aac0473 169int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 170{
771fe6b9
JG		 171 int r;
172
4aac0473
JG		 173 if (rdev->gart.table.ram.ptr) {
174 WARN(1, "R100 PCI GART already initialized.\n");
175 return 0;
176 }
771fe6b9
JG		 177 /* Initialize common gart structure */
178 r = radeon_gart_init(rdev);
4aac0473 179 if (r)
771fe6b9 180 return r;
4aac0473
JG		 181 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
182 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
183 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
184 return radeon_gart_table_ram_alloc(rdev);
185}
186
17e15b0c
DA		 187/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
188void r100_enable_bm(struct radeon_device *rdev)
189{
190 uint32_t tmp;
191 /* Enable bus mastering */
192 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
193 WREG32(RADEON_BUS_CNTL, tmp);
194}
195
4aac0473
JG		 196int r100_pci_gart_enable(struct radeon_device *rdev)
197{
198 uint32_t tmp;
199
771fe6b9
JG		 200 /* discard memory request outside of configured range */
201 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
202 WREG32(RADEON_AIC_CNTL, tmp);
203 /* set address range for PCI address translate */
204 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
205 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
206 WREG32(RADEON_AIC_HI_ADDR, tmp);
771fe6b9
JG		 207 /* set PCI GART page-table base address */
208 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
209 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
210 WREG32(RADEON_AIC_CNTL, tmp);
211 r100_pci_gart_tlb_flush(rdev);
212 rdev->gart.ready = true;
213 return 0;
214}
215
216void r100_pci_gart_disable(struct radeon_device *rdev)
217{
218 uint32_t tmp;
219
220 /* discard memory request outside of configured range */
221 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
222 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
223 WREG32(RADEON_AIC_LO_ADDR, 0);
224 WREG32(RADEON_AIC_HI_ADDR, 0);
225}
226
227int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
228{
229 if (i < 0 || i > rdev->gart.num_gpu_pages) {
230 return -EINVAL;
231 }
ed10f95d 232 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 233 return 0;
234}
235
4aac0473 236void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 237{
4aac0473
JG		 238 r100_pci_gart_disable(rdev);
239 radeon_gart_table_ram_free(rdev);
240 radeon_gart_fini(rdev);
771fe6b9
JG		 241}
242
7ed220d7
MD		 243int r100_irq_set(struct radeon_device *rdev)
244{
245 uint32_t tmp = 0;
246
003e69f9
JG		 247 if (!rdev->irq.installed) {
248 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
249 WREG32(R_000040_GEN_INT_CNTL, 0);
250 return -EINVAL;
251 }
7ed220d7
MD		 252 if (rdev->irq.sw_int) {
253 tmp |= RADEON_SW_INT_ENABLE;
254 }
255 if (rdev->irq.crtc_vblank_int[0]) {
256 tmp |= RADEON_CRTC_VBLANK_MASK;
257 }
258 if (rdev->irq.crtc_vblank_int[1]) {
259 tmp |= RADEON_CRTC2_VBLANK_MASK;
260 }
05a05c50
AD		 261 if (rdev->irq.hpd[0]) {
262 tmp |= RADEON_FP_DETECT_MASK;
263 }
264 if (rdev->irq.hpd[1]) {
265 tmp |= RADEON_FP2_DETECT_MASK;
266 }
7ed220d7
MD		 267 WREG32(RADEON_GEN_INT_CNTL, tmp);
268 return 0;
269}
270
9f022ddf
JG		 271void r100_irq_disable(struct radeon_device *rdev)
272{
273 u32 tmp;
274
275 WREG32(R_000040_GEN_INT_CNTL, 0);
276 /* Wait and acknowledge irq */
277 mdelay(1);
278 tmp = RREG32(R_000044_GEN_INT_STATUS);
279 WREG32(R_000044_GEN_INT_STATUS, tmp);
280}
281
7ed220d7
MD		 282static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
283{
284 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 285 uint32_t irq_mask = RADEON_SW_INT_TEST |
286 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
287 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 288
289 if (irqs) {
290 WREG32(RADEON_GEN_INT_STATUS, irqs);
291 }
292 return irqs & irq_mask;
293}
294
295int r100_irq_process(struct radeon_device *rdev)
296{
3e5cb98d 297 uint32_t status, msi_rearm;
d4877cf2 298 bool queue_hotplug = false;
7ed220d7
MD		 299
300 status = r100_irq_ack(rdev);
301 if (!status) {
302 return IRQ_NONE;
303 }
a513c184
JG		 304 if (rdev->shutdown) {
305 return IRQ_NONE;
306 }
7ed220d7
MD		 307 while (status) {
308 /* SW interrupt */
309 if (status & RADEON_SW_INT_TEST) {
310 radeon_fence_process(rdev);
311 }
312 /* Vertical blank interrupts */
313 if (status & RADEON_CRTC_VBLANK_STAT) {
314 drm_handle_vblank(rdev->ddev, 0);
c913e23a
RM		 315 if (rdev->pm.vblank_callback)
316 queue_work(rdev->wq, &rdev->pm.reclock_work);
7ed220d7
MD		 317 }
318 if (status & RADEON_CRTC2_VBLANK_STAT) {
319 drm_handle_vblank(rdev->ddev, 1);
c913e23a
RM		 320 if (rdev->pm.vblank_callback)
321 queue_work(rdev->wq, &rdev->pm.reclock_work);
7ed220d7 322 }
05a05c50 323 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 324 queue_hotplug = true;
325 DRM_DEBUG("HPD1\n");
05a05c50
AD		 326 }
327 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 328 queue_hotplug = true;
329 DRM_DEBUG("HPD2\n");
05a05c50 330 }
7ed220d7
MD		 331 status = r100_irq_ack(rdev);
332 }
d4877cf2
AD		 333 if (queue_hotplug)
334 queue_work(rdev->wq, &rdev->hotplug_work);
3e5cb98d
AD		 335 if (rdev->msi_enabled) {
336 switch (rdev->family) {
337 case CHIP_RS400:
338 case CHIP_RS480:
339 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
340 WREG32(RADEON_AIC_CNTL, msi_rearm);
341 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
342 break;
343 default:
344 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
345 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
346 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
347 break;
348 }
349 }
7ed220d7
MD		 350 return IRQ_HANDLED;
351}
352
353u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
354{
355 if (crtc == 0)
356 return RREG32(RADEON_CRTC_CRNT_FRAME);
357 else
358 return RREG32(RADEON_CRTC2_CRNT_FRAME);
359}
360
9e5b2af7
PN		 361/* Who ever call radeon_fence_emit should call ring_lock and ask
362 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 363void r100_fence_ring_emit(struct radeon_device *rdev,
364 struct radeon_fence *fence)
365{
9e5b2af7
PN		 366 /* We have to make sure that caches are flushed before
367 * CPU might read something from VRAM. */
368 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
369 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
370 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
371 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 372 /* Wait until IDLE & CLEAN */
4612dc97
AD		 373 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
374 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
cafe6609
JG		 375 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
376 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
377 RADEON_HDP_READ_BUFFER_INVALIDATE);
378 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
379 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 380 /* Emit fence sequence & fire IRQ */
381 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
382 radeon_ring_write(rdev, fence->seq);
383 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
384 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
385}
386
771fe6b9
JG		 387int r100_wb_init(struct radeon_device *rdev)
388{
389 int r;
390
391 if (rdev->wb.wb_obj == NULL) {
4c788679
JG		 392 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
393 RADEON_GEM_DOMAIN_GTT,
394 &rdev->wb.wb_obj);
771fe6b9 395 if (r) {
4c788679 396 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
771fe6b9
JG		 397 return r;
398 }
4c788679
JG		 399 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
400 if (unlikely(r != 0))
401 return r;
402 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
403 &rdev->wb.gpu_addr);
771fe6b9 404 if (r) {
4c788679
JG		 405 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
406 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9
JG		 407 return r;
408 }
4c788679
JG		 409 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
410 radeon_bo_unreserve(rdev->wb.wb_obj);
771fe6b9 411 if (r) {
4c788679 412 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
771fe6b9
JG		 413 return r;
414 }
415 }
9f022ddf
JG		 416 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
417 WREG32(R_00070C_CP_RB_RPTR_ADDR,
418 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
419 WREG32(R_000770_SCRATCH_UMSK, 0xff);
771fe6b9
JG		 420 return 0;
421}
422
9f022ddf
JG		 423void r100_wb_disable(struct radeon_device *rdev)
424{
425 WREG32(R_000770_SCRATCH_UMSK, 0);
426}
427
771fe6b9
JG		 428void r100_wb_fini(struct radeon_device *rdev)
429{
4c788679
JG		 430 int r;
431
9f022ddf 432 r100_wb_disable(rdev);
771fe6b9 433 if (rdev->wb.wb_obj) {
4c788679
JG		 434 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
435 if (unlikely(r != 0)) {
436 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
437 return;
438 }
439 radeon_bo_kunmap(rdev->wb.wb_obj);
440 radeon_bo_unpin(rdev->wb.wb_obj);
441 radeon_bo_unreserve(rdev->wb.wb_obj);
442 radeon_bo_unref(&rdev->wb.wb_obj);
771fe6b9
JG		 443 rdev->wb.wb = NULL;
444 rdev->wb.wb_obj = NULL;
445 }
446}
447
448int r100_copy_blit(struct radeon_device *rdev,
449 uint64_t src_offset,
450 uint64_t dst_offset,
451 unsigned num_pages,
452 struct radeon_fence *fence)
453{
454 uint32_t cur_pages;
455 uint32_t stride_bytes = PAGE_SIZE;
456 uint32_t pitch;
457 uint32_t stride_pixels;
458 unsigned ndw;
459 int num_loops;
460 int r = 0;
461
462 /* radeon limited to 16k stride */
463 stride_bytes &= 0x3fff;
464 /* radeon pitch is /64 */
465 pitch = stride_bytes / 64;
466 stride_pixels = stride_bytes / 4;
467 num_loops = DIV_ROUND_UP(num_pages, 8191);
468
469 /* Ask for enough room for blit + flush + fence */
470 ndw = 64 + (10 * num_loops);
471 r = radeon_ring_lock(rdev, ndw);
472 if (r) {
473 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
474 return -EINVAL;
475 }
476 while (num_pages > 0) {
477 cur_pages = num_pages;
478 if (cur_pages > 8191) {
479 cur_pages = 8191;
480 }
481 num_pages -= cur_pages;
482
483 /* pages are in Y direction - height
484 page width in X direction - width */
485 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
486 radeon_ring_write(rdev,
487 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
488 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
489 RADEON_GMC_SRC_CLIPPING |
490 RADEON_GMC_DST_CLIPPING |
491 RADEON_GMC_BRUSH_NONE |
492 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
493 RADEON_GMC_SRC_DATATYPE_COLOR |
494 RADEON_ROP3_S |
495 RADEON_DP_SRC_SOURCE_MEMORY |
496 RADEON_GMC_CLR_CMP_CNTL_DIS |
497 RADEON_GMC_WR_MSK_DIS);
498 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
499 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
500 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
501 radeon_ring_write(rdev, 0);
502 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
503 radeon_ring_write(rdev, num_pages);
504 radeon_ring_write(rdev, num_pages);
505 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
506 }
507 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
508 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
509 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
510 radeon_ring_write(rdev,
511 RADEON_WAIT_2D_IDLECLEAN |
512 RADEON_WAIT_HOST_IDLECLEAN |
513 RADEON_WAIT_DMA_GUI_IDLE);
514 if (fence) {
515 r = radeon_fence_emit(rdev, fence);
516 }
517 radeon_ring_unlock_commit(rdev);
518 return r;
519}
520
45600232
JG		 521static int r100_cp_wait_for_idle(struct radeon_device *rdev)
522{
523 unsigned i;
524 u32 tmp;
525
526 for (i = 0; i < rdev->usec_timeout; i++) {
527 tmp = RREG32(R_000E40_RBBM_STATUS);
528 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
529 return 0;
530 }
531 udelay(1);
532 }
533 return -1;
534}
535
771fe6b9
JG		 536void r100_ring_start(struct radeon_device *rdev)
537{
538 int r;
539
540 r = radeon_ring_lock(rdev, 2);
541 if (r) {
542 return;
543 }
544 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
545 radeon_ring_write(rdev,
546 RADEON_ISYNC_ANY2D_IDLE3D |
547 RADEON_ISYNC_ANY3D_IDLE2D |
548 RADEON_ISYNC_WAIT_IDLEGUI |
549 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
550 radeon_ring_unlock_commit(rdev);
551}
552
70967ab9
BH		 553
554/* Load the microcode for the CP */
555static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 556{
70967ab9
BH		 557 struct platform_device *pdev;
558 const char *fw_name = NULL;
559 int err;
771fe6b9 560
70967ab9 561 DRM_DEBUG("\n");
771fe6b9 562
70967ab9
BH		 563 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
564 err = IS_ERR(pdev);
565 if (err) {
566 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
567 return -EINVAL;
568 }
771fe6b9
JG		 569 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
570 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
571 (rdev->family == CHIP_RS200)) {
572 DRM_INFO("Loading R100 Microcode\n");
70967ab9 573 fw_name = FIRMWARE_R100;
771fe6b9
JG		 574 } else if ((rdev->family == CHIP_R200) ||
575 (rdev->family == CHIP_RV250) ||
576 (rdev->family == CHIP_RV280) ||
577 (rdev->family == CHIP_RS300)) {
578 DRM_INFO("Loading R200 Microcode\n");
70967ab9 579 fw_name = FIRMWARE_R200;
771fe6b9
JG		 580 } else if ((rdev->family == CHIP_R300) ||
581 (rdev->family == CHIP_R350) ||
582 (rdev->family == CHIP_RV350) ||
583 (rdev->family == CHIP_RV380) ||
584 (rdev->family == CHIP_RS400) ||
585 (rdev->family == CHIP_RS480)) {
586 DRM_INFO("Loading R300 Microcode\n");
70967ab9 587 fw_name = FIRMWARE_R300;
771fe6b9
JG		 588 } else if ((rdev->family == CHIP_R420) ||
589 (rdev->family == CHIP_R423) ||
590 (rdev->family == CHIP_RV410)) {
591 DRM_INFO("Loading R400 Microcode\n");
70967ab9 592 fw_name = FIRMWARE_R420;
771fe6b9
JG		 593 } else if ((rdev->family == CHIP_RS690) ||
594 (rdev->family == CHIP_RS740)) {
595 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 596 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 597 } else if (rdev->family == CHIP_RS600) {
598 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 599 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 600 } else if ((rdev->family == CHIP_RV515) ||
601 (rdev->family == CHIP_R520) ||
602 (rdev->family == CHIP_RV530) ||
603 (rdev->family == CHIP_R580) ||
604 (rdev->family == CHIP_RV560) ||
605 (rdev->family == CHIP_RV570)) {
606 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 607 fw_name = FIRMWARE_R520;
608 }
609
3ce0a23d 610 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 611 platform_device_unregister(pdev);
612 if (err) {
613 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
614 fw_name);
3ce0a23d 615 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 616 printk(KERN_ERR
617 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 618 rdev->me_fw->size, fw_name);
70967ab9 619 err = -EINVAL;
3ce0a23d
JG		 620 release_firmware(rdev->me_fw);
621 rdev->me_fw = NULL;
70967ab9
BH		 622 }
623 return err;
624}
d4550907 625
70967ab9
BH		 626static void r100_cp_load_microcode(struct radeon_device *rdev)
627{
628 const __be32 *fw_data;
629 int i, size;
630
631 if (r100_gui_wait_for_idle(rdev)) {
632 printk(KERN_WARNING "Failed to wait GUI idle while "
633 "programming pipes. Bad things might happen.\n");
634 }
635
3ce0a23d
JG		 636 if (rdev->me_fw) {
637 size = rdev->me_fw->size / 4;
638 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 639 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
640 for (i = 0; i < size; i += 2) {
641 WREG32(RADEON_CP_ME_RAM_DATAH,
642 be32_to_cpup(&fw_data[i]));
643 WREG32(RADEON_CP_ME_RAM_DATAL,
644 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 645 }
646 }
647}
648
649int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
650{
651 unsigned rb_bufsz;
652 unsigned rb_blksz;
653 unsigned max_fetch;
654 unsigned pre_write_timer;
655 unsigned pre_write_limit;
656 unsigned indirect2_start;
657 unsigned indirect1_start;
658 uint32_t tmp;
659 int r;
660
661 if (r100_debugfs_cp_init(rdev)) {
662 DRM_ERROR("Failed to register debugfs file for CP !\n");
663 }
664 /* Reset CP */
665 tmp = RREG32(RADEON_CP_CSQ_STAT);
666 if ((tmp & (1 << 31))) {
667 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
668 WREG32(RADEON_CP_CSQ_MODE, 0);
669 WREG32(RADEON_CP_CSQ_CNTL, 0);
670 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
671 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
672 mdelay(2);
673 WREG32(RADEON_RBBM_SOFT_RESET, 0);
674 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
675 mdelay(2);
676 tmp = RREG32(RADEON_CP_CSQ_STAT);
677 if ((tmp & (1 << 31))) {
678 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
679 }
680 } else {
681 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
682 }
70967ab9 683
3ce0a23d 684 if (!rdev->me_fw) {
70967ab9
BH		 685 r = r100_cp_init_microcode(rdev);
686 if (r) {
687 DRM_ERROR("Failed to load firmware!\n");
688 return r;
689 }
690 }
691
771fe6b9
JG		 692 /* Align ring size */
693 rb_bufsz = drm_order(ring_size / 8);
694 ring_size = (1 << (rb_bufsz + 1)) * 4;
695 r100_cp_load_microcode(rdev);
696 r = radeon_ring_init(rdev, ring_size);
697 if (r) {
698 return r;
699 }
700 /* Each time the cp read 1024 bytes (16 dword/quadword) update
701 * the rptr copy in system ram */
702 rb_blksz = 9;
703 /* cp will read 128bytes at a time (4 dwords) */
704 max_fetch = 1;
705 rdev->cp.align_mask = 16 - 1;
706 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
707 pre_write_timer = 64;
708 /* Force CP_RB_WPTR write if written more than one time before the
709 * delay expire
710 */
711 pre_write_limit = 0;
712 /* Setup the cp cache like this (cache size is 96 dwords) :
713 * RING 0 to 15
714 * INDIRECT1 16 to 79
715 * INDIRECT2 80 to 95
716 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
717 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
718 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
719 * Idea being that most of the gpu cmd will be through indirect1 buffer
720 * so it gets the bigger cache.
721 */
722 indirect2_start = 80;
723 indirect1_start = 16;
724 /* cp setup */
725 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 726 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9
JG		 727 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
728 REG_SET(RADEON_MAX_FETCH, max_fetch) |
729 RADEON_RB_NO_UPDATE);
d6f28938
AD		 730#ifdef __BIG_ENDIAN
731 tmp |= RADEON_BUF_SWAP_32BIT;
732#endif
733 WREG32(RADEON_CP_RB_CNTL, tmp);
734
771fe6b9
JG		 735 /* Set ring address */
736 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
737 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
738 /* Force read & write ptr to 0 */
771fe6b9
JG		 739 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
740 WREG32(RADEON_CP_RB_RPTR_WR, 0);
741 WREG32(RADEON_CP_RB_WPTR, 0);
742 WREG32(RADEON_CP_RB_CNTL, tmp);
743 udelay(10);
744 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
745 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
746 /* Set cp mode to bus mastering & enable cp*/
747 WREG32(RADEON_CP_CSQ_MODE,
748 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
749 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
750 WREG32(0x718, 0);
751 WREG32(0x744, 0x00004D4D);
752 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
753 radeon_ring_start(rdev);
754 r = radeon_ring_test(rdev);
755 if (r) {
756 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
757 return r;
758 }
759 rdev->cp.ready = true;
760 return 0;
761}
762
763void r100_cp_fini(struct radeon_device *rdev)
764{
45600232
JG		 765 if (r100_cp_wait_for_idle(rdev)) {
766 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
767 }
771fe6b9 768 /* Disable ring */
a18d7ea1 769 r100_cp_disable(rdev);
771fe6b9
JG		 770 radeon_ring_fini(rdev);
771 DRM_INFO("radeon: cp finalized\n");
772}
773
774void r100_cp_disable(struct radeon_device *rdev)
775{
776 /* Disable ring */
777 rdev->cp.ready = false;
778 WREG32(RADEON_CP_CSQ_MODE, 0);
779 WREG32(RADEON_CP_CSQ_CNTL, 0);
780 if (r100_gui_wait_for_idle(rdev)) {
781 printk(KERN_WARNING "Failed to wait GUI idle while "
782 "programming pipes. Bad things might happen.\n");
783 }
784}
785
786int r100_cp_reset(struct radeon_device *rdev)
787{
788 uint32_t tmp;
789 bool reinit_cp;
790 int i;
791
792 reinit_cp = rdev->cp.ready;
793 rdev->cp.ready = false;
794 WREG32(RADEON_CP_CSQ_MODE, 0);
795 WREG32(RADEON_CP_CSQ_CNTL, 0);
796 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
797 (void)RREG32(RADEON_RBBM_SOFT_RESET);
798 udelay(200);
799 WREG32(RADEON_RBBM_SOFT_RESET, 0);
800 /* Wait to prevent race in RBBM_STATUS */
801 mdelay(1);
802 for (i = 0; i < rdev->usec_timeout; i++) {
803 tmp = RREG32(RADEON_RBBM_STATUS);
804 if (!(tmp & (1 << 16))) {
805 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
806 tmp);
807 if (reinit_cp) {
808 return r100_cp_init(rdev, rdev->cp.ring_size);
809 }
810 return 0;
811 }
812 DRM_UDELAY(1);
813 }
814 tmp = RREG32(RADEON_RBBM_STATUS);
815 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
816 return -1;
817}
818
3ce0a23d
JG		 819void r100_cp_commit(struct radeon_device *rdev)
820{
821 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
822 (void)RREG32(RADEON_CP_RB_WPTR);
823}
824
771fe6b9
JG		 825
826/*
827 * CS functions
828 */
829int r100_cs_parse_packet0(struct radeon_cs_parser *p,
830 struct radeon_cs_packet *pkt,
068a117c 831 const unsigned *auth, unsigned n,
771fe6b9
JG		 832 radeon_packet0_check_t check)
833{
834 unsigned reg;
835 unsigned i, j, m;
836 unsigned idx;
837 int r;
838
839 idx = pkt->idx + 1;
840 reg = pkt->reg;
068a117c
JG		 841 /* Check that register fall into register range
842 * determined by the number of entry (n) in the
843 * safe register bitmap.
844 */
771fe6b9
JG		 845 if (pkt->one_reg_wr) {
846 if ((reg >> 7) > n) {
847 return -EINVAL;
848 }
849 } else {
850 if (((reg + (pkt->count << 2)) >> 7) > n) {
851 return -EINVAL;
852 }
853 }
854 for (i = 0; i <= pkt->count; i++, idx++) {
855 j = (reg >> 7);
856 m = 1 << ((reg >> 2) & 31);
857 if (auth[j] & m) {
858 r = check(p, pkt, idx, reg);
859 if (r) {
860 return r;
861 }
862 }
863 if (pkt->one_reg_wr) {
864 if (!(auth[j] & m)) {
865 break;
866 }
867 } else {
868 reg += 4;
869 }
870 }
871 return 0;
872}
873
771fe6b9
JG		 874void r100_cs_dump_packet(struct radeon_cs_parser *p,
875 struct radeon_cs_packet *pkt)
876{
771fe6b9
JG		 877 volatile uint32_t *ib;
878 unsigned i;
879 unsigned idx;
880
881 ib = p->ib->ptr;
771fe6b9
JG		 882 idx = pkt->idx;
883 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
884 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
885 }
886}
887
888/**
889 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
890 * @parser: parser structure holding parsing context.
891 * @pkt: where to store packet informations
892 *
893 * Assume that chunk_ib_index is properly set. Will return -EINVAL
894 * if packet is bigger than remaining ib size. or if packets is unknown.
895 **/
896int r100_cs_packet_parse(struct radeon_cs_parser *p,
897 struct radeon_cs_packet *pkt,
898 unsigned idx)
899{
900 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 901 uint32_t header;
771fe6b9
JG		 902
903 if (idx >= ib_chunk->length_dw) {
904 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
905 idx, ib_chunk->length_dw);
906 return -EINVAL;
907 }
513bcb46 908 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 909 pkt->idx = idx;
910 pkt->type = CP_PACKET_GET_TYPE(header);
911 pkt->count = CP_PACKET_GET_COUNT(header);
912 switch (pkt->type) {
913 case PACKET_TYPE0:
914 pkt->reg = CP_PACKET0_GET_REG(header);
915 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
916 break;
917 case PACKET_TYPE3:
918 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
919 break;
920 case PACKET_TYPE2:
921 pkt->count = -1;
922 break;
923 default:
924 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
925 return -EINVAL;
926 }
927 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
928 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
929 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
930 return -EINVAL;
931 }
932 return 0;
933}
934
531369e6
DA		 935/**
936 * r100_cs_packet_next_vline() - parse userspace VLINE packet
937 * @parser: parser structure holding parsing context.
938 *
939 * Userspace sends a special sequence for VLINE waits.
940 * PACKET0 - VLINE_START_END + value
941 * PACKET0 - WAIT_UNTIL +_value
942 * RELOC (P3) - crtc_id in reloc.
943 *
944 * This function parses this and relocates the VLINE START END
945 * and WAIT UNTIL packets to the correct crtc.
946 * It also detects a switched off crtc and nulls out the
947 * wait in that case.
948 */
949int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
950{
531369e6
DA		 951 struct drm_mode_object *obj;
952 struct drm_crtc *crtc;
953 struct radeon_crtc *radeon_crtc;
954 struct radeon_cs_packet p3reloc, waitreloc;
955 int crtc_id;
956 int r;
957 uint32_t header, h_idx, reg;
513bcb46 958 volatile uint32_t *ib;
531369e6 959
513bcb46 960 ib = p->ib->ptr;
531369e6
DA		 961
962 /* parse the wait until */
963 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
964 if (r)
965 return r;
966
967 /* check its a wait until and only 1 count */
968 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
969 waitreloc.count != 0) {
970 DRM_ERROR("vline wait had illegal wait until segment\n");
971 r = -EINVAL;
972 return r;
973 }
974
513bcb46 975 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 976 DRM_ERROR("vline wait had illegal wait until\n");
977 r = -EINVAL;
978 return r;
979 }
980
981 /* jump over the NOP */
90ebd065 982 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 983 if (r)
984 return r;
985
986 h_idx = p->idx - 2;
90ebd065
AD		 987 p->idx += waitreloc.count + 2;
988 p->idx += p3reloc.count + 2;
531369e6 989
513bcb46
DA		 990 header = radeon_get_ib_value(p, h_idx);
991 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 992 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 993 mutex_lock(&p->rdev->ddev->mode_config.mutex);
994 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
995 if (!obj) {
996 DRM_ERROR("cannot find crtc %d\n", crtc_id);
997 r = -EINVAL;
998 goto out;
999 }
1000 crtc = obj_to_crtc(obj);
1001 radeon_crtc = to_radeon_crtc(crtc);
1002 crtc_id = radeon_crtc->crtc_id;
1003
1004 if (!crtc->enabled) {
1005 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1006 ib[h_idx + 2] = PACKET2(0);
1007 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1008 } else if (crtc_id == 1) {
1009 switch (reg) {
1010 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1011 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1012 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1013 break;
1014 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1015 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1016 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1017 break;
1018 default:
1019 DRM_ERROR("unknown crtc reloc\n");
1020 r = -EINVAL;
1021 goto out;
1022 }
513bcb46
DA		 1023 ib[h_idx] = header;
1024 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1025 }
1026out:
1027 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1028 return r;
1029}
1030
771fe6b9
JG		 1031/**
1032 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1033 * @parser: parser structure holding parsing context.
1034 * @data: pointer to relocation data
1035 * @offset_start: starting offset
1036 * @offset_mask: offset mask (to align start offset on)
1037 * @reloc: reloc informations
1038 *
1039 * Check next packet is relocation packet3, do bo validation and compute
1040 * GPU offset using the provided start.
1041 **/
1042int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1043 struct radeon_cs_reloc **cs_reloc)
1044{
771fe6b9
JG		 1045 struct radeon_cs_chunk *relocs_chunk;
1046 struct radeon_cs_packet p3reloc;
1047 unsigned idx;
1048 int r;
1049
1050 if (p->chunk_relocs_idx == -1) {
1051 DRM_ERROR("No relocation chunk !\n");
1052 return -EINVAL;
1053 }
1054 *cs_reloc = NULL;
771fe6b9
JG		 1055 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1056 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1057 if (r) {
1058 return r;
1059 }
1060 p->idx += p3reloc.count + 2;
1061 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1062 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1063 p3reloc.idx);
1064 r100_cs_dump_packet(p, &p3reloc);
1065 return -EINVAL;
1066 }
513bcb46 1067 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1068 if (idx >= relocs_chunk->length_dw) {
1069 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1070 idx, relocs_chunk->length_dw);
1071 r100_cs_dump_packet(p, &p3reloc);
1072 return -EINVAL;
1073 }
1074 /* FIXME: we assume reloc size is 4 dwords */
1075 *cs_reloc = p->relocs_ptr[(idx / 4)];
1076 return 0;
1077}
1078
551ebd83
DA		 1079static int r100_get_vtx_size(uint32_t vtx_fmt)
1080{
1081 int vtx_size;
1082 vtx_size = 2;
1083 /* ordered according to bits in spec */
1084 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1085 vtx_size++;
1086 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1087 vtx_size += 3;
1088 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1089 vtx_size++;
1090 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1091 vtx_size++;
1092 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1093 vtx_size += 3;
1094 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1095 vtx_size++;
1096 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1097 vtx_size++;
1098 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1099 vtx_size += 2;
1100 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1101 vtx_size += 2;
1102 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1103 vtx_size++;
1104 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1105 vtx_size += 2;
1106 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1107 vtx_size++;
1108 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1109 vtx_size += 2;
1110 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1111 vtx_size++;
1112 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1113 vtx_size++;
1114 /* blend weight */
1115 if (vtx_fmt & (0x7 << 15))
1116 vtx_size += (vtx_fmt >> 15) & 0x7;
1117 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1118 vtx_size += 3;
1119 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1120 vtx_size += 2;
1121 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1122 vtx_size++;
1123 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1124 vtx_size++;
1125 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1126 vtx_size++;
1127 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1128 vtx_size++;
1129 return vtx_size;
1130}
1131
771fe6b9 1132static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1133 struct radeon_cs_packet *pkt,
1134 unsigned idx, unsigned reg)
771fe6b9 1135{
771fe6b9 1136 struct radeon_cs_reloc *reloc;
551ebd83 1137 struct r100_cs_track *track;
771fe6b9
JG		 1138 volatile uint32_t *ib;
1139 uint32_t tmp;
771fe6b9 1140 int r;
551ebd83 1141 int i, face;
e024e110 1142 u32 tile_flags = 0;
513bcb46 1143 u32 idx_value;
771fe6b9
JG		 1144
1145 ib = p->ib->ptr;
551ebd83
DA		 1146 track = (struct r100_cs_track *)p->track;
1147
513bcb46
DA		 1148 idx_value = radeon_get_ib_value(p, idx);
1149
551ebd83
DA		 1150 switch (reg) {
1151 case RADEON_CRTC_GUI_TRIG_VLINE:
1152 r = r100_cs_packet_parse_vline(p);
1153 if (r) {
1154 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1155 idx, reg);
1156 r100_cs_dump_packet(p, pkt);
1157 return r;
1158 }
1159 break;
771fe6b9
JG		 1160 /* FIXME: only allow PACKET3 blit? easier to check for out of
1161 * range access */
551ebd83
DA		 1162 case RADEON_DST_PITCH_OFFSET:
1163 case RADEON_SRC_PITCH_OFFSET:
1164 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1165 if (r)
1166 return r;
1167 break;
1168 case RADEON_RB3D_DEPTHOFFSET:
1169 r = r100_cs_packet_next_reloc(p, &reloc);
1170 if (r) {
1171 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1172 idx, reg);
1173 r100_cs_dump_packet(p, pkt);
1174 return r;
1175 }
1176 track->zb.robj = reloc->robj;
513bcb46
DA		 1177 track->zb.offset = idx_value;
1178 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1179 break;
1180 case RADEON_RB3D_COLOROFFSET:
1181 r = r100_cs_packet_next_reloc(p, &reloc);
1182 if (r) {
1183 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1184 idx, reg);
1185 r100_cs_dump_packet(p, pkt);
1186 return r;
1187 }
1188 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1189 track->cb[0].offset = idx_value;
1190 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1191 break;
1192 case RADEON_PP_TXOFFSET_0:
1193 case RADEON_PP_TXOFFSET_1:
1194 case RADEON_PP_TXOFFSET_2:
1195 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1196 r = r100_cs_packet_next_reloc(p, &reloc);
1197 if (r) {
1198 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1199 idx, reg);
1200 r100_cs_dump_packet(p, pkt);
1201 return r;
1202 }
513bcb46 1203 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1204 track->textures[i].robj = reloc->robj;
1205 break;
1206 case RADEON_PP_CUBIC_OFFSET_T0_0:
1207 case RADEON_PP_CUBIC_OFFSET_T0_1:
1208 case RADEON_PP_CUBIC_OFFSET_T0_2:
1209 case RADEON_PP_CUBIC_OFFSET_T0_3:
1210 case RADEON_PP_CUBIC_OFFSET_T0_4:
1211 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1212 r = r100_cs_packet_next_reloc(p, &reloc);
1213 if (r) {
1214 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1215 idx, reg);
1216 r100_cs_dump_packet(p, pkt);
1217 return r;
1218 }
513bcb46
DA		 1219 track->textures[0].cube_info[i].offset = idx_value;
1220 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1221 track->textures[0].cube_info[i].robj = reloc->robj;
1222 break;
1223 case RADEON_PP_CUBIC_OFFSET_T1_0:
1224 case RADEON_PP_CUBIC_OFFSET_T1_1:
1225 case RADEON_PP_CUBIC_OFFSET_T1_2:
1226 case RADEON_PP_CUBIC_OFFSET_T1_3:
1227 case RADEON_PP_CUBIC_OFFSET_T1_4:
1228 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1229 r = r100_cs_packet_next_reloc(p, &reloc);
1230 if (r) {
1231 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1232 idx, reg);
1233 r100_cs_dump_packet(p, pkt);
1234 return r;
1235 }
513bcb46
DA		 1236 track->textures[1].cube_info[i].offset = idx_value;
1237 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1238 track->textures[1].cube_info[i].robj = reloc->robj;
1239 break;
1240 case RADEON_PP_CUBIC_OFFSET_T2_0:
1241 case RADEON_PP_CUBIC_OFFSET_T2_1:
1242 case RADEON_PP_CUBIC_OFFSET_T2_2:
1243 case RADEON_PP_CUBIC_OFFSET_T2_3:
1244 case RADEON_PP_CUBIC_OFFSET_T2_4:
1245 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1246 r = r100_cs_packet_next_reloc(p, &reloc);
1247 if (r) {
1248 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1249 idx, reg);
1250 r100_cs_dump_packet(p, pkt);
1251 return r;
1252 }
513bcb46
DA		 1253 track->textures[2].cube_info[i].offset = idx_value;
1254 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1255 track->textures[2].cube_info[i].robj = reloc->robj;
1256 break;
1257 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1258 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1259 break;
1260 case RADEON_RB3D_COLORPITCH:
1261 r = r100_cs_packet_next_reloc(p, &reloc);
1262 if (r) {
1263 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1264 idx, reg);
1265 r100_cs_dump_packet(p, pkt);
1266 return r;
1267 }
e024e110 1268
551ebd83
DA		 1269 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1270 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1271 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1272 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1273
513bcb46 1274 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1275 tmp |= tile_flags;
1276 ib[idx] = tmp;
e024e110 1277
513bcb46 1278 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1279 break;
1280 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1281 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1282 break;
1283 case RADEON_RB3D_CNTL:
513bcb46 1284 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1285 case 7:
1286 case 8:
1287 case 9:
1288 case 11:
1289 case 12:
1290 track->cb[0].cpp = 1;
e024e110 1291 break;
551ebd83
DA		 1292 case 3:
1293 case 4:
1294 case 15:
1295 track->cb[0].cpp = 2;
1296 break;
1297 case 6:
1298 track->cb[0].cpp = 4;
1299 break;
1300 default:
1301 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1302 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1303 return -EINVAL;
1304 }
513bcb46 1305 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1306 break;
1307 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1308 switch (idx_value & 0xf) {
551ebd83
DA		 1309 case 0:
1310 track->zb.cpp = 2;
1311 break;
1312 case 2:
1313 case 3:
1314 case 4:
1315 case 5:
1316 case 9:
1317 case 11:
1318 track->zb.cpp = 4;
17782d99 1319 break;
771fe6b9 1320 default:
771fe6b9
JG		 1321 break;
1322 }
551ebd83
DA		 1323 break;
1324 case RADEON_RB3D_ZPASS_ADDR:
1325 r = r100_cs_packet_next_reloc(p, &reloc);
1326 if (r) {
1327 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1328 idx, reg);
1329 r100_cs_dump_packet(p, pkt);
1330 return r;
1331 }
513bcb46 1332 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1333 break;
1334 case RADEON_PP_CNTL:
1335 {
513bcb46 1336 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1337 for (i = 0; i < track->num_texture; i++)
1338 track->textures[i].enabled = !!(temp & (1 << i));
1339 }
1340 break;
1341 case RADEON_SE_VF_CNTL:
513bcb46 1342 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1343 break;
1344 case RADEON_SE_VTX_FMT:
513bcb46 1345 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1346 break;
1347 case RADEON_PP_TEX_SIZE_0:
1348 case RADEON_PP_TEX_SIZE_1:
1349 case RADEON_PP_TEX_SIZE_2:
1350 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1351 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1352 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1353 break;
1354 case RADEON_PP_TEX_PITCH_0:
1355 case RADEON_PP_TEX_PITCH_1:
1356 case RADEON_PP_TEX_PITCH_2:
1357 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1358 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1359 break;
1360 case RADEON_PP_TXFILTER_0:
1361 case RADEON_PP_TXFILTER_1:
1362 case RADEON_PP_TXFILTER_2:
1363 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1364 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1365 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1366 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1367 if (tmp == 2 || tmp == 6)
1368 track->textures[i].roundup_w = false;
513bcb46 1369 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1370 if (tmp == 2 || tmp == 6)
1371 track->textures[i].roundup_h = false;
1372 break;
1373 case RADEON_PP_TXFORMAT_0:
1374 case RADEON_PP_TXFORMAT_1:
1375 case RADEON_PP_TXFORMAT_2:
1376 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1377 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1378 track->textures[i].use_pitch = 1;
1379 } else {
1380 track->textures[i].use_pitch = 0;
513bcb46
DA		 1381 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1382 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1383 }
513bcb46 1384 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1385 track->textures[i].tex_coord_type = 2;
513bcb46 1386 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1387 case RADEON_TXFORMAT_I8:
1388 case RADEON_TXFORMAT_RGB332:
1389 case RADEON_TXFORMAT_Y8:
1390 track->textures[i].cpp = 1;
1391 break;
1392 case RADEON_TXFORMAT_AI88:
1393 case RADEON_TXFORMAT_ARGB1555:
1394 case RADEON_TXFORMAT_RGB565:
1395 case RADEON_TXFORMAT_ARGB4444:
1396 case RADEON_TXFORMAT_VYUY422:
1397 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1398 case RADEON_TXFORMAT_SHADOW16:
1399 case RADEON_TXFORMAT_LDUDV655:
1400 case RADEON_TXFORMAT_DUDV88:
1401 track->textures[i].cpp = 2;
771fe6b9 1402 break;
551ebd83
DA		 1403 case RADEON_TXFORMAT_ARGB8888:
1404 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1405 case RADEON_TXFORMAT_SHADOW32:
1406 case RADEON_TXFORMAT_LDUDUV8888:
1407 track->textures[i].cpp = 4;
1408 break;
d785d78b
DA		 1409 case RADEON_TXFORMAT_DXT1:
1410 track->textures[i].cpp = 1;
1411 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1412 break;
1413 case RADEON_TXFORMAT_DXT23:
1414 case RADEON_TXFORMAT_DXT45:
1415 track->textures[i].cpp = 1;
1416 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1417 break;
551ebd83 1418 }
513bcb46
DA		 1419 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1420 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1421 break;
1422 case RADEON_PP_CUBIC_FACES_0:
1423 case RADEON_PP_CUBIC_FACES_1:
1424 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1425 tmp = idx_value;
551ebd83
DA		 1426 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1427 for (face = 0; face < 4; face++) {
1428 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1429 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1430 }
551ebd83
DA		 1431 break;
1432 default:
1433 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1434 reg, idx);
1435 return -EINVAL;
771fe6b9
JG		 1436 }
1437 return 0;
1438}
1439
068a117c
JG		 1440int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1441 struct radeon_cs_packet *pkt,
4c788679 1442 struct radeon_bo *robj)
068a117c 1443{
068a117c 1444 unsigned idx;
513bcb46 1445 u32 value;
068a117c 1446 idx = pkt->idx + 1;
513bcb46 1447 value = radeon_get_ib_value(p, idx + 2);
4c788679 1448 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1449 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1450 "(need %u have %lu) !\n",
513bcb46 1451 value + 1,
4c788679 1452 radeon_bo_size(robj));
068a117c
JG		 1453 return -EINVAL;
1454 }
1455 return 0;
1456}
1457
771fe6b9
JG		 1458static int r100_packet3_check(struct radeon_cs_parser *p,
1459 struct radeon_cs_packet *pkt)
1460{
771fe6b9 1461 struct radeon_cs_reloc *reloc;
551ebd83 1462 struct r100_cs_track *track;
771fe6b9 1463 unsigned idx;
771fe6b9
JG		 1464 volatile uint32_t *ib;
1465 int r;
1466
1467 ib = p->ib->ptr;
771fe6b9 1468 idx = pkt->idx + 1;
551ebd83 1469 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1470 switch (pkt->opcode) {
1471 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1472 r = r100_packet3_load_vbpntr(p, pkt, idx);
1473 if (r)
1474 return r;
771fe6b9
JG		 1475 break;
1476 case PACKET3_INDX_BUFFER:
1477 r = r100_cs_packet_next_reloc(p, &reloc);
1478 if (r) {
1479 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1480 r100_cs_dump_packet(p, pkt);
1481 return r;
1482 }
513bcb46 1483 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1484 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1485 if (r) {
1486 return r;
1487 }
771fe6b9
JG		 1488 break;
1489 case 0x23:
771fe6b9
JG		 1490 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1491 r = r100_cs_packet_next_reloc(p, &reloc);
1492 if (r) {
1493 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1494 r100_cs_dump_packet(p, pkt);
1495 return r;
1496 }
513bcb46 1497 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1498 track->num_arrays = 1;
513bcb46 1499 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1500
1501 track->arrays[0].robj = reloc->robj;
1502 track->arrays[0].esize = track->vtx_size;
1503
513bcb46 1504 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1505
513bcb46 1506 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1507 track->immd_dwords = pkt->count - 1;
1508 r = r100_cs_track_check(p->rdev, track);
1509 if (r)
1510 return r;
771fe6b9
JG		 1511 break;
1512 case PACKET3_3D_DRAW_IMMD:
513bcb46 1513 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1514 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1515 return -EINVAL;
1516 }
cf57fc7a 1517 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1518 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1519 track->immd_dwords = pkt->count - 1;
1520 r = r100_cs_track_check(p->rdev, track);
1521 if (r)
1522 return r;
1523 break;
771fe6b9
JG		 1524 /* triggers drawing using in-packet vertex data */
1525 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1526 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1527 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1528 return -EINVAL;
1529 }
513bcb46 1530 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1531 track->immd_dwords = pkt->count;
1532 r = r100_cs_track_check(p->rdev, track);
1533 if (r)
1534 return r;
1535 break;
771fe6b9
JG		 1536 /* triggers drawing using in-packet vertex data */
1537 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1538 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1539 r = r100_cs_track_check(p->rdev, track);
1540 if (r)
1541 return r;
1542 break;
771fe6b9
JG		 1543 /* triggers drawing of vertex buffers setup elsewhere */
1544 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1545 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1546 r = r100_cs_track_check(p->rdev, track);
1547 if (r)
1548 return r;
1549 break;
771fe6b9
JG		 1550 /* triggers drawing using indices to vertex buffer */
1551 case PACKET3_3D_DRAW_VBUF:
513bcb46 1552 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1553 r = r100_cs_track_check(p->rdev, track);
1554 if (r)
1555 return r;
1556 break;
771fe6b9
JG		 1557 /* triggers drawing of vertex buffers setup elsewhere */
1558 case PACKET3_3D_DRAW_INDX:
513bcb46 1559 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1560 r = r100_cs_track_check(p->rdev, track);
1561 if (r)
1562 return r;
1563 break;
771fe6b9
JG		 1564 /* triggers drawing using indices to vertex buffer */
1565 case PACKET3_NOP:
1566 break;
1567 default:
1568 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1569 return -EINVAL;
1570 }
1571 return 0;
1572}
1573
1574int r100_cs_parse(struct radeon_cs_parser *p)
1575{
1576 struct radeon_cs_packet pkt;
9f022ddf 1577 struct r100_cs_track *track;
771fe6b9
JG		 1578 int r;
1579
9f022ddf
JG		 1580 track = kzalloc(sizeof(*track), GFP_KERNEL);
1581 r100_cs_track_clear(p->rdev, track);
1582 p->track = track;
771fe6b9
JG		 1583 do {
1584 r = r100_cs_packet_parse(p, &pkt, p->idx);
1585 if (r) {
1586 return r;
1587 }
1588 p->idx += pkt.count + 2;
1589 switch (pkt.type) {
068a117c 1590 case PACKET_TYPE0:
551ebd83
DA		 1591 if (p->rdev->family >= CHIP_R200)
1592 r = r100_cs_parse_packet0(p, &pkt,
1593 p->rdev->config.r100.reg_safe_bm,
1594 p->rdev->config.r100.reg_safe_bm_size,
1595 &r200_packet0_check);
1596 else
1597 r = r100_cs_parse_packet0(p, &pkt,
1598 p->rdev->config.r100.reg_safe_bm,
1599 p->rdev->config.r100.reg_safe_bm_size,
1600 &r100_packet0_check);
068a117c
JG		 1601 break;
1602 case PACKET_TYPE2:
1603 break;
1604 case PACKET_TYPE3:
1605 r = r100_packet3_check(p, &pkt);
1606 break;
1607 default:
1608 DRM_ERROR("Unknown packet type %d !\n",
1609 pkt.type);
1610 return -EINVAL;
771fe6b9
JG		 1611 }
1612 if (r) {
1613 return r;
1614 }
1615 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1616 return 0;
1617}
1618
1619
1620/*
1621 * Global GPU functions
1622 */
1623void r100_errata(struct radeon_device *rdev)
1624{
1625 rdev->pll_errata = 0;
1626
1627 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1628 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1629 }
1630
1631 if (rdev->family == CHIP_RV100 ||
1632 rdev->family == CHIP_RS100 ||
1633 rdev->family == CHIP_RS200) {
1634 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1635 }
1636}
1637
1638/* Wait for vertical sync on primary CRTC */
1639void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1640{
1641 uint32_t crtc_gen_cntl, tmp;
1642 int i;
1643
1644 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1645 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1646 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1647 return;
1648 }
1649 /* Clear the CRTC_VBLANK_SAVE bit */
1650 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1651 for (i = 0; i < rdev->usec_timeout; i++) {
1652 tmp = RREG32(RADEON_CRTC_STATUS);
1653 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1654 return;
1655 }
1656 DRM_UDELAY(1);
1657 }
1658}
1659
1660/* Wait for vertical sync on secondary CRTC */
1661void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1662{
1663 uint32_t crtc2_gen_cntl, tmp;
1664 int i;
1665
1666 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1667 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1668 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1669 return;
1670
1671 /* Clear the CRTC_VBLANK_SAVE bit */
1672 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1673 for (i = 0; i < rdev->usec_timeout; i++) {
1674 tmp = RREG32(RADEON_CRTC2_STATUS);
1675 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1676 return;
1677 }
1678 DRM_UDELAY(1);
1679 }
1680}
1681
1682int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1683{
1684 unsigned i;
1685 uint32_t tmp;
1686
1687 for (i = 0; i < rdev->usec_timeout; i++) {
1688 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1689 if (tmp >= n) {
1690 return 0;
1691 }
1692 DRM_UDELAY(1);
1693 }
1694 return -1;
1695}
1696
1697int r100_gui_wait_for_idle(struct radeon_device *rdev)
1698{
1699 unsigned i;
1700 uint32_t tmp;
1701
1702 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1703 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1704 " Bad things might happen.\n");
1705 }
1706 for (i = 0; i < rdev->usec_timeout; i++) {
1707 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 1708 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 1709 return 0;
1710 }
1711 DRM_UDELAY(1);
1712 }
1713 return -1;
1714}
1715
1716int r100_mc_wait_for_idle(struct radeon_device *rdev)
1717{
1718 unsigned i;
1719 uint32_t tmp;
1720
1721 for (i = 0; i < rdev->usec_timeout; i++) {
1722 /* read MC_STATUS */
4612dc97
AD		 1723 tmp = RREG32(RADEON_MC_STATUS);
1724 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 1725 return 0;
1726 }
1727 DRM_UDELAY(1);
1728 }
1729 return -1;
1730}
1731
1732void r100_gpu_init(struct radeon_device *rdev)
1733{
1734 /* TODO: anythings to do here ? pipes ? */
1735 r100_hdp_reset(rdev);
1736}
1737
1738void r100_hdp_reset(struct radeon_device *rdev)
1739{
1740 uint32_t tmp;
1741
1742 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1743 tmp |= (7 << 28);
1744 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1745 (void)RREG32(RADEON_HOST_PATH_CNTL);
1746 udelay(200);
1747 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1748 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1749 (void)RREG32(RADEON_HOST_PATH_CNTL);
1750}
1751
1752int r100_rb2d_reset(struct radeon_device *rdev)
1753{
1754 uint32_t tmp;
1755 int i;
1756
1757 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1758 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1759 udelay(200);
1760 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1761 /* Wait to prevent race in RBBM_STATUS */
1762 mdelay(1);
1763 for (i = 0; i < rdev->usec_timeout; i++) {
1764 tmp = RREG32(RADEON_RBBM_STATUS);
1765 if (!(tmp & (1 << 26))) {
1766 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1767 tmp);
1768 return 0;
1769 }
1770 DRM_UDELAY(1);
1771 }
1772 tmp = RREG32(RADEON_RBBM_STATUS);
1773 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1774 return -1;
1775}
1776
1777int r100_gpu_reset(struct radeon_device *rdev)
1778{
1779 uint32_t status;
1780
1781 /* reset order likely matter */
1782 status = RREG32(RADEON_RBBM_STATUS);
1783 /* reset HDP */
1784 r100_hdp_reset(rdev);
1785 /* reset rb2d */
1786 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1787 r100_rb2d_reset(rdev);
1788 }
1789 /* TODO: reset 3D engine */
1790 /* reset CP */
1791 status = RREG32(RADEON_RBBM_STATUS);
1792 if (status & (1 << 16)) {
1793 r100_cp_reset(rdev);
1794 }
1795 /* Check if GPU is idle */
1796 status = RREG32(RADEON_RBBM_STATUS);
4612dc97 1797 if (status & RADEON_RBBM_ACTIVE) {
771fe6b9
JG		 1798 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1799 return -1;
1800 }
1801 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1802 return 0;
1803}
1804
92cde00c
AD		 1805void r100_set_common_regs(struct radeon_device *rdev)
1806{
2739d49c
AD		 1807 struct drm_device *dev = rdev->ddev;
1808 bool force_dac2 = false;
1809
92cde00c
AD		 1810 /* set these so they don't interfere with anything */
1811 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1812 WREG32(RADEON_SUBPIC_CNTL, 0);
1813 WREG32(RADEON_VIPH_CONTROL, 0);
1814 WREG32(RADEON_I2C_CNTL_1, 0);
1815 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1816 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1817 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 1818
1819 /* always set up dac2 on rn50 and some rv100 as lots
1820 * of servers seem to wire it up to a VGA port but
1821 * don't report it in the bios connector
1822 * table.
1823 */
1824 switch (dev->pdev->device) {
1825 /* RN50 */
1826 case 0x515e:
1827 case 0x5969:
1828 force_dac2 = true;
1829 break;
1830 /* RV100*/
1831 case 0x5159:
1832 case 0x515a:
1833 /* DELL triple head servers */
1834 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1835 ((dev->pdev->subsystem_device == 0x016c) ||
1836 (dev->pdev->subsystem_device == 0x016d) ||
1837 (dev->pdev->subsystem_device == 0x016e) ||
1838 (dev->pdev->subsystem_device == 0x016f) ||
1839 (dev->pdev->subsystem_device == 0x0170) ||
1840 (dev->pdev->subsystem_device == 0x017d) ||
1841 (dev->pdev->subsystem_device == 0x017e) ||
1842 (dev->pdev->subsystem_device == 0x0183) ||
1843 (dev->pdev->subsystem_device == 0x018a) ||
1844 (dev->pdev->subsystem_device == 0x019a)))
1845 force_dac2 = true;
1846 break;
1847 }
1848
1849 if (force_dac2) {
1850 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1851 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1852 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1853
1854 /* For CRT on DAC2, don't turn it on if BIOS didn't
1855 enable it, even it's detected.
1856 */
1857
1858 /* force it to crtc0 */
1859 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1860 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1861 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1862
1863 /* set up the TV DAC */
1864 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1865 RADEON_TV_DAC_STD_MASK |
1866 RADEON_TV_DAC_RDACPD |
1867 RADEON_TV_DAC_GDACPD |
1868 RADEON_TV_DAC_BDACPD |
1869 RADEON_TV_DAC_BGADJ_MASK |
1870 RADEON_TV_DAC_DACADJ_MASK);
1871 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1872 RADEON_TV_DAC_NHOLD |
1873 RADEON_TV_DAC_STD_PS2 |
1874 (0x58 << 16));
1875
1876 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1877 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1878 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1879 }
92cde00c 1880}
771fe6b9
JG		 1881
1882/*
1883 * VRAM info
1884 */
1885static void r100_vram_get_type(struct radeon_device *rdev)
1886{
1887 uint32_t tmp;
1888
1889 rdev->mc.vram_is_ddr = false;
1890 if (rdev->flags & RADEON_IS_IGP)
1891 rdev->mc.vram_is_ddr = true;
1892 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1893 rdev->mc.vram_is_ddr = true;
1894 if ((rdev->family == CHIP_RV100) ||
1895 (rdev->family == CHIP_RS100) ||
1896 (rdev->family == CHIP_RS200)) {
1897 tmp = RREG32(RADEON_MEM_CNTL);
1898 if (tmp & RV100_HALF_MODE) {
1899 rdev->mc.vram_width = 32;
1900 } else {
1901 rdev->mc.vram_width = 64;
1902 }
1903 if (rdev->flags & RADEON_SINGLE_CRTC) {
1904 rdev->mc.vram_width /= 4;
1905 rdev->mc.vram_is_ddr = true;
1906 }
1907 } else if (rdev->family <= CHIP_RV280) {
1908 tmp = RREG32(RADEON_MEM_CNTL);
1909 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1910 rdev->mc.vram_width = 128;
1911 } else {
1912 rdev->mc.vram_width = 64;
1913 }
1914 } else {
1915 /* newer IGPs */
1916 rdev->mc.vram_width = 128;
1917 }
1918}
1919
2a0f8918 1920static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1921{
2a0f8918
DA		 1922 u32 aper_size;
1923 u8 byte;
1924
1925 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1926
1927 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1928 * that is has the 2nd generation multifunction PCI interface
1929 */
1930 if (rdev->family == CHIP_RV280 ||
1931 rdev->family >= CHIP_RV350) {
1932 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1933 ~RADEON_HDP_APER_CNTL);
1934 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1935 return aper_size * 2;
1936 }
1937
1938 /* Older cards have all sorts of funny issues to deal with. First
1939 * check if it's a multifunction card by reading the PCI config
1940 * header type... Limit those to one aperture size
1941 */
1942 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1943 if (byte & 0x80) {
1944 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1945 DRM_INFO("Limiting VRAM to one aperture\n");
1946 return aper_size;
1947 }
1948
1949 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1950 * have set it up. We don't write this as it's broken on some ASICs but
1951 * we expect the BIOS to have done the right thing (might be too optimistic...)
1952 */
1953 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1954 return aper_size * 2;
1955 return aper_size;
1956}
1957
1958void r100_vram_init_sizes(struct radeon_device *rdev)
1959{
1960 u64 config_aper_size;
1961 u32 accessible;
1962
1963 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1964
1965 if (rdev->flags & RADEON_IS_IGP) {
1966 uint32_t tom;
1967 /* read NB_TOM to get the amount of ram stolen for the GPU */
1968 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1969 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
3e43d821
DA		 1970 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1971 rdev->mc.vram_location = (tom & 0xffff) << 16;
7a50f01a
DA		 1972 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1973 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1974 } else {
7a50f01a 1975 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1976 /* Some production boards of m6 will report 0
1977 * if it's 8 MB
1978 */
7a50f01a
DA		 1979 if (rdev->mc.real_vram_size == 0) {
1980 rdev->mc.real_vram_size = 8192 * 1024;
1981 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1982 }
3e43d821
DA		 1983 /* let driver place VRAM */
1984 rdev->mc.vram_location = 0xFFFFFFFFUL;
2a0f8918
DA		 1985 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1986 * Novell bug 204882 + along with lots of ubuntu ones */
7a50f01a
DA		 1987 if (config_aper_size > rdev->mc.real_vram_size)
1988 rdev->mc.mc_vram_size = config_aper_size;
1989 else
1990 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 1991 }
1992
2a0f8918
DA		 1993 /* work out accessible VRAM */
1994 accessible = r100_get_accessible_vram(rdev);
1995
771fe6b9
JG		 1996 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1997 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2a0f8918
DA		 1998
1999 if (accessible > rdev->mc.aper_size)
2000 accessible = rdev->mc.aper_size;
2001
7a50f01a
DA		 2002 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
2003 rdev->mc.mc_vram_size = rdev->mc.aper_size;
2004
2005 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
2006 rdev->mc.real_vram_size = rdev->mc.aper_size;
2a0f8918
DA		 2007}
2008
28d52043
DA		 2009void r100_vga_set_state(struct radeon_device *rdev, bool state)
2010{
2011 uint32_t temp;
2012
2013 temp = RREG32(RADEON_CONFIG_CNTL);
2014 if (state == false) {
2015 temp &= ~(1<<8);
2016 temp |= (1<<9);
2017 } else {
2018 temp &= ~(1<<9);
2019 }
2020 WREG32(RADEON_CONFIG_CNTL, temp);
2021}
2022
2a0f8918
DA		 2023void r100_vram_info(struct radeon_device *rdev)
2024{
2025 r100_vram_get_type(rdev);
2026
2027 r100_vram_init_sizes(rdev);
771fe6b9
JG		 2028}
2029
2030
2031/*
2032 * Indirect registers accessor
2033 */
2034void r100_pll_errata_after_index(struct radeon_device *rdev)
2035{
2036 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2037 return;
2038 }
2039 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2040 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2041}
2042
2043static void r100_pll_errata_after_data(struct radeon_device *rdev)
2044{
2045 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2046 * or the chip could hang on a subsequent access
2047 */
2048 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2049 udelay(5000);
2050 }
2051
2052 /* This function is required to workaround a hardware bug in some (all?)
2053 * revisions of the R300. This workaround should be called after every
2054 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2055 * may not be correct.
2056 */
2057 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2058 uint32_t save, tmp;
2059
2060 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2061 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2062 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2063 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2064 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2065 }
2066}
2067
2068uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2069{
2070 uint32_t data;
2071
2072 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2073 r100_pll_errata_after_index(rdev);
2074 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2075 r100_pll_errata_after_data(rdev);
2076 return data;
2077}
2078
2079void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2080{
2081 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2082 r100_pll_errata_after_index(rdev);
2083 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2084 r100_pll_errata_after_data(rdev);
2085}
2086
d4550907 2087void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2088{
551ebd83
DA		 2089 if (ASIC_IS_RN50(rdev)) {
2090 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2091 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2092 } else if (rdev->family < CHIP_R200) {
2093 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2094 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2095 } else {
d4550907 2096 r200_set_safe_registers(rdev);
551ebd83 2097 }
068a117c
JG		 2098}
2099
771fe6b9
JG		 2100/*
2101 * Debugfs info
2102 */
2103#if defined(CONFIG_DEBUG_FS)
2104static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2105{
2106 struct drm_info_node *node = (struct drm_info_node *) m->private;
2107 struct drm_device *dev = node->minor->dev;
2108 struct radeon_device *rdev = dev->dev_private;
2109 uint32_t reg, value;
2110 unsigned i;
2111
2112 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2113 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2114 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2115 for (i = 0; i < 64; i++) {
2116 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2117 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2118 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2119 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2120 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2121 }
2122 return 0;
2123}
2124
2125static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2126{
2127 struct drm_info_node *node = (struct drm_info_node *) m->private;
2128 struct drm_device *dev = node->minor->dev;
2129 struct radeon_device *rdev = dev->dev_private;
2130 uint32_t rdp, wdp;
2131 unsigned count, i, j;
2132
2133 radeon_ring_free_size(rdev);
2134 rdp = RREG32(RADEON_CP_RB_RPTR);
2135 wdp = RREG32(RADEON_CP_RB_WPTR);
2136 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2137 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2138 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2139 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2140 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2141 seq_printf(m, "%u dwords in ring\n", count);
2142 for (j = 0; j <= count; j++) {
2143 i = (rdp + j) & rdev->cp.ptr_mask;
2144 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2145 }
2146 return 0;
2147}
2148
2149
2150static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2151{
2152 struct drm_info_node *node = (struct drm_info_node *) m->private;
2153 struct drm_device *dev = node->minor->dev;
2154 struct radeon_device *rdev = dev->dev_private;
2155 uint32_t csq_stat, csq2_stat, tmp;
2156 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2157 unsigned i;
2158
2159 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2160 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2161 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2162 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2163 r_rptr = (csq_stat >> 0) & 0x3ff;
2164 r_wptr = (csq_stat >> 10) & 0x3ff;
2165 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2166 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2167 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2168 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2169 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2170 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2171 seq_printf(m, "Ring rptr %u\n", r_rptr);
2172 seq_printf(m, "Ring wptr %u\n", r_wptr);
2173 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2174 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2175 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2176 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2177 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2178 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2179 seq_printf(m, "Ring fifo:\n");
2180 for (i = 0; i < 256; i++) {
2181 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2182 tmp = RREG32(RADEON_CP_CSQ_DATA);
2183 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2184 }
2185 seq_printf(m, "Indirect1 fifo:\n");
2186 for (i = 256; i <= 512; i++) {
2187 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2188 tmp = RREG32(RADEON_CP_CSQ_DATA);
2189 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2190 }
2191 seq_printf(m, "Indirect2 fifo:\n");
2192 for (i = 640; i < ib1_wptr; i++) {
2193 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2194 tmp = RREG32(RADEON_CP_CSQ_DATA);
2195 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2196 }
2197 return 0;
2198}
2199
2200static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2201{
2202 struct drm_info_node *node = (struct drm_info_node *) m->private;
2203 struct drm_device *dev = node->minor->dev;
2204 struct radeon_device *rdev = dev->dev_private;
2205 uint32_t tmp;
2206
2207 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2208 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2209 tmp = RREG32(RADEON_MC_FB_LOCATION);
2210 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2211 tmp = RREG32(RADEON_BUS_CNTL);
2212 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2213 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2214 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2215 tmp = RREG32(RADEON_AGP_BASE);
2216 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2217 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2218 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2219 tmp = RREG32(0x01D0);
2220 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2221 tmp = RREG32(RADEON_AIC_LO_ADDR);
2222 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2223 tmp = RREG32(RADEON_AIC_HI_ADDR);
2224 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2225 tmp = RREG32(0x01E4);
2226 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2227 return 0;
2228}
2229
2230static struct drm_info_list r100_debugfs_rbbm_list[] = {
2231 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2232};
2233
2234static struct drm_info_list r100_debugfs_cp_list[] = {
2235 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2236 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2237};
2238
2239static struct drm_info_list r100_debugfs_mc_info_list[] = {
2240 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2241};
2242#endif
2243
2244int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2245{
2246#if defined(CONFIG_DEBUG_FS)
2247 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2248#else
2249 return 0;
2250#endif
2251}
2252
2253int r100_debugfs_cp_init(struct radeon_device *rdev)
2254{
2255#if defined(CONFIG_DEBUG_FS)
2256 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2257#else
2258 return 0;
2259#endif
2260}
2261
2262int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2263{
2264#if defined(CONFIG_DEBUG_FS)
2265 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2266#else
2267 return 0;
2268#endif
2269}
e024e110
DA		 2270
2271int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2272 uint32_t tiling_flags, uint32_t pitch,
2273 uint32_t offset, uint32_t obj_size)
2274{
2275 int surf_index = reg * 16;
2276 int flags = 0;
2277
2278 /* r100/r200 divide by 16 */
2279 if (rdev->family < CHIP_R300)
2280 flags = pitch / 16;
2281 else
2282 flags = pitch / 8;
2283
2284 if (rdev->family <= CHIP_RS200) {
2285 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2286 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2287 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2288 if (tiling_flags & RADEON_TILING_MACRO)
2289 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2290 } else if (rdev->family <= CHIP_RV280) {
2291 if (tiling_flags & (RADEON_TILING_MACRO))
2292 flags |= R200_SURF_TILE_COLOR_MACRO;
2293 if (tiling_flags & RADEON_TILING_MICRO)
2294 flags |= R200_SURF_TILE_COLOR_MICRO;
2295 } else {
2296 if (tiling_flags & RADEON_TILING_MACRO)
2297 flags |= R300_SURF_TILE_MACRO;
2298 if (tiling_flags & RADEON_TILING_MICRO)
2299 flags |= R300_SURF_TILE_MICRO;
2300 }
2301
c88f9f0c
MD		 2302 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2303 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2304 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2305 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2306
e024e110
DA		 2307 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2308 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2309 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2310 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2311 return 0;
2312}
2313
2314void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2315{
2316 int surf_index = reg * 16;
2317 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2318}
c93bb85b
JG		 2319
2320void r100_bandwidth_update(struct radeon_device *rdev)
2321{
2322 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2323 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2324 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2325 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2326 fixed20_12 memtcas_ff[8] = {
2327 fixed_init(1),
2328 fixed_init(2),
2329 fixed_init(3),
2330 fixed_init(0),
2331 fixed_init_half(1),
2332 fixed_init_half(2),
2333 fixed_init(0),
2334 };
2335 fixed20_12 memtcas_rs480_ff[8] = {
2336 fixed_init(0),
2337 fixed_init(1),
2338 fixed_init(2),
2339 fixed_init(3),
2340 fixed_init(0),
2341 fixed_init_half(1),
2342 fixed_init_half(2),
2343 fixed_init_half(3),
2344 };
2345 fixed20_12 memtcas2_ff[8] = {
2346 fixed_init(0),
2347 fixed_init(1),
2348 fixed_init(2),
2349 fixed_init(3),
2350 fixed_init(4),
2351 fixed_init(5),
2352 fixed_init(6),
2353 fixed_init(7),
2354 };
2355 fixed20_12 memtrbs[8] = {
2356 fixed_init(1),
2357 fixed_init_half(1),
2358 fixed_init(2),
2359 fixed_init_half(2),
2360 fixed_init(3),
2361 fixed_init_half(3),
2362 fixed_init(4),
2363 fixed_init_half(4)
2364 };
2365 fixed20_12 memtrbs_r4xx[8] = {
2366 fixed_init(4),
2367 fixed_init(5),
2368 fixed_init(6),
2369 fixed_init(7),
2370 fixed_init(8),
2371 fixed_init(9),
2372 fixed_init(10),
2373 fixed_init(11)
2374 };
2375 fixed20_12 min_mem_eff;
2376 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2377 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2378 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2379 disp_drain_rate2, read_return_rate;
2380 fixed20_12 time_disp1_drop_priority;
2381 int c;
2382 int cur_size = 16; /* in octawords */
2383 int critical_point = 0, critical_point2;
2384/* uint32_t read_return_rate, time_disp1_drop_priority; */
2385 int stop_req, max_stop_req;
2386 struct drm_display_mode *mode1 = NULL;
2387 struct drm_display_mode *mode2 = NULL;
2388 uint32_t pixel_bytes1 = 0;
2389 uint32_t pixel_bytes2 = 0;
2390
2391 if (rdev->mode_info.crtcs[0]->base.enabled) {
2392 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2393 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2394 }
dfee5614
DA		 2395 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2396 if (rdev->mode_info.crtcs[1]->base.enabled) {
2397 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2398 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2399 }
c93bb85b
JG		 2400 }
2401
2402 min_mem_eff.full = rfixed_const_8(0);
2403 /* get modes */
2404 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2405 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2406 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2407 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2408 /* check crtc enables */
2409 if (mode2)
2410 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2411 if (mode1)
2412 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2413 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2414 }
2415
2416 /*
2417 * determine is there is enough bw for current mode
2418 */
2419 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2420 temp_ff.full = rfixed_const(100);
2421 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2422 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2423 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2424
2425 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2426 temp_ff.full = rfixed_const(temp);
2427 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2428
2429 pix_clk.full = 0;
2430 pix_clk2.full = 0;
2431 peak_disp_bw.full = 0;
2432 if (mode1) {
2433 temp_ff.full = rfixed_const(1000);
2434 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2435 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2436 temp_ff.full = rfixed_const(pixel_bytes1);
2437 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2438 }
2439 if (mode2) {
2440 temp_ff.full = rfixed_const(1000);
2441 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2442 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2443 temp_ff.full = rfixed_const(pixel_bytes2);
2444 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2445 }
2446
2447 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2448 if (peak_disp_bw.full >= mem_bw.full) {
2449 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2450 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2451 }
2452
2453 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2454 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2455 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2456 mem_trcd = ((temp >> 2) & 0x3) + 1;
2457 mem_trp = ((temp & 0x3)) + 1;
2458 mem_tras = ((temp & 0x70) >> 4) + 1;
2459 } else if (rdev->family == CHIP_R300 ||
2460 rdev->family == CHIP_R350) { /* r300, r350 */
2461 mem_trcd = (temp & 0x7) + 1;
2462 mem_trp = ((temp >> 8) & 0x7) + 1;
2463 mem_tras = ((temp >> 11) & 0xf) + 4;
2464 } else if (rdev->family == CHIP_RV350 ||
2465 rdev->family <= CHIP_RV380) {
2466 /* rv3x0 */
2467 mem_trcd = (temp & 0x7) + 3;
2468 mem_trp = ((temp >> 8) & 0x7) + 3;
2469 mem_tras = ((temp >> 11) & 0xf) + 6;
2470 } else if (rdev->family == CHIP_R420 ||
2471 rdev->family == CHIP_R423 ||
2472 rdev->family == CHIP_RV410) {
2473 /* r4xx */
2474 mem_trcd = (temp & 0xf) + 3;
2475 if (mem_trcd > 15)
2476 mem_trcd = 15;
2477 mem_trp = ((temp >> 8) & 0xf) + 3;
2478 if (mem_trp > 15)
2479 mem_trp = 15;
2480 mem_tras = ((temp >> 12) & 0x1f) + 6;
2481 if (mem_tras > 31)
2482 mem_tras = 31;
2483 } else { /* RV200, R200 */
2484 mem_trcd = (temp & 0x7) + 1;
2485 mem_trp = ((temp >> 8) & 0x7) + 1;
2486 mem_tras = ((temp >> 12) & 0xf) + 4;
2487 }
2488 /* convert to FF */
2489 trcd_ff.full = rfixed_const(mem_trcd);
2490 trp_ff.full = rfixed_const(mem_trp);
2491 tras_ff.full = rfixed_const(mem_tras);
2492
2493 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2494 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2495 data = (temp & (7 << 20)) >> 20;
2496 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2497 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2498 tcas_ff = memtcas_rs480_ff[data];
2499 else
2500 tcas_ff = memtcas_ff[data];
2501 } else
2502 tcas_ff = memtcas2_ff[data];
2503
2504 if (rdev->family == CHIP_RS400 ||
2505 rdev->family == CHIP_RS480) {
2506 /* extra cas latency stored in bits 23-25 0-4 clocks */
2507 data = (temp >> 23) & 0x7;
2508 if (data < 5)
2509 tcas_ff.full += rfixed_const(data);
2510 }
2511
2512 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2513 /* on the R300, Tcas is included in Trbs.
2514 */
2515 temp = RREG32(RADEON_MEM_CNTL);
2516 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2517 if (data == 1) {
2518 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2519 temp = RREG32(R300_MC_IND_INDEX);
2520 temp &= ~R300_MC_IND_ADDR_MASK;
2521 temp |= R300_MC_READ_CNTL_CD_mcind;
2522 WREG32(R300_MC_IND_INDEX, temp);
2523 temp = RREG32(R300_MC_IND_DATA);
2524 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2525 } else {
2526 temp = RREG32(R300_MC_READ_CNTL_AB);
2527 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2528 }
2529 } else {
2530 temp = RREG32(R300_MC_READ_CNTL_AB);
2531 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2532 }
2533 if (rdev->family == CHIP_RV410 ||
2534 rdev->family == CHIP_R420 ||
2535 rdev->family == CHIP_R423)
2536 trbs_ff = memtrbs_r4xx[data];
2537 else
2538 trbs_ff = memtrbs[data];
2539 tcas_ff.full += trbs_ff.full;
2540 }
2541
2542 sclk_eff_ff.full = sclk_ff.full;
2543
2544 if (rdev->flags & RADEON_IS_AGP) {
2545 fixed20_12 agpmode_ff;
2546 agpmode_ff.full = rfixed_const(radeon_agpmode);
2547 temp_ff.full = rfixed_const_666(16);
2548 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2549 }
2550 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2551
2552 if (ASIC_IS_R300(rdev)) {
2553 sclk_delay_ff.full = rfixed_const(250);
2554 } else {
2555 if ((rdev->family == CHIP_RV100) ||
2556 rdev->flags & RADEON_IS_IGP) {
2557 if (rdev->mc.vram_is_ddr)
2558 sclk_delay_ff.full = rfixed_const(41);
2559 else
2560 sclk_delay_ff.full = rfixed_const(33);
2561 } else {
2562 if (rdev->mc.vram_width == 128)
2563 sclk_delay_ff.full = rfixed_const(57);
2564 else
2565 sclk_delay_ff.full = rfixed_const(41);
2566 }
2567 }
2568
2569 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2570
2571 if (rdev->mc.vram_is_ddr) {
2572 if (rdev->mc.vram_width == 32) {
2573 k1.full = rfixed_const(40);
2574 c = 3;
2575 } else {
2576 k1.full = rfixed_const(20);
2577 c = 1;
2578 }
2579 } else {
2580 k1.full = rfixed_const(40);
2581 c = 3;
2582 }
2583
2584 temp_ff.full = rfixed_const(2);
2585 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2586 temp_ff.full = rfixed_const(c);
2587 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2588 temp_ff.full = rfixed_const(4);
2589 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2590 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2591 mc_latency_mclk.full += k1.full;
2592
2593 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2594 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2595
2596 /*
2597 HW cursor time assuming worst case of full size colour cursor.
2598 */
2599 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2600 temp_ff.full += trcd_ff.full;
2601 if (temp_ff.full < tras_ff.full)
2602 temp_ff.full = tras_ff.full;
2603 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2604
2605 temp_ff.full = rfixed_const(cur_size);
2606 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2607 /*
2608 Find the total latency for the display data.
2609 */
b5fc9010 2610 disp_latency_overhead.full = rfixed_const(8);
c93bb85b
JG		 2611 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2612 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2613 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2614
2615 if (mc_latency_mclk.full > mc_latency_sclk.full)
2616 disp_latency.full = mc_latency_mclk.full;
2617 else
2618 disp_latency.full = mc_latency_sclk.full;
2619
2620 /* setup Max GRPH_STOP_REQ default value */
2621 if (ASIC_IS_RV100(rdev))
2622 max_stop_req = 0x5c;
2623 else
2624 max_stop_req = 0x7c;
2625
2626 if (mode1) {
2627 /* CRTC1
2628 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2629 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2630 */
2631 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2632
2633 if (stop_req > max_stop_req)
2634 stop_req = max_stop_req;
2635
2636 /*
2637 Find the drain rate of the display buffer.
2638 */
2639 temp_ff.full = rfixed_const((16/pixel_bytes1));
2640 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2641
2642 /*
2643 Find the critical point of the display buffer.
2644 */
2645 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2646 crit_point_ff.full += rfixed_const_half(0);
2647
2648 critical_point = rfixed_trunc(crit_point_ff);
2649
2650 if (rdev->disp_priority == 2) {
2651 critical_point = 0;
2652 }
2653
2654 /*
2655 The critical point should never be above max_stop_req-4. Setting
2656 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2657 */
2658 if (max_stop_req - critical_point < 4)
2659 critical_point = 0;
2660
2661 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2662 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2663 critical_point = 0x10;
2664 }
2665
2666 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2667 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2668 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2669 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2670 if ((rdev->family == CHIP_R350) &&
2671 (stop_req > 0x15)) {
2672 stop_req -= 0x10;
2673 }
2674 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2675 temp |= RADEON_GRPH_BUFFER_SIZE;
2676 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2677 RADEON_GRPH_CRITICAL_AT_SOF |
2678 RADEON_GRPH_STOP_CNTL);
2679 /*
2680 Write the result into the register.
2681 */
2682 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2683 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2684
2685#if 0
2686 if ((rdev->family == CHIP_RS400) ||
2687 (rdev->family == CHIP_RS480)) {
2688 /* attempt to program RS400 disp regs correctly ??? */
2689 temp = RREG32(RS400_DISP1_REG_CNTL);
2690 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2691 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2692 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2693 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2694 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2695 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2696 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2697 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2698 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2699 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2700 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2701 }
2702#endif
2703
2704 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2705 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2706 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2707 }
2708
2709 if (mode2) {
2710 u32 grph2_cntl;
2711 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2712
2713 if (stop_req > max_stop_req)
2714 stop_req = max_stop_req;
2715
2716 /*
2717 Find the drain rate of the display buffer.
2718 */
2719 temp_ff.full = rfixed_const((16/pixel_bytes2));
2720 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2721
2722 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2723 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2724 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2725 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2726 if ((rdev->family == CHIP_R350) &&
2727 (stop_req > 0x15)) {
2728 stop_req -= 0x10;
2729 }
2730 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2731 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2732 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2733 RADEON_GRPH_CRITICAL_AT_SOF |
2734 RADEON_GRPH_STOP_CNTL);
2735
2736 if ((rdev->family == CHIP_RS100) ||
2737 (rdev->family == CHIP_RS200))
2738 critical_point2 = 0;
2739 else {
2740 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2741 temp_ff.full = rfixed_const(temp);
2742 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2743 if (sclk_ff.full < temp_ff.full)
2744 temp_ff.full = sclk_ff.full;
2745
2746 read_return_rate.full = temp_ff.full;
2747
2748 if (mode1) {
2749 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2750 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2751 } else {
2752 time_disp1_drop_priority.full = 0;
2753 }
2754 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2755 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2756 crit_point_ff.full += rfixed_const_half(0);
2757
2758 critical_point2 = rfixed_trunc(crit_point_ff);
2759
2760 if (rdev->disp_priority == 2) {
2761 critical_point2 = 0;
2762 }
2763
2764 if (max_stop_req - critical_point2 < 4)
2765 critical_point2 = 0;
2766
2767 }
2768
2769 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2770 /* some R300 cards have problem with this set to 0 */
2771 critical_point2 = 0x10;
2772 }
2773
2774 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2775 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2776
2777 if ((rdev->family == CHIP_RS400) ||
2778 (rdev->family == CHIP_RS480)) {
2779#if 0
2780 /* attempt to program RS400 disp2 regs correctly ??? */
2781 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2782 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2783 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2784 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2785 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2786 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2787 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2788 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2789 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2790 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2791 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2792 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2793#endif
2794 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2795 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2796 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2797 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2798 }
2799
2800 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2801 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2802 }
2803}
551ebd83
DA		 2804
2805static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2806{
2807 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 2808 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 2809 DRM_ERROR("width %d\n", t->width);
ceb776bc 2810 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 2811 DRM_ERROR("height %d\n", t->height);
ceb776bc 2812 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 2813 DRM_ERROR("num levels %d\n", t->num_levels);
2814 DRM_ERROR("depth %d\n", t->txdepth);
2815 DRM_ERROR("bpp %d\n", t->cpp);
2816 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2817 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2818 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 2819 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 2820}
2821
2822static int r100_cs_track_cube(struct radeon_device *rdev,
2823 struct r100_cs_track *track, unsigned idx)
2824{
2825 unsigned face, w, h;
4c788679 2826 struct radeon_bo *cube_robj;
551ebd83
DA		 2827 unsigned long size;
2828
2829 for (face = 0; face < 5; face++) {
2830 cube_robj = track->textures[idx].cube_info[face].robj;
2831 w = track->textures[idx].cube_info[face].width;
2832 h = track->textures[idx].cube_info[face].height;
2833
2834 size = w * h;
2835 size *= track->textures[idx].cpp;
2836
2837 size += track->textures[idx].cube_info[face].offset;
2838
4c788679 2839 if (size > radeon_bo_size(cube_robj)) {
551ebd83 2840 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
4c788679 2841 size, radeon_bo_size(cube_robj));
551ebd83
DA		 2842 r100_cs_track_texture_print(&track->textures[idx]);
2843 return -1;
2844 }
2845 }
2846 return 0;
2847}
2848
d785d78b
DA		 2849static int r100_track_compress_size(int compress_format, int w, int h)
2850{
2851 int block_width, block_height, block_bytes;
2852 int wblocks, hblocks;
2853 int min_wblocks;
2854 int sz;
2855
2856 block_width = 4;
2857 block_height = 4;
2858
2859 switch (compress_format) {
2860 case R100_TRACK_COMP_DXT1:
2861 block_bytes = 8;
2862 min_wblocks = 4;
2863 break;
2864 default:
2865 case R100_TRACK_COMP_DXT35:
2866 block_bytes = 16;
2867 min_wblocks = 2;
2868 break;
2869 }
2870
2871 hblocks = (h + block_height - 1) / block_height;
2872 wblocks = (w + block_width - 1) / block_width;
2873 if (wblocks < min_wblocks)
2874 wblocks = min_wblocks;
2875 sz = wblocks * hblocks * block_bytes;
2876 return sz;
2877}
2878
551ebd83
DA		 2879static int r100_cs_track_texture_check(struct radeon_device *rdev,
2880 struct r100_cs_track *track)
2881{
4c788679 2882 struct radeon_bo *robj;
551ebd83
DA		 2883 unsigned long size;
2884 unsigned u, i, w, h;
2885 int ret;
2886
2887 for (u = 0; u < track->num_texture; u++) {
2888 if (!track->textures[u].enabled)
2889 continue;
2890 robj = track->textures[u].robj;
2891 if (robj == NULL) {
2892 DRM_ERROR("No texture bound to unit %u\n", u);
2893 return -EINVAL;
2894 }
2895 size = 0;
2896 for (i = 0; i <= track->textures[u].num_levels; i++) {
2897 if (track->textures[u].use_pitch) {
2898 if (rdev->family < CHIP_R300)
2899 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2900 else
2901 w = track->textures[u].pitch / (1 << i);
2902 } else {
ceb776bc 2903 w = track->textures[u].width;
551ebd83
DA		 2904 if (rdev->family >= CHIP_RV515)
2905 w |= track->textures[u].width_11;
ceb776bc 2906 w = w / (1 << i);
551ebd83
DA		 2907 if (track->textures[u].roundup_w)
2908 w = roundup_pow_of_two(w);
2909 }
ceb776bc 2910 h = track->textures[u].height;
551ebd83
DA		 2911 if (rdev->family >= CHIP_RV515)
2912 h |= track->textures[u].height_11;
ceb776bc 2913 h = h / (1 << i);
551ebd83
DA		 2914 if (track->textures[u].roundup_h)
2915 h = roundup_pow_of_two(h);
d785d78b
DA		 2916 if (track->textures[u].compress_format) {
2917
2918 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2919 /* compressed textures are block based */
2920 } else
2921 size += w * h;
551ebd83
DA		 2922 }
2923 size *= track->textures[u].cpp;
d785d78b 2924
551ebd83
DA		 2925 switch (track->textures[u].tex_coord_type) {
2926 case 0:
2927 break;
2928 case 1:
2929 size *= (1 << track->textures[u].txdepth);
2930 break;
2931 case 2:
2932 if (track->separate_cube) {
2933 ret = r100_cs_track_cube(rdev, track, u);
2934 if (ret)
2935 return ret;
2936 } else
2937 size *= 6;
2938 break;
2939 default:
2940 DRM_ERROR("Invalid texture coordinate type %u for unit "
2941 "%u\n", track->textures[u].tex_coord_type, u);
2942 return -EINVAL;
2943 }
4c788679 2944 if (size > radeon_bo_size(robj)) {
551ebd83 2945 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 2946 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 2947 r100_cs_track_texture_print(&track->textures[u]);
2948 return -EINVAL;
2949 }
2950 }
2951 return 0;
2952}
2953
2954int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2955{
2956 unsigned i;
2957 unsigned long size;
2958 unsigned prim_walk;
2959 unsigned nverts;
2960
2961 for (i = 0; i < track->num_cb; i++) {
2962 if (track->cb[i].robj == NULL) {
46c64d4b
MO		 2963 if (!(track->fastfill || track->color_channel_mask ||
2964 track->blend_read_enable)) {
2965 continue;
2966 }
551ebd83
DA		 2967 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2968 return -EINVAL;
2969 }
2970 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2971 size += track->cb[i].offset;
4c788679 2972 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 2973 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2974 "(need %lu have %lu) !\n", i, size,
4c788679 2975 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 2976 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2977 i, track->cb[i].pitch, track->cb[i].cpp,
2978 track->cb[i].offset, track->maxy);
2979 return -EINVAL;
2980 }
2981 }
2982 if (track->z_enabled) {
2983 if (track->zb.robj == NULL) {
2984 DRM_ERROR("[drm] No buffer for z buffer !\n");
2985 return -EINVAL;
2986 }
2987 size = track->zb.pitch * track->zb.cpp * track->maxy;
2988 size += track->zb.offset;
4c788679 2989 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 2990 DRM_ERROR("[drm] Buffer too small for z buffer "
2991 "(need %lu have %lu) !\n", size,
4c788679 2992 radeon_bo_size(track->zb.robj));
551ebd83
DA		 2993 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2994 track->zb.pitch, track->zb.cpp,
2995 track->zb.offset, track->maxy);
2996 return -EINVAL;
2997 }
2998 }
2999 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3000 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3001 switch (prim_walk) {
3002 case 1:
3003 for (i = 0; i < track->num_arrays; i++) {
3004 size = track->arrays[i].esize * track->max_indx * 4;
3005 if (track->arrays[i].robj == NULL) {
3006 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3007 "bound\n", prim_walk, i);
3008 return -EINVAL;
3009 }
4c788679
JG		 3010 if (size > radeon_bo_size(track->arrays[i].robj)) {
3011 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3012 "need %lu dwords have %lu dwords\n",
3013 prim_walk, i, size >> 2,
3014 radeon_bo_size(track->arrays[i].robj)
3015 >> 2);
551ebd83
DA		 3016 DRM_ERROR("Max indices %u\n", track->max_indx);
3017 return -EINVAL;
3018 }
3019 }
3020 break;
3021 case 2:
3022 for (i = 0; i < track->num_arrays; i++) {
3023 size = track->arrays[i].esize * (nverts - 1) * 4;
3024 if (track->arrays[i].robj == NULL) {
3025 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3026 "bound\n", prim_walk, i);
3027 return -EINVAL;
3028 }
4c788679
JG		 3029 if (size > radeon_bo_size(track->arrays[i].robj)) {
3030 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3031 "need %lu dwords have %lu dwords\n",
3032 prim_walk, i, size >> 2,
3033 radeon_bo_size(track->arrays[i].robj)
3034 >> 2);
551ebd83
DA		 3035 return -EINVAL;
3036 }
3037 }
3038 break;
3039 case 3:
3040 size = track->vtx_size * nverts;
3041 if (size != track->immd_dwords) {
3042 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3043 track->immd_dwords, size);
3044 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3045 nverts, track->vtx_size);
3046 return -EINVAL;
3047 }
3048 break;
3049 default:
3050 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3051 prim_walk);
3052 return -EINVAL;
3053 }
3054 return r100_cs_track_texture_check(rdev, track);
3055}
3056
3057void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3058{
3059 unsigned i, face;
3060
3061 if (rdev->family < CHIP_R300) {
3062 track->num_cb = 1;
3063 if (rdev->family <= CHIP_RS200)
3064 track->num_texture = 3;
3065 else
3066 track->num_texture = 6;
3067 track->maxy = 2048;
3068 track->separate_cube = 1;
3069 } else {
3070 track->num_cb = 4;
3071 track->num_texture = 16;
3072 track->maxy = 4096;
3073 track->separate_cube = 0;
3074 }
3075
3076 for (i = 0; i < track->num_cb; i++) {
3077 track->cb[i].robj = NULL;
3078 track->cb[i].pitch = 8192;
3079 track->cb[i].cpp = 16;
3080 track->cb[i].offset = 0;
3081 }
3082 track->z_enabled = true;
3083 track->zb.robj = NULL;
3084 track->zb.pitch = 8192;
3085 track->zb.cpp = 4;
3086 track->zb.offset = 0;
3087 track->vtx_size = 0x7F;
3088 track->immd_dwords = 0xFFFFFFFFUL;
3089 track->num_arrays = 11;
3090 track->max_indx = 0x00FFFFFFUL;
3091 for (i = 0; i < track->num_arrays; i++) {
3092 track->arrays[i].robj = NULL;
3093 track->arrays[i].esize = 0x7F;
3094 }
3095 for (i = 0; i < track->num_texture; i++) {
d785d78b 3096 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3097 track->textures[i].pitch = 16536;
3098 track->textures[i].width = 16536;
3099 track->textures[i].height = 16536;
3100 track->textures[i].width_11 = 1 << 11;
3101 track->textures[i].height_11 = 1 << 11;
3102 track->textures[i].num_levels = 12;
3103 if (rdev->family <= CHIP_RS200) {
3104 track->textures[i].tex_coord_type = 0;
3105 track->textures[i].txdepth = 0;
3106 } else {
3107 track->textures[i].txdepth = 16;
3108 track->textures[i].tex_coord_type = 1;
3109 }
3110 track->textures[i].cpp = 64;
3111 track->textures[i].robj = NULL;
3112 /* CS IB emission code makes sure texture unit are disabled */
3113 track->textures[i].enabled = false;
3114 track->textures[i].roundup_w = true;
3115 track->textures[i].roundup_h = true;
3116 if (track->separate_cube)
3117 for (face = 0; face < 5; face++) {
3118 track->textures[i].cube_info[face].robj = NULL;
3119 track->textures[i].cube_info[face].width = 16536;
3120 track->textures[i].cube_info[face].height = 16536;
3121 track->textures[i].cube_info[face].offset = 0;
3122 }
3123 }
3124}
3ce0a23d
JG		 3125
3126int r100_ring_test(struct radeon_device *rdev)
3127{
3128 uint32_t scratch;
3129 uint32_t tmp = 0;
3130 unsigned i;
3131 int r;
3132
3133 r = radeon_scratch_get(rdev, &scratch);
3134 if (r) {
3135 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3136 return r;
3137 }
3138 WREG32(scratch, 0xCAFEDEAD);
3139 r = radeon_ring_lock(rdev, 2);
3140 if (r) {
3141 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3142 radeon_scratch_free(rdev, scratch);
3143 return r;
3144 }
3145 radeon_ring_write(rdev, PACKET0(scratch, 0));
3146 radeon_ring_write(rdev, 0xDEADBEEF);
3147 radeon_ring_unlock_commit(rdev);
3148 for (i = 0; i < rdev->usec_timeout; i++) {
3149 tmp = RREG32(scratch);
3150 if (tmp == 0xDEADBEEF) {
3151 break;
3152 }
3153 DRM_UDELAY(1);
3154 }
3155 if (i < rdev->usec_timeout) {
3156 DRM_INFO("ring test succeeded in %d usecs\n", i);
3157 } else {
3158 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3159 scratch, tmp);
3160 r = -EINVAL;
3161 }
3162 radeon_scratch_free(rdev, scratch);
3163 return r;
3164}
3165
3166void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3167{
3168 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3169 radeon_ring_write(rdev, ib->gpu_addr);
3170 radeon_ring_write(rdev, ib->length_dw);
3171}
3172
3173int r100_ib_test(struct radeon_device *rdev)
3174{
3175 struct radeon_ib *ib;
3176 uint32_t scratch;
3177 uint32_t tmp = 0;
3178 unsigned i;
3179 int r;
3180
3181 r = radeon_scratch_get(rdev, &scratch);
3182 if (r) {
3183 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3184 return r;
3185 }
3186 WREG32(scratch, 0xCAFEDEAD);
3187 r = radeon_ib_get(rdev, &ib);
3188 if (r) {
3189 return r;
3190 }
3191 ib->ptr[0] = PACKET0(scratch, 0);
3192 ib->ptr[1] = 0xDEADBEEF;
3193 ib->ptr[2] = PACKET2(0);
3194 ib->ptr[3] = PACKET2(0);
3195 ib->ptr[4] = PACKET2(0);
3196 ib->ptr[5] = PACKET2(0);
3197 ib->ptr[6] = PACKET2(0);
3198 ib->ptr[7] = PACKET2(0);
3199 ib->length_dw = 8;
3200 r = radeon_ib_schedule(rdev, ib);
3201 if (r) {
3202 radeon_scratch_free(rdev, scratch);
3203 radeon_ib_free(rdev, &ib);
3204 return r;
3205 }
3206 r = radeon_fence_wait(ib->fence, false);
3207 if (r) {
3208 return r;
3209 }
3210 for (i = 0; i < rdev->usec_timeout; i++) {
3211 tmp = RREG32(scratch);
3212 if (tmp == 0xDEADBEEF) {
3213 break;
3214 }
3215 DRM_UDELAY(1);
3216 }
3217 if (i < rdev->usec_timeout) {
3218 DRM_INFO("ib test succeeded in %u usecs\n", i);
3219 } else {
3220 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3221 scratch, tmp);
3222 r = -EINVAL;
3223 }
3224 radeon_scratch_free(rdev, scratch);
3225 radeon_ib_free(rdev, &ib);
3226 return r;
3227}
9f022ddf
JG		 3228
3229void r100_ib_fini(struct radeon_device *rdev)
3230{
3231 radeon_ib_pool_fini(rdev);
3232}
3233
3234int r100_ib_init(struct radeon_device *rdev)
3235{
3236 int r;
3237
3238 r = radeon_ib_pool_init(rdev);
3239 if (r) {
3240 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3241 r100_ib_fini(rdev);
3242 return r;
3243 }
3244 r = r100_ib_test(rdev);
3245 if (r) {
3246 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3247 r100_ib_fini(rdev);
3248 return r;
3249 }
3250 return 0;
3251}
3252
3253void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3254{
3255 /* Shutdown CP we shouldn't need to do that but better be safe than
3256 * sorry
3257 */
3258 rdev->cp.ready = false;
3259 WREG32(R_000740_CP_CSQ_CNTL, 0);
3260
3261 /* Save few CRTC registers */
ca6ffc64 3262 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3263 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3264 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3265 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3266 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3267 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3268 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3269 }
3270
3271 /* Disable VGA aperture access */
ca6ffc64 3272 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3273 /* Disable cursor, overlay, crtc */
3274 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3275 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3276 S_000054_CRTC_DISPLAY_DIS(1));
3277 WREG32(R_000050_CRTC_GEN_CNTL,
3278 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3279 S_000050_CRTC_DISP_REQ_EN_B(1));
3280 WREG32(R_000420_OV0_SCALE_CNTL,
3281 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3282 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3283 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3284 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3285 S_000360_CUR2_LOCK(1));
3286 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3287 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3288 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3289 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3290 WREG32(R_000360_CUR2_OFFSET,
3291 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3292 }
3293}
3294
3295void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3296{
3297 /* Update base address for crtc */
3298 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3299 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3300 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3301 rdev->mc.vram_location);
3302 }
3303 /* Restore CRTC registers */
ca6ffc64 3304 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3305 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3306 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3307 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3308 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3309 }
3310}
ca6ffc64
JG		 3311
3312void r100_vga_render_disable(struct radeon_device *rdev)
3313{
d4550907 3314 u32 tmp;
ca6ffc64 3315
d4550907 3316 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3317 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3318}
d4550907
JG		 3319
3320static void r100_debugfs(struct radeon_device *rdev)
3321{
3322 int r;
3323
3324 r = r100_debugfs_mc_info_init(rdev);
3325 if (r)
3326 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3327}
3328
3329static void r100_mc_program(struct radeon_device *rdev)
3330{
3331 struct r100_mc_save save;
3332
3333 /* Stops all mc clients */
3334 r100_mc_stop(rdev, &save);
3335 if (rdev->flags & RADEON_IS_AGP) {
3336 WREG32(R_00014C_MC_AGP_LOCATION,
3337 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3338 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3339 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3340 if (rdev->family > CHIP_RV200)
3341 WREG32(R_00015C_AGP_BASE_2,
3342 upper_32_bits(rdev->mc.agp_base) & 0xff);
3343 } else {
3344 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3345 WREG32(R_000170_AGP_BASE, 0);
3346 if (rdev->family > CHIP_RV200)
3347 WREG32(R_00015C_AGP_BASE_2, 0);
3348 }
3349 /* Wait for mc idle */
3350 if (r100_mc_wait_for_idle(rdev))
3351 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3352 /* Program MC, should be a 32bits limited address space */
3353 WREG32(R_000148_MC_FB_LOCATION,
3354 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3355 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3356 r100_mc_resume(rdev, &save);
3357}
3358
3359void r100_clock_startup(struct radeon_device *rdev)
3360{
3361 u32 tmp;
3362
3363 if (radeon_dynclks != -1 && radeon_dynclks)
3364 radeon_legacy_set_clock_gating(rdev, 1);
3365 /* We need to force on some of the block */
3366 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3367 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3368 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3369 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3370 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3371}
3372
3373static int r100_startup(struct radeon_device *rdev)
3374{
3375 int r;
3376
92cde00c
AD		 3377 /* set common regs */
3378 r100_set_common_regs(rdev);
3379 /* program mc */
d4550907
JG		 3380 r100_mc_program(rdev);
3381 /* Resume clock */
3382 r100_clock_startup(rdev);
3383 /* Initialize GPU configuration (# pipes, ...) */
3384 r100_gpu_init(rdev);
3385 /* Initialize GART (initialize after TTM so we can allocate
3386 * memory through TTM but finalize after TTM) */
17e15b0c 3387 r100_enable_bm(rdev);
d4550907
JG		 3388 if (rdev->flags & RADEON_IS_PCI) {
3389 r = r100_pci_gart_enable(rdev);
3390 if (r)
3391 return r;
3392 }
3393 /* Enable IRQ */
d4550907 3394 r100_irq_set(rdev);
cafe6609 3395 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3396 /* 1M ring buffer */
3397 r = r100_cp_init(rdev, 1024 * 1024);
3398 if (r) {
3399 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3400 return r;
3401 }
3402 r = r100_wb_init(rdev);
3403 if (r)
3404 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3405 r = r100_ib_init(rdev);
3406 if (r) {
3407 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3408 return r;
3409 }
3410 return 0;
3411}
3412
3413int r100_resume(struct radeon_device *rdev)
3414{
3415 /* Make sur GART are not working */
3416 if (rdev->flags & RADEON_IS_PCI)
3417 r100_pci_gart_disable(rdev);
3418 /* Resume clock before doing reset */
3419 r100_clock_startup(rdev);
3420 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3421 if (radeon_gpu_reset(rdev)) {
3422 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3423 RREG32(R_000E40_RBBM_STATUS),
3424 RREG32(R_0007C0_CP_STAT));
3425 }
3426 /* post */
3427 radeon_combios_asic_init(rdev->ddev);
3428 /* Resume clock after posting */
3429 r100_clock_startup(rdev);
550e2d92
DA		 3430 /* Initialize surface registers */
3431 radeon_surface_init(rdev);
d4550907
JG		 3432 return r100_startup(rdev);
3433}
3434
3435int r100_suspend(struct radeon_device *rdev)
3436{
3437 r100_cp_disable(rdev);
3438 r100_wb_disable(rdev);
3439 r100_irq_disable(rdev);
3440 if (rdev->flags & RADEON_IS_PCI)
3441 r100_pci_gart_disable(rdev);
3442 return 0;
3443}
3444
3445void r100_fini(struct radeon_device *rdev)
3446{
d4550907
JG		 3447 r100_cp_fini(rdev);
3448 r100_wb_fini(rdev);
3449 r100_ib_fini(rdev);
3450 radeon_gem_fini(rdev);
3451 if (rdev->flags & RADEON_IS_PCI)
3452 r100_pci_gart_fini(rdev);
d0269ed8 3453 radeon_agp_fini(rdev);
d4550907
JG		 3454 radeon_irq_kms_fini(rdev);
3455 radeon_fence_driver_fini(rdev);
4c788679 3456 radeon_bo_fini(rdev);
d4550907
JG		 3457 radeon_atombios_fini(rdev);
3458 kfree(rdev->bios);
3459 rdev->bios = NULL;
3460}
3461
3462int r100_mc_init(struct radeon_device *rdev)
3463{
3464 int r;
3465 u32 tmp;
3466
3467 /* Setup GPU memory space */
3468 rdev->mc.vram_location = 0xFFFFFFFFUL;
3469 rdev->mc.gtt_location = 0xFFFFFFFFUL;
3470 if (rdev->flags & RADEON_IS_IGP) {
3471 tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
3472 rdev->mc.vram_location = tmp << 16;
3473 }
3474 if (rdev->flags & RADEON_IS_AGP) {
3475 r = radeon_agp_init(rdev);
3476 if (r) {
700a0cc0 3477 radeon_agp_disable(rdev);
d4550907
JG		 3478 } else {
3479 rdev->mc.gtt_location = rdev->mc.agp_base;
3480 }
3481 }
3482 r = radeon_mc_setup(rdev);
3483 if (r)
3484 return r;
3485 return 0;
3486}
3487
3488int r100_init(struct radeon_device *rdev)
3489{
3490 int r;
3491
d4550907
JG		 3492 /* Register debugfs file specific to this group of asics */
3493 r100_debugfs(rdev);
3494 /* Disable VGA */
3495 r100_vga_render_disable(rdev);
3496 /* Initialize scratch registers */
3497 radeon_scratch_init(rdev);
3498 /* Initialize surface registers */
3499 radeon_surface_init(rdev);
3500 /* TODO: disable VGA need to use VGA request */
3501 /* BIOS*/
3502 if (!radeon_get_bios(rdev)) {
3503 if (ASIC_IS_AVIVO(rdev))
3504 return -EINVAL;
3505 }
3506 if (rdev->is_atom_bios) {
3507 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3508 return -EINVAL;
3509 } else {
3510 r = radeon_combios_init(rdev);
3511 if (r)
3512 return r;
3513 }
3514 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3515 if (radeon_gpu_reset(rdev)) {
3516 dev_warn(rdev->dev,
3517 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3518 RREG32(R_000E40_RBBM_STATUS),
3519 RREG32(R_0007C0_CP_STAT));
3520 }
3521 /* check if cards are posted or not */
72542d77
DA		 3522 if (radeon_boot_test_post_card(rdev) == false)
3523 return -EINVAL;
d4550907
JG		 3524 /* Set asic errata */
3525 r100_errata(rdev);
3526 /* Initialize clocks */
3527 radeon_get_clock_info(rdev->ddev);
6234077d
RM		 3528 /* Initialize power management */
3529 radeon_pm_init(rdev);
d4550907
JG		 3530 /* Get vram informations */
3531 r100_vram_info(rdev);
3532 /* Initialize memory controller (also test AGP) */
3533 r = r100_mc_init(rdev);
3534 if (r)
3535 return r;
3536 /* Fence driver */
3537 r = radeon_fence_driver_init(rdev);
3538 if (r)
3539 return r;
3540 r = radeon_irq_kms_init(rdev);
3541 if (r)
3542 return r;
3543 /* Memory manager */
4c788679 3544 r = radeon_bo_init(rdev);
d4550907
JG		 3545 if (r)
3546 return r;
3547 if (rdev->flags & RADEON_IS_PCI) {
3548 r = r100_pci_gart_init(rdev);
3549 if (r)
3550 return r;
3551 }
3552 r100_set_safe_registers(rdev);
3553 rdev->accel_working = true;
3554 r = r100_startup(rdev);
3555 if (r) {
3556 /* Somethings want wront with the accel init stop accel */
3557 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907
JG		 3558 r100_cp_fini(rdev);
3559 r100_wb_fini(rdev);
3560 r100_ib_fini(rdev);
655efd3d 3561 radeon_irq_kms_fini(rdev);
d4550907
JG		 3562 if (rdev->flags & RADEON_IS_PCI)
3563 r100_pci_gart_fini(rdev);
d4550907
JG		 3564 rdev->accel_working = false;
3565 }
3566 return 0;
3567}
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