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drm/radeon/kms/atom: fix crtc lock ordering
[net-next-2.6.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include "radeon_fixed.h"
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id;
52
53 switch (radeon_crtc->rmx_type) {
54 case RMX_CENTER:
55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
60 break;
61 case RMX_ASPECT:
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
64
65 if (a1 > a2) {
66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
68 } else if (a2 > a1) {
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
71 }
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
73 break;
74 case RMX_FULL:
75 default:
76 args.usOverscanRight = 0;
77 args.usOverscanLeft = 0;
78 args.usOverscanBottom = 0;
79 args.usOverscanTop = 0;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 break;
82 }
83}
84
85static void atombios_scaler_setup(struct drm_crtc *crtc)
86{
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 92
c93bb85b
JG		 93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 95 bool is_tv = false, is_cv = false;
96 struct drm_encoder *encoder;
c93bb85b
JG		 97
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
99 return;
100
4ce001ab
DA		 101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
102 /* find tv std */
103 if (encoder->crtc == crtc) {
104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
107 tv_std = tv_dac->tv_std;
108 is_tv = true;
109 }
110 }
111 }
112
c93bb85b
JG		 113 memset(&args, 0, sizeof(args));
114
115 args.ucScaler = radeon_crtc->crtc_id;
116
4ce001ab 117 if (is_tv) {
c93bb85b
JG		 118 switch (tv_std) {
119 case TV_STD_NTSC:
120 default:
121 args.ucTVStandard = ATOM_TV_NTSC;
122 break;
123 case TV_STD_PAL:
124 args.ucTVStandard = ATOM_TV_PAL;
125 break;
126 case TV_STD_PAL_M:
127 args.ucTVStandard = ATOM_TV_PALM;
128 break;
129 case TV_STD_PAL_60:
130 args.ucTVStandard = ATOM_TV_PAL60;
131 break;
132 case TV_STD_NTSC_J:
133 args.ucTVStandard = ATOM_TV_NTSCJ;
134 break;
135 case TV_STD_SCART_PAL:
136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
137 break;
138 case TV_STD_SECAM:
139 args.ucTVStandard = ATOM_TV_SECAM;
140 break;
141 case TV_STD_PAL_CN:
142 args.ucTVStandard = ATOM_TV_PALCN;
143 break;
144 }
145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 146 } else if (is_cv) {
c93bb85b
JG		 147 args.ucTVStandard = ATOM_TV_CV;
148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
149 } else {
150 switch (radeon_crtc->rmx_type) {
151 case RMX_FULL:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 case RMX_CENTER:
155 args.ucEnable = ATOM_SCALER_CENTER;
156 break;
157 case RMX_ASPECT:
158 args.ucEnable = ATOM_SCALER_EXPANSION;
159 break;
160 default:
161 if (ASIC_IS_AVIVO(rdev))
162 args.ucEnable = ATOM_SCALER_DISABLE;
163 else
164 args.ucEnable = ATOM_SCALER_CENTER;
165 break;
166 }
167 }
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 169 if ((is_tv || is_cv)
170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
171 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 172 }
173}
174
771fe6b9
JG		 175static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
176{
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
180 int index =
181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
182 ENABLE_CRTC_PS_ALLOCATION args;
183
184 memset(&args, 0, sizeof(args));
185
186 args.ucCRTC = radeon_crtc->crtc_id;
187 args.ucEnable = lock;
188
189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
190}
191
192static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
193{
194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
198 ENABLE_CRTC_PS_ALLOCATION args;
199
200 memset(&args, 0, sizeof(args));
201
202 args.ucCRTC = radeon_crtc->crtc_id;
203 args.ucEnable = state;
204
205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
206}
207
208static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
209{
210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
211 struct drm_device *dev = crtc->dev;
212 struct radeon_device *rdev = dev->dev_private;
213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
214 ENABLE_CRTC_PS_ALLOCATION args;
215
216 memset(&args, 0, sizeof(args));
217
218 args.ucCRTC = radeon_crtc->crtc_id;
219 args.ucEnable = state;
220
221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
222}
223
224static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
225{
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct drm_device *dev = crtc->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
230 BLANK_CRTC_PS_ALLOCATION args;
231
232 memset(&args, 0, sizeof(args));
233
234 args.ucCRTC = radeon_crtc->crtc_id;
235 args.ucBlanking = state;
236
237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
238}
239
240void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
241{
242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private;
500b7587 244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 245
246 switch (mode) {
247 case DRM_MODE_DPMS_ON:
5f9a0eb5 248 atombios_enable_crtc(crtc, 1);
771fe6b9
JG		 249 if (ASIC_IS_DCE3(rdev))
250 atombios_enable_crtc_memreq(crtc, 1);
771fe6b9 251 atombios_blank_crtc(crtc, 0);
500b7587
AD		 252 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
253 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 254 break;
255 case DRM_MODE_DPMS_STANDBY:
256 case DRM_MODE_DPMS_SUSPEND:
257 case DRM_MODE_DPMS_OFF:
500b7587 258 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
771fe6b9 259 atombios_blank_crtc(crtc, 1);
771fe6b9
JG		 260 if (ASIC_IS_DCE3(rdev))
261 atombios_enable_crtc_memreq(crtc, 0);
5f9a0eb5 262 atombios_enable_crtc(crtc, 0);
771fe6b9
JG		 263 break;
264 }
771fe6b9
JG		 265}
266
267static void
268atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 269 struct drm_display_mode *mode)
771fe6b9 270{
5a9bcacc 271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 272 struct drm_device *dev = crtc->dev;
273 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 276 u16 misc = 0;
771fe6b9 277
5a9bcacc
AD		 278 memset(&args, 0, sizeof(args));
279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
280 args.usH_Blanking_Time =
281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
283 args.usV_Blanking_Time =
284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
285 args.usH_SyncOffset =
286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
287 args.usH_SyncWidth =
288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
289 args.usV_SyncOffset =
290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
291 args.usV_SyncWidth =
292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
293 /*args.ucH_Border = mode->hborder;*/
294 /*args.ucV_Border = mode->vborder;*/
295
296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
297 misc |= ATOM_VSYNC_POLARITY;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 misc |= ATOM_HSYNC_POLARITY;
300 if (mode->flags & DRM_MODE_FLAG_CSYNC)
301 misc |= ATOM_COMPOSITESYNC;
302 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
303 misc |= ATOM_INTERLACE;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 misc |= ATOM_DOUBLE_CLOCK_MODE;
306
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9
JG		 309
310 printk("executing set crtc dtd timing\n");
5a9bcacc 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 312}
313
5a9bcacc
AD		 314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
771fe6b9 316{
5a9bcacc 317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 322 u16 misc = 0;
771fe6b9 323
5a9bcacc
AD		 324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
336 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
337 misc |= ATOM_VSYNC_POLARITY;
338 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
339 misc |= ATOM_HSYNC_POLARITY;
340 if (mode->flags & DRM_MODE_FLAG_CSYNC)
341 misc |= ATOM_COMPOSITESYNC;
342 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
343 misc |= ATOM_INTERLACE;
344 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
345 misc |= ATOM_DOUBLE_CLOCK_MODE;
346
347 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
348 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9
JG		 349
350 printk("executing set crtc timing\n");
5a9bcacc 351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 352}
353
ebbe1cb9
AD		 354static void atombios_set_ss(struct drm_crtc *crtc, int enable)
355{
356 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
357 struct drm_device *dev = crtc->dev;
358 struct radeon_device *rdev = dev->dev_private;
359 struct drm_encoder *encoder = NULL;
360 struct radeon_encoder *radeon_encoder = NULL;
361 struct radeon_encoder_atom_dig *dig = NULL;
362 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
363 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION args;
364 ENABLE_LVDS_SS_PARAMETERS legacy_args;
365 uint16_t percentage = 0;
366 uint8_t type = 0, step = 0, delay = 0, range = 0;
367
368 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
369 if (encoder->crtc == crtc) {
370 radeon_encoder = to_radeon_encoder(encoder);
ebbe1cb9 371 /* only enable spread spectrum on LVDS */
d11aa88b
AD		 372 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
373 dig = radeon_encoder->enc_priv;
374 if (dig && dig->ss) {
375 percentage = dig->ss->percentage;
376 type = dig->ss->type;
377 step = dig->ss->step;
378 delay = dig->ss->delay;
379 range = dig->ss->range;
380 } else if (enable)
381 return;
ebbe1cb9
AD		 382 } else if (enable)
383 return;
384 break;
385 }
386 }
387
388 if (!radeon_encoder)
389 return;
390
391 if (ASIC_IS_AVIVO(rdev)) {
392 memset(&args, 0, sizeof(args));
d11aa88b 393 args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
ebbe1cb9
AD		 394 args.ucSpreadSpectrumType = type;
395 args.ucSpreadSpectrumStep = step;
396 args.ucSpreadSpectrumDelay = delay;
397 args.ucSpreadSpectrumRange = range;
398 args.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
399 args.ucEnable = enable;
400 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
401 } else {
402 memset(&legacy_args, 0, sizeof(legacy_args));
d11aa88b 403 legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
ebbe1cb9
AD		 404 legacy_args.ucSpreadSpectrumType = type;
405 legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
406 legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
407 legacy_args.ucEnable = enable;
408 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&legacy_args);
409 }
410}
411
771fe6b9
JG		 412void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
413{
414 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
415 struct drm_device *dev = crtc->dev;
416 struct radeon_device *rdev = dev->dev_private;
417 struct drm_encoder *encoder = NULL;
418 struct radeon_encoder *radeon_encoder = NULL;
419 uint8_t frev, crev;
2606c886 420 int index;
771fe6b9
JG		 421 SET_PIXEL_CLOCK_PS_ALLOCATION args;
422 PIXEL_CLOCK_PARAMETERS *spc1_ptr;
423 PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
424 PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
2606c886
AD		 425 uint32_t pll_clock = mode->clock;
426 uint32_t adjusted_clock;
771fe6b9
JG		 427 uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
428 struct radeon_pll *pll;
429 int pll_flags = 0;
430
431 memset(&args, 0, sizeof(args));
432
433 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 434 if ((rdev->family == CHIP_RS600) ||
435 (rdev->family == CHIP_RS690) ||
436 (rdev->family == CHIP_RS740))
437 pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
438 RADEON_PLL_PREFER_CLOSEST_LOWER);
439
771fe6b9
JG		 440 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
441 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
442 else
443 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9
JG		 444 } else {
445 pll_flags |= RADEON_PLL_LEGACY;
446
447 if (mode->clock > 200000) /* range limits??? */
448 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
449 else
450 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
451
452 }
453
454 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
455 if (encoder->crtc == crtc) {
456 if (!ASIC_IS_AVIVO(rdev)) {
457 if (encoder->encoder_type !=
458 DRM_MODE_ENCODER_DAC)
459 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
2a008d0c
AD		 460 if (encoder->encoder_type ==
461 DRM_MODE_ENCODER_LVDS)
771fe6b9
JG		 462 pll_flags |= RADEON_PLL_USE_REF_DIV;
463 }
464 radeon_encoder = to_radeon_encoder(encoder);
3ce0a23d 465 break;
771fe6b9
JG		 466 }
467 }
468
2606c886
AD		 469 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
470 * accordingly based on the encoder/transmitter to work around
471 * special hw requirements.
472 */
473 if (ASIC_IS_DCE3(rdev)) {
474 ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args;
475
476 if (!encoder)
477 return;
478
479 memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
480 adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
481 adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
482 adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
483
484 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
485 atom_execute_table(rdev->mode_info.atom_context,
486 index, (uint32_t *)&adjust_pll_args);
487 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
d56ef9c8
AD		 488 } else {
489 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
490 if (ASIC_IS_AVIVO(rdev) &&
491 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
492 adjusted_clock = mode->clock * 2;
493 else
494 adjusted_clock = mode->clock;
495 }
2606c886 496
771fe6b9
JG		 497 if (radeon_crtc->crtc_id == 0)
498 pll = &rdev->clock.p1pll;
499 else
500 pll = &rdev->clock.p2pll;
501
b27b6375
AD		 502 if (ASIC_IS_AVIVO(rdev)) {
503 if (radeon_new_pll)
504 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock,
505 &fb_div, &frac_fb_div,
506 &ref_div, &post_div, pll_flags);
507 else
508 radeon_compute_pll(pll, adjusted_clock, &pll_clock,
509 &fb_div, &frac_fb_div,
510 &ref_div, &post_div, pll_flags);
511 } else
512 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
513 &ref_div, &post_div, pll_flags);
771fe6b9 514
39deb2d6 515 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
771fe6b9
JG		 516 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
517 &crev);
518
519 switch (frev) {
520 case 1:
521 switch (crev) {
522 case 1:
523 spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
2606c886 524 spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
771fe6b9
JG		 525 spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
526 spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
527 spc1_ptr->ucFracFbDiv = frac_fb_div;
528 spc1_ptr->ucPostDiv = post_div;
529 spc1_ptr->ucPpll =
530 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
531 spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
532 spc1_ptr->ucRefDivSrc = 1;
533 break;
534 case 2:
535 spc2_ptr =
536 (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
2606c886 537 spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
771fe6b9
JG		 538 spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
539 spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
540 spc2_ptr->ucFracFbDiv = frac_fb_div;
541 spc2_ptr->ucPostDiv = post_div;
542 spc2_ptr->ucPpll =
543 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
544 spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
545 spc2_ptr->ucRefDivSrc = 1;
546 break;
547 case 3:
548 if (!encoder)
549 return;
550 spc3_ptr =
551 (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
2606c886 552 spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
771fe6b9
JG		 553 spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
554 spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
555 spc3_ptr->ucFracFbDiv = frac_fb_div;
556 spc3_ptr->ucPostDiv = post_div;
557 spc3_ptr->ucPpll =
558 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
559 spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
560 spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
561 spc3_ptr->ucEncoderMode =
562 atombios_get_encoder_mode(encoder);
563 break;
564 default:
565 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
566 return;
567 }
568 break;
569 default:
570 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
571 return;
572 }
573
574 printk("executing set pll\n");
575 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
576}
577
54f088a9
AD		 578static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
579 struct drm_framebuffer *old_fb)
771fe6b9
JG		 580{
581 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
582 struct drm_device *dev = crtc->dev;
583 struct radeon_device *rdev = dev->dev_private;
584 struct radeon_framebuffer *radeon_fb;
585 struct drm_gem_object *obj;
4c788679 586 struct radeon_bo *rbo;
771fe6b9 587 uint64_t fb_location;
e024e110 588 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 589 int r;
771fe6b9 590
2de3b484
JG		 591 /* no fb bound */
592 if (!crtc->fb) {
593 DRM_DEBUG("No FB bound\n");
594 return 0;
595 }
771fe6b9
JG		 596
597 radeon_fb = to_radeon_framebuffer(crtc->fb);
598
4c788679 599 /* Pin framebuffer & get tilling informations */
771fe6b9 600 obj = radeon_fb->obj;
4c788679
JG		 601 rbo = obj->driver_private;
602 r = radeon_bo_reserve(rbo, false);
603 if (unlikely(r != 0))
604 return r;
605 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
606 if (unlikely(r != 0)) {
607 radeon_bo_unreserve(rbo);
771fe6b9
JG		 608 return -EINVAL;
609 }
4c788679
JG		 610 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
611 radeon_bo_unreserve(rbo);
771fe6b9
JG		 612
613 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 614 case 8:
615 fb_format =
616 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
617 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
618 break;
771fe6b9
JG		 619 case 15:
620 fb_format =
621 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
622 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
623 break;
624 case 16:
625 fb_format =
626 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
627 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
628 break;
629 case 24:
630 case 32:
631 fb_format =
632 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
633 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
634 break;
635 default:
636 DRM_ERROR("Unsupported screen depth %d\n",
637 crtc->fb->bits_per_pixel);
638 return -EINVAL;
639 }
640
cf2f05d3
DA		 641 if (tiling_flags & RADEON_TILING_MACRO)
642 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
643
e024e110
DA		 644 if (tiling_flags & RADEON_TILING_MICRO)
645 fb_format |= AVIVO_D1GRPH_TILED;
646
771fe6b9
JG		 647 if (radeon_crtc->crtc_id == 0)
648 WREG32(AVIVO_D1VGA_CONTROL, 0);
649 else
650 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 651
652 if (rdev->family >= CHIP_RV770) {
653 if (radeon_crtc->crtc_id) {
654 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
655 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
656 } else {
657 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
658 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
659 }
660 }
771fe6b9
JG		 661 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
662 (u32) fb_location);
663 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
664 radeon_crtc->crtc_offset, (u32) fb_location);
665 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
666
667 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
668 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
669 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
670 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
671 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
672 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
673
674 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
675 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
676 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
677
678 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
679 crtc->mode.vdisplay);
680 x &= ~3;
681 y &= ~1;
682 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
683 (x << 16) | y);
684 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
685 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
686
687 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
688 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
689 AVIVO_D1MODE_INTERLEAVE_EN);
690 else
691 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
692
693 if (old_fb && old_fb != crtc->fb) {
694 radeon_fb = to_radeon_framebuffer(old_fb);
4c788679
JG		 695 rbo = radeon_fb->obj->driver_private;
696 r = radeon_bo_reserve(rbo, false);
697 if (unlikely(r != 0))
698 return r;
699 radeon_bo_unpin(rbo);
700 radeon_bo_unreserve(rbo);
771fe6b9 701 }
f30f37de
MD		 702
703 /* Bytes per pixel may have changed */
704 radeon_bandwidth_update(rdev);
705
771fe6b9
JG		 706 return 0;
707}
708
54f088a9
AD		 709int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
710 struct drm_framebuffer *old_fb)
711{
712 struct drm_device *dev = crtc->dev;
713 struct radeon_device *rdev = dev->dev_private;
714
715 if (ASIC_IS_AVIVO(rdev))
716 return avivo_crtc_set_base(crtc, x, y, old_fb);
717 else
718 return radeon_crtc_set_base(crtc, x, y, old_fb);
719}
720
615e0cb6
AD		 721/* properly set additional regs when using atombios */
722static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
723{
724 struct drm_device *dev = crtc->dev;
725 struct radeon_device *rdev = dev->dev_private;
726 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
727 u32 disp_merge_cntl;
728
729 switch (radeon_crtc->crtc_id) {
730 case 0:
731 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
732 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
733 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
734 break;
735 case 1:
736 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
737 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
738 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
739 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
740 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
741 break;
742 }
743}
744
771fe6b9
JG		 745int atombios_crtc_mode_set(struct drm_crtc *crtc,
746 struct drm_display_mode *mode,
747 struct drm_display_mode *adjusted_mode,
748 int x, int y, struct drm_framebuffer *old_fb)
749{
750 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
751 struct drm_device *dev = crtc->dev;
752 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 753
754 /* TODO color tiling */
771fe6b9 755
ebbe1cb9 756 atombios_set_ss(crtc, 0);
771fe6b9 757 atombios_crtc_set_pll(crtc, adjusted_mode);
ebbe1cb9 758 atombios_set_ss(crtc, 1);
5a9bcacc 759 atombios_crtc_set_timing(crtc, adjusted_mode);
771fe6b9
JG		 760
761 if (ASIC_IS_AVIVO(rdev))
762 atombios_crtc_set_base(crtc, x, y, old_fb);
763 else {
5a9bcacc
AD		 764 if (radeon_crtc->crtc_id == 0)
765 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54f088a9 766 atombios_crtc_set_base(crtc, x, y, old_fb);
615e0cb6 767 radeon_legacy_atom_fixup(crtc);
771fe6b9 768 }
c93bb85b
JG		 769 atombios_overscan_setup(crtc, mode, adjusted_mode);
770 atombios_scaler_setup(crtc);
771fe6b9
JG		 771 return 0;
772}
773
774static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
775 struct drm_display_mode *mode,
776 struct drm_display_mode *adjusted_mode)
777{
c93bb85b
JG		 778 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
779 return false;
771fe6b9
JG		 780 return true;
781}
782
783static void atombios_crtc_prepare(struct drm_crtc *crtc)
784{
771fe6b9 785 atombios_lock_crtc(crtc, 1);
a348c84d 786 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 787}
788
789static void atombios_crtc_commit(struct drm_crtc *crtc)
790{
791 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
792 atombios_lock_crtc(crtc, 0);
793}
794
795static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
796 .dpms = atombios_crtc_dpms,
797 .mode_fixup = atombios_crtc_mode_fixup,
798 .mode_set = atombios_crtc_mode_set,
799 .mode_set_base = atombios_crtc_set_base,
800 .prepare = atombios_crtc_prepare,
801 .commit = atombios_crtc_commit,
068143d3 802 .load_lut = radeon_crtc_load_lut,
771fe6b9
JG		 803};
804
805void radeon_atombios_init_crtc(struct drm_device *dev,
806 struct radeon_crtc *radeon_crtc)
807{
808 if (radeon_crtc->crtc_id == 1)
809 radeon_crtc->crtc_offset =
810 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
811 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
812}
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