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drm/radeon/kms: use lcd pll limits when available
[net-next-2.6.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include "radeon_fixed.h"
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id;
52
53 switch (radeon_crtc->rmx_type) {
54 case RMX_CENTER:
55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
60 break;
61 case RMX_ASPECT:
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
64
65 if (a1 > a2) {
66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
68 } else if (a2 > a1) {
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
71 }
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
73 break;
74 case RMX_FULL:
75 default:
76 args.usOverscanRight = 0;
77 args.usOverscanLeft = 0;
78 args.usOverscanBottom = 0;
79 args.usOverscanTop = 0;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 break;
82 }
83}
84
85static void atombios_scaler_setup(struct drm_crtc *crtc)
86{
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 92
c93bb85b
JG		 93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 95 bool is_tv = false, is_cv = false;
96 struct drm_encoder *encoder;
c93bb85b
JG		 97
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
99 return;
100
4ce001ab
DA		 101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
102 /* find tv std */
103 if (encoder->crtc == crtc) {
104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
107 tv_std = tv_dac->tv_std;
108 is_tv = true;
109 }
110 }
111 }
112
c93bb85b
JG		 113 memset(&args, 0, sizeof(args));
114
115 args.ucScaler = radeon_crtc->crtc_id;
116
4ce001ab 117 if (is_tv) {
c93bb85b
JG		 118 switch (tv_std) {
119 case TV_STD_NTSC:
120 default:
121 args.ucTVStandard = ATOM_TV_NTSC;
122 break;
123 case TV_STD_PAL:
124 args.ucTVStandard = ATOM_TV_PAL;
125 break;
126 case TV_STD_PAL_M:
127 args.ucTVStandard = ATOM_TV_PALM;
128 break;
129 case TV_STD_PAL_60:
130 args.ucTVStandard = ATOM_TV_PAL60;
131 break;
132 case TV_STD_NTSC_J:
133 args.ucTVStandard = ATOM_TV_NTSCJ;
134 break;
135 case TV_STD_SCART_PAL:
136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
137 break;
138 case TV_STD_SECAM:
139 args.ucTVStandard = ATOM_TV_SECAM;
140 break;
141 case TV_STD_PAL_CN:
142 args.ucTVStandard = ATOM_TV_PALCN;
143 break;
144 }
145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 146 } else if (is_cv) {
c93bb85b
JG		 147 args.ucTVStandard = ATOM_TV_CV;
148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
149 } else {
150 switch (radeon_crtc->rmx_type) {
151 case RMX_FULL:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 case RMX_CENTER:
155 args.ucEnable = ATOM_SCALER_CENTER;
156 break;
157 case RMX_ASPECT:
158 args.ucEnable = ATOM_SCALER_EXPANSION;
159 break;
160 default:
161 if (ASIC_IS_AVIVO(rdev))
162 args.ucEnable = ATOM_SCALER_DISABLE;
163 else
164 args.ucEnable = ATOM_SCALER_CENTER;
165 break;
166 }
167 }
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 169 if ((is_tv || is_cv)
170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
171 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 172 }
173}
174
771fe6b9
JG		 175static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
176{
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
180 int index =
181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
182 ENABLE_CRTC_PS_ALLOCATION args;
183
184 memset(&args, 0, sizeof(args));
185
186 args.ucCRTC = radeon_crtc->crtc_id;
187 args.ucEnable = lock;
188
189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
190}
191
192static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
193{
194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
198 ENABLE_CRTC_PS_ALLOCATION args;
199
200 memset(&args, 0, sizeof(args));
201
202 args.ucCRTC = radeon_crtc->crtc_id;
203 args.ucEnable = state;
204
205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
206}
207
208static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
209{
210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
211 struct drm_device *dev = crtc->dev;
212 struct radeon_device *rdev = dev->dev_private;
213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
214 ENABLE_CRTC_PS_ALLOCATION args;
215
216 memset(&args, 0, sizeof(args));
217
218 args.ucCRTC = radeon_crtc->crtc_id;
219 args.ucEnable = state;
220
221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
222}
223
224static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
225{
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct drm_device *dev = crtc->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
230 BLANK_CRTC_PS_ALLOCATION args;
231
232 memset(&args, 0, sizeof(args));
233
234 args.ucCRTC = radeon_crtc->crtc_id;
235 args.ucBlanking = state;
236
237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
238}
239
240void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
241{
242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private;
500b7587 244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 245
246 switch (mode) {
247 case DRM_MODE_DPMS_ON:
37b4390e 248 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 249 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 250 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
251 atombios_blank_crtc(crtc, ATOM_DISABLE);
bcc1c2a1
AD		 252 /* XXX re-enable when interrupt support is added */
253 if (!ASIC_IS_DCE4(rdev))
254 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 255 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 256 break;
257 case DRM_MODE_DPMS_STANDBY:
258 case DRM_MODE_DPMS_SUSPEND:
259 case DRM_MODE_DPMS_OFF:
bcc1c2a1
AD		 260 /* XXX re-enable when interrupt support is added */
261 if (!ASIC_IS_DCE4(rdev))
262 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
37b4390e 263 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 264 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 265 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
266 atombios_enable_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 267 break;
268 }
771fe6b9
JG		 269}
270
271static void
272atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 273 struct drm_display_mode *mode)
771fe6b9 274{
5a9bcacc 275 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 276 struct drm_device *dev = crtc->dev;
277 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 278 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 279 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 280 u16 misc = 0;
771fe6b9 281
5a9bcacc
AD		 282 memset(&args, 0, sizeof(args));
283 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
284 args.usH_Blanking_Time =
285 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
286 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
287 args.usV_Blanking_Time =
288 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
289 args.usH_SyncOffset =
290 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
291 args.usH_SyncWidth =
292 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
293 args.usV_SyncOffset =
294 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
295 args.usV_SyncWidth =
296 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
297 /*args.ucH_Border = mode->hborder;*/
298 /*args.ucV_Border = mode->vborder;*/
299
300 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
301 misc |= ATOM_VSYNC_POLARITY;
302 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
303 misc |= ATOM_HSYNC_POLARITY;
304 if (mode->flags & DRM_MODE_FLAG_CSYNC)
305 misc |= ATOM_COMPOSITESYNC;
306 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
307 misc |= ATOM_INTERLACE;
308 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
309 misc |= ATOM_DOUBLE_CLOCK_MODE;
310
311 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
312 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 313
5a9bcacc 314 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 315}
316
5a9bcacc
AD		 317static void atombios_crtc_set_timing(struct drm_crtc *crtc,
318 struct drm_display_mode *mode)
771fe6b9 319{
5a9bcacc 320 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 321 struct drm_device *dev = crtc->dev;
322 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 323 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 324 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 325 u16 misc = 0;
771fe6b9 326
5a9bcacc
AD		 327 memset(&args, 0, sizeof(args));
328 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
329 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
330 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
331 args.usH_SyncWidth =
332 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
333 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
334 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
335 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
336 args.usV_SyncWidth =
337 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
338
339 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
340 misc |= ATOM_VSYNC_POLARITY;
341 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
342 misc |= ATOM_HSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_CSYNC)
344 misc |= ATOM_COMPOSITESYNC;
345 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
346 misc |= ATOM_INTERLACE;
347 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
348 misc |= ATOM_DOUBLE_CLOCK_MODE;
349
350 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
351 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 352
5a9bcacc 353 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 354}
355
b792210e
AD		 356static void atombios_disable_ss(struct drm_crtc *crtc)
357{
358 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
359 struct drm_device *dev = crtc->dev;
360 struct radeon_device *rdev = dev->dev_private;
361 u32 ss_cntl;
362
363 if (ASIC_IS_DCE4(rdev)) {
364 switch (radeon_crtc->pll_id) {
365 case ATOM_PPLL1:
366 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
367 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
368 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
369 break;
370 case ATOM_PPLL2:
371 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
372 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
373 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
374 break;
375 case ATOM_DCPLL:
376 case ATOM_PPLL_INVALID:
377 return;
378 }
379 } else if (ASIC_IS_AVIVO(rdev)) {
380 switch (radeon_crtc->pll_id) {
381 case ATOM_PPLL1:
382 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
383 ss_cntl &= ~1;
384 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
385 break;
386 case ATOM_PPLL2:
387 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
388 ss_cntl &= ~1;
389 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
390 break;
391 case ATOM_DCPLL:
392 case ATOM_PPLL_INVALID:
393 return;
394 }
395 }
396}
397
398
26b9fc3a
AD		 399union atom_enable_ss {
400 ENABLE_LVDS_SS_PARAMETERS legacy;
401 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
402};
403
b792210e 404static void atombios_enable_ss(struct drm_crtc *crtc)
ebbe1cb9
AD		 405{
406 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
407 struct drm_device *dev = crtc->dev;
408 struct radeon_device *rdev = dev->dev_private;
409 struct drm_encoder *encoder = NULL;
410 struct radeon_encoder *radeon_encoder = NULL;
411 struct radeon_encoder_atom_dig *dig = NULL;
412 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 413 union atom_enable_ss args;
ebbe1cb9
AD		 414 uint16_t percentage = 0;
415 uint8_t type = 0, step = 0, delay = 0, range = 0;
416
bcc1c2a1
AD		 417 /* XXX add ss support for DCE4 */
418 if (ASIC_IS_DCE4(rdev))
419 return;
420
ebbe1cb9
AD		 421 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
422 if (encoder->crtc == crtc) {
423 radeon_encoder = to_radeon_encoder(encoder);
ebbe1cb9 424 /* only enable spread spectrum on LVDS */
d11aa88b
AD		 425 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
426 dig = radeon_encoder->enc_priv;
427 if (dig && dig->ss) {
428 percentage = dig->ss->percentage;
429 type = dig->ss->type;
430 step = dig->ss->step;
431 delay = dig->ss->delay;
432 range = dig->ss->range;
b792210e 433 } else
d11aa88b 434 return;
b792210e 435 } else
ebbe1cb9
AD		 436 return;
437 break;
438 }
439 }
440
441 if (!radeon_encoder)
442 return;
443
26b9fc3a 444 memset(&args, 0, sizeof(args));
ebbe1cb9 445 if (ASIC_IS_AVIVO(rdev)) {
26b9fc3a
AD		 446 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
447 args.v1.ucSpreadSpectrumType = type;
448 args.v1.ucSpreadSpectrumStep = step;
449 args.v1.ucSpreadSpectrumDelay = delay;
450 args.v1.ucSpreadSpectrumRange = range;
451 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
b792210e 452 args.v1.ucEnable = ATOM_ENABLE;
ebbe1cb9 453 } else {
26b9fc3a
AD		 454 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
455 args.legacy.ucSpreadSpectrumType = type;
456 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
457 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
b792210e 458 args.legacy.ucEnable = ATOM_ENABLE;
ebbe1cb9 459 }
26b9fc3a 460 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 461}
462
4eaeca33
AD		 463union adjust_pixel_clock {
464 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 465 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 466};
467
468static u32 atombios_adjust_pll(struct drm_crtc *crtc,
469 struct drm_display_mode *mode,
470 struct radeon_pll *pll)
771fe6b9 471{
771fe6b9
JG		 472 struct drm_device *dev = crtc->dev;
473 struct radeon_device *rdev = dev->dev_private;
474 struct drm_encoder *encoder = NULL;
475 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 476 u32 adjusted_clock = mode->clock;
bcc1c2a1 477 int encoder_mode = 0;
fc10332b 478
4eaeca33
AD		 479 /* reset the pll flags */
480 pll->flags = 0;
771fe6b9 481
7c27f87d
AD		 482 /* select the PLL algo */
483 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 484 if (radeon_new_pll == 0)
485 pll->algo = PLL_ALGO_LEGACY;
486 else
487 pll->algo = PLL_ALGO_NEW;
488 } else {
489 if (radeon_new_pll == 1)
490 pll->algo = PLL_ALGO_NEW;
7c27f87d
AD		 491 else
492 pll->algo = PLL_ALGO_LEGACY;
383be5d1 493 }
7c27f87d 494
771fe6b9 495 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 496 if ((rdev->family == CHIP_RS600) ||
497 (rdev->family == CHIP_RS690) ||
498 (rdev->family == CHIP_RS740))
fc10332b
AD		 499 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
500 RADEON_PLL_PREFER_CLOSEST_LOWER);
eb1300bc 501
771fe6b9 502 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
fc10332b 503 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 504 else
fc10332b 505 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9 506 } else {
fc10332b 507 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9
JG		 508
509 if (mode->clock > 200000) /* range limits??? */
fc10332b 510 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 511 else
fc10332b 512 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9
JG		 513
514 }
515
516 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
517 if (encoder->crtc == crtc) {
4eaeca33 518 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 519 encoder_mode = atombios_get_encoder_mode(encoder);
4eaeca33
AD		 520 if (ASIC_IS_AVIVO(rdev)) {
521 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
522 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
523 adjusted_clock = mode->clock * 2;
7c27f87d
AD		 524 /* LVDS PLL quirks */
525 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
526 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
527 pll->algo = dig->pll_algo;
86cb2bbf 528 pll->flags |= RADEON_PLL_IS_LCD;
7c27f87d 529 }
4eaeca33
AD		 530 } else {
531 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 532 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 533 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 534 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 535 }
3ce0a23d 536 break;
771fe6b9
JG		 537 }
538 }
539
2606c886
AD		 540 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
541 * accordingly based on the encoder/transmitter to work around
542 * special hw requirements.
543 */
544 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 545 union adjust_pixel_clock args;
4eaeca33
AD		 546 u8 frev, crev;
547 int index;
2606c886 548
2606c886 549 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
4eaeca33
AD		 550 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
551 &crev);
552
553 memset(&args, 0, sizeof(args));
554
555 switch (frev) {
556 case 1:
557 switch (crev) {
558 case 1:
559 case 2:
560 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
561 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 562 args.v1.ucEncodeMode = encoder_mode;
4eaeca33
AD		 563
564 atom_execute_table(rdev->mode_info.atom_context,
565 index, (uint32_t *)&args);
566 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
567 break;
bcc1c2a1
AD		 568 case 3:
569 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
570 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
571 args.v3.sInput.ucEncodeMode = encoder_mode;
572 args.v3.sInput.ucDispPllConfig = 0;
573 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
574 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
575
576 if (encoder_mode == ATOM_ENCODER_MODE_DP)
577 args.v3.sInput.ucDispPllConfig |=
578 DISPPLL_CONFIG_COHERENT_MODE;
579 else {
580 if (dig->coherent_mode)
581 args.v3.sInput.ucDispPllConfig |=
582 DISPPLL_CONFIG_COHERENT_MODE;
583 if (mode->clock > 165000)
584 args.v3.sInput.ucDispPllConfig |=
585 DISPPLL_CONFIG_DUAL_LINK;
586 }
587 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
588 /* may want to enable SS on DP/eDP eventually */
589 args.v3.sInput.ucDispPllConfig |=
590 DISPPLL_CONFIG_SS_ENABLE;
591 if (mode->clock > 165000)
592 args.v3.sInput.ucDispPllConfig |=
593 DISPPLL_CONFIG_DUAL_LINK;
594 }
595 atom_execute_table(rdev->mode_info.atom_context,
596 index, (uint32_t *)&args);
597 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
598 if (args.v3.sOutput.ucRefDiv) {
599 pll->flags |= RADEON_PLL_USE_REF_DIV;
600 pll->reference_div = args.v3.sOutput.ucRefDiv;
601 }
602 if (args.v3.sOutput.ucPostDiv) {
603 pll->flags |= RADEON_PLL_USE_POST_DIV;
604 pll->post_div = args.v3.sOutput.ucPostDiv;
605 }
606 break;
4eaeca33
AD		 607 default:
608 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
609 return adjusted_clock;
610 }
611 break;
612 default:
613 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
614 return adjusted_clock;
615 }
d56ef9c8 616 }
4eaeca33
AD		 617 return adjusted_clock;
618}
619
620union set_pixel_clock {
621 SET_PIXEL_CLOCK_PS_ALLOCATION base;
622 PIXEL_CLOCK_PARAMETERS v1;
623 PIXEL_CLOCK_PARAMETERS_V2 v2;
624 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 625 PIXEL_CLOCK_PARAMETERS_V5 v5;
4eaeca33
AD		 626};
627
bcc1c2a1
AD		 628static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
629{
630 struct drm_device *dev = crtc->dev;
631 struct radeon_device *rdev = dev->dev_private;
632 u8 frev, crev;
633 int index;
634 union set_pixel_clock args;
635
636 memset(&args, 0, sizeof(args));
637
638 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
639 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
640 &crev);
641
642 switch (frev) {
643 case 1:
644 switch (crev) {
645 case 5:
646 /* if the default dcpll clock is specified,
647 * SetPixelClock provides the dividers
648 */
649 args.v5.ucCRTC = ATOM_CRTC_INVALID;
650 args.v5.usPixelClock = rdev->clock.default_dispclk;
651 args.v5.ucPpll = ATOM_DCPLL;
652 break;
653 default:
654 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
655 return;
656 }
657 break;
658 default:
659 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
660 return;
661 }
662 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
663}
664
665static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
4eaeca33
AD		 666{
667 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
668 struct drm_device *dev = crtc->dev;
669 struct radeon_device *rdev = dev->dev_private;
670 struct drm_encoder *encoder = NULL;
671 struct radeon_encoder *radeon_encoder = NULL;
672 u8 frev, crev;
673 int index;
674 union set_pixel_clock args;
675 u32 pll_clock = mode->clock;
676 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
677 struct radeon_pll *pll;
678 u32 adjusted_clock;
bcc1c2a1 679 int encoder_mode = 0;
4eaeca33
AD		 680
681 memset(&args, 0, sizeof(args));
682
683 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
684 if (encoder->crtc == crtc) {
685 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 686 encoder_mode = atombios_get_encoder_mode(encoder);
4eaeca33
AD		 687 break;
688 }
689 }
690
691 if (!radeon_encoder)
692 return;
693
bcc1c2a1
AD		 694 switch (radeon_crtc->pll_id) {
695 case ATOM_PPLL1:
4eaeca33 696 pll = &rdev->clock.p1pll;
bcc1c2a1
AD		 697 break;
698 case ATOM_PPLL2:
4eaeca33 699 pll = &rdev->clock.p2pll;
bcc1c2a1
AD		 700 break;
701 case ATOM_DCPLL:
702 case ATOM_PPLL_INVALID:
703 pll = &rdev->clock.dcpll;
704 break;
705 }
4eaeca33
AD		 706
707 /* adjust pixel clock as needed */
708 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
2606c886 709
7c27f87d
AD		 710 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
711 &ref_div, &post_div);
771fe6b9 712
39deb2d6 713 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
771fe6b9
JG		 714 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
715 &crev);
716
717 switch (frev) {
718 case 1:
719 switch (crev) {
720 case 1:
4eaeca33
AD		 721 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
722 args.v1.usRefDiv = cpu_to_le16(ref_div);
723 args.v1.usFbDiv = cpu_to_le16(fb_div);
724 args.v1.ucFracFbDiv = frac_fb_div;
725 args.v1.ucPostDiv = post_div;
bcc1c2a1 726 args.v1.ucPpll = radeon_crtc->pll_id;
4eaeca33
AD		 727 args.v1.ucCRTC = radeon_crtc->crtc_id;
728 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 729 break;
730 case 2:
4eaeca33
AD		 731 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
732 args.v2.usRefDiv = cpu_to_le16(ref_div);
733 args.v2.usFbDiv = cpu_to_le16(fb_div);
734 args.v2.ucFracFbDiv = frac_fb_div;
735 args.v2.ucPostDiv = post_div;
bcc1c2a1 736 args.v2.ucPpll = radeon_crtc->pll_id;
4eaeca33
AD		 737 args.v2.ucCRTC = radeon_crtc->crtc_id;
738 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 739 break;
740 case 3:
4eaeca33
AD		 741 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
742 args.v3.usRefDiv = cpu_to_le16(ref_div);
743 args.v3.usFbDiv = cpu_to_le16(fb_div);
744 args.v3.ucFracFbDiv = frac_fb_div;
745 args.v3.ucPostDiv = post_div;
bcc1c2a1
AD		 746 args.v3.ucPpll = radeon_crtc->pll_id;
747 args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
4eaeca33 748 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
bcc1c2a1
AD		 749 args.v3.ucEncoderMode = encoder_mode;
750 break;
751 case 5:
752 args.v5.ucCRTC = radeon_crtc->crtc_id;
753 args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
754 args.v5.ucRefDiv = ref_div;
755 args.v5.usFbDiv = cpu_to_le16(fb_div);
756 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
757 args.v5.ucPostDiv = post_div;
758 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
759 args.v5.ucTransmitterID = radeon_encoder->encoder_id;
760 args.v5.ucEncoderMode = encoder_mode;
761 args.v5.ucPpll = radeon_crtc->pll_id;
771fe6b9
JG		 762 break;
763 default:
764 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
765 return;
766 }
767 break;
768 default:
769 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
770 return;
771 }
772
771fe6b9
JG		 773 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
774}
775
bcc1c2a1
AD		 776static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
777 struct drm_framebuffer *old_fb)
778{
779 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
780 struct drm_device *dev = crtc->dev;
781 struct radeon_device *rdev = dev->dev_private;
782 struct radeon_framebuffer *radeon_fb;
783 struct drm_gem_object *obj;
784 struct radeon_bo *rbo;
785 uint64_t fb_location;
786 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
787 int r;
788
789 /* no fb bound */
790 if (!crtc->fb) {
791 DRM_DEBUG("No FB bound\n");
792 return 0;
793 }
794
795 radeon_fb = to_radeon_framebuffer(crtc->fb);
796
797 /* Pin framebuffer & get tilling informations */
798 obj = radeon_fb->obj;
799 rbo = obj->driver_private;
800 r = radeon_bo_reserve(rbo, false);
801 if (unlikely(r != 0))
802 return r;
803 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
804 if (unlikely(r != 0)) {
805 radeon_bo_unreserve(rbo);
806 return -EINVAL;
807 }
808 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
809 radeon_bo_unreserve(rbo);
810
811 switch (crtc->fb->bits_per_pixel) {
812 case 8:
813 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
814 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
815 break;
816 case 15:
817 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
818 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
819 break;
820 case 16:
821 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
822 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
823 break;
824 case 24:
825 case 32:
826 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
827 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
828 break;
829 default:
830 DRM_ERROR("Unsupported screen depth %d\n",
831 crtc->fb->bits_per_pixel);
832 return -EINVAL;
833 }
834
835 switch (radeon_crtc->crtc_id) {
836 case 0:
837 WREG32(AVIVO_D1VGA_CONTROL, 0);
838 break;
839 case 1:
840 WREG32(AVIVO_D2VGA_CONTROL, 0);
841 break;
842 case 2:
843 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
844 break;
845 case 3:
846 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
847 break;
848 case 4:
849 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
850 break;
851 case 5:
852 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
853 break;
854 default:
855 break;
856 }
857
858 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
859 upper_32_bits(fb_location));
860 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
861 upper_32_bits(fb_location));
862 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
863 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
864 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
865 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
866 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
867
868 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
869 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
870 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
871 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
872 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
873 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
874
875 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
876 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
877 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
878
879 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
880 crtc->mode.vdisplay);
881 x &= ~3;
882 y &= ~1;
883 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
884 (x << 16) | y);
885 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
886 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
887
888 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
889 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
890 EVERGREEN_INTERLEAVE_EN);
891 else
892 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
893
894 if (old_fb && old_fb != crtc->fb) {
895 radeon_fb = to_radeon_framebuffer(old_fb);
896 rbo = radeon_fb->obj->driver_private;
897 r = radeon_bo_reserve(rbo, false);
898 if (unlikely(r != 0))
899 return r;
900 radeon_bo_unpin(rbo);
901 radeon_bo_unreserve(rbo);
902 }
903
904 /* Bytes per pixel may have changed */
905 radeon_bandwidth_update(rdev);
906
907 return 0;
908}
909
54f088a9
AD		 910static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
911 struct drm_framebuffer *old_fb)
771fe6b9
JG		 912{
913 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
914 struct drm_device *dev = crtc->dev;
915 struct radeon_device *rdev = dev->dev_private;
916 struct radeon_framebuffer *radeon_fb;
917 struct drm_gem_object *obj;
4c788679 918 struct radeon_bo *rbo;
771fe6b9 919 uint64_t fb_location;
e024e110 920 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 921 int r;
771fe6b9 922
2de3b484
JG		 923 /* no fb bound */
924 if (!crtc->fb) {
925 DRM_DEBUG("No FB bound\n");
926 return 0;
927 }
771fe6b9
JG		 928
929 radeon_fb = to_radeon_framebuffer(crtc->fb);
930
4c788679 931 /* Pin framebuffer & get tilling informations */
771fe6b9 932 obj = radeon_fb->obj;
4c788679
JG		 933 rbo = obj->driver_private;
934 r = radeon_bo_reserve(rbo, false);
935 if (unlikely(r != 0))
936 return r;
937 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
938 if (unlikely(r != 0)) {
939 radeon_bo_unreserve(rbo);
771fe6b9
JG		 940 return -EINVAL;
941 }
4c788679
JG		 942 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
943 radeon_bo_unreserve(rbo);
771fe6b9
JG		 944
945 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 946 case 8:
947 fb_format =
948 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
949 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
950 break;
771fe6b9
JG		 951 case 15:
952 fb_format =
953 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
954 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
955 break;
956 case 16:
957 fb_format =
958 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
959 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
960 break;
961 case 24:
962 case 32:
963 fb_format =
964 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
965 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
966 break;
967 default:
968 DRM_ERROR("Unsupported screen depth %d\n",
969 crtc->fb->bits_per_pixel);
970 return -EINVAL;
971 }
972
cf2f05d3
DA		 973 if (tiling_flags & RADEON_TILING_MACRO)
974 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
975
e024e110
DA		 976 if (tiling_flags & RADEON_TILING_MICRO)
977 fb_format |= AVIVO_D1GRPH_TILED;
978
771fe6b9
JG		 979 if (radeon_crtc->crtc_id == 0)
980 WREG32(AVIVO_D1VGA_CONTROL, 0);
981 else
982 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 983
984 if (rdev->family >= CHIP_RV770) {
985 if (radeon_crtc->crtc_id) {
986 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
987 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
988 } else {
989 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
990 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
991 }
992 }
771fe6b9
JG		 993 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
994 (u32) fb_location);
995 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
996 radeon_crtc->crtc_offset, (u32) fb_location);
997 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
998
999 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1000 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1001 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1002 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1003 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1004 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1005
1006 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1007 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1008 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1009
1010 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1011 crtc->mode.vdisplay);
1012 x &= ~3;
1013 y &= ~1;
1014 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1015 (x << 16) | y);
1016 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1017 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1018
1019 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1020 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1021 AVIVO_D1MODE_INTERLEAVE_EN);
1022 else
1023 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1024
1025 if (old_fb && old_fb != crtc->fb) {
1026 radeon_fb = to_radeon_framebuffer(old_fb);
4c788679
JG		 1027 rbo = radeon_fb->obj->driver_private;
1028 r = radeon_bo_reserve(rbo, false);
1029 if (unlikely(r != 0))
1030 return r;
1031 radeon_bo_unpin(rbo);
1032 radeon_bo_unreserve(rbo);
771fe6b9 1033 }
f30f37de
MD		 1034
1035 /* Bytes per pixel may have changed */
1036 radeon_bandwidth_update(rdev);
1037
771fe6b9
JG		 1038 return 0;
1039}
1040
54f088a9
AD		 1041int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1042 struct drm_framebuffer *old_fb)
1043{
1044 struct drm_device *dev = crtc->dev;
1045 struct radeon_device *rdev = dev->dev_private;
1046
bcc1c2a1
AD		 1047 if (ASIC_IS_DCE4(rdev))
1048 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1049 else if (ASIC_IS_AVIVO(rdev))
54f088a9
AD		 1050 return avivo_crtc_set_base(crtc, x, y, old_fb);
1051 else
1052 return radeon_crtc_set_base(crtc, x, y, old_fb);
1053}
1054
615e0cb6
AD		 1055/* properly set additional regs when using atombios */
1056static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1057{
1058 struct drm_device *dev = crtc->dev;
1059 struct radeon_device *rdev = dev->dev_private;
1060 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1061 u32 disp_merge_cntl;
1062
1063 switch (radeon_crtc->crtc_id) {
1064 case 0:
1065 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1066 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1067 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1068 break;
1069 case 1:
1070 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1071 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1072 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1073 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1074 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1075 break;
1076 }
1077}
1078
bcc1c2a1
AD		 1079static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1080{
1081 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1082 struct drm_device *dev = crtc->dev;
1083 struct radeon_device *rdev = dev->dev_private;
1084 struct drm_encoder *test_encoder;
1085 struct drm_crtc *test_crtc;
1086 uint32_t pll_in_use = 0;
1087
1088 if (ASIC_IS_DCE4(rdev)) {
1089 /* if crtc is driving DP and we have an ext clock, use that */
1090 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1091 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1092 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1093 if (rdev->clock.dp_extclk)
1094 return ATOM_PPLL_INVALID;
1095 }
1096 }
1097 }
1098
1099 /* otherwise, pick one of the plls */
1100 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1101 struct radeon_crtc *radeon_test_crtc;
1102
1103 if (crtc == test_crtc)
1104 continue;
1105
1106 radeon_test_crtc = to_radeon_crtc(test_crtc);
1107 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1108 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1109 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1110 }
1111 if (!(pll_in_use & 1))
1112 return ATOM_PPLL1;
1113 return ATOM_PPLL2;
1114 } else
1115 return radeon_crtc->crtc_id;
1116
1117}
1118
771fe6b9
JG		 1119int atombios_crtc_mode_set(struct drm_crtc *crtc,
1120 struct drm_display_mode *mode,
1121 struct drm_display_mode *adjusted_mode,
1122 int x, int y, struct drm_framebuffer *old_fb)
1123{
1124 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1125 struct drm_device *dev = crtc->dev;
1126 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1127
1128 /* TODO color tiling */
771fe6b9 1129
bcc1c2a1
AD		 1130 /* pick pll */
1131 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1132
b792210e 1133 atombios_disable_ss(crtc);
bcc1c2a1
AD		 1134 /* always set DCPLL */
1135 if (ASIC_IS_DCE4(rdev))
1136 atombios_crtc_set_dcpll(crtc);
771fe6b9 1137 atombios_crtc_set_pll(crtc, adjusted_mode);
b792210e 1138 atombios_enable_ss(crtc);
771fe6b9 1139
bcc1c2a1
AD		 1140 if (ASIC_IS_DCE4(rdev))
1141 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1142 else if (ASIC_IS_AVIVO(rdev))
1143 atombios_crtc_set_timing(crtc, adjusted_mode);
771fe6b9 1144 else {
bcc1c2a1 1145 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1146 if (radeon_crtc->crtc_id == 0)
1147 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1148 radeon_legacy_atom_fixup(crtc);
771fe6b9 1149 }
bcc1c2a1 1150 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1151 atombios_overscan_setup(crtc, mode, adjusted_mode);
1152 atombios_scaler_setup(crtc);
771fe6b9
JG		 1153 return 0;
1154}
1155
1156static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1157 struct drm_display_mode *mode,
1158 struct drm_display_mode *adjusted_mode)
1159{
c93bb85b
JG		 1160 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1161 return false;
771fe6b9
JG		 1162 return true;
1163}
1164
1165static void atombios_crtc_prepare(struct drm_crtc *crtc)
1166{
37b4390e 1167 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1168 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1169}
1170
1171static void atombios_crtc_commit(struct drm_crtc *crtc)
1172{
1173 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1174 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1175}
1176
1177static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1178 .dpms = atombios_crtc_dpms,
1179 .mode_fixup = atombios_crtc_mode_fixup,
1180 .mode_set = atombios_crtc_mode_set,
1181 .mode_set_base = atombios_crtc_set_base,
1182 .prepare = atombios_crtc_prepare,
1183 .commit = atombios_crtc_commit,
068143d3 1184 .load_lut = radeon_crtc_load_lut,
771fe6b9
JG		 1185};
1186
1187void radeon_atombios_init_crtc(struct drm_device *dev,
1188 struct radeon_crtc *radeon_crtc)
1189{
bcc1c2a1
AD		 1190 struct radeon_device *rdev = dev->dev_private;
1191
1192 if (ASIC_IS_DCE4(rdev)) {
1193 switch (radeon_crtc->crtc_id) {
1194 case 0:
1195 default:
12d7798f 1196 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1197 break;
1198 case 1:
12d7798f 1199 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1200 break;
1201 case 2:
12d7798f 1202 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1203 break;
1204 case 3:
12d7798f 1205 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1206 break;
1207 case 4:
12d7798f 1208 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1209 break;
1210 case 5:
12d7798f 1211 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1212 break;
1213 }
1214 } else {
1215 if (radeon_crtc->crtc_id == 1)
1216 radeon_crtc->crtc_offset =
1217 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1218 else
1219 radeon_crtc->crtc_offset = 0;
1220 }
1221 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1222 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1223}
Clone of davem's net-next-2.6 tree