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drm/radeon/kms/atom: rework crtc modeset
[net-next-2.6.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include "radeon_fixed.h"
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
4ce001ab
DA		 34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
37 int32_t *pixel_clock);
c93bb85b
JG		 38static void atombios_overscan_setup(struct drm_crtc *crtc,
39 struct drm_display_mode *mode,
40 struct drm_display_mode *adjusted_mode)
41{
42 struct drm_device *dev = crtc->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
45 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
46 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
47 int a1, a2;
48
49 memset(&args, 0, sizeof(args));
50
51 args.usOverscanRight = 0;
52 args.usOverscanLeft = 0;
53 args.usOverscanBottom = 0;
54 args.usOverscanTop = 0;
55 args.ucCRTC = radeon_crtc->crtc_id;
56
57 switch (radeon_crtc->rmx_type) {
58 case RMX_CENTER:
59 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
60 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
61 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
62 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
63 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
64 break;
65 case RMX_ASPECT:
66 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
67 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
68
69 if (a1 > a2) {
70 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
71 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
72 } else if (a2 > a1) {
73 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
74 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77 break;
78 case RMX_FULL:
79 default:
80 args.usOverscanRight = 0;
81 args.usOverscanLeft = 0;
82 args.usOverscanBottom = 0;
83 args.usOverscanTop = 0;
84 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
85 break;
86 }
87}
88
89static void atombios_scaler_setup(struct drm_crtc *crtc)
90{
91 struct drm_device *dev = crtc->dev;
92 struct radeon_device *rdev = dev->dev_private;
93 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
94 ENABLE_SCALER_PS_ALLOCATION args;
95 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 96
c93bb85b
JG		 97 /* fixme - fill in enc_priv for atom dac */
98 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 99 bool is_tv = false, is_cv = false;
100 struct drm_encoder *encoder;
c93bb85b
JG		 101
102 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
103 return;
104
4ce001ab
DA		 105 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
106 /* find tv std */
107 if (encoder->crtc == crtc) {
108 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
109 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
110 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
111 tv_std = tv_dac->tv_std;
112 is_tv = true;
113 }
114 }
115 }
116
c93bb85b
JG		 117 memset(&args, 0, sizeof(args));
118
119 args.ucScaler = radeon_crtc->crtc_id;
120
4ce001ab 121 if (is_tv) {
c93bb85b
JG		 122 switch (tv_std) {
123 case TV_STD_NTSC:
124 default:
125 args.ucTVStandard = ATOM_TV_NTSC;
126 break;
127 case TV_STD_PAL:
128 args.ucTVStandard = ATOM_TV_PAL;
129 break;
130 case TV_STD_PAL_M:
131 args.ucTVStandard = ATOM_TV_PALM;
132 break;
133 case TV_STD_PAL_60:
134 args.ucTVStandard = ATOM_TV_PAL60;
135 break;
136 case TV_STD_NTSC_J:
137 args.ucTVStandard = ATOM_TV_NTSCJ;
138 break;
139 case TV_STD_SCART_PAL:
140 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
141 break;
142 case TV_STD_SECAM:
143 args.ucTVStandard = ATOM_TV_SECAM;
144 break;
145 case TV_STD_PAL_CN:
146 args.ucTVStandard = ATOM_TV_PALCN;
147 break;
148 }
149 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 150 } else if (is_cv) {
c93bb85b
JG		 151 args.ucTVStandard = ATOM_TV_CV;
152 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
153 } else {
154 switch (radeon_crtc->rmx_type) {
155 case RMX_FULL:
156 args.ucEnable = ATOM_SCALER_EXPANSION;
157 break;
158 case RMX_CENTER:
159 args.ucEnable = ATOM_SCALER_CENTER;
160 break;
161 case RMX_ASPECT:
162 args.ucEnable = ATOM_SCALER_EXPANSION;
163 break;
164 default:
165 if (ASIC_IS_AVIVO(rdev))
166 args.ucEnable = ATOM_SCALER_DISABLE;
167 else
168 args.ucEnable = ATOM_SCALER_CENTER;
169 break;
170 }
171 }
172 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 173 if ((is_tv || is_cv)
174 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
175 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 176 }
177}
178
771fe6b9
JG		 179static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
180{
181 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
182 struct drm_device *dev = crtc->dev;
183 struct radeon_device *rdev = dev->dev_private;
184 int index =
185 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
186 ENABLE_CRTC_PS_ALLOCATION args;
187
188 memset(&args, 0, sizeof(args));
189
190 args.ucCRTC = radeon_crtc->crtc_id;
191 args.ucEnable = lock;
192
193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
194}
195
196static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
197{
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
202 ENABLE_CRTC_PS_ALLOCATION args;
203
204 memset(&args, 0, sizeof(args));
205
206 args.ucCRTC = radeon_crtc->crtc_id;
207 args.ucEnable = state;
208
209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
210}
211
212static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
213{
214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
215 struct drm_device *dev = crtc->dev;
216 struct radeon_device *rdev = dev->dev_private;
217 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
218 ENABLE_CRTC_PS_ALLOCATION args;
219
220 memset(&args, 0, sizeof(args));
221
222 args.ucCRTC = radeon_crtc->crtc_id;
223 args.ucEnable = state;
224
225 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
226}
227
228static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
229{
230 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
231 struct drm_device *dev = crtc->dev;
232 struct radeon_device *rdev = dev->dev_private;
233 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
234 BLANK_CRTC_PS_ALLOCATION args;
235
236 memset(&args, 0, sizeof(args));
237
238 args.ucCRTC = radeon_crtc->crtc_id;
239 args.ucBlanking = state;
240
241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
242}
243
244void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
245{
246 struct drm_device *dev = crtc->dev;
247 struct radeon_device *rdev = dev->dev_private;
248
249 switch (mode) {
250 case DRM_MODE_DPMS_ON:
5f9a0eb5 251 atombios_enable_crtc(crtc, 1);
771fe6b9
JG		 252 if (ASIC_IS_DCE3(rdev))
253 atombios_enable_crtc_memreq(crtc, 1);
771fe6b9
JG		 254 atombios_blank_crtc(crtc, 0);
255 break;
256 case DRM_MODE_DPMS_STANDBY:
257 case DRM_MODE_DPMS_SUSPEND:
258 case DRM_MODE_DPMS_OFF:
259 atombios_blank_crtc(crtc, 1);
771fe6b9
JG		 260 if (ASIC_IS_DCE3(rdev))
261 atombios_enable_crtc_memreq(crtc, 0);
5f9a0eb5 262 atombios_enable_crtc(crtc, 0);
771fe6b9
JG		 263 break;
264 }
265
266 if (mode != DRM_MODE_DPMS_OFF) {
267 radeon_crtc_load_lut(crtc);
268 }
269}
270
271static void
272atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 273 struct drm_display_mode *mode)
771fe6b9 274{
5a9bcacc 275 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 276 struct drm_device *dev = crtc->dev;
277 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 278 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 279 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 280 u16 misc = 0;
771fe6b9 281
5a9bcacc
AD		 282 memset(&args, 0, sizeof(args));
283 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
284 args.usH_Blanking_Time =
285 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
286 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
287 args.usV_Blanking_Time =
288 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
289 args.usH_SyncOffset =
290 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
291 args.usH_SyncWidth =
292 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
293 args.usV_SyncOffset =
294 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
295 args.usV_SyncWidth =
296 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
297 /*args.ucH_Border = mode->hborder;*/
298 /*args.ucV_Border = mode->vborder;*/
299
300 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
301 misc |= ATOM_VSYNC_POLARITY;
302 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
303 misc |= ATOM_HSYNC_POLARITY;
304 if (mode->flags & DRM_MODE_FLAG_CSYNC)
305 misc |= ATOM_COMPOSITESYNC;
306 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
307 misc |= ATOM_INTERLACE;
308 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
309 misc |= ATOM_DOUBLE_CLOCK_MODE;
310
311 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
312 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9
JG		 313
314 printk("executing set crtc dtd timing\n");
5a9bcacc 315 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 316}
317
5a9bcacc
AD		 318static void atombios_crtc_set_timing(struct drm_crtc *crtc,
319 struct drm_display_mode *mode)
771fe6b9 320{
5a9bcacc 321 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 322 struct drm_device *dev = crtc->dev;
323 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 324 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 325 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 326 u16 misc = 0;
771fe6b9 327
5a9bcacc
AD		 328 memset(&args, 0, sizeof(args));
329 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
330 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
331 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
332 args.usH_SyncWidth =
333 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
334 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
335 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
336 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
337 args.usV_SyncWidth =
338 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
339
340 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
341 misc |= ATOM_VSYNC_POLARITY;
342 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
343 misc |= ATOM_HSYNC_POLARITY;
344 if (mode->flags & DRM_MODE_FLAG_CSYNC)
345 misc |= ATOM_COMPOSITESYNC;
346 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
347 misc |= ATOM_INTERLACE;
348 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
349 misc |= ATOM_DOUBLE_CLOCK_MODE;
350
351 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
352 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9
JG		 353
354 printk("executing set crtc timing\n");
5a9bcacc 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 356}
357
358void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 struct drm_encoder *encoder = NULL;
364 struct radeon_encoder *radeon_encoder = NULL;
365 uint8_t frev, crev;
2606c886 366 int index;
771fe6b9
JG		 367 SET_PIXEL_CLOCK_PS_ALLOCATION args;
368 PIXEL_CLOCK_PARAMETERS *spc1_ptr;
369 PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
370 PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
2606c886
AD		 371 uint32_t pll_clock = mode->clock;
372 uint32_t adjusted_clock;
771fe6b9
JG		 373 uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
374 struct radeon_pll *pll;
375 int pll_flags = 0;
376
377 memset(&args, 0, sizeof(args));
378
379 if (ASIC_IS_AVIVO(rdev)) {
380 uint32_t ss_cntl;
381
eb1300bc
AD		 382 if ((rdev->family == CHIP_RS600) ||
383 (rdev->family == CHIP_RS690) ||
384 (rdev->family == CHIP_RS740))
385 pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
386 RADEON_PLL_PREFER_CLOSEST_LOWER);
387
771fe6b9
JG		 388 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
389 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
390 else
391 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
392
393 /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
394 if (radeon_crtc->crtc_id == 0) {
395 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
396 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
397 } else {
398 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
399 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
400 }
401 } else {
402 pll_flags |= RADEON_PLL_LEGACY;
403
404 if (mode->clock > 200000) /* range limits??? */
405 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
406 else
407 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
408
409 }
410
411 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
412 if (encoder->crtc == crtc) {
413 if (!ASIC_IS_AVIVO(rdev)) {
414 if (encoder->encoder_type !=
415 DRM_MODE_ENCODER_DAC)
416 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
417 if (!ASIC_IS_AVIVO(rdev)
418 && (encoder->encoder_type ==
419 DRM_MODE_ENCODER_LVDS))
420 pll_flags |= RADEON_PLL_USE_REF_DIV;
421 }
422 radeon_encoder = to_radeon_encoder(encoder);
3ce0a23d 423 break;
771fe6b9
JG		 424 }
425 }
426
2606c886
AD		 427 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
428 * accordingly based on the encoder/transmitter to work around
429 * special hw requirements.
430 */
431 if (ASIC_IS_DCE3(rdev)) {
432 ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args;
433
434 if (!encoder)
435 return;
436
437 memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
438 adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
439 adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
440 adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
441
442 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
443 atom_execute_table(rdev->mode_info.atom_context,
444 index, (uint32_t *)&adjust_pll_args);
445 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
446 } else
447 adjusted_clock = mode->clock;
448
771fe6b9
JG		 449 if (radeon_crtc->crtc_id == 0)
450 pll = &rdev->clock.p1pll;
451 else
452 pll = &rdev->clock.p2pll;
453
2606c886 454 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
771fe6b9
JG		 455 &ref_div, &post_div, pll_flags);
456
457 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
458 &crev);
459
460 switch (frev) {
461 case 1:
462 switch (crev) {
463 case 1:
464 spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
2606c886 465 spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
771fe6b9
JG		 466 spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
467 spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
468 spc1_ptr->ucFracFbDiv = frac_fb_div;
469 spc1_ptr->ucPostDiv = post_div;
470 spc1_ptr->ucPpll =
471 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
472 spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
473 spc1_ptr->ucRefDivSrc = 1;
474 break;
475 case 2:
476 spc2_ptr =
477 (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
2606c886 478 spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
771fe6b9
JG		 479 spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
480 spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
481 spc2_ptr->ucFracFbDiv = frac_fb_div;
482 spc2_ptr->ucPostDiv = post_div;
483 spc2_ptr->ucPpll =
484 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
485 spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
486 spc2_ptr->ucRefDivSrc = 1;
487 break;
488 case 3:
489 if (!encoder)
490 return;
491 spc3_ptr =
492 (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
2606c886 493 spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
771fe6b9
JG		 494 spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
495 spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
496 spc3_ptr->ucFracFbDiv = frac_fb_div;
497 spc3_ptr->ucPostDiv = post_div;
498 spc3_ptr->ucPpll =
499 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
500 spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
501 spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
502 spc3_ptr->ucEncoderMode =
503 atombios_get_encoder_mode(encoder);
504 break;
505 default:
506 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
507 return;
508 }
509 break;
510 default:
511 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
512 return;
513 }
514
515 printk("executing set pll\n");
2606c886 516 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
771fe6b9
JG		 517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
518}
519
520int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
521 struct drm_framebuffer *old_fb)
522{
523 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
524 struct drm_device *dev = crtc->dev;
525 struct radeon_device *rdev = dev->dev_private;
526 struct radeon_framebuffer *radeon_fb;
527 struct drm_gem_object *obj;
528 struct drm_radeon_gem_object *obj_priv;
529 uint64_t fb_location;
e024e110 530 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
771fe6b9
JG		 531
532 if (!crtc->fb)
533 return -EINVAL;
534
535 radeon_fb = to_radeon_framebuffer(crtc->fb);
536
537 obj = radeon_fb->obj;
538 obj_priv = obj->driver_private;
539
540 if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) {
541 return -EINVAL;
542 }
543
544 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 545 case 8:
546 fb_format =
547 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
548 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
549 break;
771fe6b9
JG		 550 case 15:
551 fb_format =
552 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
553 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
554 break;
555 case 16:
556 fb_format =
557 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
558 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
559 break;
560 case 24:
561 case 32:
562 fb_format =
563 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
564 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
565 break;
566 default:
567 DRM_ERROR("Unsupported screen depth %d\n",
568 crtc->fb->bits_per_pixel);
569 return -EINVAL;
570 }
571
e024e110
DA		 572 radeon_object_get_tiling_flags(obj->driver_private,
573 &tiling_flags, NULL);
574 if (tiling_flags & RADEON_TILING_MACRO)
575 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
576
577 if (tiling_flags & RADEON_TILING_MICRO)
578 fb_format |= AVIVO_D1GRPH_TILED;
579
771fe6b9
JG		 580 if (radeon_crtc->crtc_id == 0)
581 WREG32(AVIVO_D1VGA_CONTROL, 0);
582 else
583 WREG32(AVIVO_D2VGA_CONTROL, 0);
584 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
585 (u32) fb_location);
586 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
587 radeon_crtc->crtc_offset, (u32) fb_location);
588 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
589
590 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
591 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
592 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
593 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
594 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
595 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
596
597 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
598 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
599 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
600
601 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
602 crtc->mode.vdisplay);
603 x &= ~3;
604 y &= ~1;
605 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
606 (x << 16) | y);
607 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
608 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
609
610 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
611 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
612 AVIVO_D1MODE_INTERLEAVE_EN);
613 else
614 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
615
616 if (old_fb && old_fb != crtc->fb) {
617 radeon_fb = to_radeon_framebuffer(old_fb);
618 radeon_gem_object_unpin(radeon_fb->obj);
619 }
f30f37de
MD		 620
621 /* Bytes per pixel may have changed */
622 radeon_bandwidth_update(rdev);
623
771fe6b9
JG		 624 return 0;
625}
626
627int atombios_crtc_mode_set(struct drm_crtc *crtc,
628 struct drm_display_mode *mode,
629 struct drm_display_mode *adjusted_mode,
630 int x, int y, struct drm_framebuffer *old_fb)
631{
632 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
633 struct drm_device *dev = crtc->dev;
634 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 635
636 /* TODO color tiling */
771fe6b9
JG		 637
638 atombios_crtc_set_pll(crtc, adjusted_mode);
5a9bcacc 639 atombios_crtc_set_timing(crtc, adjusted_mode);
771fe6b9
JG		 640
641 if (ASIC_IS_AVIVO(rdev))
642 atombios_crtc_set_base(crtc, x, y, old_fb);
643 else {
5a9bcacc
AD		 644 if (radeon_crtc->crtc_id == 0)
645 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
771fe6b9
JG		 646 radeon_crtc_set_base(crtc, x, y, old_fb);
647 radeon_legacy_atom_set_surface(crtc);
648 }
c93bb85b
JG		 649 atombios_overscan_setup(crtc, mode, adjusted_mode);
650 atombios_scaler_setup(crtc);
771fe6b9
JG		 651 return 0;
652}
653
654static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
655 struct drm_display_mode *mode,
656 struct drm_display_mode *adjusted_mode)
657{
c93bb85b
JG		 658 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
659 return false;
771fe6b9
JG		 660 return true;
661}
662
663static void atombios_crtc_prepare(struct drm_crtc *crtc)
664{
665 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
666 atombios_lock_crtc(crtc, 1);
667}
668
669static void atombios_crtc_commit(struct drm_crtc *crtc)
670{
671 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
672 atombios_lock_crtc(crtc, 0);
673}
674
675static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
676 .dpms = atombios_crtc_dpms,
677 .mode_fixup = atombios_crtc_mode_fixup,
678 .mode_set = atombios_crtc_mode_set,
679 .mode_set_base = atombios_crtc_set_base,
680 .prepare = atombios_crtc_prepare,
681 .commit = atombios_crtc_commit,
068143d3 682 .load_lut = radeon_crtc_load_lut,
771fe6b9
JG		 683};
684
685void radeon_atombios_init_crtc(struct drm_device *dev,
686 struct radeon_crtc *radeon_crtc)
687{
688 if (radeon_crtc->crtc_id == 1)
689 radeon_crtc->crtc_offset =
690 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
691 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
692}
Clone of davem's net-next-2.6 tree