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[net-next-2.6.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include "radeon_fixed.h"
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id;
52
53 switch (radeon_crtc->rmx_type) {
54 case RMX_CENTER:
55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
60 break;
61 case RMX_ASPECT:
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
64
65 if (a1 > a2) {
66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
68 } else if (a2 > a1) {
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
71 }
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
73 break;
74 case RMX_FULL:
75 default:
76 args.usOverscanRight = 0;
77 args.usOverscanLeft = 0;
78 args.usOverscanBottom = 0;
79 args.usOverscanTop = 0;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 break;
82 }
83}
84
85static void atombios_scaler_setup(struct drm_crtc *crtc)
86{
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 92
c93bb85b
JG		 93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 95 bool is_tv = false, is_cv = false;
96 struct drm_encoder *encoder;
c93bb85b
JG		 97
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
99 return;
100
4ce001ab
DA		 101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
102 /* find tv std */
103 if (encoder->crtc == crtc) {
104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
107 tv_std = tv_dac->tv_std;
108 is_tv = true;
109 }
110 }
111 }
112
c93bb85b
JG		 113 memset(&args, 0, sizeof(args));
114
115 args.ucScaler = radeon_crtc->crtc_id;
116
4ce001ab 117 if (is_tv) {
c93bb85b
JG		 118 switch (tv_std) {
119 case TV_STD_NTSC:
120 default:
121 args.ucTVStandard = ATOM_TV_NTSC;
122 break;
123 case TV_STD_PAL:
124 args.ucTVStandard = ATOM_TV_PAL;
125 break;
126 case TV_STD_PAL_M:
127 args.ucTVStandard = ATOM_TV_PALM;
128 break;
129 case TV_STD_PAL_60:
130 args.ucTVStandard = ATOM_TV_PAL60;
131 break;
132 case TV_STD_NTSC_J:
133 args.ucTVStandard = ATOM_TV_NTSCJ;
134 break;
135 case TV_STD_SCART_PAL:
136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
137 break;
138 case TV_STD_SECAM:
139 args.ucTVStandard = ATOM_TV_SECAM;
140 break;
141 case TV_STD_PAL_CN:
142 args.ucTVStandard = ATOM_TV_PALCN;
143 break;
144 }
145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 146 } else if (is_cv) {
c93bb85b
JG		 147 args.ucTVStandard = ATOM_TV_CV;
148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
149 } else {
150 switch (radeon_crtc->rmx_type) {
151 case RMX_FULL:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 case RMX_CENTER:
155 args.ucEnable = ATOM_SCALER_CENTER;
156 break;
157 case RMX_ASPECT:
158 args.ucEnable = ATOM_SCALER_EXPANSION;
159 break;
160 default:
161 if (ASIC_IS_AVIVO(rdev))
162 args.ucEnable = ATOM_SCALER_DISABLE;
163 else
164 args.ucEnable = ATOM_SCALER_CENTER;
165 break;
166 }
167 }
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 169 if ((is_tv || is_cv)
170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
171 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 172 }
173}
174
771fe6b9
JG		 175static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
176{
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
180 int index =
181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
182 ENABLE_CRTC_PS_ALLOCATION args;
183
184 memset(&args, 0, sizeof(args));
185
186 args.ucCRTC = radeon_crtc->crtc_id;
187 args.ucEnable = lock;
188
189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
190}
191
192static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
193{
194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
198 ENABLE_CRTC_PS_ALLOCATION args;
199
200 memset(&args, 0, sizeof(args));
201
202 args.ucCRTC = radeon_crtc->crtc_id;
203 args.ucEnable = state;
204
205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
206}
207
208static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
209{
210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
211 struct drm_device *dev = crtc->dev;
212 struct radeon_device *rdev = dev->dev_private;
213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
214 ENABLE_CRTC_PS_ALLOCATION args;
215
216 memset(&args, 0, sizeof(args));
217
218 args.ucCRTC = radeon_crtc->crtc_id;
219 args.ucEnable = state;
220
221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
222}
223
224static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
225{
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct drm_device *dev = crtc->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
230 BLANK_CRTC_PS_ALLOCATION args;
231
232 memset(&args, 0, sizeof(args));
233
234 args.ucCRTC = radeon_crtc->crtc_id;
235 args.ucBlanking = state;
236
237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
238}
239
240void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
241{
242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private;
500b7587 244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 245
246 switch (mode) {
247 case DRM_MODE_DPMS_ON:
5f9a0eb5 248 atombios_enable_crtc(crtc, 1);
771fe6b9
JG		 249 if (ASIC_IS_DCE3(rdev))
250 atombios_enable_crtc_memreq(crtc, 1);
771fe6b9 251 atombios_blank_crtc(crtc, 0);
500b7587
AD		 252 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
253 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 254 break;
255 case DRM_MODE_DPMS_STANDBY:
256 case DRM_MODE_DPMS_SUSPEND:
257 case DRM_MODE_DPMS_OFF:
500b7587 258 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
771fe6b9 259 atombios_blank_crtc(crtc, 1);
771fe6b9
JG		 260 if (ASIC_IS_DCE3(rdev))
261 atombios_enable_crtc_memreq(crtc, 0);
5f9a0eb5 262 atombios_enable_crtc(crtc, 0);
771fe6b9
JG		 263 break;
264 }
771fe6b9
JG		 265}
266
267static void
268atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 269 struct drm_display_mode *mode)
771fe6b9 270{
5a9bcacc 271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 272 struct drm_device *dev = crtc->dev;
273 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 276 u16 misc = 0;
771fe6b9 277
5a9bcacc
AD		 278 memset(&args, 0, sizeof(args));
279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
280 args.usH_Blanking_Time =
281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
283 args.usV_Blanking_Time =
284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
285 args.usH_SyncOffset =
286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
287 args.usH_SyncWidth =
288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
289 args.usV_SyncOffset =
290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
291 args.usV_SyncWidth =
292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
293 /*args.ucH_Border = mode->hborder;*/
294 /*args.ucV_Border = mode->vborder;*/
295
296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
297 misc |= ATOM_VSYNC_POLARITY;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 misc |= ATOM_HSYNC_POLARITY;
300 if (mode->flags & DRM_MODE_FLAG_CSYNC)
301 misc |= ATOM_COMPOSITESYNC;
302 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
303 misc |= ATOM_INTERLACE;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 misc |= ATOM_DOUBLE_CLOCK_MODE;
306
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 309
5a9bcacc 310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 311}
312
5a9bcacc
AD		 313static void atombios_crtc_set_timing(struct drm_crtc *crtc,
314 struct drm_display_mode *mode)
771fe6b9 315{
5a9bcacc 316 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 317 struct drm_device *dev = crtc->dev;
318 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 319 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 320 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 321 u16 misc = 0;
771fe6b9 322
5a9bcacc
AD		 323 memset(&args, 0, sizeof(args));
324 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
325 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
326 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
327 args.usH_SyncWidth =
328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
329 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
330 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
331 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
332 args.usV_SyncWidth =
333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
334
335 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
336 misc |= ATOM_VSYNC_POLARITY;
337 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
338 misc |= ATOM_HSYNC_POLARITY;
339 if (mode->flags & DRM_MODE_FLAG_CSYNC)
340 misc |= ATOM_COMPOSITESYNC;
341 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
342 misc |= ATOM_INTERLACE;
343 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
344 misc |= ATOM_DOUBLE_CLOCK_MODE;
345
346 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
347 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 348
5a9bcacc 349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 350}
351
ebbe1cb9
AD		 352static void atombios_set_ss(struct drm_crtc *crtc, int enable)
353{
354 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
355 struct drm_device *dev = crtc->dev;
356 struct radeon_device *rdev = dev->dev_private;
357 struct drm_encoder *encoder = NULL;
358 struct radeon_encoder *radeon_encoder = NULL;
359 struct radeon_encoder_atom_dig *dig = NULL;
360 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
361 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION args;
362 ENABLE_LVDS_SS_PARAMETERS legacy_args;
363 uint16_t percentage = 0;
364 uint8_t type = 0, step = 0, delay = 0, range = 0;
365
366 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
367 if (encoder->crtc == crtc) {
368 radeon_encoder = to_radeon_encoder(encoder);
ebbe1cb9 369 /* only enable spread spectrum on LVDS */
d11aa88b
AD		 370 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
371 dig = radeon_encoder->enc_priv;
372 if (dig && dig->ss) {
373 percentage = dig->ss->percentage;
374 type = dig->ss->type;
375 step = dig->ss->step;
376 delay = dig->ss->delay;
377 range = dig->ss->range;
378 } else if (enable)
379 return;
ebbe1cb9
AD		 380 } else if (enable)
381 return;
382 break;
383 }
384 }
385
386 if (!radeon_encoder)
387 return;
388
389 if (ASIC_IS_AVIVO(rdev)) {
390 memset(&args, 0, sizeof(args));
d11aa88b 391 args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
ebbe1cb9
AD		 392 args.ucSpreadSpectrumType = type;
393 args.ucSpreadSpectrumStep = step;
394 args.ucSpreadSpectrumDelay = delay;
395 args.ucSpreadSpectrumRange = range;
396 args.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
397 args.ucEnable = enable;
398 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
399 } else {
400 memset(&legacy_args, 0, sizeof(legacy_args));
d11aa88b 401 legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
ebbe1cb9
AD		 402 legacy_args.ucSpreadSpectrumType = type;
403 legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
404 legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
405 legacy_args.ucEnable = enable;
406 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&legacy_args);
407 }
408}
409
4eaeca33
AD		 410union adjust_pixel_clock {
411 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
412};
413
414static u32 atombios_adjust_pll(struct drm_crtc *crtc,
415 struct drm_display_mode *mode,
416 struct radeon_pll *pll)
771fe6b9 417{
771fe6b9
JG		 418 struct drm_device *dev = crtc->dev;
419 struct radeon_device *rdev = dev->dev_private;
420 struct drm_encoder *encoder = NULL;
421 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 422 u32 adjusted_clock = mode->clock;
fc10332b 423
4eaeca33
AD		 424 /* reset the pll flags */
425 pll->flags = 0;
771fe6b9 426
7c27f87d
AD		 427 /* select the PLL algo */
428 if (ASIC_IS_AVIVO(rdev)) {
429 if (radeon_new_pll)
430 pll->algo = PLL_ALGO_AVIVO;
431 else
432 pll->algo = PLL_ALGO_LEGACY;
433 } else
434 pll->algo = PLL_ALGO_LEGACY;
435
771fe6b9 436 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 437 if ((rdev->family == CHIP_RS600) ||
438 (rdev->family == CHIP_RS690) ||
439 (rdev->family == CHIP_RS740))
fc10332b
AD		 440 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
441 RADEON_PLL_PREFER_CLOSEST_LOWER);
eb1300bc 442
771fe6b9 443 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
fc10332b 444 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 445 else
fc10332b 446 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9 447 } else {
fc10332b 448 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9
JG		 449
450 if (mode->clock > 200000) /* range limits??? */
fc10332b 451 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 452 else
fc10332b 453 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9
JG		 454
455 }
456
457 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
458 if (encoder->crtc == crtc) {
4eaeca33
AD		 459 radeon_encoder = to_radeon_encoder(encoder);
460 if (ASIC_IS_AVIVO(rdev)) {
461 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
462 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
463 adjusted_clock = mode->clock * 2;
7c27f87d
AD		 464 /* LVDS PLL quirks */
465 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
466 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
467 pll->algo = dig->pll_algo;
468 }
4eaeca33
AD		 469 } else {
470 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 471 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 472 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 473 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 474 }
3ce0a23d 475 break;
771fe6b9
JG		 476 }
477 }
478
2606c886
AD		 479 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
480 * accordingly based on the encoder/transmitter to work around
481 * special hw requirements.
482 */
483 if (ASIC_IS_DCE3(rdev)) {
4eaeca33
AD		 484 union adjust_pixel_clock args;
485 struct radeon_encoder_atom_dig *dig;
486 u8 frev, crev;
487 int index;
2606c886 488
4eaeca33
AD		 489 if (!radeon_encoder->enc_priv)
490 return adjusted_clock;
491 dig = radeon_encoder->enc_priv;
2606c886
AD		 492
493 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
4eaeca33
AD		 494 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
495 &crev);
496
497 memset(&args, 0, sizeof(args));
498
499 switch (frev) {
500 case 1:
501 switch (crev) {
502 case 1:
503 case 2:
504 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
505 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
506 args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder);
507
508 atom_execute_table(rdev->mode_info.atom_context,
509 index, (uint32_t *)&args);
510 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
511 break;
512 default:
513 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
514 return adjusted_clock;
515 }
516 break;
517 default:
518 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
519 return adjusted_clock;
520 }
d56ef9c8 521 }
4eaeca33
AD		 522 return adjusted_clock;
523}
524
525union set_pixel_clock {
526 SET_PIXEL_CLOCK_PS_ALLOCATION base;
527 PIXEL_CLOCK_PARAMETERS v1;
528 PIXEL_CLOCK_PARAMETERS_V2 v2;
529 PIXEL_CLOCK_PARAMETERS_V3 v3;
530};
531
532void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
533{
534 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
535 struct drm_device *dev = crtc->dev;
536 struct radeon_device *rdev = dev->dev_private;
537 struct drm_encoder *encoder = NULL;
538 struct radeon_encoder *radeon_encoder = NULL;
539 u8 frev, crev;
540 int index;
541 union set_pixel_clock args;
542 u32 pll_clock = mode->clock;
543 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
544 struct radeon_pll *pll;
545 u32 adjusted_clock;
546
547 memset(&args, 0, sizeof(args));
548
549 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
550 if (encoder->crtc == crtc) {
551 radeon_encoder = to_radeon_encoder(encoder);
552 break;
553 }
554 }
555
556 if (!radeon_encoder)
557 return;
558
559 if (radeon_crtc->crtc_id == 0)
560 pll = &rdev->clock.p1pll;
561 else
562 pll = &rdev->clock.p2pll;
563
564 /* adjust pixel clock as needed */
565 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
2606c886 566
7c27f87d
AD		 567 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
568 &ref_div, &post_div);
771fe6b9 569
39deb2d6 570 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
771fe6b9
JG		 571 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
572 &crev);
573
574 switch (frev) {
575 case 1:
576 switch (crev) {
577 case 1:
4eaeca33
AD		 578 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
579 args.v1.usRefDiv = cpu_to_le16(ref_div);
580 args.v1.usFbDiv = cpu_to_le16(fb_div);
581 args.v1.ucFracFbDiv = frac_fb_div;
582 args.v1.ucPostDiv = post_div;
583 args.v1.ucPpll =
771fe6b9 584 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
4eaeca33
AD		 585 args.v1.ucCRTC = radeon_crtc->crtc_id;
586 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 587 break;
588 case 2:
4eaeca33
AD		 589 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
590 args.v2.usRefDiv = cpu_to_le16(ref_div);
591 args.v2.usFbDiv = cpu_to_le16(fb_div);
592 args.v2.ucFracFbDiv = frac_fb_div;
593 args.v2.ucPostDiv = post_div;
594 args.v2.ucPpll =
771fe6b9 595 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
4eaeca33
AD		 596 args.v2.ucCRTC = radeon_crtc->crtc_id;
597 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 598 break;
599 case 3:
4eaeca33
AD		 600 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
601 args.v3.usRefDiv = cpu_to_le16(ref_div);
602 args.v3.usFbDiv = cpu_to_le16(fb_div);
603 args.v3.ucFracFbDiv = frac_fb_div;
604 args.v3.ucPostDiv = post_div;
605 args.v3.ucPpll =
771fe6b9 606 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
4eaeca33
AD		 607 args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
608 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
609 args.v3.ucEncoderMode =
771fe6b9
JG		 610 atombios_get_encoder_mode(encoder);
611 break;
612 default:
613 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
614 return;
615 }
616 break;
617 default:
618 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
619 return;
620 }
621
771fe6b9
JG		 622 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
623}
624
54f088a9
AD		 625static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
626 struct drm_framebuffer *old_fb)
771fe6b9
JG		 627{
628 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
629 struct drm_device *dev = crtc->dev;
630 struct radeon_device *rdev = dev->dev_private;
631 struct radeon_framebuffer *radeon_fb;
632 struct drm_gem_object *obj;
4c788679 633 struct radeon_bo *rbo;
771fe6b9 634 uint64_t fb_location;
e024e110 635 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 636 int r;
771fe6b9 637
2de3b484
JG		 638 /* no fb bound */
639 if (!crtc->fb) {
640 DRM_DEBUG("No FB bound\n");
641 return 0;
642 }
771fe6b9
JG		 643
644 radeon_fb = to_radeon_framebuffer(crtc->fb);
645
4c788679 646 /* Pin framebuffer & get tilling informations */
771fe6b9 647 obj = radeon_fb->obj;
4c788679
JG		 648 rbo = obj->driver_private;
649 r = radeon_bo_reserve(rbo, false);
650 if (unlikely(r != 0))
651 return r;
652 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
653 if (unlikely(r != 0)) {
654 radeon_bo_unreserve(rbo);
771fe6b9
JG		 655 return -EINVAL;
656 }
4c788679
JG		 657 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
658 radeon_bo_unreserve(rbo);
771fe6b9
JG		 659
660 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 661 case 8:
662 fb_format =
663 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
664 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
665 break;
771fe6b9
JG		 666 case 15:
667 fb_format =
668 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
669 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
670 break;
671 case 16:
672 fb_format =
673 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
674 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
675 break;
676 case 24:
677 case 32:
678 fb_format =
679 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
680 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
681 break;
682 default:
683 DRM_ERROR("Unsupported screen depth %d\n",
684 crtc->fb->bits_per_pixel);
685 return -EINVAL;
686 }
687
cf2f05d3
DA		 688 if (tiling_flags & RADEON_TILING_MACRO)
689 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
690
e024e110
DA		 691 if (tiling_flags & RADEON_TILING_MICRO)
692 fb_format |= AVIVO_D1GRPH_TILED;
693
771fe6b9
JG		 694 if (radeon_crtc->crtc_id == 0)
695 WREG32(AVIVO_D1VGA_CONTROL, 0);
696 else
697 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 698
699 if (rdev->family >= CHIP_RV770) {
700 if (radeon_crtc->crtc_id) {
701 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
702 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
703 } else {
704 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
705 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
706 }
707 }
771fe6b9
JG		 708 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
709 (u32) fb_location);
710 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
711 radeon_crtc->crtc_offset, (u32) fb_location);
712 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
713
714 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
715 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
716 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
717 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
718 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
719 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
720
721 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
722 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
723 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
724
725 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
726 crtc->mode.vdisplay);
727 x &= ~3;
728 y &= ~1;
729 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
730 (x << 16) | y);
731 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
732 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
733
734 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
735 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
736 AVIVO_D1MODE_INTERLEAVE_EN);
737 else
738 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
739
740 if (old_fb && old_fb != crtc->fb) {
741 radeon_fb = to_radeon_framebuffer(old_fb);
4c788679
JG		 742 rbo = radeon_fb->obj->driver_private;
743 r = radeon_bo_reserve(rbo, false);
744 if (unlikely(r != 0))
745 return r;
746 radeon_bo_unpin(rbo);
747 radeon_bo_unreserve(rbo);
771fe6b9 748 }
f30f37de
MD		 749
750 /* Bytes per pixel may have changed */
751 radeon_bandwidth_update(rdev);
752
771fe6b9
JG		 753 return 0;
754}
755
54f088a9
AD		 756int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
757 struct drm_framebuffer *old_fb)
758{
759 struct drm_device *dev = crtc->dev;
760 struct radeon_device *rdev = dev->dev_private;
761
762 if (ASIC_IS_AVIVO(rdev))
763 return avivo_crtc_set_base(crtc, x, y, old_fb);
764 else
765 return radeon_crtc_set_base(crtc, x, y, old_fb);
766}
767
615e0cb6
AD		 768/* properly set additional regs when using atombios */
769static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
770{
771 struct drm_device *dev = crtc->dev;
772 struct radeon_device *rdev = dev->dev_private;
773 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
774 u32 disp_merge_cntl;
775
776 switch (radeon_crtc->crtc_id) {
777 case 0:
778 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
779 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
780 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
781 break;
782 case 1:
783 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
784 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
785 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
786 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
787 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
788 break;
789 }
790}
791
771fe6b9
JG		 792int atombios_crtc_mode_set(struct drm_crtc *crtc,
793 struct drm_display_mode *mode,
794 struct drm_display_mode *adjusted_mode,
795 int x, int y, struct drm_framebuffer *old_fb)
796{
797 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
798 struct drm_device *dev = crtc->dev;
799 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 800
801 /* TODO color tiling */
771fe6b9 802
ebbe1cb9 803 atombios_set_ss(crtc, 0);
771fe6b9 804 atombios_crtc_set_pll(crtc, adjusted_mode);
ebbe1cb9 805 atombios_set_ss(crtc, 1);
5a9bcacc 806 atombios_crtc_set_timing(crtc, adjusted_mode);
771fe6b9
JG		 807
808 if (ASIC_IS_AVIVO(rdev))
809 atombios_crtc_set_base(crtc, x, y, old_fb);
810 else {
5a9bcacc
AD		 811 if (radeon_crtc->crtc_id == 0)
812 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54f088a9 813 atombios_crtc_set_base(crtc, x, y, old_fb);
615e0cb6 814 radeon_legacy_atom_fixup(crtc);
771fe6b9 815 }
c93bb85b
JG		 816 atombios_overscan_setup(crtc, mode, adjusted_mode);
817 atombios_scaler_setup(crtc);
771fe6b9
JG		 818 return 0;
819}
820
821static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
822 struct drm_display_mode *mode,
823 struct drm_display_mode *adjusted_mode)
824{
c93bb85b
JG		 825 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
826 return false;
771fe6b9
JG		 827 return true;
828}
829
830static void atombios_crtc_prepare(struct drm_crtc *crtc)
831{
771fe6b9 832 atombios_lock_crtc(crtc, 1);
a348c84d 833 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 834}
835
836static void atombios_crtc_commit(struct drm_crtc *crtc)
837{
838 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
839 atombios_lock_crtc(crtc, 0);
840}
841
842static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
843 .dpms = atombios_crtc_dpms,
844 .mode_fixup = atombios_crtc_mode_fixup,
845 .mode_set = atombios_crtc_mode_set,
846 .mode_set_base = atombios_crtc_set_base,
847 .prepare = atombios_crtc_prepare,
848 .commit = atombios_crtc_commit,
068143d3 849 .load_lut = radeon_crtc_load_lut,
771fe6b9
JG		 850};
851
852void radeon_atombios_init_crtc(struct drm_device *dev,
853 struct radeon_crtc *radeon_crtc)
854{
855 if (radeon_crtc->crtc_id == 1)
856 radeon_crtc->crtc_offset =
857 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
858 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
859}
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