[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv50_fb.c

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_drm.h"

int
nv50_fb_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* Not a clue what this is exactly.  Without pointing it at a
	 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
	 * cause IOMMU "read from address 0" errors (rh#561267)
	 */
	nv_wr32(dev, 0x100c08, dev_priv->gart_info.sg_dummy_bus >> 8);

	/* This is needed to get meaningful information from 100c90
	 * on traps. No idea what these values mean exactly. */
	switch (dev_priv->chipset) {
	case 0x50:
		nv_wr32(dev, 0x100c90, 0x0707ff);
		break;
	case 0xa3:
	case 0xa5:
	case 0xa8:
		nv_wr32(dev, 0x100c90, 0x0d0fff);
		break;
	default:
		nv_wr32(dev, 0x100c90, 0x1d07ff);
		break;
	}

	return 0;
}

void
nv50_fb_takedown(struct drm_device *dev)
{
}

void
nv50_fb_vm_trap(struct drm_device *dev, int display, const char *name)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	u32 trap[6], idx, chinst;
	int i, ch;

	idx = nv_rd32(dev, 0x100c90);
	if (!(idx & 0x80000000))
		return;
	idx &= 0x00ffffff;

	for (i = 0; i < 6; i++) {
		nv_wr32(dev, 0x100c90, idx | i << 24);
		trap[i] = nv_rd32(dev, 0x100c94);
	}
	nv_wr32(dev, 0x100c90, idx | 0x80000000);

	if (!display)
		return;

	chinst = (trap[2] << 16) | trap[1];
	for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
		struct nouveau_channel *chan = dev_priv->fifos[ch];

		if (!chan || !chan->ramin)
			continue;

		if (chinst == chan->ramin->vinst >> 12)
			break;
	}

	NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x "
		     "channel %d (0x%08x)\n",
		name, (trap[5] & 0x100 ? "read" : "write"),
		trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff,
		trap[0], ch, chinst);
}
Commit	Line	Data
304424e1 MK	1	#include "drmP.h"
	2	#include "drm.h"
	3	#include "nouveau_drv.h"
	4	#include "nouveau_drm.h"
	5
	6	int
	7	nv50_fb_init(struct drm_device *dev)
	8	{
304424e1 MK	9	struct drm_nouveau_private *dev_priv = dev->dev_private;
304424e1 MK	10
4eb3033c BS	11	/* Not a clue what this is exactly. Without pointing it at a
	12	* scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
	13	* cause IOMMU "read from address 0" errors (rh#561267)
	14	*/
	15	nv_wr32(dev, 0x100c08, dev_priv->gart_info.sg_dummy_bus >> 8);
	16
	17	/* This is needed to get meaningful information from 100c90
	18	* on traps. No idea what these values mean exactly. */
304424e1 MK	19	switch (dev_priv->chipset) {
	20	case 0x50:
	21	nv_wr32(dev, 0x100c90, 0x0707ff);
	22	break;
f9aafdd3	23	case 0xa3:
304424e1 MK	24	case 0xa5:
	25	case 0xa8:
	26	nv_wr32(dev, 0x100c90, 0x0d0fff);
	27	break;
	28	default:
	29	nv_wr32(dev, 0x100c90, 0x1d07ff);
	30	break;
	31	}
	32
	33	return 0;
	34	}
	35
	36	void
	37	nv50_fb_takedown(struct drm_device *dev)
	38	{
	39	}
d96773e7 BS	40
	41	void
	42	nv50_fb_vm_trap(struct drm_device dev, int display, const char name)
	43	{
	44	struct drm_nouveau_private *dev_priv = dev->dev_private;
	45	u32 trap[6], idx, chinst;
	46	int i, ch;
	47
	48	idx = nv_rd32(dev, 0x100c90);
	49	if (!(idx & 0x80000000))
	50	return;
	51	idx &= 0x00ffffff;
	52
	53	for (i = 0; i < 6; i++) {
	54	nv_wr32(dev, 0x100c90, idx \| i << 24);
	55	trap[i] = nv_rd32(dev, 0x100c94);
	56	}
	57	nv_wr32(dev, 0x100c90, idx \| 0x80000000);
	58
	59	if (!display)
	60	return;
	61
	62	chinst = (trap[2] << 16) \| trap[1];
	63	for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
	64	struct nouveau_channel *chan = dev_priv->fifos[ch];
	65
	66	if (!chan \|\| !chan->ramin)
	67	continue;
	68
	69	if (chinst == chan->ramin->vinst >> 12)
	70	break;
	71	}
	72
	73	NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x "
	74	"channel %d (0x%08x)\n",
	75	name, (trap[5] & 0x100 ? "read" : "write"),
	76	trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff,
	77	trap[0], ch, chinst);
	78	}