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drm/nouveau: introduce gpio engine
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv50_display.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "nv50_display.h"
28#include "nouveau_crtc.h"
29#include "nouveau_encoder.h"
30#include "nouveau_connector.h"
31#include "nouveau_fb.h"
4abe3520 32#include "nouveau_fbcon.h"
6ee73861
BS		 33#include "drm_crtc_helper.h"
34
35static void
36nv50_evo_channel_del(struct nouveau_channel **pchan)
37{
38 struct nouveau_channel *chan = *pchan;
39
40 if (!chan)
41 return;
42 *pchan = NULL;
43
44 nouveau_gpuobj_channel_takedown(chan);
45 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
46
47 if (chan->user)
48 iounmap(chan->user);
49
50 kfree(chan);
51}
52
53static int
54nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
55 uint32_t tile_flags, uint32_t magic_flags,
56 uint32_t offset, uint32_t limit)
57{
58 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
59 struct drm_device *dev = evo->dev;
60 struct nouveau_gpuobj *obj = NULL;
61 int ret;
62
63 ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
64 if (ret)
65 return ret;
66 obj->engine = NVOBJ_ENGINE_DISPLAY;
67
68 ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
69 if (ret) {
70 nouveau_gpuobj_del(dev, &obj);
71 return ret;
72 }
73
6ee73861
BS		 74 nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
75 nv_wo32(dev, obj, 1, limit);
76 nv_wo32(dev, obj, 2, offset);
77 nv_wo32(dev, obj, 3, 0x00000000);
78 nv_wo32(dev, obj, 4, 0x00000000);
79 nv_wo32(dev, obj, 5, 0x00010000);
f56cb86f 80 dev_priv->engine.instmem.flush(dev);
6ee73861
BS		 81
82 return 0;
83}
84
85static int
86nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
87{
88 struct drm_nouveau_private *dev_priv = dev->dev_private;
89 struct nouveau_channel *chan;
90 int ret;
91
92 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
93 if (!chan)
94 return -ENOMEM;
95 *pchan = chan;
96
97 chan->id = -1;
98 chan->dev = dev;
99 chan->user_get = 4;
100 chan->user_put = 0;
101
102 INIT_LIST_HEAD(&chan->ramht_refs);
103
104 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
105 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
106 if (ret) {
107 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
108 nv50_evo_channel_del(pchan);
109 return ret;
110 }
111
b833ac26
BS		 112 ret = drm_mm_init(&chan->ramin_heap,
113 chan->ramin->gpuobj->im_pramin->start, 32768);
6ee73861
BS		 114 if (ret) {
115 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
116 nv50_evo_channel_del(pchan);
117 return ret;
118 }
119
120 ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
121 0, &chan->ramht);
122 if (ret) {
123 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
124 nv50_evo_channel_del(pchan);
125 return ret;
126 }
127
128 if (dev_priv->chipset != 0x50) {
129 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
130 0, 0xffffffff);
131 if (ret) {
132 nv50_evo_channel_del(pchan);
133 return ret;
134 }
135
136
137 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
138 0, 0xffffffff);
139 if (ret) {
140 nv50_evo_channel_del(pchan);
141 return ret;
142 }
143 }
144
145 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
a76fb4e8 146 0, dev_priv->vram_size);
6ee73861
BS		 147 if (ret) {
148 nv50_evo_channel_del(pchan);
149 return ret;
150 }
151
152 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
153 false, true, &chan->pushbuf_bo);
154 if (ret == 0)
155 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
156 if (ret) {
157 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
158 nv50_evo_channel_del(pchan);
159 return ret;
160 }
161
162 ret = nouveau_bo_map(chan->pushbuf_bo);
163 if (ret) {
164 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
165 nv50_evo_channel_del(pchan);
166 return ret;
167 }
168
169 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
170 NV50_PDISPLAY_USER(0), PAGE_SIZE);
171 if (!chan->user) {
172 NV_ERROR(dev, "Error mapping EVO control regs.\n");
173 nv50_evo_channel_del(pchan);
174 return -ENOMEM;
175 }
176
177 return 0;
178}
179
c88c2e06
FJ		 180int
181nv50_display_early_init(struct drm_device *dev)
182{
183 return 0;
184}
185
186void
187nv50_display_late_takedown(struct drm_device *dev)
188{
189}
190
6ee73861
BS		 191int
192nv50_display_init(struct drm_device *dev)
193{
194 struct drm_nouveau_private *dev_priv = dev->dev_private;
195 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
ee2e0131 196 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
6ee73861
BS		 197 struct nouveau_channel *evo = dev_priv->evo;
198 struct drm_connector *connector;
d0875edd 199 uint32_t val, ram_amount;
6ee73861
BS		 200 uint64_t start;
201 int ret, i;
202
ef2bb506 203 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 204
205 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
206 /*
207 * I think the 0x006101XX range is some kind of main control area
208 * that enables things.
209 */
210 /* CRTC? */
211 for (i = 0; i < 2; i++) {
212 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
213 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
214 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
215 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
216 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
217 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
218 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
219 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
220 }
221 /* DAC */
222 for (i = 0; i < 3; i++) {
223 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
224 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
225 }
226 /* SOR */
227 for (i = 0; i < 4; i++) {
228 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
229 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
230 }
231 /* Something not yet in use, tv-out maybe. */
232 for (i = 0; i < 3; i++) {
233 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
234 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
235 }
236
237 for (i = 0; i < 3; i++) {
238 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
239 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
240 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
241 }
242
243 /* This used to be in crtc unblank, but seems out of place there. */
244 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
245 /* RAM is clamped to 256 MiB. */
a76fb4e8 246 ram_amount = dev_priv->vram_size;
ef2bb506 247 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
6ee73861
BS		 248 if (ram_amount > 256*1024*1024)
249 ram_amount = 256*1024*1024;
250 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
251 nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
252 nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
253
254 /* The precise purpose is unknown, i suspect it has something to do
255 * with text mode.
256 */
257 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
258 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
259 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
260 if (!nv_wait(0x006194e8, 2, 0)) {
261 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
262 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
263 nv_rd32(dev, 0x6194e8));
264 return -EBUSY;
265 }
266 }
267
268 /* taken from nv bug #12637, attempts to un-wedge the hw if it's
269 * stuck in some unspecified state
270 */
271 start = ptimer->read(dev);
272 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
273 while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
274 if ((val & 0x9f0000) == 0x20000)
275 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
276 val | 0x800000);
277
278 if ((val & 0x3f0000) == 0x30000)
279 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
280 val | 0x200000);
281
282 if (ptimer->read(dev) - start > 1000000000ULL) {
283 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
284 NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
285 return -EBUSY;
286 }
287 }
288
289 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
290 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
291 if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
292 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
293 NV_ERROR(dev, "0x610200 = 0x%08x\n",
294 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
295 return -EBUSY;
296 }
297
298 for (i = 0; i < 2; i++) {
299 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
300 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
301 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
302 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
303 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
304 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
305 return -EBUSY;
306 }
307
308 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
309 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
310 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
311 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
312 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
313 NV_ERROR(dev, "timeout: "
314 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
315 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
316 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
317 return -EBUSY;
318 }
319 }
320
321 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
322
323 /* initialise fifo */
324 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
325 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
326 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
327 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
328 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
329 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
330 if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
331 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
332 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
333 return -EBUSY;
334 }
335 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
336 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
337 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
338 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
339 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
340 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
341 nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
342
343 evo->dma.max = (4096/4) - 2;
344 evo->dma.put = 0;
345 evo->dma.cur = evo->dma.put;
346 evo->dma.free = evo->dma.max - evo->dma.cur;
347
348 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
349 if (ret)
350 return ret;
351
352 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
353 OUT_RING(evo, 0);
354
355 ret = RING_SPACE(evo, 11);
356 if (ret)
357 return ret;
358 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
359 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
360 OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
361 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
362 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
363 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
364 OUT_RING(evo, 0);
365 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
366 OUT_RING(evo, 0);
367 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
368 OUT_RING(evo, 0);
369 FIRE_RING(evo);
370 if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
371 NV_ERROR(dev, "evo pushbuf stalled\n");
372
373 /* enable clock change interrupts. */
374 nv_wr32(dev, 0x610028, 0x00010001);
375 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
376 NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
377 NV50_PDISPLAY_INTR_EN_CLK_UNK40));
378
379 /* enable hotplug interrupts */
6ee73861
BS		 380 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
381 struct nouveau_connector *conn = nouveau_connector(connector);
6ee73861 382
ee2e0131 383 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
6ee73861
BS		 384 }
385
386 return 0;
387}
388
389static int nv50_display_disable(struct drm_device *dev)
390{
391 struct drm_nouveau_private *dev_priv = dev->dev_private;
392 struct drm_crtc *drm_crtc;
393 int ret, i;
394
ef2bb506 395 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 396
397 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
398 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
399
400 nv50_crtc_blank(crtc, true);
401 }
402
403 ret = RING_SPACE(dev_priv->evo, 2);
404 if (ret == 0) {
405 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
406 OUT_RING(dev_priv->evo, 0);
407 }
408 FIRE_RING(dev_priv->evo);
409
410 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
411 * cleaning up?
412 */
413 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
414 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
415 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
416
417 if (!crtc->base.enabled)
418 continue;
419
420 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
421 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
422 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
423 "0x%08x\n", mask, mask);
424 NV_ERROR(dev, "0x610024 = 0x%08x\n",
425 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
426 }
427 }
428
429 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
430 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
431 if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
432 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
433 NV_ERROR(dev, "0x610200 = 0x%08x\n",
434 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
435 }
436
437 for (i = 0; i < 3; i++) {
438 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
439 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
440 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
441 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
442 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
443 }
444 }
445
446 /* disable interrupts. */
447 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
448
449 /* disable hotplug interrupts */
450 nv_wr32(dev, 0xe054, 0xffffffff);
451 nv_wr32(dev, 0xe050, 0x00000000);
452 if (dev_priv->chipset >= 0x90) {
453 nv_wr32(dev, 0xe074, 0xffffffff);
454 nv_wr32(dev, 0xe070, 0x00000000);
455 }
456 return 0;
457}
458
459int nv50_display_create(struct drm_device *dev)
460{
461 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 462 struct dcb_table *dcb = &dev_priv->vbios.dcb;
8f1a6086 463 struct drm_connector *connector, *ct;
6ee73861
BS		 464 int ret, i;
465
ef2bb506 466 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 467
468 /* init basic kernel modesetting */
469 drm_mode_config_init(dev);
470
471 /* Initialise some optional connector properties. */
472 drm_mode_create_scaling_mode_property(dev);
473 drm_mode_create_dithering_property(dev);
474
475 dev->mode_config.min_width = 0;
476 dev->mode_config.min_height = 0;
477
478 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
479
480 dev->mode_config.max_width = 8192;
481 dev->mode_config.max_height = 8192;
482
483 dev->mode_config.fb_base = dev_priv->fb_phys;
484
485 /* Create EVO channel */
486 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
487 if (ret) {
488 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
489 return ret;
490 }
491
492 /* Create CRTC objects */
493 for (i = 0; i < 2; i++)
494 nv50_crtc_create(dev, i);
495
496 /* We setup the encoders from the BIOS table */
497 for (i = 0 ; i < dcb->entries; i++) {
498 struct dcb_entry *entry = &dcb->entry[i];
499
500 if (entry->location != DCB_LOC_ON_CHIP) {
501 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
502 entry->type, ffs(entry->or) - 1);
503 continue;
504 }
505
8f1a6086
BS		 506 connector = nouveau_connector_create(dev, entry->connector);
507 if (IS_ERR(connector))
508 continue;
509
6ee73861
BS		 510 switch (entry->type) {
511 case OUTPUT_TMDS:
512 case OUTPUT_LVDS:
513 case OUTPUT_DP:
8f1a6086 514 nv50_sor_create(connector, entry);
6ee73861
BS		 515 break;
516 case OUTPUT_ANALOG:
8f1a6086 517 nv50_dac_create(connector, entry);
6ee73861
BS		 518 break;
519 default:
520 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
521 continue;
522 }
6ee73861
BS		 523 }
524
8f1a6086
BS		 525 list_for_each_entry_safe(connector, ct,
526 &dev->mode_config.connector_list, head) {
527 if (!connector->encoder_ids[0]) {
528 NV_WARN(dev, "%s has no encoders, removing\n",
529 drm_get_connector_name(connector));
530 connector->funcs->destroy(connector);
531 }
6ee73861
BS		 532 }
533
534 ret = nv50_display_init(dev);
a1663ed3
BS		 535 if (ret) {
536 nv50_display_destroy(dev);
6ee73861 537 return ret;
a1663ed3 538 }
6ee73861
BS		 539
540 return 0;
541}
542
c88c2e06
FJ		 543void
544nv50_display_destroy(struct drm_device *dev)
6ee73861
BS		 545{
546 struct drm_nouveau_private *dev_priv = dev->dev_private;
547
ef2bb506 548 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 549
550 drm_mode_config_cleanup(dev);
551
552 nv50_display_disable(dev);
553 nv50_evo_channel_del(&dev_priv->evo);
6ee73861
BS		 554}
555
87c0e0e5
BS		 556static u16
557nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
558 u32 mc, int pxclk)
6ee73861
BS		 559{
560 struct drm_nouveau_private *dev_priv = dev->dev_private;
75c722d7
BS		 561 struct nouveau_connector *nv_connector = NULL;
562 struct drm_encoder *encoder;
04a39c57 563 struct nvbios *bios = &dev_priv->vbios;
87c0e0e5 564 u32 script = 0, or;
6ee73861 565
75c722d7
BS		 566 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
567 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
568
87c0e0e5 569 if (nv_encoder->dcb != dcb)
75c722d7
BS		 570 continue;
571
572 nv_connector = nouveau_encoder_connector_get(nv_encoder);
573 break;
574 }
575
87c0e0e5
BS		 576 or = ffs(dcb->or) - 1;
577 switch (dcb->type) {
6ee73861
BS		 578 case OUTPUT_LVDS:
579 script = (mc >> 8) & 0xf;
04a39c57 580 if (bios->fp_no_ddc) {
6ee73861
BS		 581 if (bios->fp.dual_link)
582 script |= 0x0100;
583 if (bios->fp.if_is_24bit)
584 script |= 0x0200;
585 } else {
586 if (pxclk >= bios->fp.duallink_transition_clk) {
587 script |= 0x0100;
588 if (bios->fp.strapless_is_24bit & 2)
589 script |= 0x0200;
590 } else
591 if (bios->fp.strapless_is_24bit & 1)
592 script |= 0x0200;
75c722d7
BS		 593
594 if (nv_connector && nv_connector->edid &&
595 (nv_connector->edid->revision >= 4) &&
596 (nv_connector->edid->input & 0x70) >= 0x20)
597 script |= 0x0200;
6ee73861
BS		 598 }
599
600 if (nouveau_uscript_lvds >= 0) {
601 NV_INFO(dev, "override script 0x%04x with 0x%04x "
602 "for output LVDS-%d\n", script,
603 nouveau_uscript_lvds, or);
604 script = nouveau_uscript_lvds;
605 }
606 break;
607 case OUTPUT_TMDS:
608 script = (mc >> 8) & 0xf;
609 if (pxclk >= 165000)
610 script |= 0x0100;
611
612 if (nouveau_uscript_tmds >= 0) {
613 NV_INFO(dev, "override script 0x%04x with 0x%04x "
614 "for output TMDS-%d\n", script,
615 nouveau_uscript_tmds, or);
616 script = nouveau_uscript_tmds;
617 }
618 break;
619 case OUTPUT_DP:
620 script = (mc >> 8) & 0xf;
621 break;
622 case OUTPUT_ANALOG:
623 script = 0xff;
624 break;
625 default:
626 NV_ERROR(dev, "modeset on unsupported output type!\n");
627 break;
628 }
629
630 return script;
631}
632
633static void
634nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
635{
636 struct drm_nouveau_private *dev_priv = dev->dev_private;
637 struct nouveau_channel *chan;
638 struct list_head *entry, *tmp;
639
640 list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
641 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
642
643 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
644 chan->nvsw.vblsem_rval);
645 list_del(&chan->nvsw.vbl_wait);
646 }
647}
648
649static void
650nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
651{
652 intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
653
654 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
655 nv50_display_vblank_crtc_handler(dev, 0);
656
657 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
658 nv50_display_vblank_crtc_handler(dev, 1);
659
660 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
661 NV50_PDISPLAY_INTR_EN) & ~intr);
662 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
663}
664
665static void
666nv50_display_unk10_handler(struct drm_device *dev)
667{
87c0e0e5
BS		 668 struct drm_nouveau_private *dev_priv = dev->dev_private;
669 u32 unk30 = nv_rd32(dev, 0x610030), mc;
670 int i, crtc, or, type = OUTPUT_ANY;
6ee73861 671
87c0e0e5
BS		 672 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
673 dev_priv->evo_irq.dcb = NULL;
6ee73861
BS		 674
675 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
676
87c0e0e5
BS		 677 /* Determine which CRTC we're dealing with, only 1 ever will be
678 * signalled at the same time with the current nouveau code.
679 */
680 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
681 if (crtc < 0)
682 goto ack;
683
684 /* Nothing needs to be done for the encoder */
685 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
686 if (crtc < 0)
687 goto ack;
6ee73861 688
87c0e0e5
BS		 689 /* Find which encoder was connected to the CRTC */
690 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
691 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
692 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
693 if (!(mc & (1 << crtc)))
694 continue;
695
696 switch ((mc & 0x00000f00) >> 8) {
697 case 0: type = OUTPUT_ANALOG; break;
698 case 1: type = OUTPUT_TV; break;
699 default:
700 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
701 goto ack;
702 }
703
704 or = i;
705 }
706
707 for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
708 if (dev_priv->chipset < 0x90 ||
709 dev_priv->chipset == 0x92 ||
710 dev_priv->chipset == 0xa0)
711 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
712 else
713 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
714
715 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
716 if (!(mc & (1 << crtc)))
717 continue;
718
719 switch ((mc & 0x00000f00) >> 8) {
720 case 0: type = OUTPUT_LVDS; break;
721 case 1: type = OUTPUT_TMDS; break;
722 case 2: type = OUTPUT_TMDS; break;
723 case 5: type = OUTPUT_TMDS; break;
724 case 8: type = OUTPUT_DP; break;
725 case 9: type = OUTPUT_DP; break;
726 default:
727 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
728 goto ack;
729 }
730
731 or = i;
732 }
733
734 /* There was no encoder to disable */
735 if (type == OUTPUT_ANY)
736 goto ack;
737
738 /* Disable the encoder */
739 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
740 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
741
742 if (dcb->type == type && (dcb->or & (1 << or))) {
743 nouveau_bios_run_display_table(dev, dcb, 0, -1);
744 dev_priv->evo_irq.dcb = dcb;
745 goto ack;
746 }
747 }
748
749 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
6ee73861
BS		 750ack:
751 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
752 nv_wr32(dev, 0x610030, 0x80000000);
753}
754
afa3b4c3
BS		 755static void
756nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
757{
758 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
759 struct drm_encoder *encoder;
760 uint32_t tmp, unk0 = 0, unk1 = 0;
761
762 if (dcb->type != OUTPUT_DP)
763 return;
764
765 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
766 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
767
768 if (nv_encoder->dcb == dcb) {
769 unk0 = nv_encoder->dp.unk0;
770 unk1 = nv_encoder->dp.unk1;
771 break;
772 }
773 }
774
775 if (unk0 || unk1) {
776 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
777 tmp &= 0xfffffe03;
778 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
779
780 tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
781 tmp &= 0xfef080c0;
782 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
783 }
784}
785
6ee73861
BS		 786static void
787nv50_display_unk20_handler(struct drm_device *dev)
788{
87c0e0e5
BS		 789 struct drm_nouveau_private *dev_priv = dev->dev_private;
790 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
791 struct dcb_entry *dcb;
792 int i, crtc, or, type = OUTPUT_ANY;
6ee73861 793
87c0e0e5
BS		 794 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
795 dcb = dev_priv->evo_irq.dcb;
796 if (dcb) {
797 nouveau_bios_run_display_table(dev, dcb, 0, -2);
798 dev_priv->evo_irq.dcb = NULL;
799 }
800
801 /* CRTC clock change requested? */
802 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
803 if (crtc >= 0) {
804 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
805 pclk &= 0x003fffff;
806
807 nv50_crtc_set_clock(dev, crtc, pclk);
808
809 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
810 tmp &= ~0x000000f;
811 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
812 }
813
814 /* Nothing needs to be done for the encoder */
815 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
816 if (crtc < 0)
6ee73861 817 goto ack;
87c0e0e5 818 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
6ee73861 819
87c0e0e5
BS		 820 /* Find which encoder is connected to the CRTC */
821 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
822 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
823 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
824 if (!(mc & (1 << crtc)))
825 continue;
6ee73861 826
87c0e0e5
BS		 827 switch ((mc & 0x00000f00) >> 8) {
828 case 0: type = OUTPUT_ANALOG; break;
829 case 1: type = OUTPUT_TV; break;
830 default:
831 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
832 goto ack;
833 }
834
835 or = i;
836 }
837
838 for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
839 if (dev_priv->chipset < 0x90 ||
840 dev_priv->chipset == 0x92 ||
841 dev_priv->chipset == 0xa0)
842 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
843 else
844 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
845
846 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
847 if (!(mc & (1 << crtc)))
848 continue;
849
850 switch ((mc & 0x00000f00) >> 8) {
851 case 0: type = OUTPUT_LVDS; break;
852 case 1: type = OUTPUT_TMDS; break;
853 case 2: type = OUTPUT_TMDS; break;
854 case 5: type = OUTPUT_TMDS; break;
855 case 8: type = OUTPUT_DP; break;
856 case 9: type = OUTPUT_DP; break;
857 default:
858 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
859 goto ack;
860 }
6ee73861 861
87c0e0e5
BS		 862 or = i;
863 }
6ee73861 864
87c0e0e5
BS		 865 if (type == OUTPUT_ANY)
866 goto ack;
6ee73861 867
87c0e0e5
BS		 868 /* Enable the encoder */
869 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
870 dcb = &dev_priv->vbios.dcb.entry[i];
871 if (dcb->type == type && (dcb->or & (1 << or)))
872 break;
873 }
afa3b4c3 874
87c0e0e5
BS		 875 if (i == dev_priv->vbios.dcb.entries) {
876 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
877 goto ack;
878 }
879
880 script = nv50_display_script_select(dev, dcb, mc, pclk);
881 nouveau_bios_run_display_table(dev, dcb, script, pclk);
6ee73861 882
87c0e0e5 883 nv50_display_unk20_dp_hack(dev, dcb);
87c0e0e5
BS		 884
885 if (dcb->type != OUTPUT_ANALOG) {
6ee73861
BS		 886 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
887 tmp &= ~0x00000f0f;
888 if (script & 0x0100)
889 tmp |= 0x00000101;
890 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
891 } else {
892 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
893 }
894
87c0e0e5
BS		 895 dev_priv->evo_irq.dcb = dcb;
896 dev_priv->evo_irq.pclk = pclk;
897 dev_priv->evo_irq.script = script;
898
6ee73861
BS		 899ack:
900 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
901 nv_wr32(dev, 0x610030, 0x80000000);
902}
903
271f29e7
BS		 904/* If programming a TMDS output on a SOR that can also be configured for
905 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
906 *
907 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
908 * the VBIOS scripts on at least one board I have only switch it off on
909 * link 0, causing a blank display if the output has previously been
910 * programmed for DisplayPort.
911 */
912static void
913nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
914{
915 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
916 struct drm_encoder *encoder;
917 u32 tmp;
918
919 if (dcb->type != OUTPUT_TMDS)
920 return;
921
922 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
923 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
924
925 if (nv_encoder->dcb->type == OUTPUT_DP &&
926 nv_encoder->dcb->or & (1 << or)) {
927 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
928 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
929 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
930 break;
931 }
932 }
933}
934
6ee73861
BS		 935static void
936nv50_display_unk40_handler(struct drm_device *dev)
937{
87c0e0e5
BS		 938 struct drm_nouveau_private *dev_priv = dev->dev_private;
939 struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
940 u16 script = dev_priv->evo_irq.script;
941 u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
6ee73861 942
87c0e0e5
BS		 943 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
944 dev_priv->evo_irq.dcb = NULL;
945 if (!dcb)
6ee73861 946 goto ack;
6ee73861 947
87c0e0e5 948 nouveau_bios_run_display_table(dev, dcb, script, -pclk);
271f29e7
BS		 949 nv50_display_unk40_dp_set_tmds(dev, dcb);
950
6ee73861
BS		 951ack:
952 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
953 nv_wr32(dev, 0x610030, 0x80000000);
954 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
955}
956
957void
958nv50_display_irq_handler_bh(struct work_struct *work)
959{
960 struct drm_nouveau_private *dev_priv =
961 container_of(work, struct drm_nouveau_private, irq_work);
962 struct drm_device *dev = dev_priv->dev;
963
964 for (;;) {
965 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
966 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
967
ef2bb506 968 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
6ee73861
BS		 969
970 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
971 nv50_display_unk10_handler(dev);
972 else
973 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
974 nv50_display_unk20_handler(dev);
975 else
976 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
977 nv50_display_unk40_handler(dev);
978 else
979 break;
980 }
981
982 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
983}
984
985static void
986nv50_display_error_handler(struct drm_device *dev)
987{
988 uint32_t addr, data;
989
990 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
991 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
992 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
993
994 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
995 0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
996
997 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
998}
999
a5acac66
BS		 1000void
1001nv50_display_irq_hotplug_bh(struct work_struct *work)
6ee73861 1002{
a5acac66
BS		 1003 struct drm_nouveau_private *dev_priv =
1004 container_of(work, struct drm_nouveau_private, hpd_work);
1005 struct drm_device *dev = dev_priv->dev;
6ee73861
BS		 1006 struct drm_connector *connector;
1007 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
1008 uint32_t unplug_mask, plug_mask, change_mask;
1009 uint32_t hpd0, hpd1 = 0;
1010
1011 hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
1012 if (dev_priv->chipset >= 0x90)
1013 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
1014
1015 plug_mask = (hpd0 & 0x0000ffff) | (hpd1 << 16);
1016 unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
1017 change_mask = plug_mask | unplug_mask;
1018
1019 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1020 struct drm_encoder_helper_funcs *helper;
1021 struct nouveau_connector *nv_connector =
1022 nouveau_connector(connector);
1023 struct nouveau_encoder *nv_encoder;
1024 struct dcb_gpio_entry *gpio;
1025 uint32_t reg;
1026 bool plugged;
1027
1028 if (!nv_connector->dcb)
1029 continue;
1030
1031 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
1032 if (!gpio || !(change_mask & (1 << gpio->line)))
1033 continue;
1034
1035 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
1036 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
1037 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1038 drm_get_connector_name(connector)) ;
1039
1040 if (!connector->encoder || !connector->encoder->crtc ||
1041 !connector->encoder->crtc->enabled)
1042 continue;
1043 nv_encoder = nouveau_encoder(connector->encoder);
1044 helper = connector->encoder->helper_private;
1045
1046 if (nv_encoder->dcb->type != OUTPUT_DP)
1047 continue;
1048
1049 if (plugged)
1050 helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
1051 else
1052 helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
1053 }
1054
1055 nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
1056 if (dev_priv->chipset >= 0x90)
1057 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
4abe3520 1058
eb1f8e4f 1059 drm_helper_hpd_irq_event(dev);
6ee73861
BS		 1060}
1061
1062void
1063nv50_display_irq_handler(struct drm_device *dev)
1064{
1065 struct drm_nouveau_private *dev_priv = dev->dev_private;
1066 uint32_t delayed = 0;
1067
a5acac66
BS		 1068 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
1069 if (!work_pending(&dev_priv->hpd_work))
1070 queue_work(dev_priv->wq, &dev_priv->hpd_work);
1071 }
6ee73861
BS		 1072
1073 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1074 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1075 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1076 uint32_t clock;
1077
ef2bb506 1078 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
6ee73861
BS		 1079
1080 if (!intr0 && !(intr1 & ~delayed))
1081 break;
1082
1083 if (intr0 & 0x00010000) {
1084 nv50_display_error_handler(dev);
1085 intr0 &= ~0x00010000;
1086 }
1087
1088 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1089 nv50_display_vblank_handler(dev, intr1);
1090 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1091 }
1092
1093 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1094 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1095 NV50_PDISPLAY_INTR_1_CLK_UNK40));
1096 if (clock) {
1097 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1098 if (!work_pending(&dev_priv->irq_work))
1099 queue_work(dev_priv->wq, &dev_priv->irq_work);
1100 delayed |= clock;
1101 intr1 &= ~clock;
1102 }
1103
1104 if (intr0) {
1105 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1106 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1107 }
1108
1109 if (intr1) {
1110 NV_ERROR(dev,
1111 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1112 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1113 }
1114 }
1115}
1116
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