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drm/nv50: fix dp_set_tmds to work on the right OR
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv50_display.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "nv50_display.h"
28#include "nouveau_crtc.h"
29#include "nouveau_encoder.h"
30#include "nouveau_connector.h"
31#include "nouveau_fb.h"
4abe3520 32#include "nouveau_fbcon.h"
6ee73861
BS		 33#include "drm_crtc_helper.h"
34
35static void
36nv50_evo_channel_del(struct nouveau_channel **pchan)
37{
38 struct nouveau_channel *chan = *pchan;
39
40 if (!chan)
41 return;
42 *pchan = NULL;
43
44 nouveau_gpuobj_channel_takedown(chan);
45 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
46
47 if (chan->user)
48 iounmap(chan->user);
49
50 kfree(chan);
51}
52
53static int
54nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
55 uint32_t tile_flags, uint32_t magic_flags,
56 uint32_t offset, uint32_t limit)
57{
58 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
59 struct drm_device *dev = evo->dev;
60 struct nouveau_gpuobj *obj = NULL;
61 int ret;
62
63 ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
64 if (ret)
65 return ret;
66 obj->engine = NVOBJ_ENGINE_DISPLAY;
67
68 ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
69 if (ret) {
70 nouveau_gpuobj_del(dev, &obj);
71 return ret;
72 }
73
6ee73861
BS		 74 nv_wo32(dev, obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
75 nv_wo32(dev, obj, 1, limit);
76 nv_wo32(dev, obj, 2, offset);
77 nv_wo32(dev, obj, 3, 0x00000000);
78 nv_wo32(dev, obj, 4, 0x00000000);
79 nv_wo32(dev, obj, 5, 0x00010000);
f56cb86f 80 dev_priv->engine.instmem.flush(dev);
6ee73861
BS		 81
82 return 0;
83}
84
85static int
86nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
87{
88 struct drm_nouveau_private *dev_priv = dev->dev_private;
89 struct nouveau_channel *chan;
90 int ret;
91
92 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
93 if (!chan)
94 return -ENOMEM;
95 *pchan = chan;
96
97 chan->id = -1;
98 chan->dev = dev;
99 chan->user_get = 4;
100 chan->user_put = 0;
101
102 INIT_LIST_HEAD(&chan->ramht_refs);
103
104 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
105 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
106 if (ret) {
107 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
108 nv50_evo_channel_del(pchan);
109 return ret;
110 }
111
b833ac26
BS		 112 ret = drm_mm_init(&chan->ramin_heap,
113 chan->ramin->gpuobj->im_pramin->start, 32768);
6ee73861
BS		 114 if (ret) {
115 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
116 nv50_evo_channel_del(pchan);
117 return ret;
118 }
119
120 ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16,
121 0, &chan->ramht);
122 if (ret) {
123 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
124 nv50_evo_channel_del(pchan);
125 return ret;
126 }
127
128 if (dev_priv->chipset != 0x50) {
129 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
130 0, 0xffffffff);
131 if (ret) {
132 nv50_evo_channel_del(pchan);
133 return ret;
134 }
135
136
137 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
138 0, 0xffffffff);
139 if (ret) {
140 nv50_evo_channel_del(pchan);
141 return ret;
142 }
143 }
144
145 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
a76fb4e8 146 0, dev_priv->vram_size);
6ee73861
BS		 147 if (ret) {
148 nv50_evo_channel_del(pchan);
149 return ret;
150 }
151
152 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
153 false, true, &chan->pushbuf_bo);
154 if (ret == 0)
155 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
156 if (ret) {
157 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
158 nv50_evo_channel_del(pchan);
159 return ret;
160 }
161
162 ret = nouveau_bo_map(chan->pushbuf_bo);
163 if (ret) {
164 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
165 nv50_evo_channel_del(pchan);
166 return ret;
167 }
168
169 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
170 NV50_PDISPLAY_USER(0), PAGE_SIZE);
171 if (!chan->user) {
172 NV_ERROR(dev, "Error mapping EVO control regs.\n");
173 nv50_evo_channel_del(pchan);
174 return -ENOMEM;
175 }
176
177 return 0;
178}
179
180int
181nv50_display_init(struct drm_device *dev)
182{
183 struct drm_nouveau_private *dev_priv = dev->dev_private;
184 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
185 struct nouveau_channel *evo = dev_priv->evo;
186 struct drm_connector *connector;
187 uint32_t val, ram_amount, hpd_en[2];
188 uint64_t start;
189 int ret, i;
190
ef2bb506 191 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 192
193 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
194 /*
195 * I think the 0x006101XX range is some kind of main control area
196 * that enables things.
197 */
198 /* CRTC? */
199 for (i = 0; i < 2; i++) {
200 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
201 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
202 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
203 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
204 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
205 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
206 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
207 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
208 }
209 /* DAC */
210 for (i = 0; i < 3; i++) {
211 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
212 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
213 }
214 /* SOR */
215 for (i = 0; i < 4; i++) {
216 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
217 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
218 }
219 /* Something not yet in use, tv-out maybe. */
220 for (i = 0; i < 3; i++) {
221 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
222 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
223 }
224
225 for (i = 0; i < 3; i++) {
226 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
227 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
228 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
229 }
230
231 /* This used to be in crtc unblank, but seems out of place there. */
232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
233 /* RAM is clamped to 256 MiB. */
a76fb4e8 234 ram_amount = dev_priv->vram_size;
ef2bb506 235 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
6ee73861
BS		 236 if (ram_amount > 256*1024*1024)
237 ram_amount = 256*1024*1024;
238 nv_wr32(dev, NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
239 nv_wr32(dev, NV50_PDISPLAY_UNK_388, 0x150000);
240 nv_wr32(dev, NV50_PDISPLAY_UNK_38C, 0);
241
242 /* The precise purpose is unknown, i suspect it has something to do
243 * with text mode.
244 */
245 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
246 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
247 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
248 if (!nv_wait(0x006194e8, 2, 0)) {
249 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
250 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
251 nv_rd32(dev, 0x6194e8));
252 return -EBUSY;
253 }
254 }
255
256 /* taken from nv bug #12637, attempts to un-wedge the hw if it's
257 * stuck in some unspecified state
258 */
259 start = ptimer->read(dev);
260 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
261 while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
262 if ((val & 0x9f0000) == 0x20000)
263 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
264 val | 0x800000);
265
266 if ((val & 0x3f0000) == 0x30000)
267 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
268 val | 0x200000);
269
270 if (ptimer->read(dev) - start > 1000000000ULL) {
271 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
272 NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
273 return -EBUSY;
274 }
275 }
276
277 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
278 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
279 if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) {
280 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
281 NV_ERROR(dev, "0x610200 = 0x%08x\n",
282 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
283 return -EBUSY;
284 }
285
286 for (i = 0; i < 2; i++) {
287 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
288 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
289 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
290 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
291 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
292 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
293 return -EBUSY;
294 }
295
296 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
297 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
298 if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
299 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
300 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
301 NV_ERROR(dev, "timeout: "
302 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
303 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
304 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
305 return -EBUSY;
306 }
307 }
308
309 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9);
310
311 /* initialise fifo */
312 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
313 ((evo->pushbuf_bo->bo.mem.mm_node->start << PAGE_SHIFT) >> 8) |
314 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
315 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
316 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
317 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
318 if (!nv_wait(0x610200, 0x80000000, 0x00000000)) {
319 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
320 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
321 return -EBUSY;
322 }
323 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
324 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
325 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
326 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
327 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
328 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
329 nv_wr32(dev, 0x610300, nv_rd32(dev, 0x610300) & ~1);
330
331 evo->dma.max = (4096/4) - 2;
332 evo->dma.put = 0;
333 evo->dma.cur = evo->dma.put;
334 evo->dma.free = evo->dma.max - evo->dma.cur;
335
336 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
337 if (ret)
338 return ret;
339
340 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
341 OUT_RING(evo, 0);
342
343 ret = RING_SPACE(evo, 11);
344 if (ret)
345 return ret;
346 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
347 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
348 OUT_RING(evo, NV50_EVO_DMA_NOTIFY_HANDLE_NONE);
349 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
350 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
351 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
352 OUT_RING(evo, 0);
353 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
354 OUT_RING(evo, 0);
355 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
356 OUT_RING(evo, 0);
357 FIRE_RING(evo);
358 if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2))
359 NV_ERROR(dev, "evo pushbuf stalled\n");
360
361 /* enable clock change interrupts. */
362 nv_wr32(dev, 0x610028, 0x00010001);
363 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, (NV50_PDISPLAY_INTR_EN_CLK_UNK10 |
364 NV50_PDISPLAY_INTR_EN_CLK_UNK20 |
365 NV50_PDISPLAY_INTR_EN_CLK_UNK40));
366
367 /* enable hotplug interrupts */
368 hpd_en[0] = hpd_en[1] = 0;
369 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
370 struct nouveau_connector *conn = nouveau_connector(connector);
371 struct dcb_gpio_entry *gpio;
372
11575639 373 if (conn->dcb->gpio_tag == 0xff)
6ee73861
BS		 374 continue;
375
376 gpio = nouveau_bios_gpio_entry(dev, conn->dcb->gpio_tag);
377 if (!gpio)
378 continue;
379
380 hpd_en[gpio->line >> 4] |= (0x00010001 << (gpio->line & 0xf));
381 }
382
383 nv_wr32(dev, 0xe054, 0xffffffff);
384 nv_wr32(dev, 0xe050, hpd_en[0]);
385 if (dev_priv->chipset >= 0x90) {
386 nv_wr32(dev, 0xe074, 0xffffffff);
387 nv_wr32(dev, 0xe070, hpd_en[1]);
388 }
389
390 return 0;
391}
392
393static int nv50_display_disable(struct drm_device *dev)
394{
395 struct drm_nouveau_private *dev_priv = dev->dev_private;
396 struct drm_crtc *drm_crtc;
397 int ret, i;
398
ef2bb506 399 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 400
401 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
402 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
403
404 nv50_crtc_blank(crtc, true);
405 }
406
407 ret = RING_SPACE(dev_priv->evo, 2);
408 if (ret == 0) {
409 BEGIN_RING(dev_priv->evo, 0, NV50_EVO_UPDATE, 1);
410 OUT_RING(dev_priv->evo, 0);
411 }
412 FIRE_RING(dev_priv->evo);
413
414 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
415 * cleaning up?
416 */
417 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
418 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
419 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
420
421 if (!crtc->base.enabled)
422 continue;
423
424 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
425 if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) {
426 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
427 "0x%08x\n", mask, mask);
428 NV_ERROR(dev, "0x610024 = 0x%08x\n",
429 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
430 }
431 }
432
433 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0);
434 nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0);
435 if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
436 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
437 NV_ERROR(dev, "0x610200 = 0x%08x\n",
438 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
439 }
440
441 for (i = 0; i < 3; i++) {
442 if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i),
443 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
444 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
445 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
446 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
447 }
448 }
449
450 /* disable interrupts. */
451 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, 0x00000000);
452
453 /* disable hotplug interrupts */
454 nv_wr32(dev, 0xe054, 0xffffffff);
455 nv_wr32(dev, 0xe050, 0x00000000);
456 if (dev_priv->chipset >= 0x90) {
457 nv_wr32(dev, 0xe074, 0xffffffff);
458 nv_wr32(dev, 0xe070, 0x00000000);
459 }
460 return 0;
461}
462
463int nv50_display_create(struct drm_device *dev)
464{
465 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 466 struct dcb_table *dcb = &dev_priv->vbios.dcb;
8f1a6086 467 struct drm_connector *connector, *ct;
6ee73861
BS		 468 int ret, i;
469
ef2bb506 470 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 471
472 /* init basic kernel modesetting */
473 drm_mode_config_init(dev);
474
475 /* Initialise some optional connector properties. */
476 drm_mode_create_scaling_mode_property(dev);
477 drm_mode_create_dithering_property(dev);
478
479 dev->mode_config.min_width = 0;
480 dev->mode_config.min_height = 0;
481
482 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
483
484 dev->mode_config.max_width = 8192;
485 dev->mode_config.max_height = 8192;
486
487 dev->mode_config.fb_base = dev_priv->fb_phys;
488
489 /* Create EVO channel */
490 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
491 if (ret) {
492 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
493 return ret;
494 }
495
496 /* Create CRTC objects */
497 for (i = 0; i < 2; i++)
498 nv50_crtc_create(dev, i);
499
500 /* We setup the encoders from the BIOS table */
501 for (i = 0 ; i < dcb->entries; i++) {
502 struct dcb_entry *entry = &dcb->entry[i];
503
504 if (entry->location != DCB_LOC_ON_CHIP) {
505 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
506 entry->type, ffs(entry->or) - 1);
507 continue;
508 }
509
8f1a6086
BS		 510 connector = nouveau_connector_create(dev, entry->connector);
511 if (IS_ERR(connector))
512 continue;
513
6ee73861
BS		 514 switch (entry->type) {
515 case OUTPUT_TMDS:
516 case OUTPUT_LVDS:
517 case OUTPUT_DP:
8f1a6086 518 nv50_sor_create(connector, entry);
6ee73861
BS		 519 break;
520 case OUTPUT_ANALOG:
8f1a6086 521 nv50_dac_create(connector, entry);
6ee73861
BS		 522 break;
523 default:
524 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
525 continue;
526 }
6ee73861
BS		 527 }
528
8f1a6086
BS		 529 list_for_each_entry_safe(connector, ct,
530 &dev->mode_config.connector_list, head) {
531 if (!connector->encoder_ids[0]) {
532 NV_WARN(dev, "%s has no encoders, removing\n",
533 drm_get_connector_name(connector));
534 connector->funcs->destroy(connector);
535 }
6ee73861
BS		 536 }
537
538 ret = nv50_display_init(dev);
a1663ed3
BS		 539 if (ret) {
540 nv50_display_destroy(dev);
6ee73861 541 return ret;
a1663ed3 542 }
6ee73861
BS		 543
544 return 0;
545}
546
547int nv50_display_destroy(struct drm_device *dev)
548{
549 struct drm_nouveau_private *dev_priv = dev->dev_private;
550
ef2bb506 551 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 552
553 drm_mode_config_cleanup(dev);
554
555 nv50_display_disable(dev);
556 nv50_evo_channel_del(&dev_priv->evo);
557
558 return 0;
559}
560
87c0e0e5
BS		 561static u16
562nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
563 u32 mc, int pxclk)
6ee73861
BS		 564{
565 struct drm_nouveau_private *dev_priv = dev->dev_private;
75c722d7
BS		 566 struct nouveau_connector *nv_connector = NULL;
567 struct drm_encoder *encoder;
04a39c57 568 struct nvbios *bios = &dev_priv->vbios;
87c0e0e5 569 u32 script = 0, or;
6ee73861 570
75c722d7
BS		 571 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
572 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
573
87c0e0e5 574 if (nv_encoder->dcb != dcb)
75c722d7
BS		 575 continue;
576
577 nv_connector = nouveau_encoder_connector_get(nv_encoder);
578 break;
579 }
580
87c0e0e5
BS		 581 or = ffs(dcb->or) - 1;
582 switch (dcb->type) {
6ee73861
BS		 583 case OUTPUT_LVDS:
584 script = (mc >> 8) & 0xf;
04a39c57 585 if (bios->fp_no_ddc) {
6ee73861
BS		 586 if (bios->fp.dual_link)
587 script |= 0x0100;
588 if (bios->fp.if_is_24bit)
589 script |= 0x0200;
590 } else {
591 if (pxclk >= bios->fp.duallink_transition_clk) {
592 script |= 0x0100;
593 if (bios->fp.strapless_is_24bit & 2)
594 script |= 0x0200;
595 } else
596 if (bios->fp.strapless_is_24bit & 1)
597 script |= 0x0200;
75c722d7
BS		 598
599 if (nv_connector && nv_connector->edid &&
600 (nv_connector->edid->revision >= 4) &&
601 (nv_connector->edid->input & 0x70) >= 0x20)
602 script |= 0x0200;
6ee73861
BS		 603 }
604
605 if (nouveau_uscript_lvds >= 0) {
606 NV_INFO(dev, "override script 0x%04x with 0x%04x "
607 "for output LVDS-%d\n", script,
608 nouveau_uscript_lvds, or);
609 script = nouveau_uscript_lvds;
610 }
611 break;
612 case OUTPUT_TMDS:
613 script = (mc >> 8) & 0xf;
614 if (pxclk >= 165000)
615 script |= 0x0100;
616
617 if (nouveau_uscript_tmds >= 0) {
618 NV_INFO(dev, "override script 0x%04x with 0x%04x "
619 "for output TMDS-%d\n", script,
620 nouveau_uscript_tmds, or);
621 script = nouveau_uscript_tmds;
622 }
623 break;
624 case OUTPUT_DP:
625 script = (mc >> 8) & 0xf;
626 break;
627 case OUTPUT_ANALOG:
628 script = 0xff;
629 break;
630 default:
631 NV_ERROR(dev, "modeset on unsupported output type!\n");
632 break;
633 }
634
635 return script;
636}
637
638static void
639nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
640{
641 struct drm_nouveau_private *dev_priv = dev->dev_private;
642 struct nouveau_channel *chan;
643 struct list_head *entry, *tmp;
644
645 list_for_each_safe(entry, tmp, &dev_priv->vbl_waiting) {
646 chan = list_entry(entry, struct nouveau_channel, nvsw.vbl_wait);
647
648 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
649 chan->nvsw.vblsem_rval);
650 list_del(&chan->nvsw.vbl_wait);
651 }
652}
653
654static void
655nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
656{
657 intr &= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
658
659 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
660 nv50_display_vblank_crtc_handler(dev, 0);
661
662 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
663 nv50_display_vblank_crtc_handler(dev, 1);
664
665 nv_wr32(dev, NV50_PDISPLAY_INTR_EN, nv_rd32(dev,
666 NV50_PDISPLAY_INTR_EN) & ~intr);
667 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr);
668}
669
670static void
671nv50_display_unk10_handler(struct drm_device *dev)
672{
87c0e0e5
BS		 673 struct drm_nouveau_private *dev_priv = dev->dev_private;
674 u32 unk30 = nv_rd32(dev, 0x610030), mc;
675 int i, crtc, or, type = OUTPUT_ANY;
6ee73861 676
87c0e0e5
BS		 677 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
678 dev_priv->evo_irq.dcb = NULL;
6ee73861
BS		 679
680 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
681
87c0e0e5
BS		 682 /* Determine which CRTC we're dealing with, only 1 ever will be
683 * signalled at the same time with the current nouveau code.
684 */
685 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
686 if (crtc < 0)
687 goto ack;
688
689 /* Nothing needs to be done for the encoder */
690 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
691 if (crtc < 0)
692 goto ack;
6ee73861 693
87c0e0e5
BS		 694 /* Find which encoder was connected to the CRTC */
695 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
696 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
697 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
698 if (!(mc & (1 << crtc)))
699 continue;
700
701 switch ((mc & 0x00000f00) >> 8) {
702 case 0: type = OUTPUT_ANALOG; break;
703 case 1: type = OUTPUT_TV; break;
704 default:
705 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
706 goto ack;
707 }
708
709 or = i;
710 }
711
712 for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
713 if (dev_priv->chipset < 0x90 ||
714 dev_priv->chipset == 0x92 ||
715 dev_priv->chipset == 0xa0)
716 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
717 else
718 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
719
720 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
721 if (!(mc & (1 << crtc)))
722 continue;
723
724 switch ((mc & 0x00000f00) >> 8) {
725 case 0: type = OUTPUT_LVDS; break;
726 case 1: type = OUTPUT_TMDS; break;
727 case 2: type = OUTPUT_TMDS; break;
728 case 5: type = OUTPUT_TMDS; break;
729 case 8: type = OUTPUT_DP; break;
730 case 9: type = OUTPUT_DP; break;
731 default:
732 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
733 goto ack;
734 }
735
736 or = i;
737 }
738
739 /* There was no encoder to disable */
740 if (type == OUTPUT_ANY)
741 goto ack;
742
743 /* Disable the encoder */
744 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
745 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
746
747 if (dcb->type == type && (dcb->or & (1 << or))) {
748 nouveau_bios_run_display_table(dev, dcb, 0, -1);
749 dev_priv->evo_irq.dcb = dcb;
750 goto ack;
751 }
752 }
753
754 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
6ee73861
BS		 755ack:
756 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
757 nv_wr32(dev, 0x610030, 0x80000000);
758}
759
afa3b4c3
BS		 760static void
761nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
762{
763 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
764 struct drm_encoder *encoder;
765 uint32_t tmp, unk0 = 0, unk1 = 0;
766
767 if (dcb->type != OUTPUT_DP)
768 return;
769
770 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
771 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
772
773 if (nv_encoder->dcb == dcb) {
774 unk0 = nv_encoder->dp.unk0;
775 unk1 = nv_encoder->dp.unk1;
776 break;
777 }
778 }
779
780 if (unk0 || unk1) {
781 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
782 tmp &= 0xfffffe03;
783 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
784
785 tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
786 tmp &= 0xfef080c0;
787 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
788 }
789}
790
7149eee8
BS		 791/* If programming a TMDS output on a SOR that can also be configured for
792 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
793 *
794 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
795 * the VBIOS scripts on at least one board I have only switch it off on
796 * link 0, causing a blank display if the output has previously been
797 * programmed for DisplayPort.
798 */
799static void
800nv50_display_unk20_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
801{
802 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
803 struct drm_encoder *encoder;
804 u32 tmp;
805
806 if (dcb->type != OUTPUT_TMDS)
807 return;
808
809 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
810 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
811
946cbc82
BS		 812 if (nv_encoder->dcb->type == OUTPUT_DP &&
813 nv_encoder->dcb->or & (1 << or)) {
7149eee8
BS		 814 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
815 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
816 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
817 break;
818 }
819 }
820}
821
6ee73861
BS		 822static void
823nv50_display_unk20_handler(struct drm_device *dev)
824{
87c0e0e5
BS		 825 struct drm_nouveau_private *dev_priv = dev->dev_private;
826 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc;
827 struct dcb_entry *dcb;
828 int i, crtc, or, type = OUTPUT_ANY;
6ee73861 829
87c0e0e5
BS		 830 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
831 dcb = dev_priv->evo_irq.dcb;
832 if (dcb) {
833 nouveau_bios_run_display_table(dev, dcb, 0, -2);
834 dev_priv->evo_irq.dcb = NULL;
835 }
836
837 /* CRTC clock change requested? */
838 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
839 if (crtc >= 0) {
840 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
841 pclk &= 0x003fffff;
842
843 nv50_crtc_set_clock(dev, crtc, pclk);
844
845 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
846 tmp &= ~0x000000f;
847 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
848 }
849
850 /* Nothing needs to be done for the encoder */
851 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
852 if (crtc < 0)
6ee73861 853 goto ack;
87c0e0e5 854 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
6ee73861 855
87c0e0e5
BS		 856 /* Find which encoder is connected to the CRTC */
857 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
858 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
859 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
860 if (!(mc & (1 << crtc)))
861 continue;
6ee73861 862
87c0e0e5
BS		 863 switch ((mc & 0x00000f00) >> 8) {
864 case 0: type = OUTPUT_ANALOG; break;
865 case 1: type = OUTPUT_TV; break;
866 default:
867 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
868 goto ack;
869 }
870
871 or = i;
872 }
873
874 for (i = 0; type == OUTPUT_ANY && i < 4; i++) {
875 if (dev_priv->chipset < 0x90 ||
876 dev_priv->chipset == 0x92 ||
877 dev_priv->chipset == 0xa0)
878 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
879 else
880 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
881
882 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
883 if (!(mc & (1 << crtc)))
884 continue;
885
886 switch ((mc & 0x00000f00) >> 8) {
887 case 0: type = OUTPUT_LVDS; break;
888 case 1: type = OUTPUT_TMDS; break;
889 case 2: type = OUTPUT_TMDS; break;
890 case 5: type = OUTPUT_TMDS; break;
891 case 8: type = OUTPUT_DP; break;
892 case 9: type = OUTPUT_DP; break;
893 default:
894 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
895 goto ack;
896 }
6ee73861 897
87c0e0e5
BS		 898 or = i;
899 }
6ee73861 900
87c0e0e5
BS		 901 if (type == OUTPUT_ANY)
902 goto ack;
6ee73861 903
87c0e0e5
BS		 904 /* Enable the encoder */
905 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
906 dcb = &dev_priv->vbios.dcb.entry[i];
907 if (dcb->type == type && (dcb->or & (1 << or)))
908 break;
909 }
afa3b4c3 910
87c0e0e5
BS		 911 if (i == dev_priv->vbios.dcb.entries) {
912 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
913 goto ack;
914 }
915
916 script = nv50_display_script_select(dev, dcb, mc, pclk);
917 nouveau_bios_run_display_table(dev, dcb, script, pclk);
6ee73861 918
87c0e0e5
BS		 919 nv50_display_unk20_dp_hack(dev, dcb);
920 nv50_display_unk20_dp_set_tmds(dev, dcb);
921
922 if (dcb->type != OUTPUT_ANALOG) {
6ee73861
BS		 923 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
924 tmp &= ~0x00000f0f;
925 if (script & 0x0100)
926 tmp |= 0x00000101;
927 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
928 } else {
929 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
930 }
931
87c0e0e5
BS		 932 dev_priv->evo_irq.dcb = dcb;
933 dev_priv->evo_irq.pclk = pclk;
934 dev_priv->evo_irq.script = script;
935
6ee73861
BS		 936ack:
937 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
938 nv_wr32(dev, 0x610030, 0x80000000);
939}
940
941static void
942nv50_display_unk40_handler(struct drm_device *dev)
943{
87c0e0e5
BS		 944 struct drm_nouveau_private *dev_priv = dev->dev_private;
945 struct dcb_entry *dcb = dev_priv->evo_irq.dcb;
946 u16 script = dev_priv->evo_irq.script;
947 u32 unk30 = nv_rd32(dev, 0x610030), pclk = dev_priv->evo_irq.pclk;
6ee73861 948
87c0e0e5
BS		 949 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
950 dev_priv->evo_irq.dcb = NULL;
951 if (!dcb)
6ee73861 952 goto ack;
6ee73861 953
87c0e0e5 954 nouveau_bios_run_display_table(dev, dcb, script, -pclk);
6ee73861
BS		 955ack:
956 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
957 nv_wr32(dev, 0x610030, 0x80000000);
958 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
959}
960
961void
962nv50_display_irq_handler_bh(struct work_struct *work)
963{
964 struct drm_nouveau_private *dev_priv =
965 container_of(work, struct drm_nouveau_private, irq_work);
966 struct drm_device *dev = dev_priv->dev;
967
968 for (;;) {
969 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
970 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
971
ef2bb506 972 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
6ee73861
BS		 973
974 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
975 nv50_display_unk10_handler(dev);
976 else
977 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
978 nv50_display_unk20_handler(dev);
979 else
980 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
981 nv50_display_unk40_handler(dev);
982 else
983 break;
984 }
985
986 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
987}
988
989static void
990nv50_display_error_handler(struct drm_device *dev)
991{
992 uint32_t addr, data;
993
994 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000);
995 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR);
996 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA);
997
998 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x (0x%04x 0x%02x)\n",
999 0, addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
1000
1001 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
1002}
1003
a5acac66
BS		 1004void
1005nv50_display_irq_hotplug_bh(struct work_struct *work)
6ee73861 1006{
a5acac66
BS		 1007 struct drm_nouveau_private *dev_priv =
1008 container_of(work, struct drm_nouveau_private, hpd_work);
1009 struct drm_device *dev = dev_priv->dev;
6ee73861
BS		 1010 struct drm_connector *connector;
1011 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
1012 uint32_t unplug_mask, plug_mask, change_mask;
1013 uint32_t hpd0, hpd1 = 0;
1014
1015 hpd0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
1016 if (dev_priv->chipset >= 0x90)
1017 hpd1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
1018
1019 plug_mask = (hpd0 & 0x0000ffff) | (hpd1 << 16);
1020 unplug_mask = (hpd0 >> 16) | (hpd1 & 0xffff0000);
1021 change_mask = plug_mask | unplug_mask;
1022
1023 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1024 struct drm_encoder_helper_funcs *helper;
1025 struct nouveau_connector *nv_connector =
1026 nouveau_connector(connector);
1027 struct nouveau_encoder *nv_encoder;
1028 struct dcb_gpio_entry *gpio;
1029 uint32_t reg;
1030 bool plugged;
1031
1032 if (!nv_connector->dcb)
1033 continue;
1034
1035 gpio = nouveau_bios_gpio_entry(dev, nv_connector->dcb->gpio_tag);
1036 if (!gpio || !(change_mask & (1 << gpio->line)))
1037 continue;
1038
1039 reg = nv_rd32(dev, gpio_reg[gpio->line >> 3]);
1040 plugged = !!(reg & (4 << ((gpio->line & 7) << 2)));
1041 NV_INFO(dev, "%splugged %s\n", plugged ? "" : "un",
1042 drm_get_connector_name(connector)) ;
1043
1044 if (!connector->encoder || !connector->encoder->crtc ||
1045 !connector->encoder->crtc->enabled)
1046 continue;
1047 nv_encoder = nouveau_encoder(connector->encoder);
1048 helper = connector->encoder->helper_private;
1049
1050 if (nv_encoder->dcb->type != OUTPUT_DP)
1051 continue;
1052
1053 if (plugged)
1054 helper->dpms(connector->encoder, DRM_MODE_DPMS_ON);
1055 else
1056 helper->dpms(connector->encoder, DRM_MODE_DPMS_OFF);
1057 }
1058
1059 nv_wr32(dev, 0xe054, nv_rd32(dev, 0xe054));
1060 if (dev_priv->chipset >= 0x90)
1061 nv_wr32(dev, 0xe074, nv_rd32(dev, 0xe074));
4abe3520 1062
eb1f8e4f 1063 drm_helper_hpd_irq_event(dev);
6ee73861
BS		 1064}
1065
1066void
1067nv50_display_irq_handler(struct drm_device *dev)
1068{
1069 struct drm_nouveau_private *dev_priv = dev->dev_private;
1070 uint32_t delayed = 0;
1071
a5acac66
BS		 1072 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
1073 if (!work_pending(&dev_priv->hpd_work))
1074 queue_work(dev_priv->wq, &dev_priv->hpd_work);
1075 }
6ee73861
BS		 1076
1077 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
1078 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
1079 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
1080 uint32_t clock;
1081
ef2bb506 1082 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
6ee73861
BS		 1083
1084 if (!intr0 && !(intr1 & ~delayed))
1085 break;
1086
1087 if (intr0 & 0x00010000) {
1088 nv50_display_error_handler(dev);
1089 intr0 &= ~0x00010000;
1090 }
1091
1092 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
1093 nv50_display_vblank_handler(dev, intr1);
1094 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
1095 }
1096
1097 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
1098 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
1099 NV50_PDISPLAY_INTR_1_CLK_UNK40));
1100 if (clock) {
1101 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
1102 if (!work_pending(&dev_priv->irq_work))
1103 queue_work(dev_priv->wq, &dev_priv->irq_work);
1104 delayed |= clock;
1105 intr1 &= ~clock;
1106 }
1107
1108 if (intr0) {
1109 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
1110 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1111 }
1112
1113 if (intr1) {
1114 NV_ERROR(dev,
1115 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1116 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1117 }
1118 }
1119}
1120
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