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Merge branch 'flock' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/bkl
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv50_crtc.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drmP.h"
28#include "drm_mode.h"
29#include "drm_crtc_helper.h"
30
31#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
32#include "nouveau_reg.h"
33#include "nouveau_drv.h"
34#include "nouveau_hw.h"
35#include "nouveau_encoder.h"
36#include "nouveau_crtc.h"
37#include "nouveau_fb.h"
38#include "nouveau_connector.h"
39#include "nv50_display.h"
40
41static void
42nv50_crtc_lut_load(struct drm_crtc *crtc)
43{
44 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
46 int i;
47
ef2bb506 48 NV_DEBUG_KMS(crtc->dev, "\n");
6ee73861
BS		 49
50 for (i = 0; i < 256; i++) {
51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
52 writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2);
53 writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4);
54 }
55
56 if (nv_crtc->lut.depth == 30) {
57 writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0);
58 writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2);
59 writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4);
60 }
61}
62
63int
64nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
65{
66 struct drm_device *dev = nv_crtc->base.dev;
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nouveau_channel *evo = dev_priv->evo;
69 int index = nv_crtc->index, ret;
70
ef2bb506
MM		 71 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
72 NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
6ee73861
BS		 73
74 if (blanked) {
75 nv_crtc->cursor.hide(nv_crtc, false);
76
77 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5);
78 if (ret) {
79 NV_ERROR(dev, "no space while blanking crtc\n");
80 return ret;
81 }
82 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
83 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
84 OUT_RING(evo, 0);
85 if (dev_priv->chipset != 0x50) {
86 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
87 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
88 }
89
90 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
91 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
92 } else {
93 if (nv_crtc->cursor.visible)
94 nv_crtc->cursor.show(nv_crtc, false);
95 else
96 nv_crtc->cursor.hide(nv_crtc, false);
97
98 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8);
99 if (ret) {
100 NV_ERROR(dev, "no space while unblanking crtc\n");
101 return ret;
102 }
103 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
104 OUT_RING(evo, nv_crtc->lut.depth == 8 ?
105 NV50_EVO_CRTC_CLUT_MODE_OFF :
106 NV50_EVO_CRTC_CLUT_MODE_ON);
d961db75 107 OUT_RING(evo, (nv_crtc->lut.nvbo->bo.mem.start << PAGE_SHIFT) >> 8);
6ee73861
BS		 108 if (dev_priv->chipset != 0x50) {
109 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
110 OUT_RING(evo, NvEvoVRAM);
111 }
112
113 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2);
114 OUT_RING(evo, nv_crtc->fb.offset >> 8);
115 OUT_RING(evo, 0);
116 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
117 if (dev_priv->chipset != 0x50)
118 if (nv_crtc->fb.tile_flags == 0x7a00)
119 OUT_RING(evo, NvEvoFB32);
120 else
121 if (nv_crtc->fb.tile_flags == 0x7000)
122 OUT_RING(evo, NvEvoFB16);
123 else
124 OUT_RING(evo, NvEvoVRAM);
125 else
126 OUT_RING(evo, NvEvoVRAM);
127 }
128
129 nv_crtc->fb.blanked = blanked;
130 return 0;
131}
132
133static int
134nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
135{
136 struct drm_device *dev = nv_crtc->base.dev;
137 struct drm_nouveau_private *dev_priv = dev->dev_private;
138 struct nouveau_channel *evo = dev_priv->evo;
139 int ret;
140
ef2bb506 141 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 142
143 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
144 if (ret) {
145 NV_ERROR(dev, "no space while setting dither\n");
146 return ret;
147 }
148
149 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DITHER_CTRL), 1);
150 if (on)
151 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_ON);
152 else
153 OUT_RING(evo, NV50_EVO_CRTC_DITHER_CTRL_OFF);
154
155 if (update) {
156 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
157 OUT_RING(evo, 0);
158 FIRE_RING(evo);
159 }
160
161 return 0;
162}
163
164struct nouveau_connector *
165nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
166{
167 struct drm_device *dev = nv_crtc->base.dev;
168 struct drm_connector *connector;
169 struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
170
171 /* The safest approach is to find an encoder with the right crtc, that
172 * is also linked to a connector. */
173 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
174 if (connector->encoder)
175 if (connector->encoder->crtc == crtc)
176 return nouveau_connector(connector);
177 }
178
179 return NULL;
180}
181
182static int
183nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, int scaling_mode, bool update)
184{
185 struct nouveau_connector *nv_connector =
186 nouveau_crtc_connector_get(nv_crtc);
187 struct drm_device *dev = nv_crtc->base.dev;
188 struct drm_nouveau_private *dev_priv = dev->dev_private;
189 struct nouveau_channel *evo = dev_priv->evo;
190 struct drm_display_mode *native_mode = NULL;
191 struct drm_display_mode *mode = &nv_crtc->base.mode;
192 uint32_t outX, outY, horiz, vert;
193 int ret;
194
ef2bb506 195 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 196
197 switch (scaling_mode) {
198 case DRM_MODE_SCALE_NONE:
199 break;
200 default:
201 if (!nv_connector || !nv_connector->native_mode) {
202 NV_ERROR(dev, "No native mode, forcing panel scaling\n");
203 scaling_mode = DRM_MODE_SCALE_NONE;
204 } else {
205 native_mode = nv_connector->native_mode;
206 }
207 break;
208 }
209
210 switch (scaling_mode) {
211 case DRM_MODE_SCALE_ASPECT:
212 horiz = (native_mode->hdisplay << 19) / mode->hdisplay;
213 vert = (native_mode->vdisplay << 19) / mode->vdisplay;
214
215 if (vert > horiz) {
216 outX = (mode->hdisplay * horiz) >> 19;
217 outY = (mode->vdisplay * horiz) >> 19;
218 } else {
219 outX = (mode->hdisplay * vert) >> 19;
220 outY = (mode->vdisplay * vert) >> 19;
221 }
222 break;
223 case DRM_MODE_SCALE_FULLSCREEN:
224 outX = native_mode->hdisplay;
225 outY = native_mode->vdisplay;
226 break;
227 case DRM_MODE_SCALE_CENTER:
228 case DRM_MODE_SCALE_NONE:
229 default:
230 outX = mode->hdisplay;
231 outY = mode->vdisplay;
232 break;
233 }
234
235 ret = RING_SPACE(evo, update ? 7 : 5);
236 if (ret)
237 return ret;
238
239 /* Got a better name for SCALER_ACTIVE? */
240 /* One day i've got to really figure out why this is needed. */
241 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1);
242 if ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ||
243 (mode->flags & DRM_MODE_FLAG_INTERLACE) ||
244 mode->hdisplay != outX || mode->vdisplay != outY) {
245 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_ACTIVE);
246 } else {
247 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CTRL_INACTIVE);
248 }
249
250 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2);
251 OUT_RING(evo, outY << 16 | outX);
252 OUT_RING(evo, outY << 16 | outX);
253
254 if (update) {
255 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
256 OUT_RING(evo, 0);
257 FIRE_RING(evo);
258 }
259
260 return 0;
261}
262
263int
264nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
265{
1ac7b528 266 struct drm_nouveau_private *dev_priv = dev->dev_private;
e9ebb68b 267 struct pll_lims pll;
5b32165b 268 uint32_t reg1, reg2;
e9ebb68b 269 int ret, N1, M1, N2, M2, P;
6ee73861 270
5b32165b 271 ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll);
6ee73861
BS		 272 if (ret)
273 return ret;
274
e9ebb68b
BS		 275 if (pll.vco2.maxfreq) {
276 ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
277 if (ret <= 0)
278 return 0;
6ee73861 279
17b96cc3 280 NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
e9ebb68b
BS		 281 pclk, ret, N1, M1, N2, M2, P);
282
5b32165b
BS		 283 reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00;
284 reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00;
285 nv_wr32(dev, pll.reg + 0, 0x10000611);
286 nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1);
287 nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
1ac7b528
BS		 288 } else
289 if (dev_priv->chipset < NV_C0) {
e9ebb68b
BS		 290 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
291 if (ret <= 0)
292 return 0;
293
294 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
295 pclk, ret, N1, N2, M1, P);
17b96cc3 296
5b32165b
BS		 297 reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000;
298 nv_wr32(dev, pll.reg + 0, 0x50000610);
299 nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
300 nv_wr32(dev, pll.reg + 8, N2);
1ac7b528
BS		 301 } else {
302 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
303 if (ret <= 0)
304 return 0;
305
306 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
307 pclk, ret, N1, N2, M1, P);
308
5b32165b
BS		 309 nv_mask(dev, pll.reg + 0x0c, 0x00000000, 0x00000100);
310 nv_wr32(dev, pll.reg + 0x04, (P << 16) | (N1 << 8) | M1);
311 nv_wr32(dev, pll.reg + 0x10, N2 << 16);
6ee73861
BS		 312 }
313
314 return 0;
315}
316
317static void
318nv50_crtc_destroy(struct drm_crtc *crtc)
319{
dd19e44b
MS		 320 struct drm_device *dev;
321 struct nouveau_crtc *nv_crtc;
6ee73861
BS		 322
323 if (!crtc)
324 return;
325
dd19e44b
MS		 326 dev = crtc->dev;
327 nv_crtc = nouveau_crtc(crtc);
328
329 NV_DEBUG_KMS(dev, "\n");
330
6ee73861
BS		 331 drm_crtc_cleanup(&nv_crtc->base);
332
333 nv50_cursor_fini(nv_crtc);
334
9d59e8a1 335 nouveau_bo_unmap(nv_crtc->lut.nvbo);
6ee73861 336 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
9d59e8a1 337 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
6ee73861
BS		 338 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
339 kfree(nv_crtc->mode);
340 kfree(nv_crtc);
341}
342
343int
344nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
345 uint32_t buffer_handle, uint32_t width, uint32_t height)
346{
347 struct drm_device *dev = crtc->dev;
348 struct drm_nouveau_private *dev_priv = dev->dev_private;
349 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
350 struct nouveau_bo *cursor = NULL;
351 struct drm_gem_object *gem;
352 int ret = 0, i;
353
354 if (width != 64 || height != 64)
355 return -EINVAL;
356
357 if (!buffer_handle) {
358 nv_crtc->cursor.hide(nv_crtc, true);
359 return 0;
360 }
361
362 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
363 if (!gem)
bf79cb91 364 return -ENOENT;
6ee73861
BS		 365 cursor = nouveau_gem_object(gem);
366
367 ret = nouveau_bo_map(cursor);
368 if (ret)
369 goto out;
370
371 /* The simple will do for now. */
372 for (i = 0; i < 64 * 64; i++)
373 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i));
374
375 nouveau_bo_unmap(cursor);
376
377 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset -
378 dev_priv->vm_vram_base);
379 nv_crtc->cursor.show(nv_crtc, true);
380
381out:
bc9025bd 382 drm_gem_object_unreference_unlocked(gem);
6ee73861
BS		 383 return ret;
384}
385
386int
387nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
388{
389 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
390
391 nv_crtc->cursor.set_pos(nv_crtc, x, y);
392 return 0;
393}
394
395static void
396nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
7203425a 397 uint32_t start, uint32_t size)
6ee73861 398{
7203425a 399 int end = (start + size > 256) ? 256 : start + size, i;
6ee73861 400 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
6ee73861 401
7203425a 402 for (i = start; i < end; i++) {
6ee73861
BS		 403 nv_crtc->lut.r[i] = r[i];
404 nv_crtc->lut.g[i] = g[i];
405 nv_crtc->lut.b[i] = b[i];
406 }
407
408 /* We need to know the depth before we upload, but it's possible to
409 * get called before a framebuffer is bound. If this is the case,
410 * mark the lut values as dirty by setting depth==0, and it'll be
411 * uploaded on the first mode_set_base()
412 */
413 if (!nv_crtc->base.fb) {
414 nv_crtc->lut.depth = 0;
415 return;
416 }
417
418 nv50_crtc_lut_load(crtc);
419}
420
421static void
422nv50_crtc_save(struct drm_crtc *crtc)
423{
424 NV_ERROR(crtc->dev, "!!\n");
425}
426
427static void
428nv50_crtc_restore(struct drm_crtc *crtc)
429{
430 NV_ERROR(crtc->dev, "!!\n");
431}
432
433static const struct drm_crtc_funcs nv50_crtc_funcs = {
434 .save = nv50_crtc_save,
435 .restore = nv50_crtc_restore,
436 .cursor_set = nv50_crtc_cursor_set,
437 .cursor_move = nv50_crtc_cursor_move,
438 .gamma_set = nv50_crtc_gamma_set,
439 .set_config = drm_crtc_helper_set_config,
440 .destroy = nv50_crtc_destroy,
441};
442
443static void
444nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
445{
446}
447
448static void
449nv50_crtc_prepare(struct drm_crtc *crtc)
450{
451 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
452 struct drm_device *dev = crtc->dev;
6ee73861 453
ef2bb506 454 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
6ee73861 455
6ee73861
BS		 456 nv50_crtc_blank(nv_crtc, true);
457}
458
459static void
460nv50_crtc_commit(struct drm_crtc *crtc)
461{
6ee73861
BS		 462 struct drm_device *dev = crtc->dev;
463 struct drm_nouveau_private *dev_priv = dev->dev_private;
464 struct nouveau_channel *evo = dev_priv->evo;
465 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
466 int ret;
467
ef2bb506 468 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
6ee73861
BS		 469
470 nv50_crtc_blank(nv_crtc, false);
471
6ee73861
BS		 472 ret = RING_SPACE(evo, 2);
473 if (ret) {
474 NV_ERROR(dev, "no space while committing crtc\n");
475 return;
476 }
477 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
835aadbe
BS		 478 OUT_RING (evo, 0);
479 FIRE_RING (evo);
6ee73861
BS		 480}
481
482static bool
483nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
484 struct drm_display_mode *adjusted_mode)
485{
486 return true;
487}
488
489static int
be64c2bb
CB		 490nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
491 struct drm_framebuffer *passed_fb,
492 int x, int y, bool update, bool atomic)
6ee73861
BS		 493{
494 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
495 struct drm_device *dev = nv_crtc->base.dev;
496 struct drm_nouveau_private *dev_priv = dev->dev_private;
497 struct nouveau_channel *evo = dev_priv->evo;
498 struct drm_framebuffer *drm_fb = nv_crtc->base.fb;
499 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
500 int ret, format;
501
ef2bb506 502 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
6ee73861 503
be64c2bb
CB		 504 /* If atomic, we want to switch to the fb we were passed, so
505 * now we update pointers to do that. (We don't pin; just
506 * assume we're already pinned and update the base address.)
507 */
508 if (atomic) {
509 drm_fb = passed_fb;
510 fb = nouveau_framebuffer(passed_fb);
511 }
512 else {
513 /* If not atomic, we can go ahead and pin, and unpin the
514 * old fb we were passed.
515 */
516 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
517 if (ret)
518 return ret;
519
520 if (passed_fb) {
521 struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
522 nouveau_bo_unpin(ofb->nvbo);
523 }
524 }
525
6ee73861
BS		 526 switch (drm_fb->depth) {
527 case 8:
528 format = NV50_EVO_CRTC_FB_DEPTH_8;
529 break;
530 case 15:
531 format = NV50_EVO_CRTC_FB_DEPTH_15;
532 break;
533 case 16:
534 format = NV50_EVO_CRTC_FB_DEPTH_16;
535 break;
536 case 24:
537 case 32:
538 format = NV50_EVO_CRTC_FB_DEPTH_24;
539 break;
540 case 30:
541 format = NV50_EVO_CRTC_FB_DEPTH_30;
542 break;
543 default:
544 NV_ERROR(dev, "unknown depth %d\n", drm_fb->depth);
545 return -EINVAL;
546 }
547
6ee73861
BS		 548 nv_crtc->fb.offset = fb->nvbo->bo.offset - dev_priv->vm_vram_base;
549 nv_crtc->fb.tile_flags = fb->nvbo->tile_flags;
550 nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
551 if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) {
552 ret = RING_SPACE(evo, 2);
553 if (ret)
554 return ret;
555
556 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
557 if (nv_crtc->fb.tile_flags == 0x7a00)
558 OUT_RING(evo, NvEvoFB32);
559 else
560 if (nv_crtc->fb.tile_flags == 0x7000)
561 OUT_RING(evo, NvEvoFB16);
562 else
563 OUT_RING(evo, NvEvoVRAM);
564 }
565
566 ret = RING_SPACE(evo, 12);
567 if (ret)
568 return ret;
569
570 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5);
571 OUT_RING(evo, nv_crtc->fb.offset >> 8);
572 OUT_RING(evo, 0);
573 OUT_RING(evo, (drm_fb->height << 16) | drm_fb->width);
574 if (!nv_crtc->fb.tile_flags) {
575 OUT_RING(evo, drm_fb->pitch | (1 << 20));
576 } else {
577 OUT_RING(evo, ((drm_fb->pitch / 4) << 4) |
578 fb->nvbo->tile_mode);
579 }
580 if (dev_priv->chipset == 0x50)
581 OUT_RING(evo, (fb->nvbo->tile_flags << 8) | format);
582 else
583 OUT_RING(evo, format);
584
585 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1);
586 OUT_RING(evo, fb->base.depth == 8 ?
587 NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON);
588
589 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
590 OUT_RING(evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
591 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
592 OUT_RING(evo, (y << 16) | x);
593
594 if (nv_crtc->lut.depth != fb->base.depth) {
595 nv_crtc->lut.depth = fb->base.depth;
596 nv50_crtc_lut_load(crtc);
597 }
598
599 if (update) {
600 ret = RING_SPACE(evo, 2);
601 if (ret)
602 return ret;
603 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
604 OUT_RING(evo, 0);
605 FIRE_RING(evo);
606 }
607
608 return 0;
609}
610
611static int
612nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
613 struct drm_display_mode *adjusted_mode, int x, int y,
614 struct drm_framebuffer *old_fb)
615{
616 struct drm_device *dev = crtc->dev;
617 struct drm_nouveau_private *dev_priv = dev->dev_private;
618 struct nouveau_channel *evo = dev_priv->evo;
619 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
620 struct nouveau_connector *nv_connector = NULL;
621 uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end;
622 uint32_t hunk1, vunk1, vunk2a, vunk2b;
623 int ret;
624
625 /* Find the connector attached to this CRTC */
626 nv_connector = nouveau_crtc_connector_get(nv_crtc);
627
628 *nv_crtc->mode = *adjusted_mode;
629
ef2bb506 630 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
6ee73861
BS		 631
632 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
633 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
634 hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start;
635 vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start;
636 /* I can't give this a proper name, anyone else can? */
637 hunk1 = adjusted_mode->htotal -
638 adjusted_mode->hsync_start + adjusted_mode->hdisplay;
639 vunk1 = adjusted_mode->vtotal -
640 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
641 /* Another strange value, this time only for interlaced adjusted_modes. */
642 vunk2a = 2 * adjusted_mode->vtotal -
643 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
644 vunk2b = adjusted_mode->vtotal -
645 adjusted_mode->vsync_start + adjusted_mode->vtotal;
646
647 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
648 vsync_dur /= 2;
649 vsync_start_to_end /= 2;
650 vunk1 /= 2;
651 vunk2a /= 2;
652 vunk2b /= 2;
653 /* magic */
654 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
655 vsync_start_to_end -= 1;
656 vunk1 -= 1;
657 vunk2a -= 1;
658 vunk2b -= 1;
659 }
660 }
661
662 ret = RING_SPACE(evo, 17);
663 if (ret)
664 return ret;
665
666 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2);
667 OUT_RING(evo, adjusted_mode->clock | 0x800000);
668 OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0);
669
670 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5);
671 OUT_RING(evo, 0);
672 OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal);
673 OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1));
674 OUT_RING(evo, (vsync_start_to_end - 1) << 16 |
675 (hsync_start_to_end - 1));
676 OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1));
677
678 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
679 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1);
680 OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1));
681 } else {
682 OUT_RING(evo, 0);
683 OUT_RING(evo, 0);
684 }
685
686 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
687 OUT_RING(evo, 0);
688
689 /* This is the actual resolution of the mode. */
690 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
691 OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay);
692 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1);
693 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0));
694
695 nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false);
696 nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false);
697
be64c2bb 698 return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false, false);
6ee73861
BS		 699}
700
701static int
702nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
703 struct drm_framebuffer *old_fb)
704{
be64c2bb
CB		 705 return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, true, false);
706}
707
708static int
709nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
710 struct drm_framebuffer *fb,
21c74a8e 711 int x, int y, enum mode_set_atomic state)
be64c2bb
CB		 712{
713 return nv50_crtc_do_mode_set_base(crtc, fb, x, y, true, true);
6ee73861
BS		 714}
715
716static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
717 .dpms = nv50_crtc_dpms,
718 .prepare = nv50_crtc_prepare,
719 .commit = nv50_crtc_commit,
720 .mode_fixup = nv50_crtc_mode_fixup,
721 .mode_set = nv50_crtc_mode_set,
722 .mode_set_base = nv50_crtc_mode_set_base,
be64c2bb 723 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
6ee73861
BS		 724 .load_lut = nv50_crtc_lut_load,
725};
726
727int
728nv50_crtc_create(struct drm_device *dev, int index)
729{
730 struct nouveau_crtc *nv_crtc = NULL;
731 int ret, i;
732
ef2bb506 733 NV_DEBUG_KMS(dev, "\n");
6ee73861
BS		 734
735 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
736 if (!nv_crtc)
737 return -ENOMEM;
738
739 nv_crtc->mode = kzalloc(sizeof(*nv_crtc->mode), GFP_KERNEL);
740 if (!nv_crtc->mode) {
741 kfree(nv_crtc);
742 return -ENOMEM;
743 }
744
745 /* Default CLUT parameters, will be activated on the hw upon
746 * first mode set.
747 */
748 for (i = 0; i < 256; i++) {
749 nv_crtc->lut.r[i] = i << 8;
750 nv_crtc->lut.g[i] = i << 8;
751 nv_crtc->lut.b[i] = i << 8;
752 }
753 nv_crtc->lut.depth = 0;
754
755 ret = nouveau_bo_new(dev, NULL, 4096, 0x100, TTM_PL_FLAG_VRAM,
756 0, 0x0000, false, true, &nv_crtc->lut.nvbo);
757 if (!ret) {
758 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
759 if (!ret)
760 ret = nouveau_bo_map(nv_crtc->lut.nvbo);
761 if (ret)
762 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
763 }
764
765 if (ret) {
766 kfree(nv_crtc->mode);
767 kfree(nv_crtc);
768 return ret;
769 }
770
771 nv_crtc->index = index;
772
773 /* set function pointers */
774 nv_crtc->set_dither = nv50_crtc_set_dither;
775 nv_crtc->set_scale = nv50_crtc_set_scale;
776
777 drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs);
778 drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs);
779 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
780
781 ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
782 0, 0x0000, false, true, &nv_crtc->cursor.nvbo);
783 if (!ret) {
784 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
785 if (!ret)
786 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
787 if (ret)
788 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
789 }
790
791 nv50_cursor_init(nv_crtc);
792 return 0;
793}
Clone of davem's net-next-2.6 tree