[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv40_graph.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_grctx.h"

struct nouveau_channel *
nv40_graph_channel(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t inst;
	int i;

	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
		return NULL;
	inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;

	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
		struct nouveau_channel *chan = dev_priv->fifos[i];

		if (chan && chan->ramin_grctx &&
		    chan->ramin_grctx->instance == inst)
			return chan;
	}

	return NULL;
}

int
nv40_graph_create_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	int ret;

	ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
				     16, NVOBJ_FLAG_ZERO_ALLOC,
				     &chan->ramin_grctx);
	if (ret)
		return ret;

	/* Initialise default context values */
	dev_priv->engine.instmem.prepare_access(dev, true);
	if (!pgraph->ctxprog) {
		struct nouveau_grctx ctx = {};

		ctx.dev = chan->dev;
		ctx.mode = NOUVEAU_GRCTX_VALS;
		ctx.data = chan->ramin_grctx->gpuobj;
		nv40_grctx_init(&ctx);
	} else {
		nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
	}
	nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
		     chan->ramin_grctx->gpuobj->im_pramin->start);
	dev_priv->engine.instmem.finish_access(dev);
	return 0;
}

void
nv40_graph_destroy_context(struct nouveau_channel *chan)
{
	nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx);
}

static int
nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
{
	uint32_t old_cp, tv = 1000, tmp;
	int i;

	old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);

	tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
	tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
		      NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);

	tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
	tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);

	nouveau_wait_for_idle(dev);

	for (i = 0; i < tv; i++) {
		if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
			break;
	}

	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);

	if (i == tv) {
		uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
		NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
		NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
			 ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
			 ucstat  & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
		NV_ERROR(dev, "0x40030C = 0x%08x\n",
			 nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
		return -EBUSY;
	}

	return 0;
}

/* Restore the context for a specific channel into PGRAPH */
int
nv40_graph_load_context(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	uint32_t inst;
	int ret;

	if (!chan->ramin_grctx)
		return -EINVAL;
	inst = chan->ramin_grctx->instance >> 4;

	ret = nv40_graph_transfer_context(dev, inst, 0);
	if (ret)
		return ret;

	/* 0x40032C, no idea of it's exact function.  Could simply be a
	 * record of the currently active PGRAPH context.  It's currently
	 * unknown as to what bit 24 does.  The nv ddx has it set, so we will
	 * set it here too.
	 */
	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
		 (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
		  NV40_PGRAPH_CTXCTL_CUR_LOADED);
	/* 0x32E0 records the instance address of the active FIFO's PGRAPH
	 * context.  If at any time this doesn't match 0x40032C, you will
	 * recieve PGRAPH_INTR_CONTEXT_SWITCH
	 */
	nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
	return 0;
}

int
nv40_graph_unload_context(struct drm_device *dev)
{
	uint32_t inst;
	int ret;

	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
		return 0;
	inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;

	ret = nv40_graph_transfer_context(dev, inst, 1);

	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
	return ret;
}

void
nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
			     uint32_t size, uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	uint32_t limit = max(1u, addr + size) - 1;

	if (pitch)
		addr |= 1;

	switch (dev_priv->chipset) {
	case 0x44:
	case 0x4a:
	case 0x4e:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
		break;

	case 0x46:
	case 0x47:
	case 0x49:
	case 0x4b:
		nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
		nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
		nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
		break;

	default:
		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
		nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
		nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
		nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
		break;
	}
}

/*
 * G70		0x47
 * G71		0x49
 * NV45		0x48
 * G72[M]	0x46
 * G73		0x4b
 * C51_G7X	0x4c
 * C51		0x4e
 */
int
nv40_graph_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv =
		(struct drm_nouveau_private *)dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	uint32_t vramsz;
	int i, j;

	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
			~NV_PMC_ENABLE_PGRAPH);
	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
			 NV_PMC_ENABLE_PGRAPH);

	if (nouveau_ctxfw) {
		nouveau_grctx_prog_load(dev);
		dev_priv->engine.graph.grctx_size = 175 * 1024;
	}

	if (!dev_priv->engine.graph.ctxprog) {
		struct nouveau_grctx ctx = {};
		uint32_t cp[256];

		ctx.dev = dev;
		ctx.mode = NOUVEAU_GRCTX_PROG;
		ctx.data = cp;
		ctx.ctxprog_max = 256;
		nv40_grctx_init(&ctx);
		dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;

		nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
		for (i = 0; i < ctx.ctxprog_len; i++)
			nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
	}

	/* No context present currently */
	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);

	nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);

	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);

	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);

	j = nv_rd32(dev, 0x1540) & 0xff;
	if (j) {
		for (i = 0; !(j & 1); j >>= 1, i++)
			;
		nv_wr32(dev, 0x405000, i);
	}

	if (dev_priv->chipset == 0x40) {
		nv_wr32(dev, 0x4009b0, 0x83280fff);
		nv_wr32(dev, 0x4009b4, 0x000000a0);
	} else {
		nv_wr32(dev, 0x400820, 0x83280eff);
		nv_wr32(dev, 0x400824, 0x000000a0);
	}

	switch (dev_priv->chipset) {
	case 0x40:
	case 0x45:
		nv_wr32(dev, 0x4009b8, 0x0078e366);
		nv_wr32(dev, 0x4009bc, 0x0000014c);
		break;
	case 0x41:
	case 0x42: /* pciid also 0x00Cx */
	/* case 0x0120: XXX (pciid) */
		nv_wr32(dev, 0x400828, 0x007596ff);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x43:
		nv_wr32(dev, 0x400828, 0x0072cb77);
		nv_wr32(dev, 0x40082c, 0x00000108);
		break;
	case 0x44:
	case 0x46: /* G72 */
	case 0x4a:
	case 0x4c: /* G7x-based C51 */
	case 0x4e:
		nv_wr32(dev, 0x400860, 0);
		nv_wr32(dev, 0x400864, 0);
		break;
	case 0x47: /* G70 */
	case 0x49: /* G71 */
	case 0x4b: /* G73 */
		nv_wr32(dev, 0x400828, 0x07830610);
		nv_wr32(dev, 0x40082c, 0x0000016A);
		break;
	default:
		break;
	}

	nv_wr32(dev, 0x400b38, 0x2ffff800);
	nv_wr32(dev, 0x400b3c, 0x00006000);

	/* Turn all the tiling regions off. */
	for (i = 0; i < pfb->num_tiles; i++)
		nv40_graph_set_region_tiling(dev, i, 0, 0, 0);

	/* begin RAM config */
	vramsz = drm_get_resource_len(dev, 0) - 1;
	switch (dev_priv->chipset) {
	case 0x40:
		nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400820, 0);
		nv_wr32(dev, 0x400824, 0);
		nv_wr32(dev, 0x400864, vramsz);
		nv_wr32(dev, 0x400868, vramsz);
		break;
	default:
		switch (dev_priv->chipset) {
		case 0x46:
		case 0x47:
		case 0x49:
		case 0x4b:
			nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		default:
			nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
			nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
			break;
		}
		nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
		nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
		nv_wr32(dev, 0x400840, 0);
		nv_wr32(dev, 0x400844, 0);
		nv_wr32(dev, 0x4008A0, vramsz);
		nv_wr32(dev, 0x4008A4, vramsz);
		break;
	}

	return 0;
}

void nv40_graph_takedown(struct drm_device *dev)
{
	nouveau_grctx_fini(dev);
}

struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
	{ 0x0030, false, NULL }, /* null */
	{ 0x0039, false, NULL }, /* m2mf */
	{ 0x004a, false, NULL }, /* gdirect */
	{ 0x009f, false, NULL }, /* imageblit (nv12) */
	{ 0x008a, false, NULL }, /* ifc */
	{ 0x0089, false, NULL }, /* sifm */
	{ 0x3089, false, NULL }, /* sifm (nv40) */
	{ 0x0062, false, NULL }, /* surf2d */
	{ 0x3062, false, NULL }, /* surf2d (nv40) */
	{ 0x0043, false, NULL }, /* rop */
	{ 0x0012, false, NULL }, /* beta1 */
	{ 0x0072, false, NULL }, /* beta4 */
	{ 0x0019, false, NULL }, /* cliprect */
	{ 0x0044, false, NULL }, /* pattern */
	{ 0x309e, false, NULL }, /* swzsurf */
	{ 0x4097, false, NULL }, /* curie (nv40) */
	{ 0x4497, false, NULL }, /* curie (nv44) */
	{}
};
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
6ee73861 BS	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "nouveau_drv.h"
054b93e4	30	#include "nouveau_grctx.h"
6ee73861 BS	31
	32	struct nouveau_channel *
	33	nv40_graph_channel(struct drm_device *dev)
	34	{
	35	struct drm_nouveau_private *dev_priv = dev->dev_private;
	36	uint32_t inst;
	37	int i;
	38
	39	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
	40	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
	41	return NULL;
	42	inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
	43
	44	for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
	45	struct nouveau_channel *chan = dev_priv->fifos[i];
	46
	47	if (chan && chan->ramin_grctx &&
	48	chan->ramin_grctx->instance == inst)
	49	return chan;
	50	}
	51
	52	return NULL;
	53	}
	54
	55	int
	56	nv40_graph_create_context(struct nouveau_channel *chan)
	57	{
	58	struct drm_device *dev = chan->dev;
	59	struct drm_nouveau_private *dev_priv = dev->dev_private;
054b93e4	60	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
6ee73861 BS	61	int ret;
6ee73861 BS	62
054b93e4 BS	63	ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
	64	16, NVOBJ_FLAG_ZERO_ALLOC,
	65	&chan->ramin_grctx);
6ee73861 BS	66	if (ret)
6ee73861 BS	67	return ret;
6ee73861 BS	68
	69	/* Initialise default context values */
	70	dev_priv->engine.instmem.prepare_access(dev, true);
054b93e4 BS	71	if (!pgraph->ctxprog) {
054b93e4 BS	72	struct nouveau_grctx ctx = {};
6ee73861	73
054b93e4 BS	74	ctx.dev = chan->dev;
	75	ctx.mode = NOUVEAU_GRCTX_VALS;
	76	ctx.data = chan->ramin_grctx->gpuobj;
	77	nv40_grctx_init(&ctx);
	78	} else {
	79	nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
	80	}
	81	nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
	82	chan->ramin_grctx->gpuobj->im_pramin->start);
	83	dev_priv->engine.instmem.finish_access(dev);
6ee73861 BS	84	return 0;
	85	}
	86
	87	void
	88	nv40_graph_destroy_context(struct nouveau_channel *chan)
	89	{
	90	nouveau_gpuobj_ref_del(chan->dev, &chan->ramin_grctx);
	91	}
	92
	93	static int
	94	nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
	95	{
	96	uint32_t old_cp, tv = 1000, tmp;
	97	int i;
	98
	99	old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
	100	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
	101
	102	tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
	103	tmp \|= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
	104	NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
	105	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
	106
	107	tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
	108	tmp \|= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
	109	nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
	110
	111	nouveau_wait_for_idle(dev);
	112
	113	for (i = 0; i < tv; i++) {
	114	if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
	115	break;
	116	}
	117
	118	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
	119
	120	if (i == tv) {
	121	uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
	122	NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
	123	NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
	124	ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
	125	ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
	126	NV_ERROR(dev, "0x40030C = 0x%08x\n",
	127	nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
	128	return -EBUSY;
	129	}
	130
	131	return 0;
	132	}
	133
	134	/* Restore the context for a specific channel into PGRAPH */
	135	int
	136	nv40_graph_load_context(struct nouveau_channel *chan)
	137	{
	138	struct drm_device *dev = chan->dev;
	139	uint32_t inst;
	140	int ret;
	141
	142	if (!chan->ramin_grctx)
	143	return -EINVAL;
	144	inst = chan->ramin_grctx->instance >> 4;
	145
	146	ret = nv40_graph_transfer_context(dev, inst, 0);
	147	if (ret)
148	return ret;
149
150	/* 0x40032C, no idea of it's exact function. Could simply be a
151	* record of the currently active PGRAPH context. It's currently
152	* unknown as to what bit 24 does. The nv ddx has it set, so we will
153	* set it here too.
154	*/
155	nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
156	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
157	(inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) \|
158	NV40_PGRAPH_CTXCTL_CUR_LOADED);
159	/* 0x32E0 records the instance address of the active FIFO's PGRAPH
160	* context. If at any time this doesn't match 0x40032C, you will
161	* recieve PGRAPH_INTR_CONTEXT_SWITCH
162	*/
163	nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
164	return 0;
165	}
166
167	int
168	nv40_graph_unload_context(struct drm_device *dev)
169	{
170	uint32_t inst;
171	int ret;
172
173	inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
174	if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
175	return 0;
176	inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
177
178	ret = nv40_graph_transfer_context(dev, inst, 1);
179
180	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
181	return ret;
182	}
183
cb00f7c1 FJ	184	void
	185	nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
	186	uint32_t size, uint32_t pitch)
	187	{
	188	struct drm_nouveau_private *dev_priv = dev->dev_private;
	189	uint32_t limit = max(1u, addr + size) - 1;
	190
	191	if (pitch)
	192	addr \|= 1;
	193
	194	switch (dev_priv->chipset) {
	195	case 0x44:
	196	case 0x4a:
	197	case 0x4e:
	198	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
	199	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
	200	nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
	201	break;
	202
	203	case 0x46:
	204	case 0x47:
	205	case 0x49:
	206	case 0x4b:
	207	nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
	208	nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
	209	nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
	210	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
	211	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
	212	nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
	213	break;
	214
	215	default:
	216	nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
	217	nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
	218	nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
	219	nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
	220	nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
	221	nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
	222	break;
	223	}
	224	}
	225
6ee73861 BS	226	/*
	227	* G70 0x47
	228	* G71 0x49
	229	* NV45 0x48
	230	* G72[M] 0x46
	231	* G73 0x4b
	232	* C51_G7X 0x4c
	233	* C51 0x4e
	234	*/
	235	int
	236	nv40_graph_init(struct drm_device *dev)
	237	{
	238	struct drm_nouveau_private *dev_priv =
	239	(struct drm_nouveau_private *)dev->dev_private;
cb00f7c1 FJ	240	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
cb00f7c1 FJ	241	uint32_t vramsz;
6ee73861 BS	242	int i, j;
	243
	244	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
	245	~NV_PMC_ENABLE_PGRAPH);
	246	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \|
	247	NV_PMC_ENABLE_PGRAPH);
	248
054b93e4 BS	249	if (nouveau_ctxfw) {
	250	nouveau_grctx_prog_load(dev);
	251	dev_priv->engine.graph.grctx_size = 175 * 1024;
	252	}
	253
	254	if (!dev_priv->engine.graph.ctxprog) {
	255	struct nouveau_grctx ctx = {};
	256	uint32_t cp[256];
	257
	258	ctx.dev = dev;
	259	ctx.mode = NOUVEAU_GRCTX_PROG;
	260	ctx.data = cp;
	261	ctx.ctxprog_max = 256;
	262	nv40_grctx_init(&ctx);
	263	dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
	264
	265	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
	266	for (i = 0; i < ctx.ctxprog_len; i++)
	267	nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
	268	}
6ee73861 BS	269
	270	/* No context present currently */
	271	nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
	272
	273	nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
	274	nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
	275
	276	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
	277	nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
	278	nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
	279	nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
	280	nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
	281	nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
	282
	283	nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
	284	nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
	285
	286	j = nv_rd32(dev, 0x1540) & 0xff;
	287	if (j) {
	288	for (i = 0; !(j & 1); j >>= 1, i++)
	289	;
	290	nv_wr32(dev, 0x405000, i);
	291	}
	292
	293	if (dev_priv->chipset == 0x40) {
	294	nv_wr32(dev, 0x4009b0, 0x83280fff);
	295	nv_wr32(dev, 0x4009b4, 0x000000a0);
	296	} else {
	297	nv_wr32(dev, 0x400820, 0x83280eff);
	298	nv_wr32(dev, 0x400824, 0x000000a0);
	299	}
	300
	301	switch (dev_priv->chipset) {
	302	case 0x40:
	303	case 0x45:
	304	nv_wr32(dev, 0x4009b8, 0x0078e366);
	305	nv_wr32(dev, 0x4009bc, 0x0000014c);
	306	break;
	307	case 0x41:
	308	case 0x42: /* pciid also 0x00Cx */
	309	/* case 0x0120: XXX (pciid) */
	310	nv_wr32(dev, 0x400828, 0x007596ff);
	311	nv_wr32(dev, 0x40082c, 0x00000108);
	312	break;
	313	case 0x43:
	314	nv_wr32(dev, 0x400828, 0x0072cb77);
	315	nv_wr32(dev, 0x40082c, 0x00000108);
	316	break;
	317	case 0x44:
	318	case 0x46: /* G72 */
	319	case 0x4a:
	320	case 0x4c: /* G7x-based C51 */
	321	case 0x4e:
	322	nv_wr32(dev, 0x400860, 0);
	323	nv_wr32(dev, 0x400864, 0);
	324	break;
	325	case 0x47: /* G70 */
	326	case 0x49: /* G71 */
	327	case 0x4b: /* G73 */
	328	nv_wr32(dev, 0x400828, 0x07830610);
	329	nv_wr32(dev, 0x40082c, 0x0000016A);
	330	break;
	331	default:
	332	break;
333	}
334
335	nv_wr32(dev, 0x400b38, 0x2ffff800);
336	nv_wr32(dev, 0x400b3c, 0x00006000);
337
cb00f7c1 FJ	338	/* Turn all the tiling regions off. */
	339	for (i = 0; i < pfb->num_tiles; i++)
	340	nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
6ee73861 BS	341
	342	/* begin RAM config */
	343	vramsz = drm_get_resource_len(dev, 0) - 1;
	344	switch (dev_priv->chipset) {
	345	case 0x40:
	346	nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
	347	nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
	348	nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
	349	nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
	350	nv_wr32(dev, 0x400820, 0);
	351	nv_wr32(dev, 0x400824, 0);
	352	nv_wr32(dev, 0x400864, vramsz);
	353	nv_wr32(dev, 0x400868, vramsz);
	354	break;
	355	default:
	356	switch (dev_priv->chipset) {
	357	case 0x46:
	358	case 0x47:
	359	case 0x49:
	360	case 0x4b:
	361	nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
	362	nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
	363	break;
	364	default:
	365	nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
	366	nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
	367	break;
	368	}
	369	nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
	370	nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
	371	nv_wr32(dev, 0x400840, 0);
	372	nv_wr32(dev, 0x400844, 0);
	373	nv_wr32(dev, 0x4008A0, vramsz);
	374	nv_wr32(dev, 0x4008A4, vramsz);
	375	break;
	376	}
	377
	378	return 0;
	379	}
	380
	381	void nv40_graph_takedown(struct drm_device *dev)
	382	{
054b93e4	383	nouveau_grctx_fini(dev);
6ee73861 BS	384	}
	385
	386	struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
	387	{ 0x0030, false, NULL }, /* null */
	388	{ 0x0039, false, NULL }, /* m2mf */
	389	{ 0x004a, false, NULL }, /* gdirect */
	390	{ 0x009f, false, NULL }, /* imageblit (nv12) */
	391	{ 0x008a, false, NULL }, /* ifc */
	392	{ 0x0089, false, NULL }, /* sifm */
	393	{ 0x3089, false, NULL }, /* sifm (nv40) */
	394	{ 0x0062, false, NULL }, /* surf2d */
	395	{ 0x3062, false, NULL }, /* surf2d (nv40) */
	396	{ 0x0043, false, NULL }, /* rop */
	397	{ 0x0012, false, NULL }, /* beta1 */
	398	{ 0x0072, false, NULL }, /* beta4 */
	399	{ 0x0019, false, NULL }, /* cliprect */
	400	{ 0x0044, false, NULL }, /* pattern */
	401	{ 0x309e, false, NULL }, /* swzsurf */
	402	{ 0x4097, false, NULL }, /* curie (nv40) */
	403	{ 0x4497, false, NULL }, /* curie (nv44) */
	404	{}
	405	};
	406