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Merge branch 'drm-fixes' of /home/airlied/kernel/linux-2.6 into drm-core-next
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv17_tv.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) 2009 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drmP.h"
28#include "drm_crtc_helper.h"
29#include "nouveau_drv.h"
30#include "nouveau_encoder.h"
31#include "nouveau_connector.h"
32#include "nouveau_crtc.h"
33#include "nouveau_hw.h"
34#include "nv17_tv.h"
35
0829168b
FJ		 36static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
37{
38 struct drm_device *dev = encoder->dev;
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
ee2e0131 40 struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
0829168b
FJ		 41 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
42 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
43 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
44 uint32_t sample = 0;
45 int head;
46
47#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
48 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
04a39c57
BS		 49 if (dev_priv->vbios.tvdactestval)
50 testval = dev_priv->vbios.tvdactestval;
0829168b
FJ		 51
52 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
53 head = (dacclk & 0x100) >> 8;
54
55 /* Save the previous state. */
ee2e0131
BS		 56 gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1);
57 gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0);
0829168b
FJ		 58 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
59 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
60 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
61 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
62 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
63 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
64 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
65 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
66
67 /* Prepare the DAC for load detection. */
ee2e0131
BS		 68 gpio->set(dev, DCB_GPIO_TVDAC1, true);
69 gpio->set(dev, DCB_GPIO_TVDAC0, true);
0829168b
FJ		 70
71 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
72 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
73 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
74 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
75 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
76 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
77 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
78 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
79 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
80
81 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
82
83 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
84 (dacclk & ~0xff) | 0x22);
85 msleep(1);
86 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
87 (dacclk & ~0xff) | 0x21);
88
89 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
90 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
91
92 /* Sample pin 0x4 (usually S-video luma). */
93 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
94 msleep(20);
95 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
96 & 0x4 << 28;
97
98 /* Sample the remaining pins. */
99 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
100 msleep(20);
101 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
102 & 0xa << 28;
103
104 /* Restore the previous state. */
105 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
106 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
107 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
108 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
109 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
110 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
111 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
112 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
113 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
ee2e0131
BS		 114 gpio->set(dev, DCB_GPIO_TVDAC1, gpio1);
115 gpio->set(dev, DCB_GPIO_TVDAC0, gpio0);
0829168b
FJ		 116
117 return sample;
118}
119
4664c67b
FJ		 120static bool
121get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
122{
123 /* Zotac FX5200 */
acae116c
FJ		 124 if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) ||
125 nv_match_device(dev, 0x0322, 0x19da, 0x2035)) {
4664c67b
FJ		 126 *pin_mask = 0xc;
127 return false;
128 }
129
19bf5f7d 130 /* MSI nForce2 IGP */
acae116c 131 if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) {
19bf5f7d
FJ		 132 *pin_mask = 0xc;
133 return false;
134 }
135
4664c67b
FJ		 136 return true;
137}
138
11d6eb2a
FJ		 139static enum drm_connector_status
140nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
6ee73861 141{
11d6eb2a 142 struct drm_device *dev = encoder->dev;
0829168b 143 struct drm_nouveau_private *dev_priv = dev->dev_private;
11d6eb2a 144 struct drm_mode_config *conf = &dev->mode_config;
6ee73861 145 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
11d6eb2a 146 struct dcb_entry *dcb = tv_enc->base.dcb;
4664c67b 147 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
6ee73861 148
8ccfe9e0
FJ		 149 if (nv04_dac_in_use(encoder))
150 return connector_status_disconnected;
151
4664c67b
FJ		 152 if (reliable) {
153 if (dev_priv->chipset == 0x42 ||
154 dev_priv->chipset == 0x43)
155 tv_enc->pin_mask =
156 nv42_tv_sample_load(encoder) >> 28 & 0xe;
157 else
158 tv_enc->pin_mask =
159 nv17_dac_sample_load(encoder) >> 28 & 0xe;
160 }
6ee73861
BS		 161
162 switch (tv_enc->pin_mask) {
163 case 0x2:
164 case 0x4:
165 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
166 break;
167 case 0xc:
168 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
169 break;
170 case 0xe:
11d6eb2a 171 if (dcb->tvconf.has_component_output)
6ee73861
BS		 172 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
173 else
174 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
175 break;
176 default:
177 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
178 break;
179 }
180
181 drm_connector_property_set_value(connector,
11d6eb2a
FJ		 182 conf->tv_subconnector_property,
183 tv_enc->subconnector);
6ee73861 184
4664c67b
FJ		 185 if (!reliable) {
186 return connector_status_unknown;
187 } else if (tv_enc->subconnector) {
11d6eb2a
FJ		 188 NV_INFO(dev, "Load detected on output %c\n",
189 '@' + ffs(dcb->or));
190 return connector_status_connected;
191 } else {
192 return connector_status_disconnected;
193 }
6ee73861
BS		 194}
195
f2434237
FJ		 196static int nv17_tv_get_ld_modes(struct drm_encoder *encoder,
197 struct drm_connector *connector)
6ee73861
BS		 198{
199 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
f2434237 200 struct drm_display_mode *mode, *tv_mode;
6ee73861 201 int n = 0;
6ee73861 202
f2434237
FJ		 203 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
204 mode = drm_mode_duplicate(encoder->dev, tv_mode);
6ee73861 205
f2434237
FJ		 206 mode->clock = tv_norm->tv_enc_mode.vrefresh *
207 mode->htotal / 1000 *
208 mode->vtotal / 1000;
6ee73861 209
f2434237
FJ		 210 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
211 mode->clock *= 2;
6ee73861 212
f2434237
FJ		 213 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
214 mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
215 mode->type |= DRM_MODE_TYPE_PREFERRED;
6ee73861 216
f2434237
FJ		 217 drm_mode_probed_add(connector, mode);
218 n++;
6ee73861
BS		 219 }
220
f2434237
FJ		 221 return n;
222}
223
224static int nv17_tv_get_hd_modes(struct drm_encoder *encoder,
225 struct drm_connector *connector)
226{
227 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
228 struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode;
229 struct drm_display_mode *mode;
230 const struct {
231 int hdisplay;
232 int vdisplay;
233 } modes[] = {
234 { 640, 400 },
235 { 640, 480 },
236 { 720, 480 },
237 { 720, 576 },
238 { 800, 600 },
239 { 1024, 768 },
240 { 1280, 720 },
241 { 1280, 1024 },
242 { 1920, 1080 }
243 };
244 int i, n = 0;
245
6ee73861
BS		 246 for (i = 0; i < ARRAY_SIZE(modes); i++) {
247 if (modes[i].hdisplay > output_mode->hdisplay ||
248 modes[i].vdisplay > output_mode->vdisplay)
249 continue;
250
251 if (modes[i].hdisplay == output_mode->hdisplay &&
252 modes[i].vdisplay == output_mode->vdisplay) {
253 mode = drm_mode_duplicate(encoder->dev, output_mode);
254 mode->type |= DRM_MODE_TYPE_PREFERRED;
f2434237 255
6ee73861
BS		 256 } else {
257 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
f2434237
FJ		 258 modes[i].vdisplay, 60, false,
259 (output_mode->flags &
260 DRM_MODE_FLAG_INTERLACE), false);
6ee73861
BS		 261 }
262
263 /* CVT modes are sometimes unsuitable... */
264 if (output_mode->hdisplay <= 720
265 || output_mode->hdisplay >= 1920) {
266 mode->htotal = output_mode->htotal;
267 mode->hsync_start = (mode->hdisplay + (mode->htotal
268 - mode->hdisplay) * 9 / 10) & ~7;
269 mode->hsync_end = mode->hsync_start + 8;
270 }
f2434237 271
6ee73861
BS		 272 if (output_mode->vdisplay >= 1024) {
273 mode->vtotal = output_mode->vtotal;
274 mode->vsync_start = output_mode->vsync_start;
275 mode->vsync_end = output_mode->vsync_end;
276 }
277
278 mode->type |= DRM_MODE_TYPE_DRIVER;
279 drm_mode_probed_add(connector, mode);
280 n++;
281 }
f2434237 282
6ee73861
BS		 283 return n;
284}
285
f2434237
FJ		 286static int nv17_tv_get_modes(struct drm_encoder *encoder,
287 struct drm_connector *connector)
288{
289 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
290
291 if (tv_norm->kind == CTV_ENC_MODE)
292 return nv17_tv_get_hd_modes(encoder, connector);
293 else
294 return nv17_tv_get_ld_modes(encoder, connector);
295}
296
6ee73861
BS		 297static int nv17_tv_mode_valid(struct drm_encoder *encoder,
298 struct drm_display_mode *mode)
299{
300 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
301
302 if (tv_norm->kind == CTV_ENC_MODE) {
303 struct drm_display_mode *output_mode =
304 &tv_norm->ctv_enc_mode.mode;
305
306 if (mode->clock > 400000)
307 return MODE_CLOCK_HIGH;
308
309 if (mode->hdisplay > output_mode->hdisplay ||
310 mode->vdisplay > output_mode->vdisplay)
311 return MODE_BAD;
312
313 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
314 (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
315 return MODE_NO_INTERLACE;
316
317 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
318 return MODE_NO_DBLESCAN;
319
320 } else {
321 const int vsync_tolerance = 600;
322
323 if (mode->clock > 70000)
324 return MODE_CLOCK_HIGH;
325
326 if (abs(drm_mode_vrefresh(mode) * 1000 -
327 tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
328 return MODE_VSYNC;
329
330 /* The encoder takes care of the actual interlacing */
331 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
332 return MODE_NO_INTERLACE;
333 }
334
335 return MODE_OK;
336}
337
338static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
339 struct drm_display_mode *mode,
340 struct drm_display_mode *adjusted_mode)
341{
342 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
343
8ccfe9e0
FJ		 344 if (nv04_dac_in_use(encoder))
345 return false;
346
6ee73861
BS		 347 if (tv_norm->kind == CTV_ENC_MODE)
348 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
349 else
350 adjusted_mode->clock = 90000;
351
352 return true;
353}
354
355static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
356{
357 struct drm_device *dev = encoder->dev;
ee2e0131
BS		 358 struct drm_nouveau_private *dev_priv = dev->dev_private;
359 struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
6ee73861
BS		 360 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
361 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
362
363 if (nouveau_encoder(encoder)->last_dpms == mode)
364 return;
365 nouveau_encoder(encoder)->last_dpms = mode;
366
ef2bb506 367 NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
6ee73861
BS		 368 mode, nouveau_encoder(encoder)->dcb->index);
369
370 regs->ptv_200 &= ~1;
371
372 if (tv_norm->kind == CTV_ENC_MODE) {
373 nv04_dfp_update_fp_control(encoder, mode);
374
375 } else {
376 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
377
378 if (mode == DRM_MODE_DPMS_ON)
379 regs->ptv_200 |= 1;
380 }
381
382 nv_load_ptv(dev, regs, 200);
383
ee2e0131
BS		 384 gpio->set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
385 gpio->set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
6ee73861
BS		 386
387 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
388}
389
390static void nv17_tv_prepare(struct drm_encoder *encoder)
391{
392 struct drm_device *dev = encoder->dev;
393 struct drm_nouveau_private *dev_priv = dev->dev_private;
394 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
395 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
396 int head = nouveau_crtc(encoder->crtc)->index;
397 uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
398 NV_CIO_CRE_LCD__INDEX];
399 uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
400 nv04_dac_output_offset(encoder);
401 uint32_t dacclk;
402
403 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
404
405 nv04_dfp_disable(dev, head);
406
407 /* Unbind any FP encoders from this head if we need the FP
408 * stuff enabled. */
409 if (tv_norm->kind == CTV_ENC_MODE) {
410 struct drm_encoder *enc;
411
412 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
413 struct dcb_entry *dcb = nouveau_encoder(enc)->dcb;
414
415 if ((dcb->type == OUTPUT_TMDS ||
416 dcb->type == OUTPUT_LVDS) &&
417 !enc->crtc &&
418 nv04_dfp_get_bound_head(dev, dcb) == head) {
419 nv04_dfp_bind_head(dev, dcb, head ^ 1,
04a39c57 420 dev_priv->vbios.fp.dual_link);
6ee73861
BS		 421 }
422 }
423
424 }
425
217275d0 426 if (tv_norm->kind == CTV_ENC_MODE)
cd2fb2e9 427 *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
6ee73861
BS		 428
429 /* Set the DACCLK register */
430 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
431
432 if (dev_priv->card_type == NV_40)
433 dacclk |= 0x1a << 16;
434
435 if (tv_norm->kind == CTV_ENC_MODE) {
436 dacclk |= 0x20;
437
438 if (head)
439 dacclk |= 0x100;
440 else
441 dacclk &= ~0x100;
442
443 } else {
444 dacclk |= 0x10;
445
446 }
447
448 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
449}
450
451static void nv17_tv_mode_set(struct drm_encoder *encoder,
452 struct drm_display_mode *drm_mode,
453 struct drm_display_mode *adjusted_mode)
454{
455 struct drm_device *dev = encoder->dev;
456 struct drm_nouveau_private *dev_priv = dev->dev_private;
457 int head = nouveau_crtc(encoder->crtc)->index;
458 struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
459 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
460 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
461 int i;
462
463 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
464 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
465 regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
466 regs->tv_setup = 1;
467 regs->ramdac_8c0 = 0x0;
468
469 if (tv_norm->kind == TV_ENC_MODE) {
470 tv_regs->ptv_200 = 0x13111100;
471 if (head)
472 tv_regs->ptv_200 |= 0x10;
473
474 tv_regs->ptv_20c = 0x808010;
475 tv_regs->ptv_304 = 0x2d00000;
476 tv_regs->ptv_600 = 0x0;
477 tv_regs->ptv_60c = 0x0;
478 tv_regs->ptv_610 = 0x1e00000;
479
480 if (tv_norm->tv_enc_mode.vdisplay == 576) {
481 tv_regs->ptv_508 = 0x1200000;
482 tv_regs->ptv_614 = 0x33;
483
484 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
485 tv_regs->ptv_508 = 0xf00000;
486 tv_regs->ptv_614 = 0x13;
487 }
488
489 if (dev_priv->card_type >= NV_30) {
490 tv_regs->ptv_500 = 0xe8e0;
491 tv_regs->ptv_504 = 0x1710;
492 tv_regs->ptv_604 = 0x0;
493 tv_regs->ptv_608 = 0x0;
494 } else {
495 if (tv_norm->tv_enc_mode.vdisplay == 576) {
496 tv_regs->ptv_604 = 0x20;
497 tv_regs->ptv_608 = 0x10;
498 tv_regs->ptv_500 = 0x19710;
499 tv_regs->ptv_504 = 0x68f0;
500
501 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
502 tv_regs->ptv_604 = 0x10;
503 tv_regs->ptv_608 = 0x20;
504 tv_regs->ptv_500 = 0x4b90;
505 tv_regs->ptv_504 = 0x1b480;
506 }
507 }
508
509 for (i = 0; i < 0x40; i++)
510 tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
511
512 } else {
513 struct drm_display_mode *output_mode =
514 &tv_norm->ctv_enc_mode.mode;
515
516 /* The registers in PRAMDAC+0xc00 control some timings and CSC
517 * parameters for the CTV encoder (It's only used for "HD" TV
518 * modes, I don't think I have enough working to guess what
519 * they exactly mean...), it's probably connected at the
520 * output of the FP encoder, but it also needs the analog
521 * encoder in its OR enabled and routed to the head it's
522 * using. It's enabled with the DACCLK register, bits [5:4].
523 */
524 for (i = 0; i < 38; i++)
525 regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
526
527 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
528 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
529 regs->fp_horiz_regs[FP_SYNC_START] =
530 output_mode->hsync_start - 1;
531 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
532 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
533 max((output_mode->hdisplay-600)/40 - 1, 1);
534
535 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
536 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
537 regs->fp_vert_regs[FP_SYNC_START] =
538 output_mode->vsync_start - 1;
539 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
540 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
541
542 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
543 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
544 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
545
546 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
547 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
548 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
549 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
550
551 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
552 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
553 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
554 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
555 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
556 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
557 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
558
559 regs->fp_debug_2 = 0;
560
561 regs->fp_margin_color = 0x801080;
562
563 }
564}
565
566static void nv17_tv_commit(struct drm_encoder *encoder)
567{
568 struct drm_device *dev = encoder->dev;
569 struct drm_nouveau_private *dev_priv = dev->dev_private;
570 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
571 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
572 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
573
574 if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
575 nv17_tv_update_rescaler(encoder);
576 nv17_tv_update_properties(encoder);
577 } else {
578 nv17_ctv_update_rescaler(encoder);
579 }
580
581 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
582
583 /* This could use refinement for flatpanels, but it should work */
584 if (dev_priv->chipset < 0x44)
585 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
586 nv04_dac_output_offset(encoder),
587 0xf0000000);
588 else
589 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
590 nv04_dac_output_offset(encoder),
591 0x00100000);
592
593 helper->dpms(encoder, DRM_MODE_DPMS_ON);
594
595 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
596 drm_get_connector_name(
597 &nouveau_encoder_connector_get(nv_encoder)->base),
598 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
599}
600
601static void nv17_tv_save(struct drm_encoder *encoder)
602{
603 struct drm_device *dev = encoder->dev;
604 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
605
606 nouveau_encoder(encoder)->restore.output =
607 NVReadRAMDAC(dev, 0,
608 NV_PRAMDAC_DACCLK +
609 nv04_dac_output_offset(encoder));
610
611 nv17_tv_state_save(dev, &tv_enc->saved_state);
612
613 tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
614}
615
616static void nv17_tv_restore(struct drm_encoder *encoder)
617{
618 struct drm_device *dev = encoder->dev;
619
620 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
621 nv04_dac_output_offset(encoder),
622 nouveau_encoder(encoder)->restore.output);
623
624 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
bf929efa
FJ		 625
626 nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
6ee73861
BS		 627}
628
629static int nv17_tv_create_resources(struct drm_encoder *encoder,
630 struct drm_connector *connector)
631{
632 struct drm_device *dev = encoder->dev;
633 struct drm_mode_config *conf = &dev->mode_config;
634 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
635 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
636 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
637 NUM_LD_TV_NORMS;
638 int i;
639
640 if (nouveau_tv_norm) {
641 for (i = 0; i < num_tv_norms; i++) {
642 if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
643 tv_enc->tv_norm = i;
644 break;
645 }
646 }
647
648 if (i == num_tv_norms)
649 NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
650 nouveau_tv_norm);
651 }
652
653 drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
654
655 drm_connector_attach_property(connector,
656 conf->tv_select_subconnector_property,
657 tv_enc->select_subconnector);
658 drm_connector_attach_property(connector,
659 conf->tv_subconnector_property,
660 tv_enc->subconnector);
661 drm_connector_attach_property(connector,
662 conf->tv_mode_property,
663 tv_enc->tv_norm);
664 drm_connector_attach_property(connector,
665 conf->tv_flicker_reduction_property,
666 tv_enc->flicker);
667 drm_connector_attach_property(connector,
668 conf->tv_saturation_property,
669 tv_enc->saturation);
670 drm_connector_attach_property(connector,
671 conf->tv_hue_property,
672 tv_enc->hue);
673 drm_connector_attach_property(connector,
674 conf->tv_overscan_property,
675 tv_enc->overscan);
676
677 return 0;
678}
679
680static int nv17_tv_set_property(struct drm_encoder *encoder,
681 struct drm_connector *connector,
682 struct drm_property *property,
683 uint64_t val)
684{
685 struct drm_mode_config *conf = &encoder->dev->mode_config;
686 struct drm_crtc *crtc = encoder->crtc;
687 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
688 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
689 bool modes_changed = false;
690
691 if (property == conf->tv_overscan_property) {
692 tv_enc->overscan = val;
693 if (encoder->crtc) {
694 if (tv_norm->kind == CTV_ENC_MODE)
695 nv17_ctv_update_rescaler(encoder);
696 else
697 nv17_tv_update_rescaler(encoder);
698 }
699
700 } else if (property == conf->tv_saturation_property) {
701 if (tv_norm->kind != TV_ENC_MODE)
702 return -EINVAL;
703
704 tv_enc->saturation = val;
705 nv17_tv_update_properties(encoder);
706
707 } else if (property == conf->tv_hue_property) {
708 if (tv_norm->kind != TV_ENC_MODE)
709 return -EINVAL;
710
711 tv_enc->hue = val;
712 nv17_tv_update_properties(encoder);
713
714 } else if (property == conf->tv_flicker_reduction_property) {
715 if (tv_norm->kind != TV_ENC_MODE)
716 return -EINVAL;
717
718 tv_enc->flicker = val;
719 if (encoder->crtc)
720 nv17_tv_update_rescaler(encoder);
721
722 } else if (property == conf->tv_mode_property) {
723 if (connector->dpms != DRM_MODE_DPMS_OFF)
724 return -EINVAL;
725
726 tv_enc->tv_norm = val;
727
728 modes_changed = true;
729
730 } else if (property == conf->tv_select_subconnector_property) {
731 if (tv_norm->kind != TV_ENC_MODE)
732 return -EINVAL;
733
734 tv_enc->select_subconnector = val;
735 nv17_tv_update_properties(encoder);
736
737 } else {
738 return -EINVAL;
739 }
740
741 if (modes_changed) {
742 drm_helper_probe_single_connector_modes(connector, 0, 0);
743
744 /* Disable the crtc to ensure a full modeset is
745 * performed whenever it's turned on again. */
746 if (crtc) {
747 struct drm_mode_set modeset = {
748 .crtc = crtc,
749 };
750
751 crtc->funcs->set_config(&modeset);
752 }
753 }
754
755 return 0;
756}
757
758static void nv17_tv_destroy(struct drm_encoder *encoder)
759{
760 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
761
ef2bb506 762 NV_DEBUG_KMS(encoder->dev, "\n");
6ee73861
BS		 763
764 drm_encoder_cleanup(encoder);
765 kfree(tv_enc);
766}
767
768static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
769 .dpms = nv17_tv_dpms,
770 .save = nv17_tv_save,
771 .restore = nv17_tv_restore,
772 .mode_fixup = nv17_tv_mode_fixup,
773 .prepare = nv17_tv_prepare,
774 .commit = nv17_tv_commit,
775 .mode_set = nv17_tv_mode_set,
11d6eb2a 776 .detect = nv17_tv_detect,
6ee73861
BS		 777};
778
779static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
780 .get_modes = nv17_tv_get_modes,
781 .mode_valid = nv17_tv_mode_valid,
782 .create_resources = nv17_tv_create_resources,
783 .set_property = nv17_tv_set_property,
784};
785
786static struct drm_encoder_funcs nv17_tv_funcs = {
787 .destroy = nv17_tv_destroy,
788};
789
8f1a6086
BS		 790int
791nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
6ee73861 792{
8f1a6086 793 struct drm_device *dev = connector->dev;
6ee73861
BS		 794 struct drm_encoder *encoder;
795 struct nv17_tv_encoder *tv_enc = NULL;
796
797 tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
798 if (!tv_enc)
799 return -ENOMEM;
800
801 tv_enc->overscan = 50;
802 tv_enc->flicker = 50;
803 tv_enc->saturation = 50;
804 tv_enc->hue = 0;
805 tv_enc->tv_norm = TV_NORM_PAL;
806 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
807 tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
808 tv_enc->pin_mask = 0;
809
810 encoder = to_drm_encoder(&tv_enc->base);
811
812 tv_enc->base.dcb = entry;
813 tv_enc->base.or = ffs(entry->or) - 1;
814
815 drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
816 drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
817 to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
818
819 encoder->possible_crtcs = entry->heads;
820 encoder->possible_clones = 0;
821
8f1a6086
BS		 822 nv17_tv_create_resources(encoder, connector);
823 drm_mode_connector_attach_encoder(connector, encoder);
6ee73861
BS		 824 return 0;
825}
Clone of davem's net-next-2.6 tree