]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/nouveau/nv17_tv.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/nouveau: Workaround broken TV load detection on a "Zotac FX5200".
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv17_tv.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) 2009 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drmP.h"
28#include "drm_crtc_helper.h"
29#include "nouveau_drv.h"
30#include "nouveau_encoder.h"
31#include "nouveau_connector.h"
32#include "nouveau_crtc.h"
33#include "nouveau_hw.h"
34#include "nv17_tv.h"
35
0829168b
FJ		 36static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
37{
38 struct drm_device *dev = encoder->dev;
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
40 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
41 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
42 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
43 uint32_t sample = 0;
44 int head;
45
46#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
47 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
04a39c57
BS		 48 if (dev_priv->vbios.tvdactestval)
49 testval = dev_priv->vbios.tvdactestval;
0829168b
FJ		 50
51 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
52 head = (dacclk & 0x100) >> 8;
53
54 /* Save the previous state. */
55 gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1);
56 gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0);
57 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
58 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
59 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
60 fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
61 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
62 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
63 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
64 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
65
66 /* Prepare the DAC for load detection. */
67 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, true);
68 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, true);
69
70 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
71 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
72 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
73 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
74 NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
75 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
76 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
77 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
78 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
79
80 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
81
82 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
83 (dacclk & ~0xff) | 0x22);
84 msleep(1);
85 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
86 (dacclk & ~0xff) | 0x21);
87
88 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
89 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
90
91 /* Sample pin 0x4 (usually S-video luma). */
92 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
93 msleep(20);
94 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
95 & 0x4 << 28;
96
97 /* Sample the remaining pins. */
98 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
99 msleep(20);
100 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
101 & 0xa << 28;
102
103 /* Restore the previous state. */
104 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
105 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
106 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
107 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
108 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
109 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
110 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
111 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
112 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
113 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, gpio1);
114 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, gpio0);
115
116 return sample;
117}
118
4664c67b
FJ		 119static bool
120get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
121{
122 /* Zotac FX5200 */
123 if ((dev->pdev->device == 0x0322) &&
124 (dev->pdev->subsystem_vendor == 0x19da) &&
125 (dev->pdev->subsystem_device == 0x2035)) {
126 *pin_mask = 0xc;
127 return false;
128 }
129
130 return true;
131}
132
11d6eb2a
FJ		 133static enum drm_connector_status
134nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
6ee73861 135{
11d6eb2a 136 struct drm_device *dev = encoder->dev;
0829168b 137 struct drm_nouveau_private *dev_priv = dev->dev_private;
11d6eb2a 138 struct drm_mode_config *conf = &dev->mode_config;
6ee73861 139 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
11d6eb2a 140 struct dcb_entry *dcb = tv_enc->base.dcb;
4664c67b 141 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
6ee73861 142
8ccfe9e0
FJ		 143 if (nv04_dac_in_use(encoder))
144 return connector_status_disconnected;
145
4664c67b
FJ		 146 if (reliable) {
147 if (dev_priv->chipset == 0x42 ||
148 dev_priv->chipset == 0x43)
149 tv_enc->pin_mask =
150 nv42_tv_sample_load(encoder) >> 28 & 0xe;
151 else
152 tv_enc->pin_mask =
153 nv17_dac_sample_load(encoder) >> 28 & 0xe;
154 }
6ee73861
BS		 155
156 switch (tv_enc->pin_mask) {
157 case 0x2:
158 case 0x4:
159 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
160 break;
161 case 0xc:
162 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
163 break;
164 case 0xe:
11d6eb2a 165 if (dcb->tvconf.has_component_output)
6ee73861
BS		 166 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
167 else
168 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
169 break;
170 default:
171 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
172 break;
173 }
174
175 drm_connector_property_set_value(connector,
11d6eb2a
FJ		 176 conf->tv_subconnector_property,
177 tv_enc->subconnector);
6ee73861 178
4664c67b
FJ		 179 if (!reliable) {
180 return connector_status_unknown;
181 } else if (tv_enc->subconnector) {
11d6eb2a
FJ		 182 NV_INFO(dev, "Load detected on output %c\n",
183 '@' + ffs(dcb->or));
184 return connector_status_connected;
185 } else {
186 return connector_status_disconnected;
187 }
6ee73861
BS		 188}
189
190static const struct {
191 int hdisplay;
192 int vdisplay;
193} modes[] = {
194 { 640, 400 },
195 { 640, 480 },
196 { 720, 480 },
197 { 720, 576 },
198 { 800, 600 },
199 { 1024, 768 },
200 { 1280, 720 },
201 { 1280, 1024 },
202 { 1920, 1080 }
203};
204
205static int nv17_tv_get_modes(struct drm_encoder *encoder,
206 struct drm_connector *connector)
207{
208 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
209 struct drm_display_mode *mode;
210 struct drm_display_mode *output_mode;
211 int n = 0;
212 int i;
213
214 if (tv_norm->kind != CTV_ENC_MODE) {
215 struct drm_display_mode *tv_mode;
216
217 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
218 mode = drm_mode_duplicate(encoder->dev, tv_mode);
219
220 mode->clock = tv_norm->tv_enc_mode.vrefresh *
221 mode->htotal / 1000 *
222 mode->vtotal / 1000;
223
224 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
225 mode->clock *= 2;
226
227 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
228 mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
229 mode->type |= DRM_MODE_TYPE_PREFERRED;
230
231 drm_mode_probed_add(connector, mode);
232 n++;
233 }
234 return n;
235 }
236
237 /* tv_norm->kind == CTV_ENC_MODE */
238 output_mode = &tv_norm->ctv_enc_mode.mode;
239 for (i = 0; i < ARRAY_SIZE(modes); i++) {
240 if (modes[i].hdisplay > output_mode->hdisplay ||
241 modes[i].vdisplay > output_mode->vdisplay)
242 continue;
243
244 if (modes[i].hdisplay == output_mode->hdisplay &&
245 modes[i].vdisplay == output_mode->vdisplay) {
246 mode = drm_mode_duplicate(encoder->dev, output_mode);
247 mode->type |= DRM_MODE_TYPE_PREFERRED;
248 } else {
249 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
250 modes[i].vdisplay, 60, false,
251 output_mode->flags & DRM_MODE_FLAG_INTERLACE,
252 false);
253 }
254
255 /* CVT modes are sometimes unsuitable... */
256 if (output_mode->hdisplay <= 720
257 || output_mode->hdisplay >= 1920) {
258 mode->htotal = output_mode->htotal;
259 mode->hsync_start = (mode->hdisplay + (mode->htotal
260 - mode->hdisplay) * 9 / 10) & ~7;
261 mode->hsync_end = mode->hsync_start + 8;
262 }
263 if (output_mode->vdisplay >= 1024) {
264 mode->vtotal = output_mode->vtotal;
265 mode->vsync_start = output_mode->vsync_start;
266 mode->vsync_end = output_mode->vsync_end;
267 }
268
269 mode->type |= DRM_MODE_TYPE_DRIVER;
270 drm_mode_probed_add(connector, mode);
271 n++;
272 }
273 return n;
274}
275
276static int nv17_tv_mode_valid(struct drm_encoder *encoder,
277 struct drm_display_mode *mode)
278{
279 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
280
281 if (tv_norm->kind == CTV_ENC_MODE) {
282 struct drm_display_mode *output_mode =
283 &tv_norm->ctv_enc_mode.mode;
284
285 if (mode->clock > 400000)
286 return MODE_CLOCK_HIGH;
287
288 if (mode->hdisplay > output_mode->hdisplay ||
289 mode->vdisplay > output_mode->vdisplay)
290 return MODE_BAD;
291
292 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
293 (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
294 return MODE_NO_INTERLACE;
295
296 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
297 return MODE_NO_DBLESCAN;
298
299 } else {
300 const int vsync_tolerance = 600;
301
302 if (mode->clock > 70000)
303 return MODE_CLOCK_HIGH;
304
305 if (abs(drm_mode_vrefresh(mode) * 1000 -
306 tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
307 return MODE_VSYNC;
308
309 /* The encoder takes care of the actual interlacing */
310 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
311 return MODE_NO_INTERLACE;
312 }
313
314 return MODE_OK;
315}
316
317static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
318 struct drm_display_mode *mode,
319 struct drm_display_mode *adjusted_mode)
320{
321 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
322
8ccfe9e0
FJ		 323 if (nv04_dac_in_use(encoder))
324 return false;
325
6ee73861
BS		 326 if (tv_norm->kind == CTV_ENC_MODE)
327 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
328 else
329 adjusted_mode->clock = 90000;
330
331 return true;
332}
333
334static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
335{
336 struct drm_device *dev = encoder->dev;
337 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
338 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
339
340 if (nouveau_encoder(encoder)->last_dpms == mode)
341 return;
342 nouveau_encoder(encoder)->last_dpms = mode;
343
ef2bb506 344 NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
6ee73861
BS		 345 mode, nouveau_encoder(encoder)->dcb->index);
346
347 regs->ptv_200 &= ~1;
348
349 if (tv_norm->kind == CTV_ENC_MODE) {
350 nv04_dfp_update_fp_control(encoder, mode);
351
352 } else {
353 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
354
355 if (mode == DRM_MODE_DPMS_ON)
356 regs->ptv_200 |= 1;
357 }
358
359 nv_load_ptv(dev, regs, 200);
360
361 nv17_gpio_set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
362 nv17_gpio_set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
363
364 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
365}
366
367static void nv17_tv_prepare(struct drm_encoder *encoder)
368{
369 struct drm_device *dev = encoder->dev;
370 struct drm_nouveau_private *dev_priv = dev->dev_private;
371 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
372 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
373 int head = nouveau_crtc(encoder->crtc)->index;
374 uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
375 NV_CIO_CRE_LCD__INDEX];
376 uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
377 nv04_dac_output_offset(encoder);
378 uint32_t dacclk;
379
380 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
381
382 nv04_dfp_disable(dev, head);
383
384 /* Unbind any FP encoders from this head if we need the FP
385 * stuff enabled. */
386 if (tv_norm->kind == CTV_ENC_MODE) {
387 struct drm_encoder *enc;
388
389 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
390 struct dcb_entry *dcb = nouveau_encoder(enc)->dcb;
391
392 if ((dcb->type == OUTPUT_TMDS ||
393 dcb->type == OUTPUT_LVDS) &&
394 !enc->crtc &&
395 nv04_dfp_get_bound_head(dev, dcb) == head) {
396 nv04_dfp_bind_head(dev, dcb, head ^ 1,
04a39c57 397 dev_priv->vbios.fp.dual_link);
6ee73861
BS		 398 }
399 }
400
401 }
402
403 /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
404 * at LCD__INDEX which we don't alter
405 */
406 if (!(*cr_lcd & 0x44)) {
407 if (tv_norm->kind == CTV_ENC_MODE)
408 *cr_lcd = 0x1 | (head ? 0x0 : 0x8);
409 else
410 *cr_lcd = 0;
411 }
412
413 /* Set the DACCLK register */
414 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
415
416 if (dev_priv->card_type == NV_40)
417 dacclk |= 0x1a << 16;
418
419 if (tv_norm->kind == CTV_ENC_MODE) {
420 dacclk |= 0x20;
421
422 if (head)
423 dacclk |= 0x100;
424 else
425 dacclk &= ~0x100;
426
427 } else {
428 dacclk |= 0x10;
429
430 }
431
432 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
433}
434
435static void nv17_tv_mode_set(struct drm_encoder *encoder,
436 struct drm_display_mode *drm_mode,
437 struct drm_display_mode *adjusted_mode)
438{
439 struct drm_device *dev = encoder->dev;
440 struct drm_nouveau_private *dev_priv = dev->dev_private;
441 int head = nouveau_crtc(encoder->crtc)->index;
442 struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
443 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
444 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
445 int i;
446
447 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
448 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
449 regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
450 regs->tv_setup = 1;
451 regs->ramdac_8c0 = 0x0;
452
453 if (tv_norm->kind == TV_ENC_MODE) {
454 tv_regs->ptv_200 = 0x13111100;
455 if (head)
456 tv_regs->ptv_200 |= 0x10;
457
458 tv_regs->ptv_20c = 0x808010;
459 tv_regs->ptv_304 = 0x2d00000;
460 tv_regs->ptv_600 = 0x0;
461 tv_regs->ptv_60c = 0x0;
462 tv_regs->ptv_610 = 0x1e00000;
463
464 if (tv_norm->tv_enc_mode.vdisplay == 576) {
465 tv_regs->ptv_508 = 0x1200000;
466 tv_regs->ptv_614 = 0x33;
467
468 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
469 tv_regs->ptv_508 = 0xf00000;
470 tv_regs->ptv_614 = 0x13;
471 }
472
473 if (dev_priv->card_type >= NV_30) {
474 tv_regs->ptv_500 = 0xe8e0;
475 tv_regs->ptv_504 = 0x1710;
476 tv_regs->ptv_604 = 0x0;
477 tv_regs->ptv_608 = 0x0;
478 } else {
479 if (tv_norm->tv_enc_mode.vdisplay == 576) {
480 tv_regs->ptv_604 = 0x20;
481 tv_regs->ptv_608 = 0x10;
482 tv_regs->ptv_500 = 0x19710;
483 tv_regs->ptv_504 = 0x68f0;
484
485 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
486 tv_regs->ptv_604 = 0x10;
487 tv_regs->ptv_608 = 0x20;
488 tv_regs->ptv_500 = 0x4b90;
489 tv_regs->ptv_504 = 0x1b480;
490 }
491 }
492
493 for (i = 0; i < 0x40; i++)
494 tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
495
496 } else {
497 struct drm_display_mode *output_mode =
498 &tv_norm->ctv_enc_mode.mode;
499
500 /* The registers in PRAMDAC+0xc00 control some timings and CSC
501 * parameters for the CTV encoder (It's only used for "HD" TV
502 * modes, I don't think I have enough working to guess what
503 * they exactly mean...), it's probably connected at the
504 * output of the FP encoder, but it also needs the analog
505 * encoder in its OR enabled and routed to the head it's
506 * using. It's enabled with the DACCLK register, bits [5:4].
507 */
508 for (i = 0; i < 38; i++)
509 regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
510
511 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
512 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
513 regs->fp_horiz_regs[FP_SYNC_START] =
514 output_mode->hsync_start - 1;
515 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
516 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
517 max((output_mode->hdisplay-600)/40 - 1, 1);
518
519 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
520 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
521 regs->fp_vert_regs[FP_SYNC_START] =
522 output_mode->vsync_start - 1;
523 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
524 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
525
526 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
527 NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
528 NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
529
530 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
531 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
532 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
533 regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
534
535 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
536 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
537 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
538 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
539 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
540 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
541 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
542
543 regs->fp_debug_2 = 0;
544
545 regs->fp_margin_color = 0x801080;
546
547 }
548}
549
550static void nv17_tv_commit(struct drm_encoder *encoder)
551{
552 struct drm_device *dev = encoder->dev;
553 struct drm_nouveau_private *dev_priv = dev->dev_private;
554 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
555 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
556 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
557
558 if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
559 nv17_tv_update_rescaler(encoder);
560 nv17_tv_update_properties(encoder);
561 } else {
562 nv17_ctv_update_rescaler(encoder);
563 }
564
565 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
566
567 /* This could use refinement for flatpanels, but it should work */
568 if (dev_priv->chipset < 0x44)
569 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
570 nv04_dac_output_offset(encoder),
571 0xf0000000);
572 else
573 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
574 nv04_dac_output_offset(encoder),
575 0x00100000);
576
577 helper->dpms(encoder, DRM_MODE_DPMS_ON);
578
579 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
580 drm_get_connector_name(
581 &nouveau_encoder_connector_get(nv_encoder)->base),
582 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
583}
584
585static void nv17_tv_save(struct drm_encoder *encoder)
586{
587 struct drm_device *dev = encoder->dev;
588 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
589
590 nouveau_encoder(encoder)->restore.output =
591 NVReadRAMDAC(dev, 0,
592 NV_PRAMDAC_DACCLK +
593 nv04_dac_output_offset(encoder));
594
595 nv17_tv_state_save(dev, &tv_enc->saved_state);
596
597 tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
598}
599
600static void nv17_tv_restore(struct drm_encoder *encoder)
601{
602 struct drm_device *dev = encoder->dev;
603
604 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
605 nv04_dac_output_offset(encoder),
606 nouveau_encoder(encoder)->restore.output);
607
608 nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
bf929efa
FJ		 609
610 nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
6ee73861
BS		 611}
612
613static int nv17_tv_create_resources(struct drm_encoder *encoder,
614 struct drm_connector *connector)
615{
616 struct drm_device *dev = encoder->dev;
617 struct drm_mode_config *conf = &dev->mode_config;
618 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
619 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
620 int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
621 NUM_LD_TV_NORMS;
622 int i;
623
624 if (nouveau_tv_norm) {
625 for (i = 0; i < num_tv_norms; i++) {
626 if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
627 tv_enc->tv_norm = i;
628 break;
629 }
630 }
631
632 if (i == num_tv_norms)
633 NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
634 nouveau_tv_norm);
635 }
636
637 drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
638
639 drm_connector_attach_property(connector,
640 conf->tv_select_subconnector_property,
641 tv_enc->select_subconnector);
642 drm_connector_attach_property(connector,
643 conf->tv_subconnector_property,
644 tv_enc->subconnector);
645 drm_connector_attach_property(connector,
646 conf->tv_mode_property,
647 tv_enc->tv_norm);
648 drm_connector_attach_property(connector,
649 conf->tv_flicker_reduction_property,
650 tv_enc->flicker);
651 drm_connector_attach_property(connector,
652 conf->tv_saturation_property,
653 tv_enc->saturation);
654 drm_connector_attach_property(connector,
655 conf->tv_hue_property,
656 tv_enc->hue);
657 drm_connector_attach_property(connector,
658 conf->tv_overscan_property,
659 tv_enc->overscan);
660
661 return 0;
662}
663
664static int nv17_tv_set_property(struct drm_encoder *encoder,
665 struct drm_connector *connector,
666 struct drm_property *property,
667 uint64_t val)
668{
669 struct drm_mode_config *conf = &encoder->dev->mode_config;
670 struct drm_crtc *crtc = encoder->crtc;
671 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
672 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
673 bool modes_changed = false;
674
675 if (property == conf->tv_overscan_property) {
676 tv_enc->overscan = val;
677 if (encoder->crtc) {
678 if (tv_norm->kind == CTV_ENC_MODE)
679 nv17_ctv_update_rescaler(encoder);
680 else
681 nv17_tv_update_rescaler(encoder);
682 }
683
684 } else if (property == conf->tv_saturation_property) {
685 if (tv_norm->kind != TV_ENC_MODE)
686 return -EINVAL;
687
688 tv_enc->saturation = val;
689 nv17_tv_update_properties(encoder);
690
691 } else if (property == conf->tv_hue_property) {
692 if (tv_norm->kind != TV_ENC_MODE)
693 return -EINVAL;
694
695 tv_enc->hue = val;
696 nv17_tv_update_properties(encoder);
697
698 } else if (property == conf->tv_flicker_reduction_property) {
699 if (tv_norm->kind != TV_ENC_MODE)
700 return -EINVAL;
701
702 tv_enc->flicker = val;
703 if (encoder->crtc)
704 nv17_tv_update_rescaler(encoder);
705
706 } else if (property == conf->tv_mode_property) {
707 if (connector->dpms != DRM_MODE_DPMS_OFF)
708 return -EINVAL;
709
710 tv_enc->tv_norm = val;
711
712 modes_changed = true;
713
714 } else if (property == conf->tv_select_subconnector_property) {
715 if (tv_norm->kind != TV_ENC_MODE)
716 return -EINVAL;
717
718 tv_enc->select_subconnector = val;
719 nv17_tv_update_properties(encoder);
720
721 } else {
722 return -EINVAL;
723 }
724
725 if (modes_changed) {
726 drm_helper_probe_single_connector_modes(connector, 0, 0);
727
728 /* Disable the crtc to ensure a full modeset is
729 * performed whenever it's turned on again. */
730 if (crtc) {
731 struct drm_mode_set modeset = {
732 .crtc = crtc,
733 };
734
735 crtc->funcs->set_config(&modeset);
736 }
737 }
738
739 return 0;
740}
741
742static void nv17_tv_destroy(struct drm_encoder *encoder)
743{
744 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
745
ef2bb506 746 NV_DEBUG_KMS(encoder->dev, "\n");
6ee73861
BS		 747
748 drm_encoder_cleanup(encoder);
749 kfree(tv_enc);
750}
751
752static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
753 .dpms = nv17_tv_dpms,
754 .save = nv17_tv_save,
755 .restore = nv17_tv_restore,
756 .mode_fixup = nv17_tv_mode_fixup,
757 .prepare = nv17_tv_prepare,
758 .commit = nv17_tv_commit,
759 .mode_set = nv17_tv_mode_set,
11d6eb2a 760 .detect = nv17_tv_detect,
6ee73861
BS		 761};
762
763static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
764 .get_modes = nv17_tv_get_modes,
765 .mode_valid = nv17_tv_mode_valid,
766 .create_resources = nv17_tv_create_resources,
767 .set_property = nv17_tv_set_property,
768};
769
770static struct drm_encoder_funcs nv17_tv_funcs = {
771 .destroy = nv17_tv_destroy,
772};
773
8f1a6086
BS		 774int
775nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
6ee73861 776{
8f1a6086 777 struct drm_device *dev = connector->dev;
6ee73861
BS		 778 struct drm_encoder *encoder;
779 struct nv17_tv_encoder *tv_enc = NULL;
780
781 tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
782 if (!tv_enc)
783 return -ENOMEM;
784
785 tv_enc->overscan = 50;
786 tv_enc->flicker = 50;
787 tv_enc->saturation = 50;
788 tv_enc->hue = 0;
789 tv_enc->tv_norm = TV_NORM_PAL;
790 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
791 tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
792 tv_enc->pin_mask = 0;
793
794 encoder = to_drm_encoder(&tv_enc->base);
795
796 tv_enc->base.dcb = entry;
797 tv_enc->base.or = ffs(entry->or) - 1;
798
799 drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
800 drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
801 to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
802
803 encoder->possible_crtcs = entry->heads;
804 encoder->possible_clones = 0;
805
8f1a6086
BS		 806 nv17_tv_create_resources(encoder, connector);
807 drm_mode_connector_attach_encoder(connector, encoder);
6ee73861
BS		 808 return 0;
809}
Clone of davem's net-next-2.6 tree