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Merge branch 'drm-fixes' of /home/airlied/kernel/linux-2.6 into drm-core-next
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nv04_dfp.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 * Copyright 2007-2009 Stuart Bennett
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27#include "drmP.h"
28#include "drm_crtc_helper.h"
29
30#include "nouveau_drv.h"
31#include "nouveau_encoder.h"
32#include "nouveau_connector.h"
33#include "nouveau_crtc.h"
34#include "nouveau_hw.h"
35#include "nvreg.h"
36
4a9f822f
FJ		 37#include "i2c/sil164.h"
38
6ee73861
BS		 39#define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \
40 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \
41 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
42#define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \
43 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \
44 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
45
46static inline bool is_fpc_off(uint32_t fpc)
47{
48 return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
49 FP_TG_CONTROL_OFF);
50}
51
52int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent)
53{
54 /* special case of nv_read_tmds to find crtc associated with an output.
55 * this does not give a correct answer for off-chip dvi, but there's no
56 * use for such an answer anyway
57 */
58 int ramdac = (dcbent->or & OUTPUT_C) >> 2;
59
60 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
61 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
62 return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
63}
64
65void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
66 int head, bool dl)
67{
68 /* The BIOS scripts don't do this for us, sadly
69 * Luckily we do know the values ;-)
70 *
71 * head < 0 indicates we wish to force a setting with the overrideval
72 * (for VT restore etc.)
73 */
74
75 int ramdac = (dcbent->or & OUTPUT_C) >> 2;
76 uint8_t tmds04 = 0x80;
77
78 if (head != ramdac)
79 tmds04 = 0x88;
80
81 if (dcbent->type == OUTPUT_LVDS)
82 tmds04 |= 0x01;
83
84 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
85
86 if (dl) /* dual link */
87 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
88}
89
90void nv04_dfp_disable(struct drm_device *dev, int head)
91{
92 struct drm_nouveau_private *dev_priv = dev->dev_private;
93 struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
94
95 if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
96 FP_TG_CONTROL_ON) {
97 /* digital remnants must be cleaned before new crtc
98 * values programmed. delay is time for the vga stuff
99 * to realise it's in control again
100 */
101 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
102 FP_TG_CONTROL_OFF);
103 msleep(50);
104 }
105 /* don't inadvertently turn it on when state written later */
106 crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
cd2fb2e9
FJ		 107 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
108 ~NV_CIO_CRE_LCD_ROUTE_MASK;
6ee73861
BS		 109}
110
111void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
112{
113 struct drm_device *dev = encoder->dev;
114 struct drm_nouveau_private *dev_priv = dev->dev_private;
115 struct drm_crtc *crtc;
116 struct nouveau_crtc *nv_crtc;
117 uint32_t *fpc;
118
119 if (mode == DRM_MODE_DPMS_ON) {
120 nv_crtc = nouveau_crtc(encoder->crtc);
121 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
122
123 if (is_fpc_off(*fpc)) {
124 /* using saved value is ok, as (is_digital && dpms_on &&
125 * fp_control==OFF) is (at present) *only* true when
126 * fpc's most recent change was by below "off" code
127 */
128 *fpc = nv_crtc->dpms_saved_fp_control;
129 }
130
131 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
132 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
133 } else {
134 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
135 nv_crtc = nouveau_crtc(crtc);
136 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
137
138 nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
139 if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
140 nv_crtc->dpms_saved_fp_control = *fpc;
141 /* cut the FP output */
142 *fpc &= ~FP_TG_CONTROL_ON;
143 *fpc |= FP_TG_CONTROL_OFF;
144 NVWriteRAMDAC(dev, nv_crtc->index,
145 NV_PRAMDAC_FP_TG_CONTROL, *fpc);
146 }
147 }
148 }
149}
150
2d14e35c
FJ		 151static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
152{
153 struct drm_device *dev = encoder->dev;
154 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
155 struct drm_encoder *slave;
156
157 if (dcb->type != OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
158 return NULL;
159
160 /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
161 * TMDS transmitters at the same I2C address, in the same I2C
162 * bus. This can still work because in that case one of them is
163 * always hard-wired to a reasonable configuration using straps,
164 * and the other one needs to be programmed.
165 *
166 * I don't think there's a way to know which is which, even the
167 * blob programs the one exposed via I2C for *both* heads, so
168 * let's do the same.
169 */
170 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
171 struct dcb_entry *slave_dcb = nouveau_encoder(slave)->dcb;
172
173 if (slave_dcb->type == OUTPUT_TMDS && get_slave_funcs(slave) &&
174 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
175 return slave;
176 }
177
178 return NULL;
179}
180
6ee73861
BS		 181static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
182 struct drm_display_mode *mode,
183 struct drm_display_mode *adjusted_mode)
184{
185 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
186 struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
187
188 /* For internal panels and gpu scaling on DVI we need the native mode */
189 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
190 if (!nv_connector->native_mode)
191 return false;
192 nv_encoder->mode = *nv_connector->native_mode;
193 adjusted_mode->clock = nv_connector->native_mode->clock;
194 } else {
195 nv_encoder->mode = *adjusted_mode;
196 }
197
198 return true;
199}
200
201static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
202 struct nouveau_encoder *nv_encoder, int head)
203{
204 struct drm_nouveau_private *dev_priv = dev->dev_private;
205 struct nv04_mode_state *state = &dev_priv->mode_reg;
206 uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
207
208 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
209 return;
210
211 /* SEL_CLK is only used on the primary ramdac
212 * It toggles spread spectrum PLL output and sets the bindings of PLLs
213 * to heads on digital outputs
214 */
215 if (head)
216 state->sel_clk |= bits1618;
217 else
218 state->sel_clk &= ~bits1618;
219
220 /* nv30:
221 * bit 0 NVClk spread spectrum on/off
222 * bit 2 MemClk spread spectrum on/off
223 * bit 4 PixClk1 spread spectrum on/off toggle
224 * bit 6 PixClk2 spread spectrum on/off toggle
225 *
226 * nv40 (observations from bios behaviour and mmio traces):
227 * bits 4&6 as for nv30
228 * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6;
229 * maybe a different spread mode
230 * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
231 * The logic behind turning spread spectrum on/off in the first place,
232 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
233 * entry has the necessary info)
234 */
235 if (nv_encoder->dcb->type == OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) {
236 int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1;
237
238 state->sel_clk &= ~0xf0;
239 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
240 }
241}
242
243static void nv04_dfp_prepare(struct drm_encoder *encoder)
244{
245 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
246 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
247 struct drm_device *dev = encoder->dev;
248 struct drm_nouveau_private *dev_priv = dev->dev_private;
249 int head = nouveau_crtc(encoder->crtc)->index;
250 struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
251 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
252 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
253
254 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
255
256 nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
257
cd2fb2e9 258 *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;
217275d0
FJ		 259
260 if (nv_two_heads(dev)) {
261 if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
262 *cr_lcd |= head ? 0x0 : 0x8;
263 else {
264 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
265 if (nv_encoder->dcb->type == OUTPUT_LVDS)
266 *cr_lcd |= 0x30;
267 if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
268 /* avoid being connected to both crtcs */
269 *cr_lcd_oth &= ~0x30;
270 NVWriteVgaCrtc(dev, head ^ 1,
271 NV_CIO_CRE_LCD__INDEX,
272 *cr_lcd_oth);
6ee73861
BS		 273 }
274 }
275 }
276}
277
278
279static void nv04_dfp_mode_set(struct drm_encoder *encoder,
280 struct drm_display_mode *mode,
281 struct drm_display_mode *adjusted_mode)
282{
283 struct drm_device *dev = encoder->dev;
284 struct drm_nouveau_private *dev_priv = dev->dev_private;
285 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
286 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
287 struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
288 struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
289 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
290 struct drm_display_mode *output_mode = &nv_encoder->mode;
291 uint32_t mode_ratio, panel_ratio;
292
ef2bb506 293 NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
6ee73861
BS		 294 drm_mode_debug_printmodeline(output_mode);
295
296 /* Initialize the FP registers in this CRTC. */
297 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
298 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
299 if (!nv_gf4_disp_arch(dev) ||
300 (output_mode->hsync_start - output_mode->hdisplay) >=
04a39c57 301 dev_priv->vbios.digital_min_front_porch)
6ee73861
BS		 302 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
303 else
04a39c57 304 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1;
6ee73861
BS		 305 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
306 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
307 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
308 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
309
310 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
311 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
312 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
313 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
314 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
315 regp->fp_vert_regs[FP_VALID_START] = 0;
316 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
317
318 /* bit26: a bit seen on some g7x, no as yet discernable purpose */
319 regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
320 (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
321 /* Deal with vsync/hsync polarity */
322 /* LVDS screens do set this, but modes with +ve syncs are very rare */
323 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
324 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
325 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
326 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
327 /* panel scaling first, as native would get set otherwise */
328 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
329 nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */
330 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
331 else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
332 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
333 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
334 else /* gpu needs to scale */
335 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
336 if (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
337 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
338 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
339 output_mode->clock > 165000)
340 regp->fp_control |= (2 << 24);
341 if (nv_encoder->dcb->type == OUTPUT_LVDS) {
342 bool duallink, dummy;
343
344 nouveau_bios_parse_lvds_table(dev, nv_connector->native_mode->
345 clock, &duallink, &dummy);
346 if (duallink)
347 regp->fp_control |= (8 << 28);
348 } else
349 if (output_mode->clock > 165000)
350 regp->fp_control |= (8 << 28);
351
352 regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
353 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
354 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
355 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
356 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
357 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
358 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
359
360 /* We want automatic scaling */
361 regp->fp_debug_1 = 0;
362 /* This can override HTOTAL and VTOTAL */
363 regp->fp_debug_2 = 0;
364
365 /* Use 20.12 fixed point format to avoid floats */
366 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
367 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
368 /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
369 * get treated the same as SCALE_FULLSCREEN */
370 if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
371 mode_ratio != panel_ratio) {
372 uint32_t diff, scale;
373 bool divide_by_2 = nv_gf4_disp_arch(dev);
374
375 if (mode_ratio < panel_ratio) {
376 /* vertical needs to expand to glass size (automatic)
377 * horizontal needs to be scaled at vertical scale factor
378 * to maintain aspect */
379
380 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
381 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
382 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
383
384 /* restrict area of screen used, horizontally */
385 diff = output_mode->hdisplay -
386 output_mode->vdisplay * mode_ratio / (1 << 12);
387 regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
388 regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
389 }
390
391 if (mode_ratio > panel_ratio) {
392 /* horizontal needs to expand to glass size (automatic)
393 * vertical needs to be scaled at horizontal scale factor
394 * to maintain aspect */
395
396 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
397 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
398 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
399
400 /* restrict area of screen used, vertically */
401 diff = output_mode->vdisplay -
402 (1 << 12) * output_mode->hdisplay / mode_ratio;
403 regp->fp_vert_regs[FP_VALID_START] += diff / 2;
404 regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
405 }
406 }
407
408 /* Output property. */
409 if (nv_connector->use_dithering) {
410 if (dev_priv->chipset == 0x11)
411 regp->dither = savep->dither | 0x00010000;
412 else {
413 int i;
414 regp->dither = savep->dither | 0x00000001;
415 for (i = 0; i < 3; i++) {
416 regp->dither_regs[i] = 0xe4e4e4e4;
417 regp->dither_regs[i + 3] = 0x44444444;
418 }
419 }
420 } else {
421 if (dev_priv->chipset != 0x11) {
422 /* reset them */
423 int i;
424 for (i = 0; i < 3; i++) {
425 regp->dither_regs[i] = savep->dither_regs[i];
426 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
427 }
428 }
429 regp->dither = savep->dither;
430 }
431
432 regp->fp_margin_color = 0;
433}
434
435static void nv04_dfp_commit(struct drm_encoder *encoder)
436{
437 struct drm_device *dev = encoder->dev;
438 struct drm_nouveau_private *dev_priv = dev->dev_private;
439 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
440 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
441 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
442 struct dcb_entry *dcbe = nv_encoder->dcb;
443 int head = nouveau_crtc(encoder->crtc)->index;
f5cb8ab1 444 struct drm_encoder *slave_encoder;
6ee73861 445
6ee73861
BS		 446 if (dcbe->type == OUTPUT_TMDS)
447 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
448 else if (dcbe->type == OUTPUT_LVDS)
449 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
450
451 /* update fp_control state for any changes made by scripts,
452 * so correct value is written at DPMS on */
453 dev_priv->mode_reg.crtc_reg[head].fp_control =
454 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
455
456 /* This could use refinement for flatpanels, but it should work this way */
457 if (dev_priv->chipset < 0x44)
458 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
459 else
460 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
461
4a9f822f 462 /* Init external transmitters */
f5cb8ab1
PM		 463 slave_encoder = get_tmds_slave(encoder);
464 if (slave_encoder)
465 get_slave_funcs(slave_encoder)->mode_set(
466 slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
4a9f822f 467
6ee73861
BS		 468 helper->dpms(encoder, DRM_MODE_DPMS_ON);
469
470 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
471 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
472 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
473}
474
d31e078d
FJ		 475static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
476{
477#ifdef __powerpc__
478 struct drm_device *dev = encoder->dev;
479
480 /* BIOS scripts usually take care of the backlight, thanks
481 * Apple for your consistency.
482 */
483 if (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
484 dev->pci_device == 0x0329) {
485 if (mode == DRM_MODE_DPMS_ON) {
486 nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 0, 1 << 31);
487 nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 1);
488 } else {
489 nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
490 nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 0);
491 }
492 }
493#endif
494}
495
6ee73861
BS		 496static inline bool is_powersaving_dpms(int mode)
497{
498 return (mode != DRM_MODE_DPMS_ON);
499}
500
501static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
502{
503 struct drm_device *dev = encoder->dev;
504 struct drm_crtc *crtc = encoder->crtc;
505 struct drm_nouveau_private *dev_priv = dev->dev_private;
506 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
507 bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
508
509 if (nv_encoder->last_dpms == mode)
510 return;
511 nv_encoder->last_dpms = mode;
512
513 NV_INFO(dev, "Setting dpms mode %d on lvds encoder (output %d)\n",
514 mode, nv_encoder->dcb->index);
515
516 if (was_powersaving && is_powersaving_dpms(mode))
517 return;
518
519 if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
520 struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
521
522 /* when removing an output, crtc may not be set, but PANEL_OFF
523 * must still be run
524 */
525 int head = crtc ? nouveau_crtc(crtc)->index :
526 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
527
528 if (mode == DRM_MODE_DPMS_ON) {
529 if (!nv_connector->native_mode) {
530 NV_ERROR(dev, "Not turning on LVDS without native mode\n");
531 return;
532 }
533 call_lvds_script(dev, nv_encoder->dcb, head,
534 LVDS_PANEL_ON, nv_connector->native_mode->clock);
535 } else
536 /* pxclk of 0 is fine for PANEL_OFF, and for a
537 * disconnected LVDS encoder there is no native_mode
538 */
539 call_lvds_script(dev, nv_encoder->dcb, head,
540 LVDS_PANEL_OFF, 0);
541 }
542
d31e078d 543 nv04_dfp_update_backlight(encoder, mode);
6ee73861
BS		 544 nv04_dfp_update_fp_control(encoder, mode);
545
546 if (mode == DRM_MODE_DPMS_ON)
547 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
548 else {
549 dev_priv->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
550 dev_priv->mode_reg.sel_clk &= ~0xf0;
551 }
552 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
553}
554
555static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
556{
557 struct drm_device *dev = encoder->dev;
558 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
559
560 if (nv_encoder->last_dpms == mode)
561 return;
562 nv_encoder->last_dpms = mode;
563
564 NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n",
565 mode, nv_encoder->dcb->index);
566
d31e078d 567 nv04_dfp_update_backlight(encoder, mode);
6ee73861
BS		 568 nv04_dfp_update_fp_control(encoder, mode);
569}
570
571static void nv04_dfp_save(struct drm_encoder *encoder)
572{
573 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
574 struct drm_device *dev = encoder->dev;
575
576 if (nv_two_heads(dev))
577 nv_encoder->restore.head =
578 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
579}
580
581static void nv04_dfp_restore(struct drm_encoder *encoder)
582{
583 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
584 struct drm_device *dev = encoder->dev;
585 struct drm_nouveau_private *dev_priv = dev->dev_private;
586 int head = nv_encoder->restore.head;
587
588 if (nv_encoder->dcb->type == OUTPUT_LVDS) {
589 struct drm_display_mode *native_mode = nouveau_encoder_connector_get(nv_encoder)->native_mode;
590 if (native_mode)
591 call_lvds_script(dev, nv_encoder->dcb, head, LVDS_PANEL_ON,
592 native_mode->clock);
593 else
594 NV_ERROR(dev, "Not restoring LVDS without native mode\n");
595
596 } else if (nv_encoder->dcb->type == OUTPUT_TMDS) {
597 int clock = nouveau_hw_pllvals_to_clk
598 (&dev_priv->saved_reg.crtc_reg[head].pllvals);
599
600 run_tmds_table(dev, nv_encoder->dcb, head, clock);
601 }
602
603 nv_encoder->last_dpms = NV_DPMS_CLEARED;
604}
605
606static void nv04_dfp_destroy(struct drm_encoder *encoder)
607{
608 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
609
ef2bb506 610 NV_DEBUG_KMS(encoder->dev, "\n");
6ee73861 611
4a9f822f
FJ		 612 if (get_slave_funcs(encoder))
613 get_slave_funcs(encoder)->destroy(encoder);
614
6ee73861
BS		 615 drm_encoder_cleanup(encoder);
616 kfree(nv_encoder);
617}
618
4a9f822f
FJ		 619static void nv04_tmds_slave_init(struct drm_encoder *encoder)
620{
621 struct drm_device *dev = encoder->dev;
622 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
623 struct nouveau_i2c_chan *i2c = nouveau_i2c_find(dev, 2);
624 struct i2c_board_info info[] = {
625 {
626 .type = "sil164",
627 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
628 .platform_data = &(struct sil164_encoder_params) {
629 SIL164_INPUT_EDGE_RISING
630 }
631 },
632 { }
633 };
634 int type;
635
2d14e35c
FJ		 636 if (!nv_gf4_disp_arch(dev) || !i2c ||
637 get_tmds_slave(encoder))
4a9f822f
FJ		 638 return;
639
66146da0 640 type = nouveau_i2c_identify(dev, "TMDS transmitter", info, NULL, 2);
4a9f822f
FJ		 641 if (type < 0)
642 return;
643
644 drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
645 &i2c->adapter, &info[type]);
646}
647
6ee73861
BS		 648static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
649 .dpms = nv04_lvds_dpms,
650 .save = nv04_dfp_save,
651 .restore = nv04_dfp_restore,
652 .mode_fixup = nv04_dfp_mode_fixup,
653 .prepare = nv04_dfp_prepare,
654 .commit = nv04_dfp_commit,
655 .mode_set = nv04_dfp_mode_set,
656 .detect = NULL,
657};
658
659static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
660 .dpms = nv04_tmds_dpms,
661 .save = nv04_dfp_save,
662 .restore = nv04_dfp_restore,
663 .mode_fixup = nv04_dfp_mode_fixup,
664 .prepare = nv04_dfp_prepare,
665 .commit = nv04_dfp_commit,
666 .mode_set = nv04_dfp_mode_set,
667 .detect = NULL,
668};
669
670static const struct drm_encoder_funcs nv04_dfp_funcs = {
671 .destroy = nv04_dfp_destroy,
672};
673
8f1a6086
BS		 674int
675nv04_dfp_create(struct drm_connector *connector, struct dcb_entry *entry)
6ee73861
BS		 676{
677 const struct drm_encoder_helper_funcs *helper;
6ee73861 678 struct nouveau_encoder *nv_encoder = NULL;
8f1a6086 679 struct drm_encoder *encoder;
6ee73861
BS		 680 int type;
681
682 switch (entry->type) {
683 case OUTPUT_TMDS:
684 type = DRM_MODE_ENCODER_TMDS;
685 helper = &nv04_tmds_helper_funcs;
686 break;
687 case OUTPUT_LVDS:
688 type = DRM_MODE_ENCODER_LVDS;
689 helper = &nv04_lvds_helper_funcs;
690 break;
691 default:
692 return -EINVAL;
693 }
694
695 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
696 if (!nv_encoder)
697 return -ENOMEM;
698
699 encoder = to_drm_encoder(nv_encoder);
700
701 nv_encoder->dcb = entry;
702 nv_encoder->or = ffs(entry->or) - 1;
703
8f1a6086 704 drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type);
6ee73861
BS		 705 drm_encoder_helper_add(encoder, helper);
706
707 encoder->possible_crtcs = entry->heads;
708 encoder->possible_clones = 0;
709
4a9f822f
FJ		 710 if (entry->type == OUTPUT_TMDS &&
711 entry->location != DCB_LOC_ON_CHIP)
712 nv04_tmds_slave_init(encoder);
713
8f1a6086 714 drm_mode_connector_attach_encoder(connector, encoder);
6ee73861
BS		 715 return 0;
716}
Clone of davem's net-next-2.6 tree