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drm/nouveau: detect vram amount once, and save the value
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_state.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/swab.h>
27#include "drmP.h"
28#include "drm.h"
29#include "drm_sarea.h"
30#include "drm_crtc_helper.h"
31#include <linux/vgaarb.h>
6a9ee8af 32#include <linux/vga_switcheroo.h>
6ee73861
BS		 33
34#include "nouveau_drv.h"
35#include "nouveau_drm.h"
36#include "nv50_display.h"
37
6ee73861
BS		 38static void nouveau_stub_takedown(struct drm_device *dev) {}
39
40static int nouveau_init_engine_ptrs(struct drm_device *dev)
41{
42 struct drm_nouveau_private *dev_priv = dev->dev_private;
43 struct nouveau_engine *engine = &dev_priv->engine;
44
45 switch (dev_priv->chipset & 0xf0) {
46 case 0x00:
47 engine->instmem.init = nv04_instmem_init;
48 engine->instmem.takedown = nv04_instmem_takedown;
49 engine->instmem.suspend = nv04_instmem_suspend;
50 engine->instmem.resume = nv04_instmem_resume;
51 engine->instmem.populate = nv04_instmem_populate;
52 engine->instmem.clear = nv04_instmem_clear;
53 engine->instmem.bind = nv04_instmem_bind;
54 engine->instmem.unbind = nv04_instmem_unbind;
55 engine->instmem.prepare_access = nv04_instmem_prepare_access;
56 engine->instmem.finish_access = nv04_instmem_finish_access;
57 engine->mc.init = nv04_mc_init;
58 engine->mc.takedown = nv04_mc_takedown;
59 engine->timer.init = nv04_timer_init;
60 engine->timer.read = nv04_timer_read;
61 engine->timer.takedown = nv04_timer_takedown;
62 engine->fb.init = nv04_fb_init;
63 engine->fb.takedown = nv04_fb_takedown;
64 engine->graph.grclass = nv04_graph_grclass;
65 engine->graph.init = nv04_graph_init;
66 engine->graph.takedown = nv04_graph_takedown;
67 engine->graph.fifo_access = nv04_graph_fifo_access;
68 engine->graph.channel = nv04_graph_channel;
69 engine->graph.create_context = nv04_graph_create_context;
70 engine->graph.destroy_context = nv04_graph_destroy_context;
71 engine->graph.load_context = nv04_graph_load_context;
72 engine->graph.unload_context = nv04_graph_unload_context;
73 engine->fifo.channels = 16;
74 engine->fifo.init = nv04_fifo_init;
75 engine->fifo.takedown = nouveau_stub_takedown;
76 engine->fifo.disable = nv04_fifo_disable;
77 engine->fifo.enable = nv04_fifo_enable;
78 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 79 engine->fifo.cache_flush = nv04_fifo_cache_flush;
80 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 81 engine->fifo.channel_id = nv04_fifo_channel_id;
82 engine->fifo.create_context = nv04_fifo_create_context;
83 engine->fifo.destroy_context = nv04_fifo_destroy_context;
84 engine->fifo.load_context = nv04_fifo_load_context;
85 engine->fifo.unload_context = nv04_fifo_unload_context;
86 break;
87 case 0x10:
88 engine->instmem.init = nv04_instmem_init;
89 engine->instmem.takedown = nv04_instmem_takedown;
90 engine->instmem.suspend = nv04_instmem_suspend;
91 engine->instmem.resume = nv04_instmem_resume;
92 engine->instmem.populate = nv04_instmem_populate;
93 engine->instmem.clear = nv04_instmem_clear;
94 engine->instmem.bind = nv04_instmem_bind;
95 engine->instmem.unbind = nv04_instmem_unbind;
96 engine->instmem.prepare_access = nv04_instmem_prepare_access;
97 engine->instmem.finish_access = nv04_instmem_finish_access;
98 engine->mc.init = nv04_mc_init;
99 engine->mc.takedown = nv04_mc_takedown;
100 engine->timer.init = nv04_timer_init;
101 engine->timer.read = nv04_timer_read;
102 engine->timer.takedown = nv04_timer_takedown;
103 engine->fb.init = nv10_fb_init;
104 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 105 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 106 engine->graph.grclass = nv10_graph_grclass;
107 engine->graph.init = nv10_graph_init;
108 engine->graph.takedown = nv10_graph_takedown;
109 engine->graph.channel = nv10_graph_channel;
110 engine->graph.create_context = nv10_graph_create_context;
111 engine->graph.destroy_context = nv10_graph_destroy_context;
112 engine->graph.fifo_access = nv04_graph_fifo_access;
113 engine->graph.load_context = nv10_graph_load_context;
114 engine->graph.unload_context = nv10_graph_unload_context;
cb00f7c1 115 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
6ee73861
BS		 116 engine->fifo.channels = 32;
117 engine->fifo.init = nv10_fifo_init;
118 engine->fifo.takedown = nouveau_stub_takedown;
119 engine->fifo.disable = nv04_fifo_disable;
120 engine->fifo.enable = nv04_fifo_enable;
121 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 122 engine->fifo.cache_flush = nv04_fifo_cache_flush;
123 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 124 engine->fifo.channel_id = nv10_fifo_channel_id;
125 engine->fifo.create_context = nv10_fifo_create_context;
126 engine->fifo.destroy_context = nv10_fifo_destroy_context;
127 engine->fifo.load_context = nv10_fifo_load_context;
128 engine->fifo.unload_context = nv10_fifo_unload_context;
129 break;
130 case 0x20:
131 engine->instmem.init = nv04_instmem_init;
132 engine->instmem.takedown = nv04_instmem_takedown;
133 engine->instmem.suspend = nv04_instmem_suspend;
134 engine->instmem.resume = nv04_instmem_resume;
135 engine->instmem.populate = nv04_instmem_populate;
136 engine->instmem.clear = nv04_instmem_clear;
137 engine->instmem.bind = nv04_instmem_bind;
138 engine->instmem.unbind = nv04_instmem_unbind;
139 engine->instmem.prepare_access = nv04_instmem_prepare_access;
140 engine->instmem.finish_access = nv04_instmem_finish_access;
141 engine->mc.init = nv04_mc_init;
142 engine->mc.takedown = nv04_mc_takedown;
143 engine->timer.init = nv04_timer_init;
144 engine->timer.read = nv04_timer_read;
145 engine->timer.takedown = nv04_timer_takedown;
146 engine->fb.init = nv10_fb_init;
147 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 148 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 149 engine->graph.grclass = nv20_graph_grclass;
150 engine->graph.init = nv20_graph_init;
151 engine->graph.takedown = nv20_graph_takedown;
152 engine->graph.channel = nv10_graph_channel;
153 engine->graph.create_context = nv20_graph_create_context;
154 engine->graph.destroy_context = nv20_graph_destroy_context;
155 engine->graph.fifo_access = nv04_graph_fifo_access;
156 engine->graph.load_context = nv20_graph_load_context;
157 engine->graph.unload_context = nv20_graph_unload_context;
cb00f7c1 158 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
6ee73861
BS		 159 engine->fifo.channels = 32;
160 engine->fifo.init = nv10_fifo_init;
161 engine->fifo.takedown = nouveau_stub_takedown;
162 engine->fifo.disable = nv04_fifo_disable;
163 engine->fifo.enable = nv04_fifo_enable;
164 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 165 engine->fifo.cache_flush = nv04_fifo_cache_flush;
166 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 167 engine->fifo.channel_id = nv10_fifo_channel_id;
168 engine->fifo.create_context = nv10_fifo_create_context;
169 engine->fifo.destroy_context = nv10_fifo_destroy_context;
170 engine->fifo.load_context = nv10_fifo_load_context;
171 engine->fifo.unload_context = nv10_fifo_unload_context;
172 break;
173 case 0x30:
174 engine->instmem.init = nv04_instmem_init;
175 engine->instmem.takedown = nv04_instmem_takedown;
176 engine->instmem.suspend = nv04_instmem_suspend;
177 engine->instmem.resume = nv04_instmem_resume;
178 engine->instmem.populate = nv04_instmem_populate;
179 engine->instmem.clear = nv04_instmem_clear;
180 engine->instmem.bind = nv04_instmem_bind;
181 engine->instmem.unbind = nv04_instmem_unbind;
182 engine->instmem.prepare_access = nv04_instmem_prepare_access;
183 engine->instmem.finish_access = nv04_instmem_finish_access;
184 engine->mc.init = nv04_mc_init;
185 engine->mc.takedown = nv04_mc_takedown;
186 engine->timer.init = nv04_timer_init;
187 engine->timer.read = nv04_timer_read;
188 engine->timer.takedown = nv04_timer_takedown;
189 engine->fb.init = nv10_fb_init;
190 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 191 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 192 engine->graph.grclass = nv30_graph_grclass;
193 engine->graph.init = nv30_graph_init;
194 engine->graph.takedown = nv20_graph_takedown;
195 engine->graph.fifo_access = nv04_graph_fifo_access;
196 engine->graph.channel = nv10_graph_channel;
197 engine->graph.create_context = nv20_graph_create_context;
198 engine->graph.destroy_context = nv20_graph_destroy_context;
199 engine->graph.load_context = nv20_graph_load_context;
200 engine->graph.unload_context = nv20_graph_unload_context;
cb00f7c1 201 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
6ee73861
BS		 202 engine->fifo.channels = 32;
203 engine->fifo.init = nv10_fifo_init;
204 engine->fifo.takedown = nouveau_stub_takedown;
205 engine->fifo.disable = nv04_fifo_disable;
206 engine->fifo.enable = nv04_fifo_enable;
207 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 208 engine->fifo.cache_flush = nv04_fifo_cache_flush;
209 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 210 engine->fifo.channel_id = nv10_fifo_channel_id;
211 engine->fifo.create_context = nv10_fifo_create_context;
212 engine->fifo.destroy_context = nv10_fifo_destroy_context;
213 engine->fifo.load_context = nv10_fifo_load_context;
214 engine->fifo.unload_context = nv10_fifo_unload_context;
215 break;
216 case 0x40:
217 case 0x60:
218 engine->instmem.init = nv04_instmem_init;
219 engine->instmem.takedown = nv04_instmem_takedown;
220 engine->instmem.suspend = nv04_instmem_suspend;
221 engine->instmem.resume = nv04_instmem_resume;
222 engine->instmem.populate = nv04_instmem_populate;
223 engine->instmem.clear = nv04_instmem_clear;
224 engine->instmem.bind = nv04_instmem_bind;
225 engine->instmem.unbind = nv04_instmem_unbind;
226 engine->instmem.prepare_access = nv04_instmem_prepare_access;
227 engine->instmem.finish_access = nv04_instmem_finish_access;
228 engine->mc.init = nv40_mc_init;
229 engine->mc.takedown = nv40_mc_takedown;
230 engine->timer.init = nv04_timer_init;
231 engine->timer.read = nv04_timer_read;
232 engine->timer.takedown = nv04_timer_takedown;
233 engine->fb.init = nv40_fb_init;
234 engine->fb.takedown = nv40_fb_takedown;
cb00f7c1 235 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
6ee73861
BS		 236 engine->graph.grclass = nv40_graph_grclass;
237 engine->graph.init = nv40_graph_init;
238 engine->graph.takedown = nv40_graph_takedown;
239 engine->graph.fifo_access = nv04_graph_fifo_access;
240 engine->graph.channel = nv40_graph_channel;
241 engine->graph.create_context = nv40_graph_create_context;
242 engine->graph.destroy_context = nv40_graph_destroy_context;
243 engine->graph.load_context = nv40_graph_load_context;
244 engine->graph.unload_context = nv40_graph_unload_context;
cb00f7c1 245 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
6ee73861
BS		 246 engine->fifo.channels = 32;
247 engine->fifo.init = nv40_fifo_init;
248 engine->fifo.takedown = nouveau_stub_takedown;
249 engine->fifo.disable = nv04_fifo_disable;
250 engine->fifo.enable = nv04_fifo_enable;
251 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 252 engine->fifo.cache_flush = nv04_fifo_cache_flush;
253 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 254 engine->fifo.channel_id = nv10_fifo_channel_id;
255 engine->fifo.create_context = nv40_fifo_create_context;
256 engine->fifo.destroy_context = nv40_fifo_destroy_context;
257 engine->fifo.load_context = nv40_fifo_load_context;
258 engine->fifo.unload_context = nv40_fifo_unload_context;
259 break;
260 case 0x50:
261 case 0x80: /* gotta love NVIDIA's consistency.. */
262 case 0x90:
263 case 0xA0:
264 engine->instmem.init = nv50_instmem_init;
265 engine->instmem.takedown = nv50_instmem_takedown;
266 engine->instmem.suspend = nv50_instmem_suspend;
267 engine->instmem.resume = nv50_instmem_resume;
268 engine->instmem.populate = nv50_instmem_populate;
269 engine->instmem.clear = nv50_instmem_clear;
270 engine->instmem.bind = nv50_instmem_bind;
271 engine->instmem.unbind = nv50_instmem_unbind;
272 engine->instmem.prepare_access = nv50_instmem_prepare_access;
273 engine->instmem.finish_access = nv50_instmem_finish_access;
274 engine->mc.init = nv50_mc_init;
275 engine->mc.takedown = nv50_mc_takedown;
276 engine->timer.init = nv04_timer_init;
277 engine->timer.read = nv04_timer_read;
278 engine->timer.takedown = nv04_timer_takedown;
304424e1
MK		 279 engine->fb.init = nv50_fb_init;
280 engine->fb.takedown = nv50_fb_takedown;
6ee73861
BS		 281 engine->graph.grclass = nv50_graph_grclass;
282 engine->graph.init = nv50_graph_init;
283 engine->graph.takedown = nv50_graph_takedown;
284 engine->graph.fifo_access = nv50_graph_fifo_access;
285 engine->graph.channel = nv50_graph_channel;
286 engine->graph.create_context = nv50_graph_create_context;
287 engine->graph.destroy_context = nv50_graph_destroy_context;
288 engine->graph.load_context = nv50_graph_load_context;
289 engine->graph.unload_context = nv50_graph_unload_context;
290 engine->fifo.channels = 128;
291 engine->fifo.init = nv50_fifo_init;
292 engine->fifo.takedown = nv50_fifo_takedown;
293 engine->fifo.disable = nv04_fifo_disable;
294 engine->fifo.enable = nv04_fifo_enable;
295 engine->fifo.reassign = nv04_fifo_reassign;
296 engine->fifo.channel_id = nv50_fifo_channel_id;
297 engine->fifo.create_context = nv50_fifo_create_context;
298 engine->fifo.destroy_context = nv50_fifo_destroy_context;
299 engine->fifo.load_context = nv50_fifo_load_context;
300 engine->fifo.unload_context = nv50_fifo_unload_context;
301 break;
302 default:
303 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
304 return 1;
305 }
306
307 return 0;
308}
309
310static unsigned int
311nouveau_vga_set_decode(void *priv, bool state)
312{
9967b948
MK		 313 struct drm_device *dev = priv;
314 struct drm_nouveau_private *dev_priv = dev->dev_private;
315
316 if (dev_priv->chipset >= 0x40)
317 nv_wr32(dev, 0x88054, state);
318 else
319 nv_wr32(dev, 0x1854, state);
320
6ee73861
BS		 321 if (state)
322 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
323 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
324 else
325 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
326}
327
0735f62e
BS		 328static int
329nouveau_card_init_channel(struct drm_device *dev)
330{
331 struct drm_nouveau_private *dev_priv = dev->dev_private;
332 struct nouveau_gpuobj *gpuobj;
333 int ret;
334
335 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
336 (struct drm_file *)-2,
337 NvDmaFB, NvDmaTT);
338 if (ret)
339 return ret;
340
341 gpuobj = NULL;
342 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
a76fb4e8 343 0, dev_priv->vram_size,
0735f62e
BS		 344 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
345 &gpuobj);
346 if (ret)
347 goto out_err;
348
349 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
350 gpuobj, NULL);
351 if (ret)
352 goto out_err;
353
354 gpuobj = NULL;
355 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
356 dev_priv->gart_info.aper_size,
357 NV_DMA_ACCESS_RW, &gpuobj, NULL);
358 if (ret)
359 goto out_err;
360
361 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
362 gpuobj, NULL);
363 if (ret)
364 goto out_err;
365
366 return 0;
367out_err:
368 nouveau_gpuobj_del(dev, &gpuobj);
369 nouveau_channel_free(dev_priv->channel);
370 dev_priv->channel = NULL;
371 return ret;
372}
373
6a9ee8af
DA		 374static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
375 enum vga_switcheroo_state state)
376{
377 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
378 if (state == VGA_SWITCHEROO_ON) {
379 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
380 nouveau_pci_resume(pdev);
381 } else {
382 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
383 nouveau_pci_suspend(pdev, pmm);
384 }
385}
386
387static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
388{
389 struct drm_device *dev = pci_get_drvdata(pdev);
390 bool can_switch;
391
392 spin_lock(&dev->count_lock);
393 can_switch = (dev->open_count == 0);
394 spin_unlock(&dev->count_lock);
395 return can_switch;
396}
397
6ee73861
BS		 398int
399nouveau_card_init(struct drm_device *dev)
400{
401 struct drm_nouveau_private *dev_priv = dev->dev_private;
402 struct nouveau_engine *engine;
6ee73861
BS		 403 int ret;
404
405 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
406
407 if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
408 return 0;
409
410 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
6a9ee8af
DA		 411 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
412 nouveau_switcheroo_can_switch);
6ee73861
BS		 413
414 /* Initialise internal driver API hooks */
415 ret = nouveau_init_engine_ptrs(dev);
416 if (ret)
c5804be0 417 goto out;
6ee73861
BS		 418 engine = &dev_priv->engine;
419 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
ff9e5279 420 spin_lock_init(&dev_priv->context_switch_lock);
6ee73861
BS		 421
422 /* Parse BIOS tables / Run init tables if card not POSTed */
423 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
424 ret = nouveau_bios_init(dev);
425 if (ret)
c5804be0 426 goto out;
6ee73861
BS		 427 }
428
a76fb4e8
BS		 429 ret = nouveau_mem_detect(dev);
430 if (ret)
431 goto out_bios;
432
6ee73861
BS		 433 ret = nouveau_gpuobj_early_init(dev);
434 if (ret)
c5804be0 435 goto out_bios;
6ee73861
BS		 436
437 /* Initialise instance memory, must happen before mem_init so we
438 * know exactly how much VRAM we're able to use for "normal"
439 * purposes.
440 */
441 ret = engine->instmem.init(dev);
442 if (ret)
c5804be0 443 goto out_gpuobj_early;
6ee73861
BS		 444
445 /* Setup the memory manager */
446 ret = nouveau_mem_init(dev);
447 if (ret)
c5804be0 448 goto out_instmem;
6ee73861
BS		 449
450 ret = nouveau_gpuobj_init(dev);
451 if (ret)
c5804be0 452 goto out_mem;
6ee73861
BS		 453
454 /* PMC */
455 ret = engine->mc.init(dev);
456 if (ret)
c5804be0 457 goto out_gpuobj;
6ee73861
BS		 458
459 /* PTIMER */
460 ret = engine->timer.init(dev);
461 if (ret)
c5804be0 462 goto out_mc;
6ee73861
BS		 463
464 /* PFB */
465 ret = engine->fb.init(dev);
466 if (ret)
c5804be0 467 goto out_timer;
6ee73861 468
a32ed69d
MK		 469 if (nouveau_noaccel)
470 engine->graph.accel_blocked = true;
471 else {
472 /* PGRAPH */
473 ret = engine->graph.init(dev);
474 if (ret)
475 goto out_fb;
6ee73861 476
a32ed69d
MK		 477 /* PFIFO */
478 ret = engine->fifo.init(dev);
479 if (ret)
480 goto out_graph;
481 }
6ee73861
BS		 482
483 /* this call irq_preinstall, register irq handler and
484 * call irq_postinstall
485 */
486 ret = drm_irq_install(dev);
487 if (ret)
c5804be0 488 goto out_fifo;
6ee73861
BS		 489
490 ret = drm_vblank_init(dev, 0);
491 if (ret)
c5804be0 492 goto out_irq;
6ee73861
BS		 493
494 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
495
0735f62e
BS		 496 if (!engine->graph.accel_blocked) {
497 ret = nouveau_card_init_channel(dev);
498 if (ret)
499 goto out_irq;
6ee73861
BS		 500 }
501
502 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c5804be0 503 if (dev_priv->card_type >= NV_50)
6ee73861 504 ret = nv50_display_create(dev);
c5804be0 505 else
6ee73861 506 ret = nv04_display_create(dev);
c5804be0
MK		 507 if (ret)
508 goto out_irq;
6ee73861
BS		 509 }
510
511 ret = nouveau_backlight_init(dev);
512 if (ret)
513 NV_ERROR(dev, "Error %d registering backlight\n", ret);
514
515 dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
516
517 if (drm_core_check_feature(dev, DRIVER_MODESET))
518 drm_helper_initial_config(dev);
519
520 return 0;
c5804be0
MK		 521
522out_irq:
523 drm_irq_uninstall(dev);
524out_fifo:
a32ed69d
MK		 525 if (!nouveau_noaccel)
526 engine->fifo.takedown(dev);
c5804be0 527out_graph:
a32ed69d
MK		 528 if (!nouveau_noaccel)
529 engine->graph.takedown(dev);
c5804be0
MK		 530out_fb:
531 engine->fb.takedown(dev);
532out_timer:
533 engine->timer.takedown(dev);
534out_mc:
535 engine->mc.takedown(dev);
536out_gpuobj:
537 nouveau_gpuobj_takedown(dev);
538out_mem:
539 nouveau_mem_close(dev);
540out_instmem:
541 engine->instmem.takedown(dev);
542out_gpuobj_early:
543 nouveau_gpuobj_late_takedown(dev);
544out_bios:
545 nouveau_bios_takedown(dev);
546out:
547 vga_client_register(dev->pdev, NULL, NULL, NULL);
548 return ret;
6ee73861
BS		 549}
550
551static void nouveau_card_takedown(struct drm_device *dev)
552{
553 struct drm_nouveau_private *dev_priv = dev->dev_private;
554 struct nouveau_engine *engine = &dev_priv->engine;
555
556 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
557
558 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
559 nouveau_backlight_exit(dev);
560
561 if (dev_priv->channel) {
562 nouveau_channel_free(dev_priv->channel);
563 dev_priv->channel = NULL;
564 }
565
a32ed69d
MK		 566 if (!nouveau_noaccel) {
567 engine->fifo.takedown(dev);
568 engine->graph.takedown(dev);
569 }
6ee73861
BS		 570 engine->fb.takedown(dev);
571 engine->timer.takedown(dev);
572 engine->mc.takedown(dev);
573
574 mutex_lock(&dev->struct_mutex);
71666475 575 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
6ee73861
BS		 576 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
577 mutex_unlock(&dev->struct_mutex);
578 nouveau_sgdma_takedown(dev);
579
580 nouveau_gpuobj_takedown(dev);
581 nouveau_mem_close(dev);
582 engine->instmem.takedown(dev);
583
584 if (drm_core_check_feature(dev, DRIVER_MODESET))
585 drm_irq_uninstall(dev);
586
587 nouveau_gpuobj_late_takedown(dev);
588 nouveau_bios_takedown(dev);
589
590 vga_client_register(dev->pdev, NULL, NULL, NULL);
591
592 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
593 }
594}
595
596/* here a client dies, release the stuff that was allocated for its
597 * file_priv */
598void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
599{
600 nouveau_channel_cleanup(dev, file_priv);
601}
602
603/* first module load, setup the mmio/fb mapping */
604/* KMS: we need mmio at load time, not when the first drm client opens. */
605int nouveau_firstopen(struct drm_device *dev)
606{
607 return 0;
608}
609
610/* if we have an OF card, copy vbios to RAMIN */
611static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
612{
613#if defined(__powerpc__)
614 int size, i;
615 const uint32_t *bios;
616 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
617 if (!dn) {
618 NV_INFO(dev, "Unable to get the OF node\n");
619 return;
620 }
621
622 bios = of_get_property(dn, "NVDA,BMP", &size);
623 if (bios) {
624 for (i = 0; i < size; i += 4)
625 nv_wi32(dev, i, bios[i/4]);
626 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
627 } else {
628 NV_INFO(dev, "Unable to get the OF bios\n");
629 }
630#endif
631}
632
633int nouveau_load(struct drm_device *dev, unsigned long flags)
634{
635 struct drm_nouveau_private *dev_priv;
636 uint32_t reg0;
637 resource_size_t mmio_start_offs;
638
639 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
640 if (!dev_priv)
641 return -ENOMEM;
642 dev->dev_private = dev_priv;
643 dev_priv->dev = dev;
644
645 dev_priv->flags = flags & NOUVEAU_FLAGS;
646 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
647
648 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
649 dev->pci_vendor, dev->pci_device, dev->pdev->class);
650
6ee73861
BS		 651 dev_priv->wq = create_workqueue("nouveau");
652 if (!dev_priv->wq)
653 return -EINVAL;
654
655 /* resource 0 is mmio regs */
656 /* resource 1 is linear FB */
657 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
658 /* resource 6 is bios */
659
660 /* map the mmio regs */
661 mmio_start_offs = pci_resource_start(dev->pdev, 0);
662 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
663 if (!dev_priv->mmio) {
664 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
665 "Please report your setup to " DRIVER_EMAIL "\n");
666 return -EINVAL;
667 }
668 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
669 (unsigned long long)mmio_start_offs);
670
671#ifdef __BIG_ENDIAN
672 /* Put the card in BE mode if it's not */
673 if (nv_rd32(dev, NV03_PMC_BOOT_1))
674 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
675
676 DRM_MEMORYBARRIER();
677#endif
678
679 /* Time to determine the card architecture */
680 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
681
682 /* We're dealing with >=NV10 */
683 if ((reg0 & 0x0f000000) > 0) {
684 /* Bit 27-20 contain the architecture in hex */
685 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
686 /* NV04 or NV05 */
687 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1dee7a93
BS		 688 if (reg0 & 0x00f00000)
689 dev_priv->chipset = 0x05;
690 else
691 dev_priv->chipset = 0x04;
6ee73861
BS		 692 } else
693 dev_priv->chipset = 0xff;
694
695 switch (dev_priv->chipset & 0xf0) {
696 case 0x00:
697 case 0x10:
698 case 0x20:
699 case 0x30:
700 dev_priv->card_type = dev_priv->chipset & 0xf0;
701 break;
702 case 0x40:
703 case 0x60:
704 dev_priv->card_type = NV_40;
705 break;
706 case 0x50:
707 case 0x80:
708 case 0x90:
709 case 0xa0:
710 dev_priv->card_type = NV_50;
711 break;
712 default:
713 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
714 return -EINVAL;
715 }
716
717 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
718 dev_priv->card_type, reg0);
719
720 /* map larger RAMIN aperture on NV40 cards */
721 dev_priv->ramin = NULL;
722 if (dev_priv->card_type >= NV_40) {
723 int ramin_bar = 2;
724 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
725 ramin_bar = 3;
726
727 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
728 dev_priv->ramin = ioremap(
729 pci_resource_start(dev->pdev, ramin_bar),
730 dev_priv->ramin_size);
731 if (!dev_priv->ramin) {
732 NV_ERROR(dev, "Failed to init RAMIN mapping, "
733 "limited instance memory available\n");
734 }
735 }
736
737 /* On older cards (or if the above failed), create a map covering
738 * the BAR0 PRAMIN aperture */
739 if (!dev_priv->ramin) {
740 dev_priv->ramin_size = 1 * 1024 * 1024;
741 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
742 dev_priv->ramin_size);
743 if (!dev_priv->ramin) {
744 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
745 return -ENOMEM;
746 }
747 }
748
749 nouveau_OF_copy_vbios_to_ramin(dev);
750
751 /* Special flags */
752 if (dev->pci_device == 0x01a0)
753 dev_priv->flags |= NV_NFORCE;
754 else if (dev->pci_device == 0x01f0)
755 dev_priv->flags |= NV_NFORCE2;
756
757 /* For kernel modesetting, init card now and bring up fbcon */
758 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
759 int ret = nouveau_card_init(dev);
760 if (ret)
761 return ret;
762 }
763
764 return 0;
765}
766
767static void nouveau_close(struct drm_device *dev)
768{
769 struct drm_nouveau_private *dev_priv = dev->dev_private;
770
111b459a
FJ		 771 /* In the case of an error dev_priv may not be allocated yet */
772 if (dev_priv)
6ee73861
BS		 773 nouveau_card_takedown(dev);
774}
775
776/* KMS: we need mmio at load time, not when the first drm client opens. */
777void nouveau_lastclose(struct drm_device *dev)
778{
779 if (drm_core_check_feature(dev, DRIVER_MODESET))
780 return;
781
782 nouveau_close(dev);
783}
784
785int nouveau_unload(struct drm_device *dev)
786{
787 struct drm_nouveau_private *dev_priv = dev->dev_private;
788
789 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
790 if (dev_priv->card_type >= NV_50)
791 nv50_display_destroy(dev);
792 else
793 nv04_display_destroy(dev);
794 nouveau_close(dev);
795 }
796
797 iounmap(dev_priv->mmio);
798 iounmap(dev_priv->ramin);
799
800 kfree(dev_priv);
801 dev->dev_private = NULL;
802 return 0;
803}
804
6ee73861
BS		 805int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
806 struct drm_file *file_priv)
807{
808 struct drm_nouveau_private *dev_priv = dev->dev_private;
809 struct drm_nouveau_getparam *getparam = data;
810
811 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
812
813 switch (getparam->param) {
814 case NOUVEAU_GETPARAM_CHIPSET_ID:
815 getparam->value = dev_priv->chipset;
816 break;
817 case NOUVEAU_GETPARAM_PCI_VENDOR:
818 getparam->value = dev->pci_vendor;
819 break;
820 case NOUVEAU_GETPARAM_PCI_DEVICE:
821 getparam->value = dev->pci_device;
822 break;
823 case NOUVEAU_GETPARAM_BUS_TYPE:
824 if (drm_device_is_agp(dev))
825 getparam->value = NV_AGP;
826 else if (drm_device_is_pcie(dev))
827 getparam->value = NV_PCIE;
828 else
829 getparam->value = NV_PCI;
830 break;
831 case NOUVEAU_GETPARAM_FB_PHYSICAL:
832 getparam->value = dev_priv->fb_phys;
833 break;
834 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
835 getparam->value = dev_priv->gart_info.aper_base;
836 break;
837 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
838 if (dev->sg) {
839 getparam->value = (unsigned long)dev->sg->virtual;
840 } else {
841 NV_ERROR(dev, "Requested PCIGART address, "
842 "while no PCIGART was created\n");
843 return -EINVAL;
844 }
845 break;
846 case NOUVEAU_GETPARAM_FB_SIZE:
847 getparam->value = dev_priv->fb_available_size;
848 break;
849 case NOUVEAU_GETPARAM_AGP_SIZE:
850 getparam->value = dev_priv->gart_info.aper_size;
851 break;
852 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
853 getparam->value = dev_priv->vm_vram_base;
854 break;
69c9700b
MK		 855 case NOUVEAU_GETPARAM_GRAPH_UNITS:
856 /* NV40 and NV50 versions are quite different, but register
857 * address is the same. User is supposed to know the card
858 * family anyway... */
859 if (dev_priv->chipset >= 0x40) {
860 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
861 break;
862 }
863 /* FALLTHRU */
6ee73861
BS		 864 default:
865 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
866 return -EINVAL;
867 }
868
869 return 0;
870}
871
872int
873nouveau_ioctl_setparam(struct drm_device *dev, void *data,
874 struct drm_file *file_priv)
875{
876 struct drm_nouveau_setparam *setparam = data;
877
878 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
879
880 switch (setparam->param) {
881 default:
882 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
883 return -EINVAL;
884 }
885
886 return 0;
887}
888
889/* Wait until (value(reg) & mask) == val, up until timeout has hit */
890bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
891 uint32_t reg, uint32_t mask, uint32_t val)
892{
893 struct drm_nouveau_private *dev_priv = dev->dev_private;
894 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
895 uint64_t start = ptimer->read(dev);
896
897 do {
898 if ((nv_rd32(dev, reg) & mask) == val)
899 return true;
900 } while (ptimer->read(dev) - start < timeout);
901
902 return false;
903}
904
905/* Waits for PGRAPH to go completely idle */
906bool nouveau_wait_for_idle(struct drm_device *dev)
907{
908 if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
909 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
910 nv_rd32(dev, NV04_PGRAPH_STATUS));
911 return false;
912 }
913
914 return true;
915}
916
Clone of davem's net-next-2.6 tree