[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_mem.c

/*
 * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
 * Copyright 2005 Stephane Marchesin
 *
 * The Weather Channel (TM) funded Tungsten Graphics to develop the
 * initial release of the Radeon 8500 driver under the XFree86 license.
 * This notice must be preserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Whitwell <keith@tungstengraphics.com>
 */


#include "drmP.h"
#include "drm.h"
#include "drm_sarea.h"
#include "nouveau_drv.h"

/*
 * NV10-NV40 tiling helpers
 */

static void
nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
			   uint32_t size, uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	tile->addr = addr;
	tile->size = size;
	tile->used = !!pitch;
	nouveau_fence_unref((void **)&tile->fence);

	if (!pfifo->cache_flush(dev))
		return;

	pfifo->reassign(dev, false);
	pfifo->cache_flush(dev);
	pfifo->cache_pull(dev, false);

	nouveau_wait_for_idle(dev);

	pgraph->set_region_tiling(dev, i, addr, size, pitch);
	pfb->set_region_tiling(dev, i, addr, size, pitch);

	pfifo->cache_pull(dev, true);
	pfifo->reassign(dev, true);
}

struct nouveau_tile_reg *
nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
		    uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
	int i;

	spin_lock(&dev_priv->tile.lock);

	for (i = 0; i < pfb->num_tiles; i++) {
		if (tile[i].used)
			/* Tile region in use. */
			continue;

		if (tile[i].fence &&
		    !nouveau_fence_signalled(tile[i].fence, NULL))
			/* Pending tile region. */
			continue;

		if (max(tile[i].addr, addr) <
		    min(tile[i].addr + tile[i].size, addr + size))
			/* Kill an intersecting tile region. */
			nv10_mem_set_region_tiling(dev, i, 0, 0, 0);

		if (pitch && !found) {
			/* Free tile region. */
			nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
			found = &tile[i];
		}
	}

	spin_unlock(&dev_priv->tile.lock);

	return found;
}

void
nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
		       struct nouveau_fence *fence)
{
	if (fence) {
		/* Mark it as pending. */
		tile->fence = fence;
		nouveau_fence_ref(fence);
	}

	tile->used = false;
}

/*
 * NV50 VM helpers
 */
int
nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
			uint32_t flags, uint64_t phys)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *pgt;
	unsigned block;
	int i;

	virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
	size = (size >> 16) << 1;

	phys |= ((uint64_t)flags << 32);
	phys |= 1;
	if (dev_priv->vram_sys_base) {
		phys += dev_priv->vram_sys_base;
		phys |= 0x30;
	}

	dev_priv->engine.instmem.prepare_access(dev, true);
	while (size) {
		unsigned offset_h = upper_32_bits(phys);
		unsigned offset_l = lower_32_bits(phys);
		unsigned pte, end;

		for (i = 7; i >= 0; i--) {
			block = 1 << (i + 1);
			if (size >= block && !(virt & (block - 1)))
				break;
		}
		offset_l |= (i << 7);

		phys += block << 15;
		size -= block;

		while (block) {
			pgt = dev_priv->vm_vram_pt[virt >> 14];
			pte = virt & 0x3ffe;

			end = pte + block;
			if (end > 16384)
				end = 16384;
			block -= (end - pte);
			virt  += (end - pte);

			while (pte < end) {
				nv_wo32(dev, pgt, pte++, offset_l);
				nv_wo32(dev, pgt, pte++, offset_h);
			}
		}
	}
	dev_priv->engine.instmem.finish_access(dev);

	nv_wr32(dev, 0x100c80, 0x00050001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return -EBUSY;
	}

	nv_wr32(dev, 0x100c80, 0x00000001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return -EBUSY;
	}

	nv_wr32(dev, 0x100c80, 0x00040001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return -EBUSY;
	}

	nv_wr32(dev, 0x100c80, 0x00060001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return -EBUSY;
	}

	return 0;
}

void
nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *pgt;
	unsigned pages, pte, end;

	virt -= dev_priv->vm_vram_base;
	pages = (size >> 16) << 1;

	dev_priv->engine.instmem.prepare_access(dev, true);
	while (pages) {
		pgt = dev_priv->vm_vram_pt[virt >> 29];
		pte = (virt & 0x1ffe0000ULL) >> 15;

		end = pte + pages;
		if (end > 16384)
			end = 16384;
		pages -= (end - pte);
		virt  += (end - pte) << 15;

		while (pte < end)
			nv_wo32(dev, pgt, pte++, 0);
	}
	dev_priv->engine.instmem.finish_access(dev);

	nv_wr32(dev, 0x100c80, 0x00050001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return;
	}

	nv_wr32(dev, 0x100c80, 0x00000001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return;
	}

	nv_wr32(dev, 0x100c80, 0x00040001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return;
	}

	nv_wr32(dev, 0x100c80, 0x00060001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	}
}

/*
 * Cleanup everything
 */
void
nouveau_mem_close(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	nouveau_bo_unpin(dev_priv->vga_ram);
	nouveau_bo_ref(NULL, &dev_priv->vga_ram);

	ttm_bo_device_release(&dev_priv->ttm.bdev);

	nouveau_ttm_global_release(dev_priv);

	if (drm_core_has_AGP(dev) && dev->agp) {
		struct drm_agp_mem *entry, *tempe;

		/* Remove AGP resources, but leave dev->agp
		   intact until drv_cleanup is called. */
		list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
			if (entry->bound)
				drm_unbind_agp(entry->memory);
			drm_free_agp(entry->memory, entry->pages);
			kfree(entry);
		}
		INIT_LIST_HEAD(&dev->agp->memory);

		if (dev->agp->acquired)
			drm_agp_release(dev);

		dev->agp->acquired = 0;
		dev->agp->enabled = 0;
	}

	if (dev_priv->fb_mtrr) {
		drm_mtrr_del(dev_priv->fb_mtrr,
			     pci_resource_start(dev->pdev, 1),
			     pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
		dev_priv->fb_mtrr = 0;
	}
}

static uint32_t
nouveau_mem_detect_nv04(struct drm_device *dev)
{
	uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0);

	if (boot0 & 0x00000100)
		return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;

	switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) {
	case NV04_BOOT_0_RAM_AMOUNT_32MB:
		return 32 * 1024 * 1024;
	case NV04_BOOT_0_RAM_AMOUNT_16MB:
		return 16 * 1024 * 1024;
	case NV04_BOOT_0_RAM_AMOUNT_8MB:
		return 8 * 1024 * 1024;
	case NV04_BOOT_0_RAM_AMOUNT_4MB:
		return 4 * 1024 * 1024;
	}

	return 0;
}

static uint32_t
nouveau_mem_detect_nforce(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct pci_dev *bridge;
	uint32_t mem;

	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	if (!bridge) {
		NV_ERROR(dev, "no bridge device\n");
		return 0;
	}

	if (dev_priv->flags & NV_NFORCE) {
		pci_read_config_dword(bridge, 0x7C, &mem);
		return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
	} else
	if (dev_priv->flags & NV_NFORCE2) {
		pci_read_config_dword(bridge, 0x84, &mem);
		return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
	}

	NV_ERROR(dev, "impossible!\n");
	return 0;
}

/* returns the amount of FB ram in bytes */
int
nouveau_mem_detect(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (dev_priv->card_type == NV_04) {
		dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
	} else
	if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
		dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
	} else {
		dev_priv->vram_size  = nv_rd32(dev, NV04_FIFO_DATA);
		dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK;
		if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
			dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
			dev_priv->vram_sys_base <<= 12;
	}

	NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
	if (dev_priv->vram_sys_base) {
		NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
			dev_priv->vram_sys_base);
	}

	if (dev_priv->vram_size)
		return 0;
	return -ENOMEM;
}

#if __OS_HAS_AGP
static void nouveau_mem_reset_agp(struct drm_device *dev)
{
	uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable;

	saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
	saved_pci_nv_19 = nv_rd32(dev, NV04_PBUS_PCI_NV_19);

	/* clear busmaster bit */
	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
	/* clear SBA and AGP bits */
	nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff);

	/* power cycle pgraph, if enabled */
	pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
	if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
		nv_wr32(dev, NV03_PMC_ENABLE,
				pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
		nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
				NV_PMC_ENABLE_PGRAPH);
	}

	/* and restore (gives effect of resetting AGP) */
	nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
}
#endif

int
nouveau_mem_init_agp(struct drm_device *dev)
{
#if __OS_HAS_AGP
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct drm_agp_info info;
	struct drm_agp_mode mode;
	int ret;

	if (nouveau_noagp)
		return 0;

	nouveau_mem_reset_agp(dev);

	if (!dev->agp->acquired) {
		ret = drm_agp_acquire(dev);
		if (ret) {
			NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
			return ret;
		}
	}

	ret = drm_agp_info(dev, &info);
	if (ret) {
		NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
		return ret;
	}

	/* see agp.h for the AGPSTAT_* modes available */
	mode.mode = info.mode;
	ret = drm_agp_enable(dev, mode);
	if (ret) {
		NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
		return ret;
	}

	dev_priv->gart_info.type	= NOUVEAU_GART_AGP;
	dev_priv->gart_info.aper_base	= info.aperture_base;
	dev_priv->gart_info.aper_size	= info.aperture_size;
#endif
	return 0;
}

int
nouveau_mem_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	int ret, dma_bits = 32;

	dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
	dev_priv->gart_info.type = NOUVEAU_GART_NONE;

	if (dev_priv->card_type >= NV_50 &&
	    pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
		dma_bits = 40;

	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
	if (ret) {
		NV_ERROR(dev, "Error setting DMA mask: %d\n", ret);
		return ret;
	}

	ret = nouveau_ttm_global_init(dev_priv);
	if (ret)
		return ret;

	ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
				 dev_priv->ttm.bo_global_ref.ref.object,
				 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
				 dma_bits <= 32 ? true : false);
	if (ret) {
		NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
		return ret;
	}

	INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
	spin_lock_init(&dev_priv->ttm.bo_list_lock);
	spin_lock_init(&dev_priv->tile.lock);

	dev_priv->fb_available_size = dev_priv->vram_size;
	dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
	if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
		dev_priv->fb_mappable_pages =
			pci_resource_len(dev->pdev, 1);
	dev_priv->fb_mappable_pages >>= PAGE_SHIFT;

	/* remove reserved space at end of vram from available amount */
	dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
	dev_priv->fb_aper_free = dev_priv->fb_available_size;

	/* mappable vram */
	ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
			     dev_priv->fb_available_size >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
		return ret;
	}

	ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
			     0, 0, true, true, &dev_priv->vga_ram);
	if (ret == 0)
		ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
	if (ret) {
		NV_WARN(dev, "failed to reserve VGA memory\n");
		nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	}

	/* GART */
#if !defined(__powerpc__) && !defined(__ia64__)
	if (drm_device_is_agp(dev) && dev->agp) {
		ret = nouveau_mem_init_agp(dev);
		if (ret)
			NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
	}
#endif

	if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
		ret = nouveau_sgdma_init(dev);
		if (ret) {
			NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
			return ret;
		}
	}

	NV_INFO(dev, "%d MiB GART (aperture)\n",
		(int)(dev_priv->gart_info.aper_size >> 20));
	dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;

	ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
			     dev_priv->gart_info.aper_size >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
		return ret;
	}

	dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
					 pci_resource_len(dev->pdev, 1),
					 DRM_MTRR_WC);

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
	3	* Copyright 2005 Stephane Marchesin
	4	*
	5	* The Weather Channel (TM) funded Tungsten Graphics to develop the
	6	* initial release of the Radeon 8500 driver under the XFree86 license.
	7	* This notice must be preserved.
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a
	10	* copy of this software and associated documentation files (the "Software"),
	11	* to deal in the Software without restriction, including without limitation
	12	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	13	* and/or sell copies of the Software, and to permit persons to whom the
	14	* Software is furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the next
	17	* paragraph) shall be included in all copies or substantial portions of the
	18	* Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	21	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	23	* THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	24	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	25	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	26	* DEALINGS IN THE SOFTWARE.
	27	*
	28	* Authors:
	29	* Keith Whitwell <keith@tungstengraphics.com>
	30	*/
	31
	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "drm_sarea.h"
	36	#include "nouveau_drv.h"
	37
a0af9add FJ	38	/*
	39	* NV10-NV40 tiling helpers
	40	*/
	41
	42	static void
	43	nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
	44	uint32_t size, uint32_t pitch)
	45	{
	46	struct drm_nouveau_private *dev_priv = dev->dev_private;
	47	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	48	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	49	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	50	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
	51
	52	tile->addr = addr;
	53	tile->size = size;
	54	tile->used = !!pitch;
	55	nouveau_fence_unref((void **)&tile->fence);
	56
	57	if (!pfifo->cache_flush(dev))
	58	return;
	59
	60	pfifo->reassign(dev, false);
	61	pfifo->cache_flush(dev);
	62	pfifo->cache_pull(dev, false);
	63
	64	nouveau_wait_for_idle(dev);
	65
	66	pgraph->set_region_tiling(dev, i, addr, size, pitch);
	67	pfb->set_region_tiling(dev, i, addr, size, pitch);
	68
	69	pfifo->cache_pull(dev, true);
	70	pfifo->reassign(dev, true);
	71	}
	72
	73	struct nouveau_tile_reg *
	74	nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
	75	uint32_t pitch)
	76	{
	77	struct drm_nouveau_private *dev_priv = dev->dev_private;
	78	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	79	struct nouveau_tile_reg tile = dev_priv->tile.reg, found = NULL;
	80	int i;
	81
	82	spin_lock(&dev_priv->tile.lock);
	83
	84	for (i = 0; i < pfb->num_tiles; i++) {
	85	if (tile[i].used)
	86	/* Tile region in use. */
	87	continue;
	88
	89	if (tile[i].fence &&
	90	!nouveau_fence_signalled(tile[i].fence, NULL))
	91	/* Pending tile region. */
	92	continue;
	93
	94	if (max(tile[i].addr, addr) <
	95	min(tile[i].addr + tile[i].size, addr + size))
	96	/* Kill an intersecting tile region. */
	97	nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
	98
	99	if (pitch && !found) {
	100	/* Free tile region. */
	101	nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
102	found = &tile[i];
103	}
104	}
105
106	spin_unlock(&dev_priv->tile.lock);
107
108	return found;
109	}
110
111	void
112	nv10_mem_expire_tiling(struct drm_device dev, struct nouveau_tile_reg tile,
113	struct nouveau_fence *fence)
114	{
115	if (fence) {
116	/* Mark it as pending. */
117	tile->fence = fence;
118	nouveau_fence_ref(fence);
119	}
120
121	tile->used = false;
122	}
123
6ee73861 BS	124	/*
	125	* NV50 VM helpers
	126	*/
	127	int
	128	nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
	129	uint32_t flags, uint64_t phys)
	130	{
	131	struct drm_nouveau_private *dev_priv = dev->dev_private;
531e7713 BS	132	struct nouveau_gpuobj *pgt;
	133	unsigned block;
	134	int i;
6ee73861	135
531e7713 BS	136	virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
531e7713 BS	137	size = (size >> 16) << 1;
6c429667 BS	138
	139	phys \|= ((uint64_t)flags << 32);
	140	phys \|= 1;
	141	if (dev_priv->vram_sys_base) {
	142	phys += dev_priv->vram_sys_base;
	143	phys \|= 0x30;
	144	}
6ee73861 BS	145
6ee73861 BS	146	dev_priv->engine.instmem.prepare_access(dev, true);
531e7713 BS	147	while (size) {
531e7713 BS	148	unsigned offset_h = upper_32_bits(phys);
4c27bd33	149	unsigned offset_l = lower_32_bits(phys);
531e7713 BS	150	unsigned pte, end;
	151
	152	for (i = 7; i >= 0; i--) {
	153	block = 1 << (i + 1);
	154	if (size >= block && !(virt & (block - 1)))
	155	break;
	156	}
	157	offset_l \|= (i << 7);
6ee73861	158
531e7713 BS	159	phys += block << 15;
531e7713 BS	160	size -= block;
6ee73861	161
531e7713 BS	162	while (block) {
	163	pgt = dev_priv->vm_vram_pt[virt >> 14];
	164	pte = virt & 0x3ffe;
	165
	166	end = pte + block;
	167	if (end > 16384)
	168	end = 16384;
	169	block -= (end - pte);
	170	virt += (end - pte);
	171
	172	while (pte < end) {
	173	nv_wo32(dev, pgt, pte++, offset_l);
	174	nv_wo32(dev, pgt, pte++, offset_h);
	175	}
	176	}
6ee73861 BS	177	}
	178	dev_priv->engine.instmem.finish_access(dev);
	179
	180	nv_wr32(dev, 0x100c80, 0x00050001);
	181	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	182	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	183	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	184	return -EBUSY;
	185	}
	186
	187	nv_wr32(dev, 0x100c80, 0x00000001);
	188	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	189	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	190	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	191	return -EBUSY;
	192	}
	193
40b2a687 BS	194	nv_wr32(dev, 0x100c80, 0x00040001);
	195	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	196	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	197	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	198	return -EBUSY;
	199	}
	200
	201	nv_wr32(dev, 0x100c80, 0x00060001);
	202	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	203	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	204	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	205	return -EBUSY;
	206	}
	207
6ee73861 BS	208	return 0;
	209	}
	210
	211	void
	212	nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
	213	{
4c27bd33 BS	214	struct drm_nouveau_private *dev_priv = dev->dev_private;
	215	struct nouveau_gpuobj *pgt;
	216	unsigned pages, pte, end;
	217
	218	virt -= dev_priv->vm_vram_base;
	219	pages = (size >> 16) << 1;
	220
	221	dev_priv->engine.instmem.prepare_access(dev, true);
	222	while (pages) {
	223	pgt = dev_priv->vm_vram_pt[virt >> 29];
	224	pte = (virt & 0x1ffe0000ULL) >> 15;
	225
	226	end = pte + pages;
	227	if (end > 16384)
	228	end = 16384;
	229	pages -= (end - pte);
	230	virt += (end - pte) << 15;
	231
	232	while (pte < end)
	233	nv_wo32(dev, pgt, pte++, 0);
	234	}
	235	dev_priv->engine.instmem.finish_access(dev);
	236
	237	nv_wr32(dev, 0x100c80, 0x00050001);
	238	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	239	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	240	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	241	return;
	242	}
	243
	244	nv_wr32(dev, 0x100c80, 0x00000001);
40b2a687 BS	245	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	246	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	247	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	248	return;
	249	}
	250
	251	nv_wr32(dev, 0x100c80, 0x00040001);
	252	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	253	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	254	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	255	return;
	256	}
	257
	258	nv_wr32(dev, 0x100c80, 0x00060001);
4c27bd33 BS	259	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	260	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	261	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	262	}
6ee73861 BS	263	}
	264
	265	/*
	266	* Cleanup everything
	267	*/
b833ac26 BS	268	void
b833ac26 BS	269	nouveau_mem_close(struct drm_device *dev)
6ee73861 BS	270	{
	271	struct drm_nouveau_private *dev_priv = dev->dev_private;
	272
ac8fb975 BS	273	nouveau_bo_unpin(dev_priv->vga_ram);
	274	nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	275
6ee73861 BS	276	ttm_bo_device_release(&dev_priv->ttm.bdev);
	277
	278	nouveau_ttm_global_release(dev_priv);
	279
cd0b072f	280	if (drm_core_has_AGP(dev) && dev->agp) {
6ee73861 BS	281	struct drm_agp_mem entry, tempe;
	282
	283	/* Remove AGP resources, but leave dev->agp
	284	intact until drv_cleanup is called. */
	285	list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
	286	if (entry->bound)
	287	drm_unbind_agp(entry->memory);
	288	drm_free_agp(entry->memory, entry->pages);
	289	kfree(entry);
	290	}
	291	INIT_LIST_HEAD(&dev->agp->memory);
	292
	293	if (dev->agp->acquired)
	294	drm_agp_release(dev);
	295
	296	dev->agp->acquired = 0;
	297	dev->agp->enabled = 0;
	298	}
	299
	300	if (dev_priv->fb_mtrr) {
01d73a69 JC	301	drm_mtrr_del(dev_priv->fb_mtrr,
	302	pci_resource_start(dev->pdev, 1),
	303	pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
6ee73861 BS	304	dev_priv->fb_mtrr = 0;
	305	}
	306	}
	307
6ee73861	308	static uint32_t
a76fb4e8 BS	309	nouveau_mem_detect_nv04(struct drm_device *dev)
	310	{
	311	uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0);
	312
	313	if (boot0 & 0x00000100)
	314	return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
	315
	316	switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) {
	317	case NV04_BOOT_0_RAM_AMOUNT_32MB:
	318	return 32 * 1024 * 1024;
	319	case NV04_BOOT_0_RAM_AMOUNT_16MB:
	320	return 16 * 1024 * 1024;
	321	case NV04_BOOT_0_RAM_AMOUNT_8MB:
	322	return 8 * 1024 * 1024;
	323	case NV04_BOOT_0_RAM_AMOUNT_4MB:
	324	return 4 * 1024 * 1024;
	325	}
	326
	327	return 0;
	328	}
	329
	330	static uint32_t
	331	nouveau_mem_detect_nforce(struct drm_device *dev)
6ee73861 BS	332	{
	333	struct drm_nouveau_private *dev_priv = dev->dev_private;
	334	struct pci_dev *bridge;
	335	uint32_t mem;
	336
	337	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	338	if (!bridge) {
	339	NV_ERROR(dev, "no bridge device\n");
	340	return 0;
	341	}
	342
a76fb4e8	343	if (dev_priv->flags & NV_NFORCE) {
6ee73861 BS	344	pci_read_config_dword(bridge, 0x7C, &mem);
	345	return (uint64_t)(((mem >> 6) & 31) + 1)10241024;
	346	} else
a76fb4e8	347	if (dev_priv->flags & NV_NFORCE2) {
6ee73861 BS	348	pci_read_config_dword(bridge, 0x84, &mem);
	349	return (uint64_t)(((mem >> 4) & 127) + 1)10241024;
	350	}
	351
	352	NV_ERROR(dev, "impossible!\n");
	353	return 0;
	354	}
	355
	356	/* returns the amount of FB ram in bytes */
a76fb4e8 BS	357	int
a76fb4e8 BS	358	nouveau_mem_detect(struct drm_device *dev)
6ee73861 BS	359	{
6ee73861 BS	360	struct drm_nouveau_private *dev_priv = dev->dev_private;
a76fb4e8 BS	361
	362	if (dev_priv->card_type == NV_04) {
	363	dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
	364	} else
	365	if (dev_priv->flags & (NV_NFORCE \| NV_NFORCE2)) {
	366	dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
	367	} else {
	368	dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA);
	369	dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK;
	370	if (dev_priv->chipset == 0xaa \|\| dev_priv->chipset == 0xac)
8b281db5 BS	371	dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
8b281db5 BS	372	dev_priv->vram_sys_base <<= 12;
6ee73861 BS	373	}
6ee73861 BS	374
a76fb4e8 BS	375	NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
	376	if (dev_priv->vram_sys_base) {
	377	NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
	378	dev_priv->vram_sys_base);
	379	}
	380
	381	if (dev_priv->vram_size)
	382	return 0;
	383	return -ENOMEM;
6ee73861 BS	384	}
6ee73861 BS	385
b694dfb2	386	#if __OS_HAS_AGP
6ee73861 BS	387	static void nouveau_mem_reset_agp(struct drm_device *dev)
	388	{
	389	uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable;
	390
	391	saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
	392	saved_pci_nv_19 = nv_rd32(dev, NV04_PBUS_PCI_NV_19);
	393
	394	/* clear busmaster bit */
	395	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
	396	/* clear SBA and AGP bits */
	397	nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff);
	398
	399	/* power cycle pgraph, if enabled */
	400	pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
	401	if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
	402	nv_wr32(dev, NV03_PMC_ENABLE,
	403	pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
	404	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \|
	405	NV_PMC_ENABLE_PGRAPH);
	406	}
	407
	408	/* and restore (gives effect of resetting AGP) */
	409	nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
	410	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
	411	}
b694dfb2	412	#endif
6ee73861 BS	413
	414	int
	415	nouveau_mem_init_agp(struct drm_device *dev)
	416	{
b694dfb2	417	#if __OS_HAS_AGP
6ee73861 BS	418	struct drm_nouveau_private *dev_priv = dev->dev_private;
	419	struct drm_agp_info info;
	420	struct drm_agp_mode mode;
	421	int ret;
	422
	423	if (nouveau_noagp)
	424	return 0;
	425
	426	nouveau_mem_reset_agp(dev);
	427
	428	if (!dev->agp->acquired) {
	429	ret = drm_agp_acquire(dev);
	430	if (ret) {
	431	NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
	432	return ret;
	433	}
	434	}
	435
	436	ret = drm_agp_info(dev, &info);
	437	if (ret) {
	438	NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
	439	return ret;
	440	}
	441
	442	/* see agp.h for the AGPSTAT_* modes available */
	443	mode.mode = info.mode;
	444	ret = drm_agp_enable(dev, mode);
	445	if (ret) {
	446	NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
	447	return ret;
	448	}
	449
	450	dev_priv->gart_info.type = NOUVEAU_GART_AGP;
	451	dev_priv->gart_info.aper_base = info.aperture_base;
	452	dev_priv->gart_info.aper_size = info.aperture_size;
b694dfb2	453	#endif
6ee73861 BS	454	return 0;
	455	}
	456
	457	int
	458	nouveau_mem_init(struct drm_device *dev)
	459	{
	460	struct drm_nouveau_private *dev_priv = dev->dev_private;
	461	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	462	int ret, dma_bits = 32;
	463
01d73a69	464	dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
6ee73861 BS	465	dev_priv->gart_info.type = NOUVEAU_GART_NONE;
	466
	467	if (dev_priv->card_type >= NV_50 &&
	468	pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
	469	dma_bits = 40;
	470
	471	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
	472	if (ret) {
	473	NV_ERROR(dev, "Error setting DMA mask: %d\n", ret);
	474	return ret;
	475	}
	476
	477	ret = nouveau_ttm_global_init(dev_priv);
	478	if (ret)
	479	return ret;
	480
	481	ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
	482	dev_priv->ttm.bo_global_ref.ref.object,
	483	&nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
	484	dma_bits <= 32 ? true : false);
	485	if (ret) {
	486	NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
	487	return ret;
	488	}
	489
	490	INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
	491	spin_lock_init(&dev_priv->ttm.bo_list_lock);
a0af9add	492	spin_lock_init(&dev_priv->tile.lock);
6ee73861	493
a76fb4e8	494	dev_priv->fb_available_size = dev_priv->vram_size;
6ee73861	495	dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
01d73a69 JC	496	if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
	497	dev_priv->fb_mappable_pages =
	498	pci_resource_len(dev->pdev, 1);
6ee73861 BS	499	dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
6ee73861 BS	500
6ee73861 BS	501	/* remove reserved space at end of vram from available amount */
	502	dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
	503	dev_priv->fb_aper_free = dev_priv->fb_available_size;
	504
	505	/* mappable vram */
	506	ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
	507	dev_priv->fb_available_size >> PAGE_SHIFT);
	508	if (ret) {
	509	NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
	510	return ret;
	511	}
	512
ac8fb975 BS	513	ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
	514	0, 0, true, true, &dev_priv->vga_ram);
	515	if (ret == 0)
	516	ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
	517	if (ret) {
	518	NV_WARN(dev, "failed to reserve VGA memory\n");
	519	nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	520	}
	521
6ee73861 BS	522	/* GART */
	523	#if !defined(__powerpc__) && !defined(__ia64__)
	524	if (drm_device_is_agp(dev) && dev->agp) {
	525	ret = nouveau_mem_init_agp(dev);
	526	if (ret)
	527	NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
	528	}
	529	#endif
	530
	531	if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
	532	ret = nouveau_sgdma_init(dev);
	533	if (ret) {
	534	NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
	535	return ret;
	536	}
	537	}
	538
	539	NV_INFO(dev, "%d MiB GART (aperture)\n",
	540	(int)(dev_priv->gart_info.aper_size >> 20));
	541	dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
	542
	543	ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
	544	dev_priv->gart_info.aper_size >> PAGE_SHIFT);
	545	if (ret) {
	546	NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
	547	return ret;
	548	}
	549
01d73a69 JC	550	dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
01d73a69 JC	551	pci_resource_len(dev->pdev, 1),
6ee73861	552	DRM_MTRR_WC);
ac8fb975	553
6ee73861 BS	554	return 0;
	555	}
	556
	557