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drm/nouveau: reserve VGA area for the moment
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
37#define DRIVER_PATCHLEVEL 15
38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
79 struct ttm_bo_kmap_obj kmap;
80 struct list_head head;
81
82 /* protected by ttm_bo_reserve() */
83 struct drm_file *reserved_by;
84 struct list_head entry;
85 int pbbo_index;
86
87 struct nouveau_channel *channel;
88
89 bool mappable;
90 bool no_vm;
91
92 uint32_t tile_mode;
93 uint32_t tile_flags;
a0af9add 94 struct nouveau_tile_reg *tile;
6ee73861
BS		 95
96 struct drm_gem_object *gem;
97 struct drm_file *cpu_filp;
98 int pin_refcnt;
99};
100
101static inline struct nouveau_bo *
102nouveau_bo(struct ttm_buffer_object *bo)
103{
104 return container_of(bo, struct nouveau_bo, bo);
105}
106
107static inline struct nouveau_bo *
108nouveau_gem_object(struct drm_gem_object *gem)
109{
110 return gem ? gem->driver_private : NULL;
111}
112
113/* TODO: submit equivalent to TTM generic API upstream? */
114static inline void __iomem *
115nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
116{
117 bool is_iomem;
118 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
119 &nvbo->kmap, &is_iomem);
120 WARN_ON_ONCE(ioptr && !is_iomem);
121 return ioptr;
122}
123
124struct mem_block {
125 struct mem_block *next;
126 struct mem_block *prev;
127 uint64_t start;
128 uint64_t size;
129 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
130};
131
132enum nouveau_flags {
133 NV_NFORCE = 0x10000000,
134 NV_NFORCE2 = 0x20000000
135};
136
137#define NVOBJ_ENGINE_SW 0
138#define NVOBJ_ENGINE_GR 1
139#define NVOBJ_ENGINE_DISPLAY 2
140#define NVOBJ_ENGINE_INT 0xdeadbeef
141
142#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
143#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
144#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
145#define NVOBJ_FLAG_FAKE (1 << 3)
146struct nouveau_gpuobj {
147 struct list_head list;
148
149 struct nouveau_channel *im_channel;
150 struct mem_block *im_pramin;
151 struct nouveau_bo *im_backing;
152 uint32_t im_backing_start;
153 uint32_t *im_backing_suspend;
154 int im_bound;
155
156 uint32_t flags;
157 int refcount;
158
159 uint32_t engine;
160 uint32_t class;
161
162 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
163 void *priv;
164};
165
166struct nouveau_gpuobj_ref {
167 struct list_head list;
168
169 struct nouveau_gpuobj *gpuobj;
170 uint32_t instance;
171
172 struct nouveau_channel *channel;
173 int handle;
174};
175
176struct nouveau_channel {
177 struct drm_device *dev;
178 int id;
179
180 /* owner of this fifo */
181 struct drm_file *file_priv;
182 /* mapping of the fifo itself */
183 struct drm_local_map *map;
184
185 /* mapping of the regs controling the fifo */
186 void __iomem *user;
187 uint32_t user_get;
188 uint32_t user_put;
189
190 /* Fencing */
191 struct {
192 /* lock protects the pending list only */
193 spinlock_t lock;
194 struct list_head pending;
195 uint32_t sequence;
196 uint32_t sequence_ack;
197 uint32_t last_sequence_irq;
198 } fence;
199
200 /* DMA push buffer */
201 struct nouveau_gpuobj_ref *pushbuf;
202 struct nouveau_bo *pushbuf_bo;
203 uint32_t pushbuf_base;
204
205 /* Notifier memory */
206 struct nouveau_bo *notifier_bo;
207 struct mem_block *notifier_heap;
208
209 /* PFIFO context */
210 struct nouveau_gpuobj_ref *ramfc;
211 struct nouveau_gpuobj_ref *cache;
212
213 /* PGRAPH context */
214 /* XXX may be merge 2 pointers as private data ??? */
215 struct nouveau_gpuobj_ref *ramin_grctx;
216 void *pgraph_ctx;
217
218 /* NV50 VM */
219 struct nouveau_gpuobj *vm_pd;
220 struct nouveau_gpuobj_ref *vm_gart_pt;
221 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
222
223 /* Objects */
224 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
225 struct mem_block *ramin_heap; /* Private PRAMIN heap */
226 struct nouveau_gpuobj_ref *ramht; /* Hash table */
227 struct list_head ramht_refs; /* Objects referenced by RAMHT */
228
229 /* GPU object info for stuff used in-kernel (mm_enabled) */
230 uint32_t m2mf_ntfy;
231 uint32_t vram_handle;
232 uint32_t gart_handle;
233 bool accel_done;
234
235 /* Push buffer state (only for drm's channel on !mm_enabled) */
236 struct {
237 int max;
238 int free;
239 int cur;
240 int put;
241 /* access via pushbuf_bo */
242 } dma;
243
244 uint32_t sw_subchannel[8];
245
246 struct {
247 struct nouveau_gpuobj *vblsem;
248 uint32_t vblsem_offset;
249 uint32_t vblsem_rval;
250 struct list_head vbl_wait;
251 } nvsw;
252
253 struct {
254 bool active;
255 char name[32];
256 struct drm_info_list info;
257 } debugfs;
258};
259
260struct nouveau_instmem_engine {
261 void *priv;
262
263 int (*init)(struct drm_device *dev);
264 void (*takedown)(struct drm_device *dev);
265 int (*suspend)(struct drm_device *dev);
266 void (*resume)(struct drm_device *dev);
267
268 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
269 uint32_t *size);
270 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
272 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
273 void (*prepare_access)(struct drm_device *, bool write);
274 void (*finish_access)(struct drm_device *);
275};
276
277struct nouveau_mc_engine {
278 int (*init)(struct drm_device *dev);
279 void (*takedown)(struct drm_device *dev);
280};
281
282struct nouveau_timer_engine {
283 int (*init)(struct drm_device *dev);
284 void (*takedown)(struct drm_device *dev);
285 uint64_t (*read)(struct drm_device *dev);
286};
287
288struct nouveau_fb_engine {
cb00f7c1
FJ		 289 int num_tiles;
290
6ee73861
BS		 291 int (*init)(struct drm_device *dev);
292 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 293
294 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
295 uint32_t size, uint32_t pitch);
6ee73861
BS		 296};
297
298struct nouveau_fifo_engine {
299 void *priv;
300
301 int channels;
302
303 int (*init)(struct drm_device *);
304 void (*takedown)(struct drm_device *);
305
306 void (*disable)(struct drm_device *);
307 void (*enable)(struct drm_device *);
308 bool (*reassign)(struct drm_device *, bool enable);
588d7d12
FJ		 309 bool (*cache_flush)(struct drm_device *dev);
310 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 311
312 int (*channel_id)(struct drm_device *);
313
314 int (*create_context)(struct nouveau_channel *);
315 void (*destroy_context)(struct nouveau_channel *);
316 int (*load_context)(struct nouveau_channel *);
317 int (*unload_context)(struct drm_device *);
318};
319
320struct nouveau_pgraph_object_method {
321 int id;
322 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
323 uint32_t data);
324};
325
326struct nouveau_pgraph_object_class {
327 int id;
328 bool software;
329 struct nouveau_pgraph_object_method *methods;
330};
331
332struct nouveau_pgraph_engine {
333 struct nouveau_pgraph_object_class *grclass;
334 bool accel_blocked;
335 void *ctxprog;
336 void *ctxvals;
054b93e4 337 int grctx_size;
6ee73861
BS		 338
339 int (*init)(struct drm_device *);
340 void (*takedown)(struct drm_device *);
341
342 void (*fifo_access)(struct drm_device *, bool);
343
344 struct nouveau_channel *(*channel)(struct drm_device *);
345 int (*create_context)(struct nouveau_channel *);
346 void (*destroy_context)(struct nouveau_channel *);
347 int (*load_context)(struct nouveau_channel *);
348 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 349
350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
351 uint32_t size, uint32_t pitch);
6ee73861
BS		 352};
353
354struct nouveau_engine {
355 struct nouveau_instmem_engine instmem;
356 struct nouveau_mc_engine mc;
357 struct nouveau_timer_engine timer;
358 struct nouveau_fb_engine fb;
359 struct nouveau_pgraph_engine graph;
360 struct nouveau_fifo_engine fifo;
361};
362
363struct nouveau_pll_vals {
364 union {
365 struct {
366#ifdef __BIG_ENDIAN
367 uint8_t N1, M1, N2, M2;
368#else
369 uint8_t M1, N1, M2, N2;
370#endif
371 };
372 struct {
373 uint16_t NM1, NM2;
374 } __attribute__((packed));
375 };
376 int log2P;
377
378 int refclk;
379};
380
381enum nv04_fp_display_regs {
382 FP_DISPLAY_END,
383 FP_TOTAL,
384 FP_CRTC,
385 FP_SYNC_START,
386 FP_SYNC_END,
387 FP_VALID_START,
388 FP_VALID_END
389};
390
391struct nv04_crtc_reg {
392 unsigned char MiscOutReg; /* */
393 uint8_t CRTC[0x9f];
394 uint8_t CR58[0x10];
395 uint8_t Sequencer[5];
396 uint8_t Graphics[9];
397 uint8_t Attribute[21];
398 unsigned char DAC[768]; /* Internal Colorlookuptable */
399
400 /* PCRTC regs */
401 uint32_t fb_start;
402 uint32_t crtc_cfg;
403 uint32_t cursor_cfg;
404 uint32_t gpio_ext;
405 uint32_t crtc_830;
406 uint32_t crtc_834;
407 uint32_t crtc_850;
408 uint32_t crtc_eng_ctrl;
409
410 /* PRAMDAC regs */
411 uint32_t nv10_cursync;
412 struct nouveau_pll_vals pllvals;
413 uint32_t ramdac_gen_ctrl;
414 uint32_t ramdac_630;
415 uint32_t ramdac_634;
416 uint32_t tv_setup;
417 uint32_t tv_vtotal;
418 uint32_t tv_vskew;
419 uint32_t tv_vsync_delay;
420 uint32_t tv_htotal;
421 uint32_t tv_hskew;
422 uint32_t tv_hsync_delay;
423 uint32_t tv_hsync_delay2;
424 uint32_t fp_horiz_regs[7];
425 uint32_t fp_vert_regs[7];
426 uint32_t dither;
427 uint32_t fp_control;
428 uint32_t dither_regs[6];
429 uint32_t fp_debug_0;
430 uint32_t fp_debug_1;
431 uint32_t fp_debug_2;
432 uint32_t fp_margin_color;
433 uint32_t ramdac_8c0;
434 uint32_t ramdac_a20;
435 uint32_t ramdac_a24;
436 uint32_t ramdac_a34;
437 uint32_t ctv_regs[38];
438};
439
440struct nv04_output_reg {
441 uint32_t output;
442 int head;
443};
444
445struct nv04_mode_state {
446 uint32_t bpp;
447 uint32_t width;
448 uint32_t height;
449 uint32_t interlace;
450 uint32_t repaint0;
451 uint32_t repaint1;
452 uint32_t screen;
453 uint32_t scale;
454 uint32_t dither;
455 uint32_t extra;
456 uint32_t fifo;
457 uint32_t pixel;
458 uint32_t horiz;
459 int arbitration0;
460 int arbitration1;
461 uint32_t pll;
462 uint32_t pllB;
463 uint32_t vpll;
464 uint32_t vpll2;
465 uint32_t vpllB;
466 uint32_t vpll2B;
467 uint32_t pllsel;
468 uint32_t sel_clk;
469 uint32_t general;
470 uint32_t crtcOwner;
471 uint32_t head;
472 uint32_t head2;
473 uint32_t cursorConfig;
474 uint32_t cursor0;
475 uint32_t cursor1;
476 uint32_t cursor2;
477 uint32_t timingH;
478 uint32_t timingV;
479 uint32_t displayV;
480 uint32_t crtcSync;
481
482 struct nv04_crtc_reg crtc_reg[2];
483};
484
485enum nouveau_card_type {
486 NV_04 = 0x00,
487 NV_10 = 0x10,
488 NV_20 = 0x20,
489 NV_30 = 0x30,
490 NV_40 = 0x40,
491 NV_50 = 0x50,
492};
493
494struct drm_nouveau_private {
495 struct drm_device *dev;
496 enum {
497 NOUVEAU_CARD_INIT_DOWN,
498 NOUVEAU_CARD_INIT_DONE,
499 NOUVEAU_CARD_INIT_FAILED
500 } init_state;
501
502 /* the card type, takes NV_* as values */
503 enum nouveau_card_type card_type;
504 /* exact chipset, derived from NV_PMC_BOOT_0 */
505 int chipset;
506 int flags;
507
508 void __iomem *mmio;
509 void __iomem *ramin;
510 uint32_t ramin_size;
511
ac8fb975
BS		 512 struct nouveau_bo *vga_ram;
513
6ee73861
BS		 514 struct workqueue_struct *wq;
515 struct work_struct irq_work;
516
517 struct list_head vbl_waiting;
518
519 struct {
520 struct ttm_global_reference mem_global_ref;
521 struct ttm_bo_global_ref bo_global_ref;
522 struct ttm_bo_device bdev;
523 spinlock_t bo_list_lock;
524 struct list_head bo_list;
525 atomic_t validate_sequence;
526 } ttm;
527
528 struct fb_info *fbdev_info;
529
530 int fifo_alloc_count;
531 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
532
533 struct nouveau_engine engine;
534 struct nouveau_channel *channel;
535
536 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
537 struct nouveau_gpuobj *ramht;
538 uint32_t ramin_rsvd_vram;
539 uint32_t ramht_offset;
540 uint32_t ramht_size;
541 uint32_t ramht_bits;
542 uint32_t ramfc_offset;
543 uint32_t ramfc_size;
544 uint32_t ramro_offset;
545 uint32_t ramro_size;
546
547 /* base physical adresses */
548 uint64_t fb_phys;
549 uint64_t fb_available_size;
550 uint64_t fb_mappable_pages;
551 uint64_t fb_aper_free;
552
553 struct {
554 enum {
555 NOUVEAU_GART_NONE = 0,
556 NOUVEAU_GART_AGP,
557 NOUVEAU_GART_SGDMA
558 } type;
559 uint64_t aper_base;
560 uint64_t aper_size;
561 uint64_t aper_free;
562
563 struct nouveau_gpuobj *sg_ctxdma;
564 struct page *sg_dummy_page;
565 dma_addr_t sg_dummy_bus;
566
567 /* nottm hack */
568 struct drm_ttm_backend *sg_be;
569 unsigned long sg_handle;
570 } gart_info;
571
a0af9add
FJ		 572 /* nv10-nv40 tiling regions */
573 struct {
574 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
575 spinlock_t lock;
576 } tile;
577
6ee73861
BS		 578 /* G8x/G9x virtual address space */
579 uint64_t vm_gart_base;
580 uint64_t vm_gart_size;
581 uint64_t vm_vram_base;
582 uint64_t vm_vram_size;
583 uint64_t vm_end;
584 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
585 int vm_vram_pt_nr;
586
587 /* the mtrr covering the FB */
588 int fb_mtrr;
589
590 struct mem_block *ramin_heap;
591
592 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
593 uint32_t ctx_table_size;
594 struct nouveau_gpuobj_ref *ctx_table;
595
596 struct list_head gpuobj_list;
597
598 struct nvbios VBIOS;
599 struct nouveau_bios_info *vbios;
600
601 struct nv04_mode_state mode_reg;
602 struct nv04_mode_state saved_reg;
603 uint32_t saved_vga_font[4][16384];
604 uint32_t crtc_owner;
605 uint32_t dac_users[4];
606
607 struct nouveau_suspend_resume {
608 uint32_t fifo_mode;
609 uint32_t graph_ctx_control;
610 uint32_t graph_state;
611 uint32_t *ramin_copy;
612 uint64_t ramin_size;
613 } susres;
614
615 struct backlight_device *backlight;
616 bool acpi_dsm;
617
618 struct nouveau_channel *evo;
619
620 struct {
621 struct dentry *channel_root;
622 } debugfs;
623};
624
625static inline struct drm_nouveau_private *
626nouveau_bdev(struct ttm_bo_device *bd)
627{
628 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
629}
630
631static inline int
632nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
633{
634 struct nouveau_bo *prev;
635
636 if (!pnvbo)
637 return -EINVAL;
638 prev = *pnvbo;
639
640 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
641 if (prev) {
642 struct ttm_buffer_object *bo = &prev->bo;
643
644 ttm_bo_unref(&bo);
645 }
646
647 return 0;
648}
649
650#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
651 struct drm_nouveau_private *nv = dev->dev_private; \
652 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
653 NV_ERROR(dev, "called without init\n"); \
654 return -EINVAL; \
655 } \
656} while (0)
657
658#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
659 struct drm_nouveau_private *nv = dev->dev_private; \
660 if (!nouveau_channel_owner(dev, (cl), (id))) { \
661 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
662 DRM_CURRENTPID, (id)); \
663 return -EPERM; \
664 } \
665 (ch) = nv->fifos[(id)]; \
666} while (0)
667
668/* nouveau_drv.c */
669extern int nouveau_noagp;
670extern int nouveau_duallink;
671extern int nouveau_uscript_lvds;
672extern int nouveau_uscript_tmds;
673extern int nouveau_vram_pushbuf;
674extern int nouveau_vram_notify;
675extern int nouveau_fbpercrtc;
676extern char *nouveau_tv_norm;
677extern int nouveau_reg_debug;
678extern char *nouveau_vbios;
054b93e4 679extern int nouveau_ctxfw;
6ee73861
BS		 680
681/* nouveau_state.c */
682extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
683extern int nouveau_load(struct drm_device *, unsigned long flags);
684extern int nouveau_firstopen(struct drm_device *);
685extern void nouveau_lastclose(struct drm_device *);
686extern int nouveau_unload(struct drm_device *);
687extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
688 struct drm_file *);
689extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
690 struct drm_file *);
691extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
692 uint32_t reg, uint32_t mask, uint32_t val);
693extern bool nouveau_wait_for_idle(struct drm_device *);
694extern int nouveau_card_init(struct drm_device *);
695extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
696 struct drm_file *);
697extern int nouveau_ioctl_suspend(struct drm_device *, void *data,
698 struct drm_file *);
699extern int nouveau_ioctl_resume(struct drm_device *, void *data,
700 struct drm_file *);
701
702/* nouveau_mem.c */
703extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
704 uint64_t size);
705extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
706 uint64_t size, int align2,
707 struct drm_file *, int tail);
708extern void nouveau_mem_takedown(struct mem_block **heap);
709extern void nouveau_mem_free_block(struct mem_block *);
710extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
711extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
712extern int nouveau_mem_init(struct drm_device *);
713extern int nouveau_mem_init_agp(struct drm_device *);
714extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 715extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
716 uint32_t addr,
717 uint32_t size,
718 uint32_t pitch);
719extern void nv10_mem_expire_tiling(struct drm_device *dev,
720 struct nouveau_tile_reg *tile,
721 struct nouveau_fence *fence);
6ee73861
BS		 722extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
723 uint32_t size, uint32_t flags,
724 uint64_t phys);
725extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
726 uint32_t size);
727
728/* nouveau_notifier.c */
729extern int nouveau_notifier_init_channel(struct nouveau_channel *);
730extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
731extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
732 int cout, uint32_t *offset);
733extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
734extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
735 struct drm_file *);
736extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
737 struct drm_file *);
738
739/* nouveau_channel.c */
740extern struct drm_ioctl_desc nouveau_ioctls[];
741extern int nouveau_max_ioctl;
742extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
743extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
744 int channel);
745extern int nouveau_channel_alloc(struct drm_device *dev,
746 struct nouveau_channel **chan,
747 struct drm_file *file_priv,
748 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
749extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 750
751/* nouveau_object.c */
752extern int nouveau_gpuobj_early_init(struct drm_device *);
753extern int nouveau_gpuobj_init(struct drm_device *);
754extern void nouveau_gpuobj_takedown(struct drm_device *);
755extern void nouveau_gpuobj_late_takedown(struct drm_device *);
756extern int nouveau_gpuobj_suspend(struct drm_device *dev);
757extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
758extern void nouveau_gpuobj_resume(struct drm_device *dev);
759extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
760 uint32_t vram_h, uint32_t tt_h);
761extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
762extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
763 uint32_t size, int align, uint32_t flags,
764 struct nouveau_gpuobj **);
765extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
766extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
767 uint32_t handle, struct nouveau_gpuobj *,
768 struct nouveau_gpuobj_ref **);
769extern int nouveau_gpuobj_ref_del(struct drm_device *,
770 struct nouveau_gpuobj_ref **);
771extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
772 struct nouveau_gpuobj_ref **ref_ret);
773extern int nouveau_gpuobj_new_ref(struct drm_device *,
774 struct nouveau_channel *alloc_chan,
775 struct nouveau_channel *ref_chan,
776 uint32_t handle, uint32_t size, int align,
777 uint32_t flags, struct nouveau_gpuobj_ref **);
778extern int nouveau_gpuobj_new_fake(struct drm_device *,
779 uint32_t p_offset, uint32_t b_offset,
780 uint32_t size, uint32_t flags,
781 struct nouveau_gpuobj **,
782 struct nouveau_gpuobj_ref**);
783extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
784 uint64_t offset, uint64_t size, int access,
785 int target, struct nouveau_gpuobj **);
786extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
787 uint64_t offset, uint64_t size,
788 int access, struct nouveau_gpuobj **,
789 uint32_t *o_ret);
790extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
791 struct nouveau_gpuobj **);
f03a314b
FJ		 792extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
793 struct nouveau_gpuobj **);
6ee73861
BS		 794extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
795 struct drm_file *);
796extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
797 struct drm_file *);
798
799/* nouveau_irq.c */
800extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
801extern void nouveau_irq_preinstall(struct drm_device *);
802extern int nouveau_irq_postinstall(struct drm_device *);
803extern void nouveau_irq_uninstall(struct drm_device *);
804
805/* nouveau_sgdma.c */
806extern int nouveau_sgdma_init(struct drm_device *);
807extern void nouveau_sgdma_takedown(struct drm_device *);
808extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
809 uint32_t *page);
810extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
811
812/* nouveau_debugfs.c */
813#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
814extern int nouveau_debugfs_init(struct drm_minor *);
815extern void nouveau_debugfs_takedown(struct drm_minor *);
816extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
817extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
818#else
819static inline int
820nouveau_debugfs_init(struct drm_minor *minor)
821{
822 return 0;
823}
824
825static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
826{
827}
828
829static inline int
830nouveau_debugfs_channel_init(struct nouveau_channel *chan)
831{
832 return 0;
833}
834
835static inline void
836nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
837{
838}
839#endif
840
841/* nouveau_dma.c */
75c99da6 842extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861
BS		 843extern int nouveau_dma_init(struct nouveau_channel *);
844extern int nouveau_dma_wait(struct nouveau_channel *, int size);
845
846/* nouveau_acpi.c */
847#ifdef CONFIG_ACPI
848extern int nouveau_hybrid_setup(struct drm_device *dev);
849extern bool nouveau_dsm_probe(struct drm_device *dev);
850#else
851static inline int nouveau_hybrid_setup(struct drm_device *dev)
852{
853 return 0;
854}
855static inline bool nouveau_dsm_probe(struct drm_device *dev)
856{
857 return false;
858}
859#endif
860
861/* nouveau_backlight.c */
862#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
863extern int nouveau_backlight_init(struct drm_device *);
864extern void nouveau_backlight_exit(struct drm_device *);
865#else
866static inline int nouveau_backlight_init(struct drm_device *dev)
867{
868 return 0;
869}
870
871static inline void nouveau_backlight_exit(struct drm_device *dev) { }
872#endif
873
874/* nouveau_bios.c */
875extern int nouveau_bios_init(struct drm_device *);
876extern void nouveau_bios_takedown(struct drm_device *dev);
877extern int nouveau_run_vbios_init(struct drm_device *);
878extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
879 struct dcb_entry *);
880extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
881 enum dcb_gpio_tag);
882extern struct dcb_connector_table_entry *
883nouveau_bios_connector_entry(struct drm_device *, int index);
884extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
885 struct pll_lims *);
886extern int nouveau_bios_run_display_table(struct drm_device *,
887 struct dcb_entry *,
888 uint32_t script, int pxclk);
889extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
890 int *length);
891extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
892extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
893extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
894 bool *dl, bool *if_is_24bit);
895extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
896 int head, int pxclk);
897extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
898 enum LVDS_script, int pxclk);
899
900/* nouveau_ttm.c */
901int nouveau_ttm_global_init(struct drm_nouveau_private *);
902void nouveau_ttm_global_release(struct drm_nouveau_private *);
903int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
904
905/* nouveau_dp.c */
906int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
907 uint8_t *data, int data_nr);
908bool nouveau_dp_detect(struct drm_encoder *);
909bool nouveau_dp_link_train(struct drm_encoder *);
910
911/* nv04_fb.c */
912extern int nv04_fb_init(struct drm_device *);
913extern void nv04_fb_takedown(struct drm_device *);
914
915/* nv10_fb.c */
916extern int nv10_fb_init(struct drm_device *);
917extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 918extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
919 uint32_t, uint32_t);
6ee73861
BS		 920
921/* nv40_fb.c */
922extern int nv40_fb_init(struct drm_device *);
923extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 924extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
925 uint32_t, uint32_t);
6ee73861
BS		 926
927/* nv04_fifo.c */
928extern int nv04_fifo_init(struct drm_device *);
929extern void nv04_fifo_disable(struct drm_device *);
930extern void nv04_fifo_enable(struct drm_device *);
931extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12
FJ		 932extern bool nv04_fifo_cache_flush(struct drm_device *);
933extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 934extern int nv04_fifo_channel_id(struct drm_device *);
935extern int nv04_fifo_create_context(struct nouveau_channel *);
936extern void nv04_fifo_destroy_context(struct nouveau_channel *);
937extern int nv04_fifo_load_context(struct nouveau_channel *);
938extern int nv04_fifo_unload_context(struct drm_device *);
939
940/* nv10_fifo.c */
941extern int nv10_fifo_init(struct drm_device *);
942extern int nv10_fifo_channel_id(struct drm_device *);
943extern int nv10_fifo_create_context(struct nouveau_channel *);
944extern void nv10_fifo_destroy_context(struct nouveau_channel *);
945extern int nv10_fifo_load_context(struct nouveau_channel *);
946extern int nv10_fifo_unload_context(struct drm_device *);
947
948/* nv40_fifo.c */
949extern int nv40_fifo_init(struct drm_device *);
950extern int nv40_fifo_create_context(struct nouveau_channel *);
951extern void nv40_fifo_destroy_context(struct nouveau_channel *);
952extern int nv40_fifo_load_context(struct nouveau_channel *);
953extern int nv40_fifo_unload_context(struct drm_device *);
954
955/* nv50_fifo.c */
956extern int nv50_fifo_init(struct drm_device *);
957extern void nv50_fifo_takedown(struct drm_device *);
958extern int nv50_fifo_channel_id(struct drm_device *);
959extern int nv50_fifo_create_context(struct nouveau_channel *);
960extern void nv50_fifo_destroy_context(struct nouveau_channel *);
961extern int nv50_fifo_load_context(struct nouveau_channel *);
962extern int nv50_fifo_unload_context(struct drm_device *);
963
964/* nv04_graph.c */
965extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
966extern int nv04_graph_init(struct drm_device *);
967extern void nv04_graph_takedown(struct drm_device *);
968extern void nv04_graph_fifo_access(struct drm_device *, bool);
969extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
970extern int nv04_graph_create_context(struct nouveau_channel *);
971extern void nv04_graph_destroy_context(struct nouveau_channel *);
972extern int nv04_graph_load_context(struct nouveau_channel *);
973extern int nv04_graph_unload_context(struct drm_device *);
974extern void nv04_graph_context_switch(struct drm_device *);
975
976/* nv10_graph.c */
977extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
978extern int nv10_graph_init(struct drm_device *);
979extern void nv10_graph_takedown(struct drm_device *);
980extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
981extern int nv10_graph_create_context(struct nouveau_channel *);
982extern void nv10_graph_destroy_context(struct nouveau_channel *);
983extern int nv10_graph_load_context(struct nouveau_channel *);
984extern int nv10_graph_unload_context(struct drm_device *);
985extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 986extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
987 uint32_t, uint32_t);
6ee73861
BS		 988
989/* nv20_graph.c */
990extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
991extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
992extern int nv20_graph_create_context(struct nouveau_channel *);
993extern void nv20_graph_destroy_context(struct nouveau_channel *);
994extern int nv20_graph_load_context(struct nouveau_channel *);
995extern int nv20_graph_unload_context(struct drm_device *);
996extern int nv20_graph_init(struct drm_device *);
997extern void nv20_graph_takedown(struct drm_device *);
998extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 999extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1000 uint32_t, uint32_t);
6ee73861
BS		 1001
1002/* nv40_graph.c */
1003extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1004extern int nv40_graph_init(struct drm_device *);
1005extern void nv40_graph_takedown(struct drm_device *);
1006extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1007extern int nv40_graph_create_context(struct nouveau_channel *);
1008extern void nv40_graph_destroy_context(struct nouveau_channel *);
1009extern int nv40_graph_load_context(struct nouveau_channel *);
1010extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1011extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1012extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1013 uint32_t, uint32_t);
6ee73861
BS		 1014
1015/* nv50_graph.c */
1016extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1017extern int nv50_graph_init(struct drm_device *);
1018extern void nv50_graph_takedown(struct drm_device *);
1019extern void nv50_graph_fifo_access(struct drm_device *, bool);
1020extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1021extern int nv50_graph_create_context(struct nouveau_channel *);
1022extern void nv50_graph_destroy_context(struct nouveau_channel *);
1023extern int nv50_graph_load_context(struct nouveau_channel *);
1024extern int nv50_graph_unload_context(struct drm_device *);
1025extern void nv50_graph_context_switch(struct drm_device *);
1026
054b93e4
BS		 1027/* nouveau_grctx.c */
1028extern int nouveau_grctx_prog_load(struct drm_device *);
1029extern void nouveau_grctx_vals_load(struct drm_device *,
1030 struct nouveau_gpuobj *);
1031extern void nouveau_grctx_fini(struct drm_device *);
1032
6ee73861
BS		 1033/* nv04_instmem.c */
1034extern int nv04_instmem_init(struct drm_device *);
1035extern void nv04_instmem_takedown(struct drm_device *);
1036extern int nv04_instmem_suspend(struct drm_device *);
1037extern void nv04_instmem_resume(struct drm_device *);
1038extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1039 uint32_t *size);
1040extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1041extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1042extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1043extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1044extern void nv04_instmem_finish_access(struct drm_device *);
1045
1046/* nv50_instmem.c */
1047extern int nv50_instmem_init(struct drm_device *);
1048extern void nv50_instmem_takedown(struct drm_device *);
1049extern int nv50_instmem_suspend(struct drm_device *);
1050extern void nv50_instmem_resume(struct drm_device *);
1051extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1052 uint32_t *size);
1053extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1054extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1055extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1056extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1057extern void nv50_instmem_finish_access(struct drm_device *);
1058
1059/* nv04_mc.c */
1060extern int nv04_mc_init(struct drm_device *);
1061extern void nv04_mc_takedown(struct drm_device *);
1062
1063/* nv40_mc.c */
1064extern int nv40_mc_init(struct drm_device *);
1065extern void nv40_mc_takedown(struct drm_device *);
1066
1067/* nv50_mc.c */
1068extern int nv50_mc_init(struct drm_device *);
1069extern void nv50_mc_takedown(struct drm_device *);
1070
1071/* nv04_timer.c */
1072extern int nv04_timer_init(struct drm_device *);
1073extern uint64_t nv04_timer_read(struct drm_device *);
1074extern void nv04_timer_takedown(struct drm_device *);
1075
1076extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1077 unsigned long arg);
1078
1079/* nv04_dac.c */
1080extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
11d6eb2a 1081extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1082extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1083extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1084
1085/* nv04_dfp.c */
1086extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1087extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1088extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1089 int head, bool dl);
1090extern void nv04_dfp_disable(struct drm_device *dev, int head);
1091extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1092
1093/* nv04_tv.c */
1094extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1095extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1096
1097/* nv17_tv.c */
1098extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
6ee73861
BS		 1099
1100/* nv04_display.c */
1101extern int nv04_display_create(struct drm_device *);
1102extern void nv04_display_destroy(struct drm_device *);
1103extern void nv04_display_restore(struct drm_device *);
1104
1105/* nv04_crtc.c */
1106extern int nv04_crtc_create(struct drm_device *, int index);
1107
1108/* nouveau_bo.c */
1109extern struct ttm_bo_driver nouveau_bo_driver;
1110extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1111 int size, int align, uint32_t flags,
1112 uint32_t tile_mode, uint32_t tile_flags,
1113 bool no_vm, bool mappable, struct nouveau_bo **);
1114extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1115extern int nouveau_bo_unpin(struct nouveau_bo *);
1116extern int nouveau_bo_map(struct nouveau_bo *);
1117extern void nouveau_bo_unmap(struct nouveau_bo *);
1118extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype);
1119extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1120extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1121extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1122extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1123
1124/* nouveau_fence.c */
1125struct nouveau_fence;
1126extern int nouveau_fence_init(struct nouveau_channel *);
1127extern void nouveau_fence_fini(struct nouveau_channel *);
1128extern void nouveau_fence_update(struct nouveau_channel *);
1129extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1130 bool emit);
1131extern int nouveau_fence_emit(struct nouveau_fence *);
1132struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1133extern bool nouveau_fence_signalled(void *obj, void *arg);
1134extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1135extern int nouveau_fence_flush(void *obj, void *arg);
1136extern void nouveau_fence_unref(void **obj);
1137extern void *nouveau_fence_ref(void *obj);
1138extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1139
1140/* nouveau_gem.c */
1141extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1142 int size, int align, uint32_t flags,
1143 uint32_t tile_mode, uint32_t tile_flags,
1144 bool no_vm, bool mappable, struct nouveau_bo **);
1145extern int nouveau_gem_object_new(struct drm_gem_object *);
1146extern void nouveau_gem_object_del(struct drm_gem_object *);
1147extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1148 struct drm_file *);
1149extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1150 struct drm_file *);
1151extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *,
1152 struct drm_file *);
1153extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *,
1154 struct drm_file *);
1155extern int nouveau_gem_ioctl_pin(struct drm_device *, void *,
1156 struct drm_file *);
1157extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *,
1158 struct drm_file *);
1159extern int nouveau_gem_ioctl_tile(struct drm_device *, void *,
1160 struct drm_file *);
1161extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1162 struct drm_file *);
1163extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1164 struct drm_file *);
1165extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1166 struct drm_file *);
1167
1168/* nv17_gpio.c */
1169int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1170int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1171
1172#ifndef ioread32_native
1173#ifdef __BIG_ENDIAN
1174#define ioread16_native ioread16be
1175#define iowrite16_native iowrite16be
1176#define ioread32_native ioread32be
1177#define iowrite32_native iowrite32be
1178#else /* def __BIG_ENDIAN */
1179#define ioread16_native ioread16
1180#define iowrite16_native iowrite16
1181#define ioread32_native ioread32
1182#define iowrite32_native iowrite32
1183#endif /* def __BIG_ENDIAN else */
1184#endif /* !ioread32_native */
1185
1186/* channel control reg access */
1187static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1188{
1189 return ioread32_native(chan->user + reg);
1190}
1191
1192static inline void nvchan_wr32(struct nouveau_channel *chan,
1193 unsigned reg, u32 val)
1194{
1195 iowrite32_native(val, chan->user + reg);
1196}
1197
1198/* register access */
1199static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1200{
1201 struct drm_nouveau_private *dev_priv = dev->dev_private;
1202 return ioread32_native(dev_priv->mmio + reg);
1203}
1204
1205static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1206{
1207 struct drm_nouveau_private *dev_priv = dev->dev_private;
1208 iowrite32_native(val, dev_priv->mmio + reg);
1209}
1210
1211static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1212{
1213 struct drm_nouveau_private *dev_priv = dev->dev_private;
1214 return ioread8(dev_priv->mmio + reg);
1215}
1216
1217static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1218{
1219 struct drm_nouveau_private *dev_priv = dev->dev_private;
1220 iowrite8(val, dev_priv->mmio + reg);
1221}
1222
1223#define nv_wait(reg, mask, val) \
1224 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1225
1226/* PRAMIN access */
1227static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1228{
1229 struct drm_nouveau_private *dev_priv = dev->dev_private;
1230 return ioread32_native(dev_priv->ramin + offset);
1231}
1232
1233static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1234{
1235 struct drm_nouveau_private *dev_priv = dev->dev_private;
1236 iowrite32_native(val, dev_priv->ramin + offset);
1237}
1238
1239/* object access */
1240static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1241 unsigned index)
1242{
1243 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1244}
1245
1246static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1247 unsigned index, u32 val)
1248{
1249 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1250}
1251
1252/*
1253 * Logging
1254 * Argument d is (struct drm_device *).
1255 */
1256#define NV_PRINTK(level, d, fmt, arg...) \
1257 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1258 pci_name(d->pdev), ##arg)
1259#ifndef NV_DEBUG_NOTRACE
1260#define NV_DEBUG(d, fmt, arg...) do { \
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MM		 1261 if (drm_debug & DRM_UT_DRIVER) { \
1262 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1263 __LINE__, ##arg); \
1264 } \
1265} while (0)
1266#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1267 if (drm_debug & DRM_UT_KMS) { \
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BS		 1268 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1269 __LINE__, ##arg); \
1270 } \
1271} while (0)
1272#else
1273#define NV_DEBUG(d, fmt, arg...) do { \
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MM		 1274 if (drm_debug & DRM_UT_DRIVER) \
1275 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1276} while (0)
1277#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1278 if (drm_debug & DRM_UT_KMS) \
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BS		 1279 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1280} while (0)
1281#endif
1282#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1283#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1284#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1285#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1286#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1287
1288/* nouveau_reg_debug bitmask */
1289enum {
1290 NOUVEAU_REG_DEBUG_MC = 0x1,
1291 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1292 NOUVEAU_REG_DEBUG_FB = 0x4,
1293 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1294 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1295 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1296 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1297 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1298 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1299 NOUVEAU_REG_DEBUG_EVO = 0x200,
1300};
1301
1302#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1303 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1304 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1305} while (0)
1306
1307static inline bool
1308nv_two_heads(struct drm_device *dev)
1309{
1310 struct drm_nouveau_private *dev_priv = dev->dev_private;
1311 const int impl = dev->pci_device & 0x0ff0;
1312
1313 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1314 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1315 return true;
1316
1317 return false;
1318}
1319
1320static inline bool
1321nv_gf4_disp_arch(struct drm_device *dev)
1322{
1323 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1324}
1325
1326static inline bool
1327nv_two_reg_pll(struct drm_device *dev)
1328{
1329 struct drm_nouveau_private *dev_priv = dev->dev_private;
1330 const int impl = dev->pci_device & 0x0ff0;
1331
1332 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1333 return true;
1334 return false;
1335}
1336
f03a314b
FJ		 1337#define NV_SW 0x0000506e
1338#define NV_SW_DMA_SEMAPHORE 0x00000060
1339#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1340#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1341#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1342#define NV_SW_DMA_VBLSEM 0x0000018c
1343#define NV_SW_VBLSEM_OFFSET 0x00000400
1344#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1345#define NV_SW_VBLSEM_RELEASE 0x00000408
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BS		 1346
1347#endif /* __NOUVEAU_DRV_H__ */
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