[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_dma.h

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __NOUVEAU_DMA_H__
#define __NOUVEAU_DMA_H__

#ifndef NOUVEAU_DMA_DEBUG
#define NOUVEAU_DMA_DEBUG 0
#endif

void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *,
		   int delta, int length);

/*
 * There's a hw race condition where you can't jump to your PUT offset,
 * to avoid this we jump to offset + SKIPS and fill the difference with
 * NOPs.
 *
 * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
 * a SKIPS value of 8.  Lets assume that the race condition is to do
 * with writing into the fetch area, we configure a fetch size of 128
 * bytes so we need a larger SKIPS value.
 */
#define NOUVEAU_DMA_SKIPS (128 / 4)

/* Hardcoded object assignments to subchannels (subchannel id). */
enum {
	NvSubM2MF	= 0,
	NvSubSw		= 1,
	NvSub2D		= 2,
	NvSubCtxSurf2D  = 2,
	NvSubGdiRect    = 3,
	NvSubImageBlit  = 4
};

/* Object handles. */
enum {
	NvM2MF		= 0x80000001,
	NvDmaFB		= 0x80000002,
	NvDmaTT		= 0x80000003,
	NvDmaVRAM	= 0x80000004,
	NvDmaGART	= 0x80000005,
	NvNotify0       = 0x80000006,
	Nv2D		= 0x80000007,
	NvCtxSurf2D	= 0x80000008,
	NvRop		= 0x80000009,
	NvImagePatt	= 0x8000000a,
	NvClipRect	= 0x8000000b,
	NvGdiRect	= 0x8000000c,
	NvImageBlit	= 0x8000000d,
	NvSw		= 0x8000000e,
	NvSema		= 0x8000000f,

	/* G80+ display objects */
	NvEvoVRAM	= 0x01000000,
	NvEvoFB16	= 0x01000001,
	NvEvoFB32	= 0x01000002
};

#define NV_MEMORY_TO_MEMORY_FORMAT                                    0x00000039
#define NV_MEMORY_TO_MEMORY_FORMAT_NAME                               0x00000000
#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF                            0x00000050
#define NV_MEMORY_TO_MEMORY_FORMAT_NOP                                0x00000100
#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY                             0x00000104
#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE                 0x00000000
#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN       0x00000001
#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY                         0x00000180
#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE                         0x00000184
#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN                          0x0000030c

#define NV50_MEMORY_TO_MEMORY_FORMAT                                  0x00005039
#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200                           0x00000200
#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C                           0x0000021c
#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH                   0x00000238
#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH                  0x0000023c

static __must_check inline int
RING_SPACE(struct nouveau_channel *chan, int size)
{
	int ret;

	ret = nouveau_dma_wait(chan, 1, size);
	if (ret)
		return ret;

	chan->dma.free -= size;
	return 0;
}

static inline void
OUT_RING(struct nouveau_channel *chan, int data)
{
	if (NOUVEAU_DMA_DEBUG) {
		NV_INFO(chan->dev, "Ch%d/0x%08x: 0x%08x\n",
			chan->id, chan->dma.cur << 2, data);
	}

	nouveau_bo_wr32(chan->pushbuf_bo, chan->dma.cur++, data);
}

extern void
OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords);

static inline void
BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size)
{
	OUT_RING(chan, (subc << 13) | (size << 18) | mthd);
}

#define WRITE_PUT(val) do {                                                    \
	DRM_MEMORYBARRIER();                                                   \
	nouveau_bo_rd32(chan->pushbuf_bo, 0);                                  \
	nvchan_wr32(chan, chan->user_put, ((val) << 2) + chan->pushbuf_base);  \
} while (0)

static inline void
FIRE_RING(struct nouveau_channel *chan)
{
	if (NOUVEAU_DMA_DEBUG) {
		NV_INFO(chan->dev, "Ch%d/0x%08x: PUSH!\n",
			chan->id, chan->dma.cur << 2);
	}

	if (chan->dma.cur == chan->dma.put)
		return;
	chan->accel_done = true;

	if (chan->dma.ib_max) {
		nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2,
			      (chan->dma.cur - chan->dma.put) << 2);
	} else {
		WRITE_PUT(chan->dma.cur);
	}

	chan->dma.put = chan->dma.cur;
}

static inline void
WIND_RING(struct nouveau_channel *chan)
{
	chan->dma.cur = chan->dma.put;
}

#endif
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
	27	#ifndef __NOUVEAU_DMA_H__
	28	#define __NOUVEAU_DMA_H__
	29
	30	#ifndef NOUVEAU_DMA_DEBUG
	31	#define NOUVEAU_DMA_DEBUG 0
	32	#endif
	33
9a391ad8	34	void nv50_dma_push(struct nouveau_channel , struct nouveau_bo ,
a1606a95	35	int delta, int length);
9a391ad8	36
6ee73861 BS	37	/*
	38	* There's a hw race condition where you can't jump to your PUT offset,
	39	* to avoid this we jump to offset + SKIPS and fill the difference with
	40	* NOPs.
	41	*
	42	* xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
	43	* a SKIPS value of 8. Lets assume that the race condition is to do
	44	* with writing into the fetch area, we configure a fetch size of 128
	45	* bytes so we need a larger SKIPS value.
	46	*/
	47	#define NOUVEAU_DMA_SKIPS (128 / 4)
	48
	49	/* Hardcoded object assignments to subchannels (subchannel id). */
	50	enum {
	51	NvSubM2MF = 0,
f03a314b FJ	52	NvSubSw = 1,
	53	NvSub2D = 2,
	54	NvSubCtxSurf2D = 2,
	55	NvSubGdiRect = 3,
	56	NvSubImageBlit = 4
6ee73861 BS	57	};
	58
	59	/* Object handles. */
	60	enum {
	61	NvM2MF = 0x80000001,
	62	NvDmaFB = 0x80000002,
	63	NvDmaTT = 0x80000003,
	64	NvDmaVRAM = 0x80000004,
	65	NvDmaGART = 0x80000005,
	66	NvNotify0 = 0x80000006,
	67	Nv2D = 0x80000007,
	68	NvCtxSurf2D = 0x80000008,
	69	NvRop = 0x80000009,
	70	NvImagePatt = 0x8000000a,
	71	NvClipRect = 0x8000000b,
	72	NvGdiRect = 0x8000000c,
	73	NvImageBlit = 0x8000000d,
f03a314b	74	NvSw = 0x8000000e,
0c6c1c2f	75	NvSema = 0x8000000f,
6ee73861 BS	76
	77	/* G80+ display objects */
	78	NvEvoVRAM = 0x01000000,
	79	NvEvoFB16 = 0x01000001,
	80	NvEvoFB32 = 0x01000002
	81	};
	82
	83	#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
	84	#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000
	85	#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050
	86	#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
	87	#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
	88	#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000
	89	#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001
	90	#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180
	91	#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184
	92	#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
	93
	94	#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
	95	#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200
	96	#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c
	97	#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
	98	#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
	99
	100	static __must_check inline int
	101	RING_SPACE(struct nouveau_channel *chan, int size)
	102	{
9a391ad8	103	int ret;
6ee73861	104
9a391ad8 BS	105	ret = nouveau_dma_wait(chan, 1, size);
	106	if (ret)
	107	return ret;
6ee73861 BS	108
	109	chan->dma.free -= size;
	110	return 0;
	111	}
	112
	113	static inline void
	114	OUT_RING(struct nouveau_channel *chan, int data)
	115	{
	116	if (NOUVEAU_DMA_DEBUG) {
	117	NV_INFO(chan->dev, "Ch%d/0x%08x: 0x%08x\n",
	118	chan->id, chan->dma.cur << 2, data);
	119	}
	120
	121	nouveau_bo_wr32(chan->pushbuf_bo, chan->dma.cur++, data);
	122	}
	123
	124	extern void
	125	OUT_RINGp(struct nouveau_channel chan, const void data, unsigned nr_dwords);
	126
	127	static inline void
	128	BEGIN_RING(struct nouveau_channel *chan, int subc, int mthd, int size)
	129	{
	130	OUT_RING(chan, (subc << 13) \| (size << 18) \| mthd);
	131	}
	132
	133	#define WRITE_PUT(val) do { \
	134	DRM_MEMORYBARRIER(); \
	135	nouveau_bo_rd32(chan->pushbuf_bo, 0); \
	136	nvchan_wr32(chan, chan->user_put, ((val) << 2) + chan->pushbuf_base); \
	137	} while (0)
	138
	139	static inline void
	140	FIRE_RING(struct nouveau_channel *chan)
	141	{
	142	if (NOUVEAU_DMA_DEBUG) {
	143	NV_INFO(chan->dev, "Ch%d/0x%08x: PUSH!\n",
	144	chan->id, chan->dma.cur << 2);
	145	}
	146
	147	if (chan->dma.cur == chan->dma.put)
	148	return;
	149	chan->accel_done = true;
	150
9a391ad8 BS	151	if (chan->dma.ib_max) {
9a391ad8 BS	152	nv50_dma_push(chan, chan->pushbuf_bo, chan->dma.put << 2,
a1606a95	153	(chan->dma.cur - chan->dma.put) << 2);
9a391ad8 BS	154	} else {
	155	WRITE_PUT(chan->dma.cur);
	156	}
	157
6ee73861 BS	158	chan->dma.put = chan->dma.cur;
	159	}
	160
	161	static inline void
	162	WIND_RING(struct nouveau_channel *chan)
	163	{
	164	chan->dma.cur = chan->dma.put;
	165	}
	166
	167	#endif