[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_dma.c

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_dma.h"

void
nouveau_dma_pre_init(struct nouveau_channel *chan)
{
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	struct nouveau_bo *pushbuf = chan->pushbuf_bo;

	if (dev_priv->card_type == NV_50) {
		const int ib_size = pushbuf->bo.mem.size / 2;

		chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
		chan->dma.ib_max = (ib_size / 8) - 1;
		chan->dma.ib_put = 0;
		chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;

		chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2;
	} else {
		chan->dma.max  = (pushbuf->bo.mem.size >> 2) - 2;
	}

	chan->dma.put  = 0;
	chan->dma.cur  = chan->dma.put;
	chan->dma.free = chan->dma.max - chan->dma.cur;
}

int
nouveau_dma_init(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *m2mf = NULL;
	struct nouveau_gpuobj *nvsw = NULL;
	int ret, i;

	/* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
	ret = nouveau_gpuobj_gr_new(chan, dev_priv->card_type < NV_50 ?
				    0x0039 : 0x5039, &m2mf);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_ref_add(dev, chan, NvM2MF, m2mf, NULL);
	if (ret)
		return ret;

	/* Create an NV_SW object for various sync purposes */
	ret = nouveau_gpuobj_sw_new(chan, NV_SW, &nvsw);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
	if (ret)
		return ret;

	/* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
	ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
	if (ret)
		return ret;

	/* Map push buffer */
	ret = nouveau_bo_map(chan->pushbuf_bo);
	if (ret)
		return ret;

	/* Map M2MF notifier object - fbcon. */
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		ret = nouveau_bo_map(chan->notifier_bo);
		if (ret)
			return ret;
	}

	/* Insert NOPS for NOUVEAU_DMA_SKIPS */
	ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
	if (ret)
		return ret;

	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
		OUT_RING(chan, 0);

	/* Initialise NV_MEMORY_TO_MEMORY_FORMAT */
	ret = RING_SPACE(chan, 4);
	if (ret)
		return ret;
	BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
	OUT_RING(chan, NvM2MF);
	BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
	OUT_RING(chan, NvNotify0);

	/* Initialise NV_SW */
	ret = RING_SPACE(chan, 2);
	if (ret)
		return ret;
	BEGIN_RING(chan, NvSubSw, 0, 1);
	OUT_RING(chan, NvSw);

	/* Sit back and pray the channel works.. */
	FIRE_RING(chan);

	return 0;
}

void
OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
{
	bool is_iomem;
	u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
	mem = &mem[chan->dma.cur];
	if (is_iomem)
		memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
	else
		memcpy(mem, data, nr_dwords * 4);
	chan->dma.cur += nr_dwords;
}

/* Fetch and adjust GPU GET pointer
 *
 * Returns:
 *  value >= 0, the adjusted GET pointer
 *  -EINVAL if GET pointer currently outside main push buffer
 *  -EBUSY if timeout exceeded
 */
static inline int
READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
{
	uint32_t val;

	val = nvchan_rd32(chan, chan->user_get);

	/* reset counter as long as GET is still advancing, this is
	 * to avoid misdetecting a GPU lockup if the GPU happens to
	 * just be processing an operation that takes a long time
	 */
	if (val != *prev_get) {
		*prev_get = val;
		*timeout = 0;
	}

	if ((++*timeout & 0xff) == 0) {
		DRM_UDELAY(1);
		if (*timeout > 100000)
			return -EBUSY;
	}

	if (val < chan->pushbuf_base ||
	    val > chan->pushbuf_base + (chan->dma.max << 2))
		return -EINVAL;

	return (val - chan->pushbuf_base) >> 2;
}

void
nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
	      int delta, int length)
{
	struct nouveau_bo *pb = chan->pushbuf_bo;
	uint64_t offset = bo->bo.offset + delta;
	int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;

	BUG_ON(chan->dma.ib_free < 1);
	nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
	nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);

	chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
	nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
	chan->dma.ib_free--;
}

static int
nv50_dma_push_wait(struct nouveau_channel *chan, int count)
{
	uint32_t cnt = 0, prev_get = 0;

	while (chan->dma.ib_free < count) {
		uint32_t get = nvchan_rd32(chan, 0x88);
		if (get != prev_get) {
			prev_get = get;
			cnt = 0;
		}

		if ((++cnt & 0xff) == 0) {
			DRM_UDELAY(1);
			if (cnt > 100000)
				return -EBUSY;
		}

		chan->dma.ib_free = get - chan->dma.ib_put;
		if (chan->dma.ib_free <= 0)
			chan->dma.ib_free += chan->dma.ib_max + 1;
	}

	return 0;
}

static int
nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
{
	uint32_t cnt = 0, prev_get = 0;
	int ret;

	ret = nv50_dma_push_wait(chan, slots + 1);
	if (unlikely(ret))
		return ret;

	while (chan->dma.free < count) {
		int get = READ_GET(chan, &prev_get, &cnt);
		if (unlikely(get < 0)) {
			if (get == -EINVAL)
				continue;

			return get;
		}

		if (get <= chan->dma.cur) {
			chan->dma.free = chan->dma.max - chan->dma.cur;
			if (chan->dma.free >= count)
				break;

			FIRE_RING(chan);
			do {
				get = READ_GET(chan, &prev_get, &cnt);
				if (unlikely(get < 0)) {
					if (get == -EINVAL)
						continue;
					return get;
				}
			} while (get == 0);
			chan->dma.cur = 0;
			chan->dma.put = 0;
		}

		chan->dma.free = get - chan->dma.cur - 1;
	}

	return 0;
}

int
nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
{
	uint32_t prev_get = 0, cnt = 0;
	int get;

	if (chan->dma.ib_max)
		return nv50_dma_wait(chan, slots, size);

	while (chan->dma.free < size) {
		get = READ_GET(chan, &prev_get, &cnt);
		if (unlikely(get == -EBUSY))
			return -EBUSY;

		/* loop until we have a usable GET pointer.  the value
		 * we read from the GPU may be outside the main ring if
		 * PFIFO is processing a buffer called from the main ring,
		 * discard these values until something sensible is seen.
		 *
		 * the other case we discard GET is while the GPU is fetching
		 * from the SKIPS area, so the code below doesn't have to deal
		 * with some fun corner cases.
		 */
		if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
			continue;

		if (get <= chan->dma.cur) {
			/* engine is fetching behind us, or is completely
			 * idle (GET == PUT) so we have free space up until
			 * the end of the push buffer
			 *
			 * we can only hit that path once per call due to
			 * looping back to the beginning of the push buffer,
			 * we'll hit the fetching-ahead-of-us path from that
			 * point on.
			 *
			 * the *one* exception to that rule is if we read
			 * GET==PUT, in which case the below conditional will
			 * always succeed and break us out of the wait loop.
			 */
			chan->dma.free = chan->dma.max - chan->dma.cur;
			if (chan->dma.free >= size)
				break;

			/* not enough space left at the end of the push buffer,
			 * instruct the GPU to jump back to the start right
			 * after processing the currently pending commands.
			 */
			OUT_RING(chan, chan->pushbuf_base | 0x20000000);

			/* wait for GET to depart from the skips area.
			 * prevents writing GET==PUT and causing a race
			 * condition that causes us to think the GPU is
			 * idle when it's not.
			 */
			do {
				get = READ_GET(chan, &prev_get, &cnt);
				if (unlikely(get == -EBUSY))
					return -EBUSY;
				if (unlikely(get == -EINVAL))
					continue;
			} while (get <= NOUVEAU_DMA_SKIPS);
			WRITE_PUT(NOUVEAU_DMA_SKIPS);

			/* we're now submitting commands at the start of
			 * the push buffer.
			 */
			chan->dma.cur  =
			chan->dma.put  = NOUVEAU_DMA_SKIPS;
		}

		/* engine fetching ahead of us, we have space up until the
		 * current GET pointer.  the "- 1" is to ensure there's
		 * space left to emit a jump back to the beginning of the
		 * push buffer if we require it.  we can never get GET == PUT
		 * here, so this is safe.
		 */
		chan->dma.free = get - chan->dma.cur - 1;
	}

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
	27	#include "drmP.h"
	28	#include "drm.h"
	29	#include "nouveau_drv.h"
	30	#include "nouveau_dma.h"
	31
75c99da6 BS	32	void
	33	nouveau_dma_pre_init(struct nouveau_channel *chan)
	34	{
9a391ad8 BS	35	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	36	struct nouveau_bo *pushbuf = chan->pushbuf_bo;
	37
	38	if (dev_priv->card_type == NV_50) {
	39	const int ib_size = pushbuf->bo.mem.size / 2;
	40
	41	chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
	42	chan->dma.ib_max = (ib_size / 8) - 1;
	43	chan->dma.ib_put = 0;
	44	chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
	45
	46	chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2;
	47	} else {
	48	chan->dma.max = (pushbuf->bo.mem.size >> 2) - 2;
	49	}
	50
75c99da6 BS	51	chan->dma.put = 0;
	52	chan->dma.cur = chan->dma.put;
	53	chan->dma.free = chan->dma.max - chan->dma.cur;
	54	}
	55
6ee73861 BS	56	int
	57	nouveau_dma_init(struct nouveau_channel *chan)
	58	{
	59	struct drm_device *dev = chan->dev;
	60	struct drm_nouveau_private *dev_priv = dev->dev_private;
	61	struct nouveau_gpuobj *m2mf = NULL;
f03a314b	62	struct nouveau_gpuobj *nvsw = NULL;
6ee73861 BS	63	int ret, i;
	64
	65	/* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
	66	ret = nouveau_gpuobj_gr_new(chan, dev_priv->card_type < NV_50 ?
	67	0x0039 : 0x5039, &m2mf);
	68	if (ret)
	69	return ret;
	70
	71	ret = nouveau_gpuobj_ref_add(dev, chan, NvM2MF, m2mf, NULL);
	72	if (ret)
	73	return ret;
	74
f03a314b FJ	75	/* Create an NV_SW object for various sync purposes */
	76	ret = nouveau_gpuobj_sw_new(chan, NV_SW, &nvsw);
	77	if (ret)
	78	return ret;
	79
	80	ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
	81	if (ret)
	82	return ret;
	83
6ee73861 BS	84	/* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
	85	ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
	86	if (ret)
	87	return ret;
	88
	89	/* Map push buffer */
	90	ret = nouveau_bo_map(chan->pushbuf_bo);
	91	if (ret)
	92	return ret;
	93
	94	/* Map M2MF notifier object - fbcon. */
	95	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
	96	ret = nouveau_bo_map(chan->notifier_bo);
	97	if (ret)
	98	return ret;
	99	}
	100
6ee73861 BS	101	/* Insert NOPS for NOUVEAU_DMA_SKIPS */
	102	ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
	103	if (ret)
	104	return ret;
	105
	106	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
	107	OUT_RING(chan, 0);
	108
	109	/* Initialise NV_MEMORY_TO_MEMORY_FORMAT */
	110	ret = RING_SPACE(chan, 4);
	111	if (ret)
	112	return ret;
	113	BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
	114	OUT_RING(chan, NvM2MF);
	115	BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
	116	OUT_RING(chan, NvNotify0);
	117
f03a314b FJ	118	/* Initialise NV_SW */
	119	ret = RING_SPACE(chan, 2);
	120	if (ret)
	121	return ret;
	122	BEGIN_RING(chan, NvSubSw, 0, 1);
	123	OUT_RING(chan, NvSw);
	124
6ee73861 BS	125	/* Sit back and pray the channel works.. */
	126	FIRE_RING(chan);
	127
	128	return 0;
	129	}
	130
	131	void
	132	OUT_RINGp(struct nouveau_channel chan, const void data, unsigned nr_dwords)
	133	{
	134	bool is_iomem;
	135	u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
	136	mem = &mem[chan->dma.cur];
	137	if (is_iomem)
	138	memcpy_toio((void __force __iomem )mem, data, nr_dwords 4);
	139	else
	140	memcpy(mem, data, nr_dwords * 4);
	141	chan->dma.cur += nr_dwords;
	142	}
	143
ba59953d BS	144	/* Fetch and adjust GPU GET pointer
	145	*
	146	* Returns:
	147	* value >= 0, the adjusted GET pointer
	148	* -EINVAL if GET pointer currently outside main push buffer
	149	* -EBUSY if timeout exceeded
	150	*/
	151	static inline int
	152	READ_GET(struct nouveau_channel chan, uint32_t prev_get, uint32_t *timeout)
6ee73861 BS	153	{
	154	uint32_t val;
	155
	156	val = nvchan_rd32(chan, chan->user_get);
ba59953d BS	157
	158	/* reset counter as long as GET is still advancing, this is
	159	* to avoid misdetecting a GPU lockup if the GPU happens to
	160	* just be processing an operation that takes a long time
	161	*/
	162	if (val != *prev_get) {
	163	*prev_get = val;
	164	*timeout = 0;
	165	}
	166
	167	if ((++*timeout & 0xff) == 0) {
	168	DRM_UDELAY(1);
	169	if (*timeout > 100000)
	170	return -EBUSY;
6ee73861 BS	171	}
6ee73861 BS	172
ba59953d BS	173	if (val < chan->pushbuf_base \|\|
	174	val > chan->pushbuf_base + (chan->dma.max << 2))
	175	return -EINVAL;
	176
	177	return (val - chan->pushbuf_base) >> 2;
6ee73861 BS	178	}
6ee73861 BS	179
9a391ad8 BS	180	void
9a391ad8 BS	181	nv50_dma_push(struct nouveau_channel chan, struct nouveau_bo bo,
a1606a95	182	int delta, int length)
9a391ad8 BS	183	{
9a391ad8 BS	184	struct nouveau_bo *pb = chan->pushbuf_bo;
d87897d4	185	uint64_t offset = bo->bo.offset + delta;
9a391ad8 BS	186	int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
	187
	188	BUG_ON(chan->dma.ib_free < 1);
d87897d4	189	nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
a1606a95	190	nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) \| length << 8);
9a391ad8 BS	191
	192	chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
	193	nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
	194	chan->dma.ib_free--;
	195	}
	196
	197	static int
	198	nv50_dma_push_wait(struct nouveau_channel *chan, int count)
	199	{
	200	uint32_t cnt = 0, prev_get = 0;
	201
	202	while (chan->dma.ib_free < count) {
	203	uint32_t get = nvchan_rd32(chan, 0x88);
	204	if (get != prev_get) {
	205	prev_get = get;
	206	cnt = 0;
	207	}
	208
	209	if ((++cnt & 0xff) == 0) {
	210	DRM_UDELAY(1);
	211	if (cnt > 100000)
	212	return -EBUSY;
	213	}
	214
	215	chan->dma.ib_free = get - chan->dma.ib_put;
	216	if (chan->dma.ib_free <= 0)
	217	chan->dma.ib_free += chan->dma.ib_max + 1;
	218	}
	219
	220	return 0;
	221	}
	222
	223	static int
	224	nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
	225	{
	226	uint32_t cnt = 0, prev_get = 0;
	227	int ret;
	228
	229	ret = nv50_dma_push_wait(chan, slots + 1);
	230	if (unlikely(ret))
	231	return ret;
	232
	233	while (chan->dma.free < count) {
	234	int get = READ_GET(chan, &prev_get, &cnt);
	235	if (unlikely(get < 0)) {
	236	if (get == -EINVAL)
	237	continue;
	238
	239	return get;
	240	}
	241
	242	if (get <= chan->dma.cur) {
	243	chan->dma.free = chan->dma.max - chan->dma.cur;
	244	if (chan->dma.free >= count)
	245	break;
	246
	247	FIRE_RING(chan);
	248	do {
	249	get = READ_GET(chan, &prev_get, &cnt);
	250	if (unlikely(get < 0)) {
	251	if (get == -EINVAL)
	252	continue;
	253	return get;
	254	}
255	} while (get == 0);
256	chan->dma.cur = 0;
257	chan->dma.put = 0;
258	}
259
260	chan->dma.free = get - chan->dma.cur - 1;
261	}
262
263	return 0;
264	}
265
6ee73861	266	int
9a391ad8	267	nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
6ee73861	268	{
ba59953d BS	269	uint32_t prev_get = 0, cnt = 0;
ba59953d BS	270	int get;
6ee73861	271
9a391ad8 BS	272	if (chan->dma.ib_max)
	273	return nv50_dma_wait(chan, slots, size);
	274
6ee73861	275	while (chan->dma.free < size) {
ba59953d BS	276	get = READ_GET(chan, &prev_get, &cnt);
	277	if (unlikely(get == -EBUSY))
	278	return -EBUSY;
6ee73861 BS	279
	280	/* loop until we have a usable GET pointer. the value
	281	* we read from the GPU may be outside the main ring if
	282	* PFIFO is processing a buffer called from the main ring,
	283	* discard these values until something sensible is seen.
	284	*
	285	* the other case we discard GET is while the GPU is fetching
	286	* from the SKIPS area, so the code below doesn't have to deal
	287	* with some fun corner cases.
	288	*/
ba59953d	289	if (unlikely(get == -EINVAL) \|\| get < NOUVEAU_DMA_SKIPS)
6ee73861 BS	290	continue;
	291
	292	if (get <= chan->dma.cur) {
	293	/* engine is fetching behind us, or is completely
	294	* idle (GET == PUT) so we have free space up until
	295	* the end of the push buffer
	296	*
	297	* we can only hit that path once per call due to
	298	* looping back to the beginning of the push buffer,
	299	* we'll hit the fetching-ahead-of-us path from that
	300	* point on.
	301	*
	302	* the one exception to that rule is if we read
	303	* GET==PUT, in which case the below conditional will
	304	* always succeed and break us out of the wait loop.
	305	*/
	306	chan->dma.free = chan->dma.max - chan->dma.cur;
	307	if (chan->dma.free >= size)
	308	break;
	309
	310	/* not enough space left at the end of the push buffer,
	311	* instruct the GPU to jump back to the start right
	312	* after processing the currently pending commands.
	313	*/
	314	OUT_RING(chan, chan->pushbuf_base \| 0x20000000);
ba59953d BS	315
	316	/* wait for GET to depart from the skips area.
	317	* prevents writing GET==PUT and causing a race
	318	* condition that causes us to think the GPU is
	319	* idle when it's not.
	320	*/
	321	do {
	322	get = READ_GET(chan, &prev_get, &cnt);
	323	if (unlikely(get == -EBUSY))
	324	return -EBUSY;
	325	if (unlikely(get == -EINVAL))
	326	continue;
	327	} while (get <= NOUVEAU_DMA_SKIPS);
6ee73861 BS	328	WRITE_PUT(NOUVEAU_DMA_SKIPS);
	329
	330	/* we're now submitting commands at the start of
	331	* the push buffer.
	332	*/
	333	chan->dma.cur =
	334	chan->dma.put = NOUVEAU_DMA_SKIPS;
	335	}
	336
	337	/* engine fetching ahead of us, we have space up until the
	338	* current GET pointer. the "- 1" is to ensure there's
	339	* space left to emit a jump back to the beginning of the
	340	* push buffer if we require it. we can never get GET == PUT
	341	* here, so this is safe.
	342	*/
	343	chan->dma.free = get - chan->dma.cur - 1;
	344	}
	345
	346	return 0;
	347	}
	348