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drm/nouveau: implement init table op 0x57, INIT_LTIME
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861 30
67eda20e
FJ		 31#include <linux/io-mapping.h>
32
6ee73861
BS		 33/* these defines are made up */
34#define NV_CIO_CRE_44_HEADA 0x0
35#define NV_CIO_CRE_44_HEADB 0x3
36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
37#define LEGACY_I2C_CRT 0x80
38#define LEGACY_I2C_PANEL 0x81
39#define LEGACY_I2C_TV 0x82
40
41#define EDID1_LEN 128
42
43#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
44#define LOG_OLD_VALUE(x)
45
46#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
47#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
48
49struct init_exec {
50 bool execute;
51 bool repeat;
52};
53
54static bool nv_cksum(const uint8_t *data, unsigned int length)
55{
56 /*
57 * There's a few checksums in the BIOS, so here's a generic checking
58 * function.
59 */
60 int i;
61 uint8_t sum = 0;
62
63 for (i = 0; i < length; i++)
64 sum += data[i];
65
66 if (sum)
67 return true;
68
69 return false;
70}
71
72static int
73score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
74{
75 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
76 NV_TRACEWARN(dev, "... BIOS signature not found\n");
77 return 0;
78 }
79
80 if (nv_cksum(data, data[2] * 512)) {
81 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
82 /* if a ro image is somewhat bad, it's probably all rubbish */
83 return writeable ? 2 : 1;
84 } else
85 NV_TRACE(dev, "... appears to be valid\n");
86
87 return 3;
88}
89
90static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
91{
92 struct drm_nouveau_private *dev_priv = dev->dev_private;
93 uint32_t pci_nv_20, save_pci_nv_20;
94 int pcir_ptr;
95 int i;
96
97 if (dev_priv->card_type >= NV_50)
98 pci_nv_20 = 0x88050;
99 else
100 pci_nv_20 = NV_PBUS_PCI_NV_20;
101
102 /* enable ROM access */
103 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
104 nvWriteMC(dev, pci_nv_20,
105 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
106
107 /* bail if no rom signature */
108 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
109 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
110 goto out;
111
112 /* additional check (see note below) - read PCI record header */
113 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
114 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
115 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
117 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
118 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
119 goto out;
120
121 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
122 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
123 * each byte. we'll hope pramin has something usable instead
124 */
125 for (i = 0; i < NV_PROM_SIZE; i++)
126 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
127
128out:
129 /* disable ROM access */
130 nvWriteMC(dev, pci_nv_20,
131 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
132}
133
134static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
135{
136 struct drm_nouveau_private *dev_priv = dev->dev_private;
137 uint32_t old_bar0_pramin = 0;
138 int i;
139
140 if (dev_priv->card_type >= NV_50) {
141 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
142
143 if (!vbios_vram)
144 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
145
146 old_bar0_pramin = nv_rd32(dev, 0x1700);
147 nv_wr32(dev, 0x1700, vbios_vram >> 16);
148 }
149
150 /* bail if no rom signature */
151 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
152 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
153 goto out;
154
155 for (i = 0; i < NV_PROM_SIZE; i++)
156 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
157
158out:
159 if (dev_priv->card_type >= NV_50)
160 nv_wr32(dev, 0x1700, old_bar0_pramin);
161}
162
163static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
164{
165 void __iomem *rom = NULL;
166 size_t rom_len;
167 int ret;
168
169 ret = pci_enable_rom(dev->pdev);
170 if (ret)
171 return;
172
173 rom = pci_map_rom(dev->pdev, &rom_len);
174 if (!rom)
175 goto out;
176 memcpy_fromio(data, rom, rom_len);
177 pci_unmap_rom(dev->pdev, rom);
178
179out:
180 pci_disable_rom(dev->pdev);
181}
182
afeb3e11
DA		 183static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
184{
185 int i;
186 int ret;
187 int size = 64 * 1024;
188
189 if (!nouveau_acpi_rom_supported(dev->pdev))
190 return;
191
192 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
193 ret = nouveau_acpi_get_bios_chunk(data,
194 (i * ROM_BIOS_PAGE),
195 ROM_BIOS_PAGE);
196 if (ret <= 0)
197 break;
198 }
199 return;
200}
201
6ee73861
BS		 202struct methods {
203 const char desc[8];
204 void (*loadbios)(struct drm_device *, uint8_t *);
205 const bool rw;
6ee73861
BS		 206};
207
41090eb4 208static struct methods shadow_methods[] = {
6ee73861
BS		 209 { "PRAMIN", load_vbios_pramin, true },
210 { "PROM", load_vbios_prom, false },
211 { "PCIROM", load_vbios_pci, true },
41090eb4 212 { "ACPI", load_vbios_acpi, true },
6ee73861 213};
eae6192a 214#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
6ee73861
BS		 215
216static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
217{
41090eb4 218 struct methods *methods = shadow_methods;
6ee73861 219 int testscore = 3;
eae6192a 220 int scores[NUM_SHADOW_METHODS], i;
6ee73861
BS		 221
222 if (nouveau_vbios) {
eae6192a 223 for (i = 0; i < NUM_SHADOW_METHODS; i++)
657b6245 224 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 225 break;
6ee73861 226
eae6192a 227 if (i < NUM_SHADOW_METHODS) {
6ee73861 228 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 229 methods[i].desc);
6ee73861 230
657b6245
MK		 231 methods[i].loadbios(dev, data);
232 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 233 return true;
234 }
235
236 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
237 }
238
eae6192a 239 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
6ee73861 240 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 241 methods[i].desc);
6ee73861 242 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 243 methods[i].loadbios(dev, data);
244 scores[i] = score_vbios(dev, data, methods[i].rw);
245 if (scores[i] == testscore)
6ee73861 246 return true;
6ee73861
BS		 247 }
248
249 while (--testscore > 0) {
eae6192a 250 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
657b6245 251 if (scores[i] == testscore) {
6ee73861 252 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 253 methods[i].desc);
254 methods[i].loadbios(dev, data);
6ee73861
BS		 255 return true;
256 }
6ee73861
BS		 257 }
258 }
259
260 NV_ERROR(dev, "No valid BIOS image found\n");
261 return false;
262}
263
264struct init_tbl_entry {
265 char *name;
266 uint8_t id;
9170a824
BS		 267 /* Return:
268 * > 0: success, length of opcode
269 * 0: success, but abort further parsing of table (INIT_DONE etc)
270 * < 0: failure, table parsing will be aborted
271 */
37383650 272 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 273};
274
275struct bit_entry {
276 uint8_t id[2];
277 uint16_t length;
278 uint16_t offset;
279};
280
281static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
282
283#define MACRO_INDEX_SIZE 2
284#define MACRO_SIZE 8
285#define CONDITION_SIZE 12
286#define IO_FLAG_CONDITION_SIZE 9
287#define IO_CONDITION_SIZE 5
288#define MEM_INIT_SIZE 66
289
290static void still_alive(void)
291{
292#if 0
293 sync();
294 msleep(2);
295#endif
296}
297
298static uint32_t
299munge_reg(struct nvbios *bios, uint32_t reg)
300{
301 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
302 struct dcb_entry *dcbent = bios->display.output;
303
304 if (dev_priv->card_type < NV_50)
305 return reg;
306
307 if (reg & 0x40000000) {
308 BUG_ON(!dcbent);
309
310 reg += (ffs(dcbent->or) - 1) * 0x800;
311 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
312 reg += 0x00000080;
313 }
314
315 reg &= ~0x60000000;
316 return reg;
317}
318
319static int
320valid_reg(struct nvbios *bios, uint32_t reg)
321{
322 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
323 struct drm_device *dev = bios->dev;
324
325 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 326 if (reg & 0x2 ||
04a39c57 327 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 328 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
329
330 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 331 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 332 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
333 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
334 reg);
335
9855e584
BS		 336 if (reg >= (8*1024*1024)) {
337 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
338 return 0;
6ee73861 339 }
9855e584
BS		 340
341 return 1;
6ee73861
BS		 342}
343
344static bool
345valid_idx_port(struct nvbios *bios, uint16_t port)
346{
347 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
348 struct drm_device *dev = bios->dev;
349
350 /*
351 * If adding more ports here, the read/write functions below will need
352 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
353 * used for the port in question
354 */
355 if (dev_priv->card_type < NV_50) {
356 if (port == NV_CIO_CRX__COLOR)
357 return true;
358 if (port == NV_VIO_SRX)
359 return true;
360 } else {
361 if (port == NV_CIO_CRX__COLOR)
362 return true;
363 }
364
365 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
366 port);
367
368 return false;
369}
370
371static bool
372valid_port(struct nvbios *bios, uint16_t port)
373{
374 struct drm_device *dev = bios->dev;
375
376 /*
377 * If adding more ports here, the read/write functions below will need
378 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
379 * used for the port in question
380 */
381 if (port == NV_VIO_VSE2)
382 return true;
383
384 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
385
386 return false;
387}
388
389static uint32_t
390bios_rd32(struct nvbios *bios, uint32_t reg)
391{
392 uint32_t data;
393
394 reg = munge_reg(bios, reg);
395 if (!valid_reg(bios, reg))
396 return 0;
397
398 /*
399 * C51 sometimes uses regs with bit0 set in the address. For these
400 * cases there should exist a translation in a BIOS table to an IO
401 * port address which the BIOS uses for accessing the reg
402 *
403 * These only seem to appear for the power control regs to a flat panel,
404 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
405 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
406 * suspend-resume mmio trace from a C51 will be required to see if this
407 * is true for the power microcode in 0x14.., or whether the direct IO
408 * port access method is needed
409 */
410 if (reg & 0x1)
411 reg &= ~0x1;
412
413 data = nv_rd32(bios->dev, reg);
414
415 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
416
417 return data;
418}
419
420static void
421bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
422{
423 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
424
425 reg = munge_reg(bios, reg);
426 if (!valid_reg(bios, reg))
427 return;
428
429 /* see note in bios_rd32 */
430 if (reg & 0x1)
431 reg &= 0xfffffffe;
432
433 LOG_OLD_VALUE(bios_rd32(bios, reg));
434 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
435
04a39c57 436 if (dev_priv->vbios.execute) {
6ee73861
BS		 437 still_alive();
438 nv_wr32(bios->dev, reg, data);
439 }
440}
441
442static uint8_t
443bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
444{
445 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
446 struct drm_device *dev = bios->dev;
447 uint8_t data;
448
449 if (!valid_idx_port(bios, port))
450 return 0;
451
452 if (dev_priv->card_type < NV_50) {
453 if (port == NV_VIO_SRX)
454 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
455 else /* assume NV_CIO_CRX__COLOR */
456 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
457 } else {
458 uint32_t data32;
459
460 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
461 data = (data32 >> ((index & 3) << 3)) & 0xff;
462 }
463
464 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
465 "Head: 0x%02X, Data: 0x%02X\n",
466 port, index, bios->state.crtchead, data);
467 return data;
468}
469
470static void
471bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
472{
473 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
474 struct drm_device *dev = bios->dev;
475
476 if (!valid_idx_port(bios, port))
477 return;
478
479 /*
480 * The current head is maintained in the nvbios member state.crtchead.
481 * We trap changes to CR44 and update the head variable and hence the
482 * register set written.
483 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
484 * of the write, and to head1 after the write
485 */
486 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
487 data != NV_CIO_CRE_44_HEADB)
488 bios->state.crtchead = 0;
489
490 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
491 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
492 "Head: 0x%02X, Data: 0x%02X\n",
493 port, index, bios->state.crtchead, data);
494
495 if (bios->execute && dev_priv->card_type < NV_50) {
496 still_alive();
497 if (port == NV_VIO_SRX)
498 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
499 else /* assume NV_CIO_CRX__COLOR */
500 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
501 } else
502 if (bios->execute) {
503 uint32_t data32, shift = (index & 3) << 3;
504
505 still_alive();
506
507 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
508 data32 &= ~(0xff << shift);
509 data32 |= (data << shift);
510 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
511 }
512
513 if (port == NV_CIO_CRX__COLOR &&
514 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
515 bios->state.crtchead = 1;
516}
517
518static uint8_t
519bios_port_rd(struct nvbios *bios, uint16_t port)
520{
521 uint8_t data, head = bios->state.crtchead;
522
523 if (!valid_port(bios, port))
524 return 0;
525
526 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
527
528 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
529 port, head, data);
530
531 return data;
532}
533
534static void
535bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
536{
537 int head = bios->state.crtchead;
538
539 if (!valid_port(bios, port))
540 return;
541
542 LOG_OLD_VALUE(bios_port_rd(bios, port));
543 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
544 port, head, data);
545
546 if (!bios->execute)
547 return;
548
549 still_alive();
550 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
551}
552
553static bool
554io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
555{
556 /*
557 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
558 * for the CRTC index; 1 byte for the mask to apply to the value
559 * retrieved from the CRTC; 1 byte for the shift right to apply to the
560 * masked CRTC value; 2 bytes for the offset to the flag array, to
561 * which the shifted value is added; 1 byte for the mask applied to the
562 * value read from the flag array; and 1 byte for the value to compare
563 * against the masked byte from the flag table.
564 */
565
566 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
567 uint16_t crtcport = ROM16(bios->data[condptr]);
568 uint8_t crtcindex = bios->data[condptr + 2];
569 uint8_t mask = bios->data[condptr + 3];
570 uint8_t shift = bios->data[condptr + 4];
571 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
572 uint8_t flagarraymask = bios->data[condptr + 7];
573 uint8_t cmpval = bios->data[condptr + 8];
574 uint8_t data;
575
576 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
577 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
578 "Cmpval: 0x%02X\n",
579 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
580
581 data = bios_idxprt_rd(bios, crtcport, crtcindex);
582
583 data = bios->data[flagarray + ((data & mask) >> shift)];
584 data &= flagarraymask;
585
586 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
587 offset, data, cmpval);
588
589 return (data == cmpval);
590}
591
592static bool
593bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
594{
595 /*
596 * The condition table entry has 4 bytes for the address of the
597 * register to check, 4 bytes for a mask to apply to the register and
598 * 4 for a test comparison value
599 */
600
601 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
602 uint32_t reg = ROM32(bios->data[condptr]);
603 uint32_t mask = ROM32(bios->data[condptr + 4]);
604 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
605 uint32_t data;
606
607 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
608 offset, cond, reg, mask);
609
610 data = bios_rd32(bios, reg) & mask;
611
612 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
613 offset, data, cmpval);
614
615 return (data == cmpval);
616}
617
618static bool
619io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
620{
621 /*
622 * The IO condition entry has 2 bytes for the IO port address; 1 byte
623 * for the index to write to io_port; 1 byte for the mask to apply to
624 * the byte read from io_port+1; and 1 byte for the value to compare
625 * against the masked byte.
626 */
627
628 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
629 uint16_t io_port = ROM16(bios->data[condptr]);
630 uint8_t port_index = bios->data[condptr + 2];
631 uint8_t mask = bios->data[condptr + 3];
632 uint8_t cmpval = bios->data[condptr + 4];
633
634 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
635
636 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
637 offset, data, cmpval);
638
639 return (data == cmpval);
640}
641
642static int
643nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
644{
645 struct drm_nouveau_private *dev_priv = dev->dev_private;
646 uint32_t reg0 = nv_rd32(dev, reg + 0);
647 uint32_t reg1 = nv_rd32(dev, reg + 4);
648 struct nouveau_pll_vals pll;
649 struct pll_lims pll_limits;
650 int ret;
651
652 ret = get_pll_limits(dev, reg, &pll_limits);
653 if (ret)
654 return ret;
655
656 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
657 if (!clk)
658 return -ERANGE;
659
660 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
661 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
662
04a39c57 663 if (dev_priv->vbios.execute) {
6ee73861
BS		 664 still_alive();
665 nv_wr32(dev, reg + 4, reg1);
666 nv_wr32(dev, reg + 0, reg0);
667 }
668
669 return 0;
670}
671
672static int
673setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
674{
675 struct drm_device *dev = bios->dev;
676 struct drm_nouveau_private *dev_priv = dev->dev_private;
677 /* clk in kHz */
678 struct pll_lims pll_lim;
679 struct nouveau_pll_vals pllvals;
680 int ret;
681
682 if (dev_priv->card_type >= NV_50)
683 return nv50_pll_set(dev, reg, clk);
684
685 /* high regs (such as in the mac g5 table) are not -= 4 */
686 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
687 if (ret)
688 return ret;
689
690 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
691 if (!clk)
692 return -ERANGE;
693
694 if (bios->execute) {
695 still_alive();
696 nouveau_hw_setpll(dev, reg, &pllvals);
697 }
698
699 return 0;
700}
701
702static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
703{
704 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 705 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 706
707 /*
708 * For the results of this function to be correct, CR44 must have been
709 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
710 * and the DCB table parsed, before the script calling the function is
711 * run. run_digital_op_script is example of how to do such setup
712 */
713
714 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
715
7f245b20 716 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 717 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
718 "(%02X)\n", dcb_entry);
719 dcb_entry = 0x7f; /* unused / invalid marker */
720 }
721
722 return dcb_entry;
723}
724
f8b0be1a
BS		 725static int
726read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
727{
728 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
729 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
730 int recordoffset = 0, rdofs = 1, wrofs = 0;
731 uint8_t port_type = 0;
732
733 if (!i2ctable)
734 return -EINVAL;
735
736 if (dcb_version >= 0x30) {
737 if (i2ctable[0] != dcb_version) /* necessary? */
738 NV_WARN(dev,
739 "DCB I2C table version mismatch (%02X vs %02X)\n",
740 i2ctable[0], dcb_version);
741 dcb_i2c_ver = i2ctable[0];
742 headerlen = i2ctable[1];
743 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
744 i2c_entries = i2ctable[2];
745 else
746 NV_WARN(dev,
747 "DCB I2C table has more entries than indexable "
748 "(%d entries, max %d)\n", i2ctable[2],
749 DCB_MAX_NUM_I2C_ENTRIES);
750 entry_len = i2ctable[3];
751 /* [4] is i2c_default_indices, read in parse_dcb_table() */
752 }
753 /*
754 * It's your own fault if you call this function on a DCB 1.1 BIOS --
755 * the test below is for DCB 1.2
756 */
757 if (dcb_version < 0x14) {
758 recordoffset = 2;
759 rdofs = 0;
760 wrofs = 1;
761 }
762
763 if (index == 0xf)
764 return 0;
765 if (index >= i2c_entries) {
766 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
767 index, i2ctable[2]);
768 return -ENOENT;
769 }
770 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
771 NV_ERROR(dev, "DCB I2C entry invalid\n");
772 return -EINVAL;
773 }
774
775 if (dcb_i2c_ver >= 0x30) {
776 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
777
778 /*
779 * Fixup for chips using same address offset for read and
780 * write.
781 */
782 if (port_type == 4) /* seen on C51 */
783 rdofs = wrofs = 1;
784 if (port_type >= 5) /* G80+ */
785 rdofs = wrofs = 0;
786 }
787
788 if (dcb_i2c_ver >= 0x40) {
789 if (port_type != 5 && port_type != 6)
790 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
791
792 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
793 }
794
795 i2c->port_type = port_type;
796 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
797 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
798
799 return 0;
800}
801
6ee73861
BS		 802static struct nouveau_i2c_chan *
803init_i2c_device_find(struct drm_device *dev, int i2c_index)
804{
805 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 806 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 807
808 if (i2c_index == 0xff) {
809 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
810 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 811 int default_indices = dcb->i2c_default_indices;
6ee73861 812
7f245b20 813 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 814 shift = 4;
815
816 i2c_index = (default_indices >> shift) & 0xf;
817 }
818 if (i2c_index == 0x80) /* g80+ */
7f245b20 819 i2c_index = dcb->i2c_default_indices & 0xf;
04f542c0
BS		 820 else
821 if (i2c_index == 0x81)
822 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
6ee73861 823
75047944 824 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
f8b0be1a
BS		 825 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
826 return NULL;
827 }
828
829 /* Make sure i2c table entry has been parsed, it may not
830 * have been if this is a bus not referenced by a DCB encoder
831 */
832 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
833 i2c_index, &dcb->i2c[i2c_index]);
834
6ee73861
BS		 835 return nouveau_i2c_find(dev, i2c_index);
836}
837
7f245b20
BS		 838static uint32_t
839get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 840{
841 /*
842 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
843 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
844 * CR58 for CR57 = 0 to index a table of offsets to the basic
845 * 0x6808b0 address.
846 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
847 * CR58 for CR57 = 0 to index a table of offsets to the basic
848 * 0x6808b0 address, and then flip the offset by 8.
849 */
850
851 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 852 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 853 const int pramdac_offset[13] = {
854 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
855 const uint32_t pramdac_table[4] = {
856 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
857
858 if (mlv >= 0x80) {
859 int dcb_entry, dacoffset;
860
861 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
862 dcb_entry = dcb_entry_idx_from_crtchead(dev);
863 if (dcb_entry == 0x7f)
864 return 0;
7f245b20 865 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 866 if (mlv == 0x81)
867 dacoffset ^= 8;
868 return 0x6808b0 + dacoffset;
869 } else {
df31ef4d 870 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 871 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
872 mlv);
873 return 0;
874 }
875 return pramdac_table[mlv];
876 }
877}
878
37383650 879static int
6ee73861
BS		 880init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
881 struct init_exec *iexec)
882{
883 /*
884 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
885 *
886 * offset (8 bit): opcode
887 * offset + 1 (16 bit): CRTC port
888 * offset + 3 (8 bit): CRTC index
889 * offset + 4 (8 bit): mask
890 * offset + 5 (8 bit): shift
891 * offset + 6 (8 bit): count
892 * offset + 7 (32 bit): register
893 * offset + 11 (32 bit): configuration 1
894 * ...
895 *
896 * Starting at offset + 11 there are "count" 32 bit values.
897 * To find out which value to use read index "CRTC index" on "CRTC
898 * port", AND this value with "mask" and then bit shift right "shift"
899 * bits. Read the appropriate value using this index and write to
900 * "register"
901 */
902
903 uint16_t crtcport = ROM16(bios->data[offset + 1]);
904 uint8_t crtcindex = bios->data[offset + 3];
905 uint8_t mask = bios->data[offset + 4];
906 uint8_t shift = bios->data[offset + 5];
907 uint8_t count = bios->data[offset + 6];
908 uint32_t reg = ROM32(bios->data[offset + 7]);
909 uint8_t config;
910 uint32_t configval;
37383650 911 int len = 11 + count * 4;
6ee73861
BS		 912
913 if (!iexec->execute)
37383650 914 return len;
6ee73861
BS		 915
916 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
917 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
918 offset, crtcport, crtcindex, mask, shift, count, reg);
919
920 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
921 if (config > count) {
922 NV_ERROR(bios->dev,
923 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
924 offset, config, count);
309b8c89 925 return len;
6ee73861
BS		 926 }
927
928 configval = ROM32(bios->data[offset + 11 + config * 4]);
929
930 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
931
932 bios_wr32(bios, reg, configval);
933
37383650 934 return len;
6ee73861
BS		 935}
936
37383650 937static int
6ee73861
BS		 938init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
939{
940 /*
941 * INIT_REPEAT opcode: 0x33 ('3')
942 *
943 * offset (8 bit): opcode
944 * offset + 1 (8 bit): count
945 *
946 * Execute script following this opcode up to INIT_REPEAT_END
947 * "count" times
948 */
949
950 uint8_t count = bios->data[offset + 1];
951 uint8_t i;
952
953 /* no iexec->execute check by design */
954
955 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
956 offset, count);
957
958 iexec->repeat = true;
959
960 /*
961 * count - 1, as the script block will execute once when we leave this
962 * opcode -- this is compatible with bios behaviour as:
963 * a) the block is always executed at least once, even if count == 0
964 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
965 * while we don't
966 */
967 for (i = 0; i < count - 1; i++)
968 parse_init_table(bios, offset + 2, iexec);
969
970 iexec->repeat = false;
971
37383650 972 return 2;
6ee73861
BS		 973}
974
37383650 975static int
6ee73861
BS		 976init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
977 struct init_exec *iexec)
978{
979 /*
980 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
981 *
982 * offset (8 bit): opcode
983 * offset + 1 (16 bit): CRTC port
984 * offset + 3 (8 bit): CRTC index
985 * offset + 4 (8 bit): mask
986 * offset + 5 (8 bit): shift
987 * offset + 6 (8 bit): IO flag condition index
988 * offset + 7 (8 bit): count
989 * offset + 8 (32 bit): register
990 * offset + 12 (16 bit): frequency 1
991 * ...
992 *
993 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
994 * Set PLL register "register" to coefficients for frequency n,
995 * selected by reading index "CRTC index" of "CRTC port" ANDed with
996 * "mask" and shifted right by "shift".
997 *
998 * If "IO flag condition index" > 0, and condition met, double
999 * frequency before setting it.
1000 */
1001
1002 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1003 uint8_t crtcindex = bios->data[offset + 3];
1004 uint8_t mask = bios->data[offset + 4];
1005 uint8_t shift = bios->data[offset + 5];
1006 int8_t io_flag_condition_idx = bios->data[offset + 6];
1007 uint8_t count = bios->data[offset + 7];
1008 uint32_t reg = ROM32(bios->data[offset + 8]);
1009 uint8_t config;
1010 uint16_t freq;
37383650 1011 int len = 12 + count * 2;
6ee73861
BS		 1012
1013 if (!iexec->execute)
37383650 1014 return len;
6ee73861
BS		 1015
1016 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1017 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1018 "Count: 0x%02X, Reg: 0x%08X\n",
1019 offset, crtcport, crtcindex, mask, shift,
1020 io_flag_condition_idx, count, reg);
1021
1022 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1023 if (config > count) {
1024 NV_ERROR(bios->dev,
1025 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1026 offset, config, count);
309b8c89 1027 return len;
6ee73861
BS		 1028 }
1029
1030 freq = ROM16(bios->data[offset + 12 + config * 2]);
1031
1032 if (io_flag_condition_idx > 0) {
1033 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1034 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1035 "frequency doubled\n", offset);
1036 freq *= 2;
1037 } else
1038 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1039 "frequency unchanged\n", offset);
1040 }
1041
1042 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1043 offset, reg, config, freq);
1044
1045 setPLL(bios, reg, freq * 10);
1046
37383650 1047 return len;
6ee73861
BS		 1048}
1049
37383650 1050static int
6ee73861
BS		 1051init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1052{
1053 /*
1054 * INIT_END_REPEAT opcode: 0x36 ('6')
1055 *
1056 * offset (8 bit): opcode
1057 *
1058 * Marks the end of the block for INIT_REPEAT to repeat
1059 */
1060
1061 /* no iexec->execute check by design */
1062
1063 /*
1064 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1065 * we're not in repeat mode
1066 */
1067 if (iexec->repeat)
37383650 1068 return 0;
6ee73861 1069
37383650 1070 return 1;
6ee73861
BS		 1071}
1072
37383650 1073static int
6ee73861
BS		 1074init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1075{
1076 /*
1077 * INIT_COPY opcode: 0x37 ('7')
1078 *
1079 * offset (8 bit): opcode
1080 * offset + 1 (32 bit): register
1081 * offset + 5 (8 bit): shift
1082 * offset + 6 (8 bit): srcmask
1083 * offset + 7 (16 bit): CRTC port
1084 * offset + 9 (8 bit): CRTC index
1085 * offset + 10 (8 bit): mask
1086 *
1087 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1088 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1089 * port
1090 */
1091
1092 uint32_t reg = ROM32(bios->data[offset + 1]);
1093 uint8_t shift = bios->data[offset + 5];
1094 uint8_t srcmask = bios->data[offset + 6];
1095 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1096 uint8_t crtcindex = bios->data[offset + 9];
1097 uint8_t mask = bios->data[offset + 10];
1098 uint32_t data;
1099 uint8_t crtcdata;
1100
1101 if (!iexec->execute)
37383650 1102 return 11;
6ee73861
BS		 1103
1104 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1105 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1106 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1107
1108 data = bios_rd32(bios, reg);
1109
1110 if (shift < 0x80)
1111 data >>= shift;
1112 else
1113 data <<= (0x100 - shift);
1114
1115 data &= srcmask;
1116
1117 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1118 crtcdata |= (uint8_t)data;
1119 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1120
37383650 1121 return 11;
6ee73861
BS		 1122}
1123
37383650 1124static int
6ee73861
BS		 1125init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1126{
1127 /*
1128 * INIT_NOT opcode: 0x38 ('8')
1129 *
1130 * offset (8 bit): opcode
1131 *
1132 * Invert the current execute / no-execute condition (i.e. "else")
1133 */
1134 if (iexec->execute)
1135 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1136 else
1137 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1138
1139 iexec->execute = !iexec->execute;
37383650 1140 return 1;
6ee73861
BS		 1141}
1142
37383650 1143static int
6ee73861
BS		 1144init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1145 struct init_exec *iexec)
1146{
1147 /*
1148 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1149 *
1150 * offset (8 bit): opcode
1151 * offset + 1 (8 bit): condition number
1152 *
1153 * Check condition "condition number" in the IO flag condition table.
1154 * If condition not met skip subsequent opcodes until condition is
1155 * inverted (INIT_NOT), or we hit INIT_RESUME
1156 */
1157
1158 uint8_t cond = bios->data[offset + 1];
1159
1160 if (!iexec->execute)
37383650 1161 return 2;
6ee73861
BS		 1162
1163 if (io_flag_condition_met(bios, offset, cond))
1164 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1165 else {
1166 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1167 iexec->execute = false;
1168 }
1169
37383650 1170 return 2;
6ee73861
BS		 1171}
1172
25908b77
BS		 1173static int
1174init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1175{
1176 /*
1177 * INIT_DP_CONDITION opcode: 0x3A ('')
1178 *
1179 * offset (8 bit): opcode
1180 * offset + 1 (8 bit): "sub" opcode
1181 * offset + 2 (8 bit): unknown
1182 *
1183 */
1184
1185 struct bit_displayport_encoder_table *dpe = NULL;
1186 struct dcb_entry *dcb = bios->display.output;
1187 struct drm_device *dev = bios->dev;
1188 uint8_t cond = bios->data[offset + 1];
1189 int dummy;
1190
1191 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1192
1193 if (!iexec->execute)
1194 return 3;
1195
1196 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1197 if (!dpe) {
1198 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
309b8c89 1199 return 3;
25908b77
BS		 1200 }
1201
1202 switch (cond) {
1203 case 0:
1204 {
1205 struct dcb_connector_table_entry *ent =
1206 &bios->dcb.connector.entry[dcb->connector];
1207
1208 if (ent->type != DCB_CONNECTOR_eDP)
1209 iexec->execute = false;
1210 }
1211 break;
1212 case 1:
1213 case 2:
1214 if (!(dpe->unknown & cond))
1215 iexec->execute = false;
1216 break;
1217 case 5:
1218 {
1219 struct nouveau_i2c_chan *auxch;
1220 int ret;
1221
1222 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
309b8c89
BS		 1223 if (!auxch) {
1224 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1225 return 3;
1226 }
25908b77
BS		 1227
1228 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
309b8c89
BS		 1229 if (ret) {
1230 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1231 return 3;
1232 }
25908b77
BS		 1233
1234 if (cond & 1)
1235 iexec->execute = false;
1236 }
1237 break;
1238 default:
1239 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1240 break;
1241 }
1242
1243 if (iexec->execute)
1244 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1245 else
1246 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1247
1248 return 3;
1249}
1250
1251static int
1252init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1253{
1254 /*
1255 * INIT_3B opcode: 0x3B ('')
1256 *
1257 * offset (8 bit): opcode
1258 * offset + 1 (8 bit): crtc index
1259 *
1260 */
1261
1262 uint8_t or = ffs(bios->display.output->or) - 1;
1263 uint8_t index = bios->data[offset + 1];
1264 uint8_t data;
1265
1266 if (!iexec->execute)
1267 return 2;
1268
1269 data = bios_idxprt_rd(bios, 0x3d4, index);
1270 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1271 return 2;
1272}
1273
1274static int
1275init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1276{
1277 /*
1278 * INIT_3C opcode: 0x3C ('')
1279 *
1280 * offset (8 bit): opcode
1281 * offset + 1 (8 bit): crtc index
1282 *
1283 */
1284
1285 uint8_t or = ffs(bios->display.output->or) - 1;
1286 uint8_t index = bios->data[offset + 1];
1287 uint8_t data;
1288
1289 if (!iexec->execute)
1290 return 2;
1291
1292 data = bios_idxprt_rd(bios, 0x3d4, index);
1293 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1294 return 2;
1295}
1296
37383650 1297static int
6ee73861
BS		 1298init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1299 struct init_exec *iexec)
1300{
1301 /*
1302 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1303 *
1304 * offset (8 bit): opcode
1305 * offset + 1 (32 bit): control register
1306 * offset + 5 (32 bit): data register
1307 * offset + 9 (32 bit): mask
1308 * offset + 13 (32 bit): data
1309 * offset + 17 (8 bit): count
1310 * offset + 18 (8 bit): address 1
1311 * offset + 19 (8 bit): data 1
1312 * ...
1313 *
1314 * For each of "count" address and data pairs, write "data n" to
1315 * "data register", read the current value of "control register",
1316 * and write it back once ANDed with "mask", ORed with "data",
1317 * and ORed with "address n"
1318 */
1319
1320 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1321 uint32_t datareg = ROM32(bios->data[offset + 5]);
1322 uint32_t mask = ROM32(bios->data[offset + 9]);
1323 uint32_t data = ROM32(bios->data[offset + 13]);
1324 uint8_t count = bios->data[offset + 17];
37383650 1325 int len = 18 + count * 2;
6ee73861
BS		 1326 uint32_t value;
1327 int i;
1328
1329 if (!iexec->execute)
37383650 1330 return len;
6ee73861
BS		 1331
1332 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1333 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1334 offset, controlreg, datareg, mask, data, count);
1335
1336 for (i = 0; i < count; i++) {
1337 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1338 uint8_t instdata = bios->data[offset + 19 + i * 2];
1339
1340 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1341 offset, instaddress, instdata);
1342
1343 bios_wr32(bios, datareg, instdata);
1344 value = bios_rd32(bios, controlreg) & mask;
1345 value |= data;
1346 value |= instaddress;
1347 bios_wr32(bios, controlreg, value);
1348 }
1349
37383650 1350 return len;
6ee73861
BS		 1351}
1352
37383650 1353static int
6ee73861
BS		 1354init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1355 struct init_exec *iexec)
1356{
1357 /*
1358 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1359 *
1360 * offset (8 bit): opcode
1361 * offset + 1 (16 bit): CRTC port
1362 * offset + 3 (8 bit): CRTC index
1363 * offset + 4 (8 bit): mask
1364 * offset + 5 (8 bit): shift
1365 * offset + 6 (8 bit): count
1366 * offset + 7 (32 bit): register
1367 * offset + 11 (32 bit): frequency 1
1368 * ...
1369 *
1370 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1371 * Set PLL register "register" to coefficients for frequency n,
1372 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1373 * "mask" and shifted right by "shift".
1374 */
1375
1376 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1377 uint8_t crtcindex = bios->data[offset + 3];
1378 uint8_t mask = bios->data[offset + 4];
1379 uint8_t shift = bios->data[offset + 5];
1380 uint8_t count = bios->data[offset + 6];
1381 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1382 int len = 11 + count * 4;
6ee73861
BS		 1383 uint8_t config;
1384 uint32_t freq;
1385
1386 if (!iexec->execute)
37383650 1387 return len;
6ee73861
BS		 1388
1389 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1390 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1391 offset, crtcport, crtcindex, mask, shift, count, reg);
1392
1393 if (!reg)
37383650 1394 return len;
6ee73861
BS		 1395
1396 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1397 if (config > count) {
1398 NV_ERROR(bios->dev,
1399 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1400 offset, config, count);
309b8c89 1401 return len;
6ee73861
BS		 1402 }
1403
1404 freq = ROM32(bios->data[offset + 11 + config * 4]);
1405
1406 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1407 offset, reg, config, freq);
1408
1409 setPLL(bios, reg, freq);
1410
37383650 1411 return len;
6ee73861
BS		 1412}
1413
37383650 1414static int
6ee73861
BS		 1415init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1416{
1417 /*
1418 * INIT_PLL2 opcode: 0x4B ('K')
1419 *
1420 * offset (8 bit): opcode
1421 * offset + 1 (32 bit): register
1422 * offset + 5 (32 bit): freq
1423 *
1424 * Set PLL register "register" to coefficients for frequency "freq"
1425 */
1426
1427 uint32_t reg = ROM32(bios->data[offset + 1]);
1428 uint32_t freq = ROM32(bios->data[offset + 5]);
1429
1430 if (!iexec->execute)
37383650 1431 return 9;
6ee73861
BS		 1432
1433 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1434 offset, reg, freq);
1435
1436 setPLL(bios, reg, freq);
37383650 1437 return 9;
6ee73861
BS		 1438}
1439
37383650 1440static int
6ee73861
BS		 1441init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1442{
1443 /*
1444 * INIT_I2C_BYTE opcode: 0x4C ('L')
1445 *
1446 * offset (8 bit): opcode
1447 * offset + 1 (8 bit): DCB I2C table entry index
1448 * offset + 2 (8 bit): I2C slave address
1449 * offset + 3 (8 bit): count
1450 * offset + 4 (8 bit): I2C register 1
1451 * offset + 5 (8 bit): mask 1
1452 * offset + 6 (8 bit): data 1
1453 * ...
1454 *
1455 * For each of "count" registers given by "I2C register n" on the device
1456 * addressed by "I2C slave address" on the I2C bus given by
1457 * "DCB I2C table entry index", read the register, AND the result with
1458 * "mask n" and OR it with "data n" before writing it back to the device
1459 */
1460
309b8c89 1461 struct drm_device *dev = bios->dev;
6ee73861 1462 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1463 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1464 uint8_t count = bios->data[offset + 3];
1465 struct nouveau_i2c_chan *chan;
893887ed
BS		 1466 int len = 4 + count * 3;
1467 int ret, i;
6ee73861
BS		 1468
1469 if (!iexec->execute)
37383650 1470 return len;
6ee73861
BS		 1471
1472 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1473 "Count: 0x%02X\n",
1474 offset, i2c_index, i2c_address, count);
1475
309b8c89
BS		 1476 chan = init_i2c_device_find(dev, i2c_index);
1477 if (!chan) {
1478 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1479 return len;
1480 }
6ee73861
BS		 1481
1482 for (i = 0; i < count; i++) {
893887ed 1483 uint8_t reg = bios->data[offset + 4 + i * 3];
6ee73861
BS		 1484 uint8_t mask = bios->data[offset + 5 + i * 3];
1485 uint8_t data = bios->data[offset + 6 + i * 3];
893887ed 1486 union i2c_smbus_data val;
6ee73861 1487
893887ed
BS		 1488 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1489 I2C_SMBUS_READ, reg,
1490 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1491 if (ret < 0) {
1492 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1493 return len;
1494 }
6ee73861
BS		 1495
1496 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1497 "Mask: 0x%02X, Data: 0x%02X\n",
893887ed 1498 offset, reg, val.byte, mask, data);
6ee73861 1499
893887ed
BS		 1500 if (!bios->execute)
1501 continue;
6ee73861 1502
893887ed
BS		 1503 val.byte &= mask;
1504 val.byte |= data;
1505 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1506 I2C_SMBUS_WRITE, reg,
1507 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1508 if (ret < 0) {
1509 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1510 return len;
1511 }
6ee73861
BS		 1512 }
1513
37383650 1514 return len;
6ee73861
BS		 1515}
1516
37383650 1517static int
6ee73861
BS		 1518init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1519{
1520 /*
1521 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1522 *
1523 * offset (8 bit): opcode
1524 * offset + 1 (8 bit): DCB I2C table entry index
1525 * offset + 2 (8 bit): I2C slave address
1526 * offset + 3 (8 bit): count
1527 * offset + 4 (8 bit): I2C register 1
1528 * offset + 5 (8 bit): data 1
1529 * ...
1530 *
1531 * For each of "count" registers given by "I2C register n" on the device
1532 * addressed by "I2C slave address" on the I2C bus given by
1533 * "DCB I2C table entry index", set the register to "data n"
1534 */
1535
309b8c89 1536 struct drm_device *dev = bios->dev;
6ee73861 1537 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1538 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1539 uint8_t count = bios->data[offset + 3];
1540 struct nouveau_i2c_chan *chan;
893887ed
BS		 1541 int len = 4 + count * 2;
1542 int ret, i;
6ee73861
BS		 1543
1544 if (!iexec->execute)
37383650 1545 return len;
6ee73861
BS		 1546
1547 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1548 "Count: 0x%02X\n",
1549 offset, i2c_index, i2c_address, count);
1550
309b8c89
BS		 1551 chan = init_i2c_device_find(dev, i2c_index);
1552 if (!chan) {
1553 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1554 return len;
1555 }
6ee73861
BS		 1556
1557 for (i = 0; i < count; i++) {
893887ed
BS		 1558 uint8_t reg = bios->data[offset + 4 + i * 2];
1559 union i2c_smbus_data val;
1560
1561 val.byte = bios->data[offset + 5 + i * 2];
6ee73861
BS		 1562
1563 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
893887ed
BS		 1564 offset, reg, val.byte);
1565
1566 if (!bios->execute)
1567 continue;
1568
1569 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1570 I2C_SMBUS_WRITE, reg,
1571 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1572 if (ret < 0) {
1573 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1574 return len;
1575 }
6ee73861
BS		 1576 }
1577
37383650 1578 return len;
6ee73861
BS		 1579}
1580
37383650 1581static int
6ee73861
BS		 1582init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1583{
1584 /*
1585 * INIT_ZM_I2C opcode: 0x4E ('N')
1586 *
1587 * offset (8 bit): opcode
1588 * offset + 1 (8 bit): DCB I2C table entry index
1589 * offset + 2 (8 bit): I2C slave address
1590 * offset + 3 (8 bit): count
1591 * offset + 4 (8 bit): data 1
1592 * ...
1593 *
1594 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1595 * address" on the I2C bus given by "DCB I2C table entry index"
1596 */
1597
309b8c89 1598 struct drm_device *dev = bios->dev;
6ee73861 1599 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1600 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1601 uint8_t count = bios->data[offset + 3];
37383650 1602 int len = 4 + count;
6ee73861
BS		 1603 struct nouveau_i2c_chan *chan;
1604 struct i2c_msg msg;
1605 uint8_t data[256];
309b8c89 1606 int ret, i;
6ee73861
BS		 1607
1608 if (!iexec->execute)
37383650 1609 return len;
6ee73861
BS		 1610
1611 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1612 "Count: 0x%02X\n",
1613 offset, i2c_index, i2c_address, count);
1614
309b8c89
BS		 1615 chan = init_i2c_device_find(dev, i2c_index);
1616 if (!chan) {
1617 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1618 return len;
1619 }
6ee73861
BS		 1620
1621 for (i = 0; i < count; i++) {
1622 data[i] = bios->data[offset + 4 + i];
1623
1624 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1625 }
1626
1627 if (bios->execute) {
1628 msg.addr = i2c_address;
1629 msg.flags = 0;
1630 msg.len = count;
1631 msg.buf = data;
309b8c89
BS		 1632 ret = i2c_transfer(&chan->adapter, &msg, 1);
1633 if (ret != 1) {
1634 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1635 return len;
1636 }
6ee73861
BS		 1637 }
1638
37383650 1639 return len;
6ee73861
BS		 1640}
1641
37383650 1642static int
6ee73861
BS		 1643init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1644{
1645 /*
1646 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1647 *
1648 * offset (8 bit): opcode
1649 * offset + 1 (8 bit): magic lookup value
1650 * offset + 2 (8 bit): TMDS address
1651 * offset + 3 (8 bit): mask
1652 * offset + 4 (8 bit): data
1653 *
1654 * Read the data reg for TMDS address "TMDS address", AND it with mask
1655 * and OR it with data, then write it back
1656 * "magic lookup value" determines which TMDS base address register is
1657 * used -- see get_tmds_index_reg()
1658 */
1659
309b8c89 1660 struct drm_device *dev = bios->dev;
6ee73861
BS		 1661 uint8_t mlv = bios->data[offset + 1];
1662 uint32_t tmdsaddr = bios->data[offset + 2];
1663 uint8_t mask = bios->data[offset + 3];
1664 uint8_t data = bios->data[offset + 4];
1665 uint32_t reg, value;
1666
1667 if (!iexec->execute)
37383650 1668 return 5;
6ee73861
BS		 1669
1670 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1671 "Mask: 0x%02X, Data: 0x%02X\n",
1672 offset, mlv, tmdsaddr, mask, data);
1673
1674 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1675 if (!reg) {
1676 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1677 return 5;
1678 }
6ee73861
BS		 1679
1680 bios_wr32(bios, reg,
1681 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1682 value = (bios_rd32(bios, reg + 4) & mask) | data;
1683 bios_wr32(bios, reg + 4, value);
1684 bios_wr32(bios, reg, tmdsaddr);
1685
37383650 1686 return 5;
6ee73861
BS		 1687}
1688
37383650 1689static int
6ee73861
BS		 1690init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1691 struct init_exec *iexec)
1692{
1693 /*
1694 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1695 *
1696 * offset (8 bit): opcode
1697 * offset + 1 (8 bit): magic lookup value
1698 * offset + 2 (8 bit): count
1699 * offset + 3 (8 bit): addr 1
1700 * offset + 4 (8 bit): data 1
1701 * ...
1702 *
1703 * For each of "count" TMDS address and data pairs write "data n" to
1704 * "addr n". "magic lookup value" determines which TMDS base address
1705 * register is used -- see get_tmds_index_reg()
1706 */
1707
309b8c89 1708 struct drm_device *dev = bios->dev;
6ee73861
BS		 1709 uint8_t mlv = bios->data[offset + 1];
1710 uint8_t count = bios->data[offset + 2];
37383650 1711 int len = 3 + count * 2;
6ee73861
BS		 1712 uint32_t reg;
1713 int i;
1714
1715 if (!iexec->execute)
37383650 1716 return len;
6ee73861
BS		 1717
1718 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1719 offset, mlv, count);
1720
1721 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1722 if (!reg) {
1723 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1724 return len;
1725 }
6ee73861
BS		 1726
1727 for (i = 0; i < count; i++) {
1728 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1729 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1730
1731 bios_wr32(bios, reg + 4, tmdsdata);
1732 bios_wr32(bios, reg, tmdsaddr);
1733 }
1734
37383650 1735 return len;
6ee73861
BS		 1736}
1737
37383650 1738static int
6ee73861
BS		 1739init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1740 struct init_exec *iexec)
1741{
1742 /*
1743 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1744 *
1745 * offset (8 bit): opcode
1746 * offset + 1 (8 bit): CRTC index1
1747 * offset + 2 (8 bit): CRTC index2
1748 * offset + 3 (8 bit): baseaddr
1749 * offset + 4 (8 bit): count
1750 * offset + 5 (8 bit): data 1
1751 * ...
1752 *
1753 * For each of "count" address and data pairs, write "baseaddr + n" to
1754 * "CRTC index1" and "data n" to "CRTC index2"
1755 * Once complete, restore initial value read from "CRTC index1"
1756 */
1757 uint8_t crtcindex1 = bios->data[offset + 1];
1758 uint8_t crtcindex2 = bios->data[offset + 2];
1759 uint8_t baseaddr = bios->data[offset + 3];
1760 uint8_t count = bios->data[offset + 4];
37383650 1761 int len = 5 + count;
6ee73861
BS		 1762 uint8_t oldaddr, data;
1763 int i;
1764
1765 if (!iexec->execute)
37383650 1766 return len;
6ee73861
BS		 1767
1768 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1769 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1770 offset, crtcindex1, crtcindex2, baseaddr, count);
1771
1772 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1773
1774 for (i = 0; i < count; i++) {
1775 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1776 baseaddr + i);
1777 data = bios->data[offset + 5 + i];
1778 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1779 }
1780
1781 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1782
37383650 1783 return len;
6ee73861
BS		 1784}
1785
37383650 1786static int
6ee73861
BS		 1787init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1788{
1789 /*
1790 * INIT_CR opcode: 0x52 ('R')
1791 *
1792 * offset (8 bit): opcode
1793 * offset + 1 (8 bit): CRTC index
1794 * offset + 2 (8 bit): mask
1795 * offset + 3 (8 bit): data
1796 *
1797 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1798 * data back to "CRTC index"
1799 */
1800
1801 uint8_t crtcindex = bios->data[offset + 1];
1802 uint8_t mask = bios->data[offset + 2];
1803 uint8_t data = bios->data[offset + 3];
1804 uint8_t value;
1805
1806 if (!iexec->execute)
37383650 1807 return 4;
6ee73861
BS		 1808
1809 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1810 offset, crtcindex, mask, data);
1811
1812 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1813 value |= data;
1814 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1815
37383650 1816 return 4;
6ee73861
BS		 1817}
1818
37383650 1819static int
6ee73861
BS		 1820init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1821{
1822 /*
1823 * INIT_ZM_CR opcode: 0x53 ('S')
1824 *
1825 * offset (8 bit): opcode
1826 * offset + 1 (8 bit): CRTC index
1827 * offset + 2 (8 bit): value
1828 *
1829 * Assign "value" to CRTC register with index "CRTC index".
1830 */
1831
1832 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1833 uint8_t data = bios->data[offset + 2];
1834
1835 if (!iexec->execute)
37383650 1836 return 3;
6ee73861
BS		 1837
1838 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1839
37383650 1840 return 3;
6ee73861
BS		 1841}
1842
37383650 1843static int
6ee73861
BS		 1844init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1845{
1846 /*
1847 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1848 *
1849 * offset (8 bit): opcode
1850 * offset + 1 (8 bit): count
1851 * offset + 2 (8 bit): CRTC index 1
1852 * offset + 3 (8 bit): value 1
1853 * ...
1854 *
1855 * For "count", assign "value n" to CRTC register with index
1856 * "CRTC index n".
1857 */
1858
1859 uint8_t count = bios->data[offset + 1];
37383650 1860 int len = 2 + count * 2;
6ee73861
BS		 1861 int i;
1862
1863 if (!iexec->execute)
37383650 1864 return len;
6ee73861
BS		 1865
1866 for (i = 0; i < count; i++)
1867 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1868
37383650 1869 return len;
6ee73861
BS		 1870}
1871
37383650 1872static int
6ee73861
BS		 1873init_condition_time(struct nvbios *bios, uint16_t offset,
1874 struct init_exec *iexec)
1875{
1876 /*
1877 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1878 *
1879 * offset (8 bit): opcode
1880 * offset + 1 (8 bit): condition number
1881 * offset + 2 (8 bit): retries / 50
1882 *
1883 * Check condition "condition number" in the condition table.
1884 * Bios code then sleeps for 2ms if the condition is not met, and
1885 * repeats up to "retries" times, but on one C51 this has proved
1886 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1887 * this, and bail after "retries" times, or 2s, whichever is less.
1888 * If still not met after retries, clear execution flag for this table.
1889 */
1890
1891 uint8_t cond = bios->data[offset + 1];
1892 uint16_t retries = bios->data[offset + 2] * 50;
1893 unsigned cnt;
1894
1895 if (!iexec->execute)
37383650 1896 return 3;
6ee73861
BS		 1897
1898 if (retries > 100)
1899 retries = 100;
1900
1901 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1902 offset, cond, retries);
1903
1904 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1905 retries = 1;
1906
1907 for (cnt = 0; cnt < retries; cnt++) {
1908 if (bios_condition_met(bios, offset, cond)) {
1909 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1910 offset);
1911 break;
1912 } else {
1913 BIOSLOG(bios, "0x%04X: "
1914 "Condition not met, sleeping for 20ms\n",
1915 offset);
1916 msleep(20);
1917 }
1918 }
1919
1920 if (!bios_condition_met(bios, offset, cond)) {
1921 NV_WARN(bios->dev,
1922 "0x%04X: Condition still not met after %dms, "
1923 "skipping following opcodes\n", offset, 20 * retries);
1924 iexec->execute = false;
1925 }
1926
37383650 1927 return 3;
6ee73861
BS		 1928}
1929
e3a1924f
MK		 1930static int
1931init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1932{
1933 /*
1934 * INIT_LTIME opcode: 0x57 ('V')
1935 *
1936 * offset (8 bit): opcode
1937 * offset + 1 (16 bit): time
1938 *
1939 * Sleep for "time" miliseconds.
1940 */
1941
1942 unsigned time = ROM16(bios->data[offset + 1]);
1943
1944 if (!iexec->execute)
1945 return 3;
1946
1947 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X miliseconds\n",
1948 offset, time);
1949
1950 msleep(time);
1951
1952 return 3;
1953}
1954
37383650 1955static int
6ee73861
BS		 1956init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1957 struct init_exec *iexec)
1958{
1959 /*
1960 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1961 *
1962 * offset (8 bit): opcode
1963 * offset + 1 (32 bit): base register
1964 * offset + 5 (8 bit): count
1965 * offset + 6 (32 bit): value 1
1966 * ...
1967 *
1968 * Starting at offset + 6 there are "count" 32 bit values.
1969 * For "count" iterations set "base register" + 4 * current_iteration
1970 * to "value current_iteration"
1971 */
1972
1973 uint32_t basereg = ROM32(bios->data[offset + 1]);
1974 uint32_t count = bios->data[offset + 5];
37383650 1975 int len = 6 + count * 4;
6ee73861
BS		 1976 int i;
1977
1978 if (!iexec->execute)
37383650 1979 return len;
6ee73861
BS		 1980
1981 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1982 offset, basereg, count);
1983
1984 for (i = 0; i < count; i++) {
1985 uint32_t reg = basereg + i * 4;
1986 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1987
1988 bios_wr32(bios, reg, data);
1989 }
1990
37383650 1991 return len;
6ee73861
BS		 1992}
1993
37383650 1994static int
6ee73861
BS		 1995init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1996{
1997 /*
1998 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1999 *
2000 * offset (8 bit): opcode
2001 * offset + 1 (16 bit): subroutine offset (in bios)
2002 *
2003 * Calls a subroutine that will execute commands until INIT_DONE
2004 * is found.
2005 */
2006
2007 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
2008
2009 if (!iexec->execute)
37383650 2010 return 3;
6ee73861
BS		 2011
2012 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
2013 offset, sub_offset);
2014
2015 parse_init_table(bios, sub_offset, iexec);
2016
2017 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
2018
37383650 2019 return 3;
6ee73861
BS		 2020}
2021
37383650 2022static int
6ee73861
BS		 2023init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2024{
2025 /*
2026 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2027 *
2028 * offset (8 bit): opcode
2029 * offset + 1 (32 bit): src reg
2030 * offset + 5 (8 bit): shift
2031 * offset + 6 (32 bit): src mask
2032 * offset + 10 (32 bit): xor
2033 * offset + 14 (32 bit): dst reg
2034 * offset + 18 (32 bit): dst mask
2035 *
2036 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2037 * "src mask", then XOR with "xor". Write this OR'd with
2038 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2039 */
2040
2041 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2042 uint8_t shift = bios->data[offset + 5];
2043 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2044 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2045 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2046 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2047 uint32_t srcvalue, dstvalue;
2048
2049 if (!iexec->execute)
37383650 2050 return 22;
6ee73861
BS		 2051
2052 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2053 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2054 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2055
2056 srcvalue = bios_rd32(bios, srcreg);
2057
2058 if (shift < 0x80)
2059 srcvalue >>= shift;
2060 else
2061 srcvalue <<= (0x100 - shift);
2062
2063 srcvalue = (srcvalue & srcmask) ^ xor;
2064
2065 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2066
2067 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2068
37383650 2069 return 22;
6ee73861
BS		 2070}
2071
37383650 2072static int
6ee73861
BS		 2073init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2074{
2075 /*
2076 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2077 *
2078 * offset (8 bit): opcode
2079 * offset + 1 (16 bit): CRTC port
2080 * offset + 3 (8 bit): CRTC index
2081 * offset + 4 (8 bit): data
2082 *
2083 * Write "data" to index "CRTC index" of "CRTC port"
2084 */
2085 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2086 uint8_t crtcindex = bios->data[offset + 3];
2087 uint8_t data = bios->data[offset + 4];
2088
2089 if (!iexec->execute)
37383650 2090 return 5;
6ee73861
BS		 2091
2092 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2093
37383650 2094 return 5;
6ee73861
BS		 2095}
2096
67eda20e
FJ		 2097static inline void
2098bios_md32(struct nvbios *bios, uint32_t reg,
2099 uint32_t mask, uint32_t val)
2100{
2101 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2102}
2103
2104static uint32_t
2105peek_fb(struct drm_device *dev, struct io_mapping *fb,
2106 uint32_t off)
2107{
2108 uint32_t val = 0;
2109
2110 if (off < pci_resource_len(dev->pdev, 1)) {
0bf9b0e0
FJ		 2111 uint32_t __iomem *p =
2112 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0);
67eda20e 2113
0bf9b0e0 2114 val = ioread32(p + (off & ~PAGE_MASK));
67eda20e 2115
fca3ec01 2116 io_mapping_unmap_atomic(p, KM_USER0);
67eda20e
FJ		 2117 }
2118
2119 return val;
2120}
2121
2122static void
2123poke_fb(struct drm_device *dev, struct io_mapping *fb,
2124 uint32_t off, uint32_t val)
2125{
2126 if (off < pci_resource_len(dev->pdev, 1)) {
0bf9b0e0
FJ		 2127 uint32_t __iomem *p =
2128 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0);
67eda20e 2129
0bf9b0e0 2130 iowrite32(val, p + (off & ~PAGE_MASK));
67eda20e
FJ		 2131 wmb();
2132
fca3ec01 2133 io_mapping_unmap_atomic(p, KM_USER0);
67eda20e
FJ		 2134 }
2135}
2136
2137static inline bool
2138read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2139 uint32_t off, uint32_t val)
2140{
2141 poke_fb(dev, fb, off, val);
2142 return val == peek_fb(dev, fb, off);
2143}
2144
2145static int
2146nv04_init_compute_mem(struct nvbios *bios)
2147{
2148 struct drm_device *dev = bios->dev;
2149 uint32_t patt = 0xdeadbeef;
2150 struct io_mapping *fb;
2151 int i;
2152
2153 /* Map the framebuffer aperture */
2154 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2155 pci_resource_len(dev->pdev, 1));
2156 if (!fb)
2157 return -ENOMEM;
2158
2159 /* Sequencer and refresh off */
2160 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2161 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2162
2163 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2164 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2165 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2166 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2167
2168 for (i = 0; i < 4; i++)
2169 poke_fb(dev, fb, 4 * i, patt);
2170
2171 poke_fb(dev, fb, 0x400000, patt + 1);
2172
2173 if (peek_fb(dev, fb, 0) == patt + 1) {
2174 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2175 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2176 bios_md32(bios, NV04_PFB_DEBUG_0,
2177 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2178
2179 for (i = 0; i < 4; i++)
2180 poke_fb(dev, fb, 4 * i, patt);
2181
2182 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2183 bios_md32(bios, NV04_PFB_BOOT_0,
2184 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2185 NV04_PFB_BOOT_0_RAM_AMOUNT,
2186 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2187
2188 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2189 (patt & 0xffff0000)) {
2190 bios_md32(bios, NV04_PFB_BOOT_0,
2191 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2192 NV04_PFB_BOOT_0_RAM_AMOUNT,
2193 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2194
2195 } else if (peek_fb(dev, fb, 0) == patt) {
2196 if (read_back_fb(dev, fb, 0x800000, patt))
2197 bios_md32(bios, NV04_PFB_BOOT_0,
2198 NV04_PFB_BOOT_0_RAM_AMOUNT,
2199 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2200 else
2201 bios_md32(bios, NV04_PFB_BOOT_0,
2202 NV04_PFB_BOOT_0_RAM_AMOUNT,
2203 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2204
2205 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2206 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2207
2208 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2209 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2210 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2211
2212 }
2213
2214 /* Refresh on, sequencer on */
2215 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2216 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2217
2218 io_mapping_free(fb);
2219 return 0;
2220}
2221
2222static const uint8_t *
2223nv05_memory_config(struct nvbios *bios)
2224{
2225 /* Defaults for BIOSes lacking a memory config table */
2226 static const uint8_t default_config_tab[][2] = {
2227 { 0x24, 0x00 },
2228 { 0x28, 0x00 },
2229 { 0x24, 0x01 },
2230 { 0x1f, 0x00 },
2231 { 0x0f, 0x00 },
2232 { 0x17, 0x00 },
2233 { 0x06, 0x00 },
2234 { 0x00, 0x00 }
2235 };
2236 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2237 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2238
2239 if (bios->legacy.mem_init_tbl_ptr)
2240 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2241 else
2242 return default_config_tab[i];
2243}
2244
2245static int
2246nv05_init_compute_mem(struct nvbios *bios)
2247{
2248 struct drm_device *dev = bios->dev;
2249 const uint8_t *ramcfg = nv05_memory_config(bios);
2250 uint32_t patt = 0xdeadbeef;
2251 struct io_mapping *fb;
2252 int i, v;
2253
2254 /* Map the framebuffer aperture */
2255 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2256 pci_resource_len(dev->pdev, 1));
2257 if (!fb)
2258 return -ENOMEM;
2259
2260 /* Sequencer off */
2261 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2262
2263 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2264 goto out;
2265
2266 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2267
2268 /* If present load the hardcoded scrambling table */
2269 if (bios->legacy.mem_init_tbl_ptr) {
2270 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2271 bios->legacy.mem_init_tbl_ptr + 0x10];
2272
2273 for (i = 0; i < 8; i++)
2274 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2275 ROM32(scramble_tab[i]));
2276 }
2277
2278 /* Set memory type/width/length defaults depending on the straps */
2279 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2280
2281 if (ramcfg[1] & 0x80)
2282 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2283
2284 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2285 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2286
2287 /* Probe memory bus width */
2288 for (i = 0; i < 4; i++)
2289 poke_fb(dev, fb, 4 * i, patt);
2290
2291 if (peek_fb(dev, fb, 0xc) != patt)
2292 bios_md32(bios, NV04_PFB_BOOT_0,
2293 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2294
2295 /* Probe memory length */
2296 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2297
2298 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2299 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2300 !read_back_fb(dev, fb, 0, ++patt)))
2301 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2302 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2303
2304 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2305 !read_back_fb(dev, fb, 0x800000, ++patt))
2306 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2307 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2308
2309 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2310 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2311 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2312
2313out:
2314 /* Sequencer on */
2315 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2316
2317 io_mapping_free(fb);
2318 return 0;
2319}
2320
2321static int
2322nv10_init_compute_mem(struct nvbios *bios)
2323{
2324 struct drm_device *dev = bios->dev;
2325 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2326 const int mem_width[] = { 0x10, 0x00, 0x20 };
2327 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2328 uint32_t patt = 0xdeadbeef;
2329 struct io_mapping *fb;
2330 int i, j, k;
2331
2332 /* Map the framebuffer aperture */
2333 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2334 pci_resource_len(dev->pdev, 1));
2335 if (!fb)
2336 return -ENOMEM;
2337
2338 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2339
2340 /* Probe memory bus width */
2341 for (i = 0; i < mem_width_count; i++) {
2342 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2343
2344 for (j = 0; j < 4; j++) {
2345 for (k = 0; k < 4; k++)
2346 poke_fb(dev, fb, 0x1c, 0);
2347
2348 poke_fb(dev, fb, 0x1c, patt);
2349 poke_fb(dev, fb, 0x3c, 0);
2350
2351 if (peek_fb(dev, fb, 0x1c) == patt)
2352 goto mem_width_found;
2353 }
2354 }
2355
2356mem_width_found:
2357 patt <<= 1;
2358
2359 /* Probe amount of installed memory */
2360 for (i = 0; i < 4; i++) {
2361 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2362
2363 poke_fb(dev, fb, off, patt);
2364 poke_fb(dev, fb, 0, 0);
2365
2366 peek_fb(dev, fb, 0);
2367 peek_fb(dev, fb, 0);
2368 peek_fb(dev, fb, 0);
2369 peek_fb(dev, fb, 0);
2370
2371 if (peek_fb(dev, fb, off) == patt)
2372 goto amount_found;
2373 }
2374
2375 /* IC missing - disable the upper half memory space. */
2376 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2377
2378amount_found:
2379 io_mapping_free(fb);
2380 return 0;
2381}
2382
2383static int
2384nv20_init_compute_mem(struct nvbios *bios)
2385{
2386 struct drm_device *dev = bios->dev;
2387 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2388 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2389 uint32_t amount, off;
2390 struct io_mapping *fb;
2391
2392 /* Map the framebuffer aperture */
2393 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2394 pci_resource_len(dev->pdev, 1));
2395 if (!fb)
2396 return -ENOMEM;
2397
2398 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2399
2400 /* Allow full addressing */
2401 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2402
2403 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2404 for (off = amount; off > 0x2000000; off -= 0x2000000)
2405 poke_fb(dev, fb, off - 4, off);
2406
2407 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2408 if (amount != peek_fb(dev, fb, amount - 4))
2409 /* IC missing - disable the upper half memory space. */
2410 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2411
2412 io_mapping_free(fb);
2413 return 0;
2414}
2415
37383650 2416static int
6ee73861
BS		 2417init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2418{
2419 /*
2420 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2421 *
2422 * offset (8 bit): opcode
2423 *
67eda20e
FJ		 2424 * This opcode is meant to set the PFB memory config registers
2425 * appropriately so that we can correctly calculate how much VRAM it
2426 * has (on nv10 and better chipsets the amount of installed VRAM is
2427 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
6ee73861 2428 *
67eda20e
FJ		 2429 * The implementation of this opcode in general consists of several
2430 * parts:
6ee73861 2431 *
67eda20e
FJ		 2432 * 1) Determination of memory type and density. Only necessary for
2433 * really old chipsets, the memory type reported by the strap bits
2434 * (0x101000) is assumed to be accurate on nv05 and newer.
6ee73861 2435 *
67eda20e
FJ		 2436 * 2) Determination of the memory bus width. Usually done by a cunning
2437 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2438 * seeing whether the written values are read back correctly.
6ee73861 2439 *
67eda20e
FJ		 2440 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2441 * trust the straps.
6ee73861 2442 *
67eda20e
FJ		 2443 * 3) Determination of how many of the card's RAM pads have ICs
2444 * attached, usually done by a cunning combination of writes to an
2445 * offset slightly less than the maximum memory reported by
2446 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
6ee73861 2447 *
67eda20e
FJ		 2448 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2449 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2450 * card show nothing being done for this opcode. Why is it still listed
2451 * in the table?!
6ee73861
BS		 2452 */
2453
2454 /* no iexec->execute check by design */
2455
6ee73861 2456 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
67eda20e 2457 int ret;
6ee73861 2458
67eda20e
FJ		 2459 if (dev_priv->chipset >= 0x40 ||
2460 dev_priv->chipset == 0x1a ||
2461 dev_priv->chipset == 0x1f)
2462 ret = 0;
2463 else if (dev_priv->chipset >= 0x20 &&
2464 dev_priv->chipset != 0x34)
2465 ret = nv20_init_compute_mem(bios);
2466 else if (dev_priv->chipset >= 0x10)
2467 ret = nv10_init_compute_mem(bios);
2468 else if (dev_priv->chipset >= 0x5)
2469 ret = nv05_init_compute_mem(bios);
2470 else
2471 ret = nv04_init_compute_mem(bios);
6ee73861 2472
67eda20e
FJ		 2473 if (ret)
2474 return ret;
6ee73861 2475
37383650 2476 return 1;
6ee73861
BS		 2477}
2478
37383650 2479static int
6ee73861
BS		 2480init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2481{
2482 /*
2483 * INIT_RESET opcode: 0x65 ('e')
2484 *
2485 * offset (8 bit): opcode
2486 * offset + 1 (32 bit): register
2487 * offset + 5 (32 bit): value1
2488 * offset + 9 (32 bit): value2
2489 *
2490 * Assign "value1" to "register", then assign "value2" to "register"
2491 */
2492
2493 uint32_t reg = ROM32(bios->data[offset + 1]);
2494 uint32_t value1 = ROM32(bios->data[offset + 5]);
2495 uint32_t value2 = ROM32(bios->data[offset + 9]);
2496 uint32_t pci_nv_19, pci_nv_20;
2497
2498 /* no iexec->execute check by design */
2499
2500 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
190a4378
FJ		 2501 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2502
6ee73861
BS		 2503 bios_wr32(bios, reg, value1);
2504
2505 udelay(10);
2506
2507 bios_wr32(bios, reg, value2);
2508 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2509
2510 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2511 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2512 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2513
37383650 2514 return 13;
6ee73861
BS		 2515}
2516
37383650 2517static int
6ee73861
BS		 2518init_configure_mem(struct nvbios *bios, uint16_t offset,
2519 struct init_exec *iexec)
2520{
2521 /*
2522 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2523 *
2524 * offset (8 bit): opcode
2525 *
2526 * Equivalent to INIT_DONE on bios version 3 or greater.
2527 * For early bios versions, sets up the memory registers, using values
2528 * taken from the memory init table
2529 */
2530
2531 /* no iexec->execute check by design */
2532
2533 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2534 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2535 uint32_t reg, data;
2536
2537 if (bios->major_version > 2)
ae55321c 2538 return 0;
6ee73861
BS		 2539
2540 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2541 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2542
2543 if (bios->data[meminitoffs] & 1)
2544 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2545
2546 for (reg = ROM32(bios->data[seqtbloffs]);
2547 reg != 0xffffffff;
2548 reg = ROM32(bios->data[seqtbloffs += 4])) {
2549
2550 switch (reg) {
3c7066bc
FJ		 2551 case NV04_PFB_PRE:
2552 data = NV04_PFB_PRE_CMD_PRECHARGE;
6ee73861 2553 break;
3c7066bc
FJ		 2554 case NV04_PFB_PAD:
2555 data = NV04_PFB_PAD_CKE_NORMAL;
6ee73861 2556 break;
3c7066bc
FJ		 2557 case NV04_PFB_REF:
2558 data = NV04_PFB_REF_CMD_REFRESH;
6ee73861
BS		 2559 break;
2560 default:
2561 data = ROM32(bios->data[meminitdata]);
2562 meminitdata += 4;
2563 if (data == 0xffffffff)
2564 continue;
2565 }
2566
2567 bios_wr32(bios, reg, data);
2568 }
2569
37383650 2570 return 1;
6ee73861
BS		 2571}
2572
37383650 2573static int
6ee73861
BS		 2574init_configure_clk(struct nvbios *bios, uint16_t offset,
2575 struct init_exec *iexec)
2576{
2577 /*
2578 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2579 *
2580 * offset (8 bit): opcode
2581 *
2582 * Equivalent to INIT_DONE on bios version 3 or greater.
2583 * For early bios versions, sets up the NVClk and MClk PLLs, using
2584 * values taken from the memory init table
2585 */
2586
2587 /* no iexec->execute check by design */
2588
2589 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2590 int clock;
2591
2592 if (bios->major_version > 2)
ae55321c 2593 return 0;
6ee73861
BS		 2594
2595 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2596 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2597
2598 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2599 if (bios->data[meminitoffs] & 1) /* DDR */
2600 clock *= 2;
2601 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2602
37383650 2603 return 1;
6ee73861
BS		 2604}
2605
37383650 2606static int
6ee73861
BS		 2607init_configure_preinit(struct nvbios *bios, uint16_t offset,
2608 struct init_exec *iexec)
2609{
2610 /*
2611 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2612 *
2613 * offset (8 bit): opcode
2614 *
2615 * Equivalent to INIT_DONE on bios version 3 or greater.
2616 * For early bios versions, does early init, loading ram and crystal
2617 * configuration from straps into CR3C
2618 */
2619
2620 /* no iexec->execute check by design */
2621
2622 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
3c9b2534 2623 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
6ee73861
BS		 2624
2625 if (bios->major_version > 2)
ae55321c 2626 return 0;
6ee73861
BS		 2627
2628 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2629 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2630
37383650 2631 return 1;
6ee73861
BS		 2632}
2633
37383650 2634static int
6ee73861
BS		 2635init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2636{
2637 /*
2638 * INIT_IO opcode: 0x69 ('i')
2639 *
2640 * offset (8 bit): opcode
2641 * offset + 1 (16 bit): CRTC port
2642 * offset + 3 (8 bit): mask
2643 * offset + 4 (8 bit): data
2644 *
2645 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2646 */
2647
2648 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2649 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2650 uint8_t mask = bios->data[offset + 3];
2651 uint8_t data = bios->data[offset + 4];
2652
2653 if (!iexec->execute)
37383650 2654 return 5;
6ee73861
BS		 2655
2656 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2657 offset, crtcport, mask, data);
2658
2659 /*
2660 * I have no idea what this does, but NVIDIA do this magic sequence
2661 * in the places where this INIT_IO happens..
2662 */
2663 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2664 int i;
2665
2666 bios_wr32(bios, 0x614100, (bios_rd32(
2667 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2668
2669 bios_wr32(bios, 0x00e18c, bios_rd32(
2670 bios, 0x00e18c) | 0x00020000);
2671
2672 bios_wr32(bios, 0x614900, (bios_rd32(
2673 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2674
2675 bios_wr32(bios, 0x000200, bios_rd32(
2676 bios, 0x000200) & ~0x40000000);
2677
2678 mdelay(10);
2679
2680 bios_wr32(bios, 0x00e18c, bios_rd32(
2681 bios, 0x00e18c) & ~0x00020000);
2682
2683 bios_wr32(bios, 0x000200, bios_rd32(
2684 bios, 0x000200) | 0x40000000);
2685
2686 bios_wr32(bios, 0x614100, 0x00800018);
2687 bios_wr32(bios, 0x614900, 0x00800018);
2688
2689 mdelay(10);
2690
2691 bios_wr32(bios, 0x614100, 0x10000018);
2692 bios_wr32(bios, 0x614900, 0x10000018);
2693
2694 for (i = 0; i < 3; i++)
2695 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2696 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2697
2698 for (i = 0; i < 2; i++)
2699 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2700 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2701
2702 for (i = 0; i < 3; i++)
2703 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2704 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2705
2706 for (i = 0; i < 2; i++)
2707 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2708 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2709
2710 for (i = 0; i < 2; i++)
2711 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2712 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2713 return 5;
6ee73861
BS		 2714 }
2715
2716 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2717 data);
37383650 2718 return 5;
6ee73861
BS		 2719}
2720
37383650 2721static int
6ee73861
BS		 2722init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2723{
2724 /*
2725 * INIT_SUB opcode: 0x6B ('k')
2726 *
2727 * offset (8 bit): opcode
2728 * offset + 1 (8 bit): script number
2729 *
2730 * Execute script number "script number", as a subroutine
2731 */
2732
2733 uint8_t sub = bios->data[offset + 1];
2734
2735 if (!iexec->execute)
37383650 2736 return 2;
6ee73861
BS		 2737
2738 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2739
2740 parse_init_table(bios,
2741 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2742 iexec);
2743
2744 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2745
37383650 2746 return 2;
6ee73861
BS		 2747}
2748
37383650 2749static int
6ee73861
BS		 2750init_ram_condition(struct nvbios *bios, uint16_t offset,
2751 struct init_exec *iexec)
2752{
2753 /*
2754 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2755 *
2756 * offset (8 bit): opcode
2757 * offset + 1 (8 bit): mask
2758 * offset + 2 (8 bit): cmpval
2759 *
3c7066bc 2760 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
6ee73861
BS		 2761 * If condition not met skip subsequent opcodes until condition is
2762 * inverted (INIT_NOT), or we hit INIT_RESUME
2763 */
2764
2765 uint8_t mask = bios->data[offset + 1];
2766 uint8_t cmpval = bios->data[offset + 2];
2767 uint8_t data;
2768
2769 if (!iexec->execute)
37383650 2770 return 3;
6ee73861 2771
3c7066bc 2772 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
6ee73861
BS		 2773
2774 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2775 offset, data, cmpval);
2776
2777 if (data == cmpval)
2778 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2779 else {
2780 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2781 iexec->execute = false;
2782 }
2783
37383650 2784 return 3;
6ee73861
BS		 2785}
2786
37383650 2787static int
6ee73861
BS		 2788init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2789{
2790 /*
2791 * INIT_NV_REG opcode: 0x6E ('n')
2792 *
2793 * offset (8 bit): opcode
2794 * offset + 1 (32 bit): register
2795 * offset + 5 (32 bit): mask
2796 * offset + 9 (32 bit): data
2797 *
2798 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2799 */
2800
2801 uint32_t reg = ROM32(bios->data[offset + 1]);
2802 uint32_t mask = ROM32(bios->data[offset + 5]);
2803 uint32_t data = ROM32(bios->data[offset + 9]);
2804
2805 if (!iexec->execute)
37383650 2806 return 13;
6ee73861
BS		 2807
2808 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2809 offset, reg, mask, data);
2810
2811 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2812
37383650 2813 return 13;
6ee73861
BS		 2814}
2815
37383650 2816static int
6ee73861
BS		 2817init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2818{
2819 /*
2820 * INIT_MACRO opcode: 0x6F ('o')
2821 *
2822 * offset (8 bit): opcode
2823 * offset + 1 (8 bit): macro number
2824 *
2825 * Look up macro index "macro number" in the macro index table.
2826 * The macro index table entry has 1 byte for the index in the macro
2827 * table, and 1 byte for the number of times to repeat the macro.
2828 * The macro table entry has 4 bytes for the register address and
2829 * 4 bytes for the value to write to that register
2830 */
2831
2832 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2833 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2834 uint8_t macro_tbl_idx = bios->data[tmp];
2835 uint8_t count = bios->data[tmp + 1];
2836 uint32_t reg, data;
2837 int i;
2838
2839 if (!iexec->execute)
37383650 2840 return 2;
6ee73861
BS		 2841
2842 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2843 "Count: 0x%02X\n",
2844 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2845
2846 for (i = 0; i < count; i++) {
2847 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2848
2849 reg = ROM32(bios->data[macroentryptr]);
2850 data = ROM32(bios->data[macroentryptr + 4]);
2851
2852 bios_wr32(bios, reg, data);
2853 }
2854
37383650 2855 return 2;
6ee73861
BS		 2856}
2857
37383650 2858static int
6ee73861
BS		 2859init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2860{
2861 /*
2862 * INIT_DONE opcode: 0x71 ('q')
2863 *
2864 * offset (8 bit): opcode
2865 *
2866 * End the current script
2867 */
2868
2869 /* mild retval abuse to stop parsing this table */
37383650 2870 return 0;
6ee73861
BS		 2871}
2872
37383650 2873static int
6ee73861
BS		 2874init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2875{
2876 /*
2877 * INIT_RESUME opcode: 0x72 ('r')
2878 *
2879 * offset (8 bit): opcode
2880 *
2881 * End the current execute / no-execute condition
2882 */
2883
2884 if (iexec->execute)
37383650 2885 return 1;
6ee73861
BS		 2886
2887 iexec->execute = true;
2888 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2889
37383650 2890 return 1;
6ee73861
BS		 2891}
2892
37383650 2893static int
6ee73861
BS		 2894init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2895{
2896 /*
2897 * INIT_TIME opcode: 0x74 ('t')
2898 *
2899 * offset (8 bit): opcode
2900 * offset + 1 (16 bit): time
2901 *
2902 * Sleep for "time" microseconds.
2903 */
2904
2905 unsigned time = ROM16(bios->data[offset + 1]);
2906
2907 if (!iexec->execute)
37383650 2908 return 3;
6ee73861
BS		 2909
2910 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2911 offset, time);
2912
2913 if (time < 1000)
2914 udelay(time);
2915 else
2916 msleep((time + 900) / 1000);
2917
37383650 2918 return 3;
6ee73861
BS		 2919}
2920
37383650 2921static int
6ee73861
BS		 2922init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2923{
2924 /*
2925 * INIT_CONDITION opcode: 0x75 ('u')
2926 *
2927 * offset (8 bit): opcode
2928 * offset + 1 (8 bit): condition number
2929 *
2930 * Check condition "condition number" in the condition table.
2931 * If condition not met skip subsequent opcodes until condition is
2932 * inverted (INIT_NOT), or we hit INIT_RESUME
2933 */
2934
2935 uint8_t cond = bios->data[offset + 1];
2936
2937 if (!iexec->execute)
37383650 2938 return 2;
6ee73861
BS		 2939
2940 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2941
2942 if (bios_condition_met(bios, offset, cond))
2943 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2944 else {
2945 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2946 iexec->execute = false;
2947 }
2948
37383650 2949 return 2;
6ee73861
BS		 2950}
2951
37383650 2952static int
6ee73861
BS		 2953init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2954{
2955 /*
2956 * INIT_IO_CONDITION opcode: 0x76
2957 *
2958 * offset (8 bit): opcode
2959 * offset + 1 (8 bit): condition number
2960 *
2961 * Check condition "condition number" in the io condition table.
2962 * If condition not met skip subsequent opcodes until condition is
2963 * inverted (INIT_NOT), or we hit INIT_RESUME
2964 */
2965
2966 uint8_t cond = bios->data[offset + 1];
2967
2968 if (!iexec->execute)
37383650 2969 return 2;
6ee73861
BS		 2970
2971 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2972
2973 if (io_condition_met(bios, offset, cond))
2974 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2975 else {
2976 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2977 iexec->execute = false;
2978 }
2979
37383650 2980 return 2;
6ee73861
BS		 2981}
2982
37383650 2983static int
6ee73861
BS		 2984init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2985{
2986 /*
2987 * INIT_INDEX_IO opcode: 0x78 ('x')
2988 *
2989 * offset (8 bit): opcode
2990 * offset + 1 (16 bit): CRTC port
2991 * offset + 3 (8 bit): CRTC index
2992 * offset + 4 (8 bit): mask
2993 * offset + 5 (8 bit): data
2994 *
2995 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2996 * OR with "data", write-back
2997 */
2998
2999 uint16_t crtcport = ROM16(bios->data[offset + 1]);
3000 uint8_t crtcindex = bios->data[offset + 3];
3001 uint8_t mask = bios->data[offset + 4];
3002 uint8_t data = bios->data[offset + 5];
3003 uint8_t value;
3004
3005 if (!iexec->execute)
37383650 3006 return 6;
6ee73861
BS		 3007
3008 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3009 "Data: 0x%02X\n",
3010 offset, crtcport, crtcindex, mask, data);
3011
3012 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
3013 bios_idxprt_wr(bios, crtcport, crtcindex, value);
3014
37383650 3015 return 6;
6ee73861
BS		 3016}
3017
37383650 3018static int
6ee73861
BS		 3019init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3020{
3021 /*
3022 * INIT_PLL opcode: 0x79 ('y')
3023 *
3024 * offset (8 bit): opcode
3025 * offset + 1 (32 bit): register
3026 * offset + 5 (16 bit): freq
3027 *
3028 * Set PLL register "register" to coefficients for frequency (10kHz)
3029 * "freq"
3030 */
3031
3032 uint32_t reg = ROM32(bios->data[offset + 1]);
3033 uint16_t freq = ROM16(bios->data[offset + 5]);
3034
3035 if (!iexec->execute)
37383650 3036 return 7;
6ee73861
BS		 3037
3038 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3039
3040 setPLL(bios, reg, freq * 10);
3041
37383650 3042 return 7;
6ee73861
BS		 3043}
3044
37383650 3045static int
6ee73861
BS		 3046init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3047{
3048 /*
3049 * INIT_ZM_REG opcode: 0x7A ('z')
3050 *
3051 * offset (8 bit): opcode
3052 * offset + 1 (32 bit): register
3053 * offset + 5 (32 bit): value
3054 *
3055 * Assign "value" to "register"
3056 */
3057
3058 uint32_t reg = ROM32(bios->data[offset + 1]);
3059 uint32_t value = ROM32(bios->data[offset + 5]);
3060
3061 if (!iexec->execute)
37383650 3062 return 9;
6ee73861
BS		 3063
3064 if (reg == 0x000200)
3065 value |= 1;
3066
3067 bios_wr32(bios, reg, value);
3068
37383650 3069 return 9;
6ee73861
BS		 3070}
3071
37383650 3072static int
6ee73861
BS		 3073init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3074 struct init_exec *iexec)
3075{
3076 /*
3077 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3078 *
3079 * offset (8 bit): opcode
3080 * offset + 1 (8 bit): PLL type
3081 * offset + 2 (32 bit): frequency 0
3082 *
3083 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3084 * ram_restrict_table_ptr. The value read from there is used to select
3085 * a frequency from the table starting at 'frequency 0' to be
3086 * programmed into the PLL corresponding to 'type'.
3087 *
3088 * The PLL limits table on cards using this opcode has a mapping of
3089 * 'type' to the relevant registers.
3090 */
3091
3092 struct drm_device *dev = bios->dev;
3093 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3094 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3095 uint8_t type = bios->data[offset + 1];
3096 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3097 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 3098 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 3099 int i;
3100
3101 if (!iexec->execute)
37383650 3102 return len;
6ee73861
BS		 3103
3104 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3105 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 3106 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 3107 }
3108
3109 entry = pll_limits + pll_limits[1];
3110 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3111 if (entry[0] == type) {
3112 uint32_t reg = ROM32(entry[3]);
3113
3114 BIOSLOG(bios, "0x%04X: "
3115 "Type %02x Reg 0x%08x Freq %dKHz\n",
3116 offset, type, reg, freq);
3117
3118 setPLL(bios, reg, freq);
37383650 3119 return len;
6ee73861
BS		 3120 }
3121 }
3122
3123 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 3124 return len;
6ee73861
BS		 3125}
3126
37383650 3127static int
6ee73861
BS		 3128init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3129{
3130 /*
3131 * INIT_8C opcode: 0x8C ('')
3132 *
3133 * NOP so far....
3134 *
3135 */
3136
37383650 3137 return 1;
6ee73861
BS		 3138}
3139
37383650 3140static int
6ee73861
BS		 3141init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3142{
3143 /*
3144 * INIT_8D opcode: 0x8D ('')
3145 *
3146 * NOP so far....
3147 *
3148 */
3149
37383650 3150 return 1;
6ee73861
BS		 3151}
3152
37383650 3153static int
6ee73861
BS		 3154init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3155{
3156 /*
3157 * INIT_GPIO opcode: 0x8E ('')
3158 *
3159 * offset (8 bit): opcode
3160 *
3161 * Loop over all entries in the DCB GPIO table, and initialise
3162 * each GPIO according to various values listed in each entry
3163 */
3164
2535d71c 3165 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
ee2e0131 3166 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
6ee73861 3167 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
6ee73861
BS		 3168 int i;
3169
080feda5 3170 if (dev_priv->card_type < NV_50) {
2535d71c 3171 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
309b8c89 3172 return 1;
6ee73861
BS		 3173 }
3174
2535d71c
BS		 3175 if (!iexec->execute)
3176 return 1;
6ee73861 3177
2535d71c
BS		 3178 for (i = 0; i < bios->dcb.gpio.entries; i++) {
3179 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
3180 uint32_t r, s, v;
6ee73861 3181
2535d71c 3182 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 3183
73db4bed
BS		 3184 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
3185 offset, gpio->tag, gpio->state_default);
3186 if (bios->execute)
ee2e0131 3187 pgpio->set(bios->dev, gpio->tag, gpio->state_default);
6ee73861 3188
45284162
BS		 3189 /* The NVIDIA binary driver doesn't appear to actually do
3190 * any of this, my VBIOS does however.
3191 */
3192 /* Not a clue, needs de-magicing */
2535d71c
BS		 3193 r = nv50_gpio_ctl[gpio->line >> 4];
3194 s = (gpio->line & 0x0f);
6ee73861 3195 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2535d71c 3196 switch ((gpio->entry & 0x06000000) >> 25) {
6ee73861
BS		 3197 case 1:
3198 v |= (0x00000001 << s);
3199 break;
3200 case 2:
3201 v |= (0x00010000 << s);
3202 break;
3203 default:
3204 break;
3205 }
3206 bios_wr32(bios, r, v);
3207 }
3208
37383650 3209 return 1;
6ee73861
BS		 3210}
3211
37383650 3212static int
6ee73861
BS		 3213init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3214 struct init_exec *iexec)
3215{
3216 /*
3217 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3218 *
3219 * offset (8 bit): opcode
3220 * offset + 1 (32 bit): reg
3221 * offset + 5 (8 bit): regincrement
3222 * offset + 6 (8 bit): count
3223 * offset + 7 (32 bit): value 1,1
3224 * ...
3225 *
3226 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3227 * ram_restrict_table_ptr. The value read from here is 'n', and
3228 * "value 1,n" gets written to "reg". This repeats "count" times and on
3229 * each iteration 'm', "reg" increases by "regincrement" and
3230 * "value m,n" is used. The extent of n is limited by a number read
3231 * from the 'M' BIT table, herein called "blocklen"
3232 */
3233
3234 uint32_t reg = ROM32(bios->data[offset + 1]);
3235 uint8_t regincrement = bios->data[offset + 5];
3236 uint8_t count = bios->data[offset + 6];
3237 uint32_t strap_ramcfg, data;
37383650
MK		 3238 /* previously set by 'M' BIT table */
3239 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3240 int len = 7 + count * blocklen;
6ee73861
BS		 3241 uint8_t index;
3242 int i;
3243
309b8c89 3244 /* critical! to know the length of the opcode */;
6ee73861
BS		 3245 if (!blocklen) {
3246 NV_ERROR(bios->dev,
3247 "0x%04X: Zero block length - has the M table "
3248 "been parsed?\n", offset);
9170a824 3249 return -EINVAL;
6ee73861
BS		 3250 }
3251
309b8c89
BS		 3252 if (!iexec->execute)
3253 return len;
3254
6ee73861
BS		 3255 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3256 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3257
3258 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3259 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3260 offset, reg, regincrement, count, strap_ramcfg, index);
3261
3262 for (i = 0; i < count; i++) {
3263 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3264
3265 bios_wr32(bios, reg, data);
3266
3267 reg += regincrement;
3268 }
3269
37383650 3270 return len;
6ee73861
BS		 3271}
3272
37383650 3273static int
6ee73861
BS		 3274init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3275{
3276 /*
3277 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3278 *
3279 * offset (8 bit): opcode
3280 * offset + 1 (32 bit): src reg
3281 * offset + 5 (32 bit): dst reg
3282 *
3283 * Put contents of "src reg" into "dst reg"
3284 */
3285
3286 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3287 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3288
3289 if (!iexec->execute)
37383650 3290 return 9;
6ee73861
BS		 3291
3292 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3293
37383650 3294 return 9;
6ee73861
BS		 3295}
3296
37383650 3297static int
6ee73861
BS		 3298init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3299 struct init_exec *iexec)
3300{
3301 /*
3302 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3303 *
3304 * offset (8 bit): opcode
3305 * offset + 1 (32 bit): dst reg
3306 * offset + 5 (8 bit): count
3307 * offset + 6 (32 bit): data 1
3308 * ...
3309 *
3310 * For each of "count" values write "data n" to "dst reg"
3311 */
3312
3313 uint32_t reg = ROM32(bios->data[offset + 1]);
3314 uint8_t count = bios->data[offset + 5];
37383650 3315 int len = 6 + count * 4;
6ee73861
BS		 3316 int i;
3317
3318 if (!iexec->execute)
37383650 3319 return len;
6ee73861
BS		 3320
3321 for (i = 0; i < count; i++) {
3322 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3323 bios_wr32(bios, reg, data);
3324 }
3325
37383650 3326 return len;
6ee73861
BS		 3327}
3328
37383650 3329static int
6ee73861
BS		 3330init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3331{
3332 /*
3333 * INIT_RESERVED opcode: 0x92 ('')
3334 *
3335 * offset (8 bit): opcode
3336 *
3337 * Seemingly does nothing
3338 */
3339
37383650 3340 return 1;
6ee73861
BS		 3341}
3342
37383650 3343static int
6ee73861
BS		 3344init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3345{
3346 /*
3347 * INIT_96 opcode: 0x96 ('')
3348 *
3349 * offset (8 bit): opcode
3350 * offset + 1 (32 bit): sreg
3351 * offset + 5 (8 bit): sshift
3352 * offset + 6 (8 bit): smask
3353 * offset + 7 (8 bit): index
3354 * offset + 8 (32 bit): reg
3355 * offset + 12 (32 bit): mask
3356 * offset + 16 (8 bit): shift
3357 *
3358 */
3359
3360 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3361 uint32_t reg = ROM32(bios->data[offset + 8]);
3362 uint32_t mask = ROM32(bios->data[offset + 12]);
3363 uint32_t val;
3364
3365 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3366 if (bios->data[offset + 5] < 0x80)
3367 val >>= bios->data[offset + 5];
3368 else
3369 val <<= (0x100 - bios->data[offset + 5]);
3370 val &= bios->data[offset + 6];
3371
3372 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3373 val <<= bios->data[offset + 16];
3374
3375 if (!iexec->execute)
37383650 3376 return 17;
6ee73861
BS		 3377
3378 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3379 return 17;
6ee73861
BS		 3380}
3381
37383650 3382static int
6ee73861
BS		 3383init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3384{
3385 /*
3386 * INIT_97 opcode: 0x97 ('')
3387 *
3388 * offset (8 bit): opcode
3389 * offset + 1 (32 bit): register
3390 * offset + 5 (32 bit): mask
3391 * offset + 9 (32 bit): value
3392 *
3393 * Adds "value" to "register" preserving the fields specified
3394 * by "mask"
3395 */
3396
3397 uint32_t reg = ROM32(bios->data[offset + 1]);
3398 uint32_t mask = ROM32(bios->data[offset + 5]);
3399 uint32_t add = ROM32(bios->data[offset + 9]);
3400 uint32_t val;
3401
3402 val = bios_rd32(bios, reg);
3403 val = (val & mask) | ((val + add) & ~mask);
3404
3405 if (!iexec->execute)
37383650 3406 return 13;
6ee73861
BS		 3407
3408 bios_wr32(bios, reg, val);
37383650 3409 return 13;
6ee73861
BS		 3410}
3411
37383650 3412static int
6ee73861
BS		 3413init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3414{
3415 /*
3416 * INIT_AUXCH opcode: 0x98 ('')
3417 *
3418 * offset (8 bit): opcode
3419 * offset + 1 (32 bit): address
3420 * offset + 5 (8 bit): count
3421 * offset + 6 (8 bit): mask 0
3422 * offset + 7 (8 bit): data 0
3423 * ...
3424 *
3425 */
3426
3427 struct drm_device *dev = bios->dev;
3428 struct nouveau_i2c_chan *auxch;
3429 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3430 uint8_t count = bios->data[offset + 5];
3431 int len = 6 + count * 2;
6ee73861
BS		 3432 int ret, i;
3433
3434 if (!bios->display.output) {
3435 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
309b8c89 3436 return len;
6ee73861
BS		 3437 }
3438
3439 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3440 if (!auxch) {
3441 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3442 bios->display.output->i2c_index);
309b8c89 3443 return len;
6ee73861
BS		 3444 }
3445
3446 if (!iexec->execute)
37383650 3447 return len;
6ee73861
BS		 3448
3449 offset += 6;
37383650 3450 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3451 uint8_t data;
3452
3453 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3454 if (ret) {
3455 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
309b8c89 3456 return len;
6ee73861
BS		 3457 }
3458
3459 data &= bios->data[offset + 0];
3460 data |= bios->data[offset + 1];
3461
3462 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3463 if (ret) {
3464 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3465 return len;
6ee73861
BS		 3466 }
3467 }
3468
37383650 3469 return len;
6ee73861
BS		 3470}
3471
37383650 3472static int
6ee73861
BS		 3473init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3474{
3475 /*
3476 * INIT_ZM_AUXCH opcode: 0x99 ('')
3477 *
3478 * offset (8 bit): opcode
3479 * offset + 1 (32 bit): address
3480 * offset + 5 (8 bit): count
3481 * offset + 6 (8 bit): data 0
3482 * ...
3483 *
3484 */
3485
3486 struct drm_device *dev = bios->dev;
3487 struct nouveau_i2c_chan *auxch;
3488 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3489 uint8_t count = bios->data[offset + 5];
3490 int len = 6 + count;
6ee73861
BS		 3491 int ret, i;
3492
3493 if (!bios->display.output) {
3494 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
309b8c89 3495 return len;
6ee73861
BS		 3496 }
3497
3498 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3499 if (!auxch) {
3500 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3501 bios->display.output->i2c_index);
309b8c89 3502 return len;
6ee73861
BS		 3503 }
3504
3505 if (!iexec->execute)
37383650 3506 return len;
6ee73861
BS		 3507
3508 offset += 6;
37383650 3509 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3510 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3511 if (ret) {
3512 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3513 return len;
6ee73861
BS		 3514 }
3515 }
3516
37383650 3517 return len;
6ee73861
BS		 3518}
3519
3520static struct init_tbl_entry itbl_entry[] = {
3521 /* command name , id , length , offset , mult , command handler */
3522 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3523 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3524 { "INIT_REPEAT" , 0x33, init_repeat },
3525 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3526 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3527 { "INIT_COPY" , 0x37, init_copy },
3528 { "INIT_NOT" , 0x38, init_not },
3529 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3530 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3531 { "INIT_OP_3B" , 0x3B, init_op_3b },
3532 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3533 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3534 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3535 { "INIT_PLL2" , 0x4B, init_pll2 },
3536 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3537 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3538 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3539 { "INIT_TMDS" , 0x4F, init_tmds },
3540 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3541 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3542 { "INIT_CR" , 0x52, init_cr },
3543 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3544 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3545 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
e3a1924f 3546 { "INIT_LTIME" , 0x57, init_ltime },
37383650 3547 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3548 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650
MK		 3549 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3550 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3551 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3552 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3553 { "INIT_RESET" , 0x65, init_reset },
3554 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3555 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3556 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3557 { "INIT_IO" , 0x69, init_io },
3558 { "INIT_SUB" , 0x6B, init_sub },
3559 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3560 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3561 { "INIT_MACRO" , 0x6F, init_macro },
3562 { "INIT_DONE" , 0x71, init_done },
3563 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3564 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3565 { "INIT_TIME" , 0x74, init_time },
3566 { "INIT_CONDITION" , 0x75, init_condition },
3567 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3568 { "INIT_INDEX_IO" , 0x78, init_index_io },
3569 { "INIT_PLL" , 0x79, init_pll },
3570 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3571 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3572 { "INIT_8C" , 0x8C, init_8c },
3573 { "INIT_8D" , 0x8D, init_8d },
3574 { "INIT_GPIO" , 0x8E, init_gpio },
3575 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3576 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3577 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3578 { "INIT_RESERVED" , 0x92, init_reserved },
3579 { "INIT_96" , 0x96, init_96 },
3580 { "INIT_97" , 0x97, init_97 },
3581 { "INIT_AUXCH" , 0x98, init_auxch },
3582 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3583 { NULL , 0 , NULL }
6ee73861
BS		 3584};
3585
6ee73861
BS		 3586#define MAX_TABLE_OPS 1000
3587
3588static int
3589parse_init_table(struct nvbios *bios, unsigned int offset,
3590 struct init_exec *iexec)
3591{
3592 /*
3593 * Parses all commands in an init table.
3594 *
3595 * We start out executing all commands found in the init table. Some
3596 * opcodes may change the status of iexec->execute to SKIP, which will
3597 * cause the following opcodes to perform no operation until the value
3598 * is changed back to EXECUTE.
3599 */
3600
92b96187 3601 int count = 0, i, ret;
6ee73861
BS		 3602 uint8_t id;
3603
3604 /*
3605 * Loop until INIT_DONE causes us to break out of the loop
3606 * (or until offset > bios length just in case... )
3607 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3608 */
3609 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3610 id = bios->data[offset];
3611
3612 /* Find matching id in itbl_entry */
3613 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3614 ;
3615
92b96187 3616 if (!itbl_entry[i].name) {
6ee73861
BS		 3617 NV_ERROR(bios->dev,
3618 "0x%04X: Init table command not found: "
3619 "0x%02X\n", offset, id);
3620 return -ENOENT;
3621 }
92b96187
BS		 3622
3623 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3624 itbl_entry[i].id, itbl_entry[i].name);
3625
3626 /* execute eventual command handler */
3627 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3628 if (ret < 0) {
3629 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3630 "table opcode: %s %d\n", offset,
3631 itbl_entry[i].name, ret);
3632 }
3633
3634 if (ret <= 0)
3635 break;
3636
3637 /*
3638 * Add the offset of the current command including all data
3639 * of that command. The offset will then be pointing on the
3640 * next op code.
3641 */
3642 offset += ret;
6ee73861
BS		 3643 }
3644
3645 if (offset >= bios->length)
3646 NV_WARN(bios->dev,
3647 "Offset 0x%04X greater than known bios image length. "
3648 "Corrupt image?\n", offset);
3649 if (count >= MAX_TABLE_OPS)
3650 NV_WARN(bios->dev,
3651 "More than %d opcodes to a table is unlikely, "
3652 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3653
3654 return 0;
3655}
3656
3657static void
3658parse_init_tables(struct nvbios *bios)
3659{
3660 /* Loops and calls parse_init_table() for each present table. */
3661
3662 int i = 0;
3663 uint16_t table;
3664 struct init_exec iexec = {true, false};
3665
3666 if (bios->old_style_init) {
3667 if (bios->init_script_tbls_ptr)
3668 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3669 if (bios->extra_init_script_tbl_ptr)
3670 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3671
3672 return;
3673 }
3674
3675 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3676 NV_INFO(bios->dev,
3677 "Parsing VBIOS init table %d at offset 0x%04X\n",
3678 i / 2, table);
3679 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3680
3681 parse_init_table(bios, table, &iexec);
3682 i += 2;
3683 }
3684}
3685
3686static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3687{
3688 int compare_record_len, i = 0;
3689 uint16_t compareclk, scriptptr = 0;
3690
3691 if (bios->major_version < 5) /* pre BIT */
3692 compare_record_len = 3;
3693 else
3694 compare_record_len = 4;
3695
3696 do {
3697 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3698 if (pxclk >= compareclk * 10) {
3699 if (bios->major_version < 5) {
3700 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3701 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3702 } else
3703 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3704 break;
3705 }
3706 i++;
3707 } while (compareclk);
3708
3709 return scriptptr;
3710}
3711
3712static void
3713run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3714 struct dcb_entry *dcbent, int head, bool dl)
3715{
3716 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3717 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3718 struct init_exec iexec = {true, false};
3719
3720 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3721 scriptptr);
3722 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3723 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3724 /* note: if dcb entries have been merged, index may be misleading */
3725 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3726 parse_init_table(bios, scriptptr, &iexec);
3727
3728 nv04_dfp_bind_head(dev, dcbent, head, dl);
3729}
3730
3731static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3732{
3733 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3734 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3735 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3736 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3737
3738 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3739 return -EINVAL;
3740
3741 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3742
3743 if (script == LVDS_PANEL_OFF) {
3744 /* off-on delay in ms */
3745 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3746 }
3747#ifdef __powerpc__
3748 /* Powerbook specific quirks */
3d9aefb8
FJ		 3749 if ((dev->pci_device & 0xffff) == 0x0179 ||
3750 (dev->pci_device & 0xffff) == 0x0189 ||
3751 (dev->pci_device & 0xffff) == 0x0329) {
3752 if (script == LVDS_RESET) {
3753 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3754
3755 } else if (script == LVDS_PANEL_ON) {
3756 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3757 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3758 | (1 << 31));
3759 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3760 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3761
3762 } else if (script == LVDS_PANEL_OFF) {
3763 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3764 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3765 & ~(1 << 31));
3766 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3767 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
6ee73861
BS		 3768 }
3769 }
3770#endif
3771
3772 return 0;
3773}
3774
3775static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3776{
3777 /*
3778 * The BIT LVDS table's header has the information to setup the
3779 * necessary registers. Following the standard 4 byte header are:
3780 * A bitmask byte and a dual-link transition pxclk value for use in
3781 * selecting the init script when not using straps; 4 script pointers
3782 * for panel power, selected by output and on/off; and 8 table pointers
3783 * for panel init, the needed one determined by output, and bits in the
3784 * conf byte. These tables are similar to the TMDS tables, consisting
3785 * of a list of pxclks and script pointers.
3786 */
3787 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3788 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3789 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3790 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3791
3792 /*
3793 * For now we assume version 3.0 table - g80 support will need some
3794 * changes
3795 */
3796
3797 switch (script) {
3798 case LVDS_INIT:
3799 return -ENOSYS;
3800 case LVDS_BACKLIGHT_ON:
3801 case LVDS_PANEL_ON:
3802 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3803 break;
3804 case LVDS_BACKLIGHT_OFF:
3805 case LVDS_PANEL_OFF:
3806 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3807 break;
3808 case LVDS_RESET:
f3bbb9cc
BS		 3809 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3810 if (dcbent->or == 4)
3811 clktable += 8;
3812
6ee73861
BS		 3813 if (dcbent->lvdsconf.use_straps_for_mode) {
3814 if (bios->fp.dual_link)
f3bbb9cc
BS		 3815 clktable += 4;
3816 if (bios->fp.if_is_24bit)
3817 clktable += 2;
6ee73861
BS		 3818 } else {
3819 /* using EDID */
f3bbb9cc 3820 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3821
3822 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3823 clktable += 4;
3824 cmpval_24bit <<= 1;
6ee73861 3825 }
f3bbb9cc
BS		 3826
3827 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3828 clktable += 2;
6ee73861
BS		 3829 }
3830
f3bbb9cc 3831 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3832 if (!clktable) {
3833 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3834 return -ENOENT;
3835 }
3836 scriptptr = clkcmptable(bios, clktable, pxclk);
3837 }
3838
3839 if (!scriptptr) {
3840 NV_ERROR(dev, "LVDS output init script not found\n");
3841 return -ENOENT;
3842 }
3843 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3844
3845 return 0;
3846}
3847
3848int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3849{
3850 /*
3851 * LVDS operations are multiplexed in an effort to present a single API
3852 * which works with two vastly differing underlying structures.
3853 * This acts as the demux
3854 */
3855
3856 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3857 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3858 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3859 uint32_t sel_clk_binding, sel_clk;
3860 int ret;
3861
3862 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3863 (lvds_ver >= 0x30 && script == LVDS_INIT))
3864 return 0;
3865
3866 if (!bios->fp.lvds_init_run) {
3867 bios->fp.lvds_init_run = true;
3868 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3869 }
3870
3871 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3872 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3873 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3874 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3875
3876 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3877
3878 /* don't let script change pll->head binding */
3879 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3880
3881 if (lvds_ver < 0x30)
3882 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3883 else
3884 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3885
3886 bios->fp.last_script_invoc = (script << 1 | head);
3887
3888 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3889 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3890 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3891 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3892
3893 return ret;
3894}
3895
3896struct lvdstableheader {
3897 uint8_t lvds_ver, headerlen, recordlen;
3898};
3899
3900static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3901{
3902 /*
3903 * BMP version (0xa) LVDS table has a simple header of version and
3904 * record length. The BIT LVDS table has the typical BIT table header:
3905 * version byte, header length byte, record length byte, and a byte for
3906 * the maximum number of records that can be held in the table.
3907 */
3908
3909 uint8_t lvds_ver, headerlen, recordlen;
3910
3911 memset(lth, 0, sizeof(struct lvdstableheader));
3912
3913 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3914 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3915 return -EINVAL;
3916 }
3917
3918 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3919
3920 switch (lvds_ver) {
3921 case 0x0a: /* pre NV40 */
3922 headerlen = 2;
3923 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3924 break;
3925 case 0x30: /* NV4x */
3926 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3927 if (headerlen < 0x1f) {
3928 NV_ERROR(dev, "LVDS table header not understood\n");
3929 return -EINVAL;
3930 }
3931 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3932 break;
3933 case 0x40: /* G80/G90 */
3934 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3935 if (headerlen < 0x7) {
3936 NV_ERROR(dev, "LVDS table header not understood\n");
3937 return -EINVAL;
3938 }
3939 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3940 break;
3941 default:
3942 NV_ERROR(dev,
3943 "LVDS table revision %d.%d not currently supported\n",
3944 lvds_ver >> 4, lvds_ver & 0xf);
3945 return -ENOSYS;
3946 }
3947
3948 lth->lvds_ver = lvds_ver;
3949 lth->headerlen = headerlen;
3950 lth->recordlen = recordlen;
3951
3952 return 0;
3953}
3954
3955static int
3956get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3957{
3958 struct drm_nouveau_private *dev_priv = dev->dev_private;
3959
3960 /*
3961 * The fp strap is normally dictated by the "User Strap" in
3962 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3963 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3964 * by the PCI subsystem ID during POST, but not before the previous user
3965 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3966 * read and used instead
3967 */
3968
3969 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3970 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3971
3972 if (dev_priv->card_type >= NV_50)
3973 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3974 else
3975 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3976}
3977
3978static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3979{
3980 uint8_t *fptable;
3981 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3982 int ret, ofs, fpstrapping;
3983 struct lvdstableheader lth;
3984
3985 if (bios->fp.fptablepointer == 0x0) {
3986 /* Apple cards don't have the fp table; the laptops use DDC */
3987 /* The table is also missing on some x86 IGPs */
3988#ifndef __powerpc__
3989 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3990#endif
04a39c57 3991 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 3992 return 0;
3993 }
3994
3995 fptable = &bios->data[bios->fp.fptablepointer];
3996 fptable_ver = fptable[0];
3997
3998 switch (fptable_ver) {
3999 /*
4000 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4001 * version field, and miss one of the spread spectrum/PWM bytes.
4002 * This could affect early GF2Go parts (not seen any appropriate ROMs
4003 * though). Here we assume that a version of 0x05 matches this case
4004 * (combining with a BMP version check would be better), as the
4005 * common case for the panel type field is 0x0005, and that is in
4006 * fact what we are reading the first byte of.
4007 */
4008 case 0x05: /* some NV10, 11, 15, 16 */
4009 recordlen = 42;
4010 ofs = -1;
4011 break;
4012 case 0x10: /* some NV15/16, and NV11+ */
4013 recordlen = 44;
4014 ofs = 0;
4015 break;
4016 case 0x20: /* NV40+ */
4017 headerlen = fptable[1];
4018 recordlen = fptable[2];
4019 fpentries = fptable[3];
4020 /*
4021 * fptable[4] is the minimum
4022 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4023 */
04a39c57 4024 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 4025 ofs = -7;
4026 break;
4027 default:
4028 NV_ERROR(dev,
4029 "FP table revision %d.%d not currently supported\n",
4030 fptable_ver >> 4, fptable_ver & 0xf);
4031 return -ENOSYS;
4032 }
4033
4034 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4035 return 0;
4036
4037 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4038 if (ret)
4039 return ret;
4040
4041 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4042 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4043 lth.headerlen + 1;
4044 bios->fp.xlatwidth = lth.recordlen;
4045 }
4046 if (bios->fp.fpxlatetableptr == 0x0) {
4047 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4048 return -EINVAL;
4049 }
4050
4051 fpstrapping = get_fp_strap(dev, bios);
4052
4053 fpindex = bios->data[bios->fp.fpxlatetableptr +
4054 fpstrapping * bios->fp.xlatwidth];
4055
4056 if (fpindex > fpentries) {
4057 NV_ERROR(dev, "Bad flat panel table index\n");
4058 return -ENOENT;
4059 }
4060
4061 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4062 if (lth.lvds_ver > 0x10)
04a39c57 4063 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 4064
4065 /*
4066 * If either the strap or xlated fpindex value are 0xf there is no
4067 * panel using a strap-derived bios mode present. this condition
4068 * includes, but is different from, the DDC panel indicator above
4069 */
4070 if (fpstrapping == 0xf || fpindex == 0xf)
4071 return 0;
4072
4073 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4074 recordlen * fpindex + ofs;
4075
4076 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4077 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4078 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4079 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4080
4081 return 0;
4082}
4083
4084bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4085{
4086 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4087 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4088 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4089
4090 if (!mode) /* just checking whether we can produce a mode */
4091 return bios->fp.mode_ptr;
4092
4093 memset(mode, 0, sizeof(struct drm_display_mode));
4094 /*
4095 * For version 1.0 (version in byte 0):
4096 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4097 * single/dual link, and type (TFT etc.)
4098 * bytes 3-6 are bits per colour in RGBX
4099 */
4100 mode->clock = ROM16(mode_entry[7]) * 10;
4101 /* bytes 9-10 is HActive */
4102 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4103 /*
4104 * bytes 13-14 is HValid Start
4105 * bytes 15-16 is HValid End
4106 */
4107 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4108 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4109 mode->htotal = ROM16(mode_entry[21]) + 1;
4110 /* bytes 23-24, 27-30 similarly, but vertical */
4111 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4112 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4113 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4114 mode->vtotal = ROM16(mode_entry[35]) + 1;
4115 mode->flags |= (mode_entry[37] & 0x10) ?
4116 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4117 mode->flags |= (mode_entry[37] & 0x1) ?
4118 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4119 /*
4120 * bytes 38-39 relate to spread spectrum settings
4121 * bytes 40-43 are something to do with PWM
4122 */
4123
4124 mode->status = MODE_OK;
4125 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4126 drm_mode_set_name(mode);
4127 return bios->fp.mode_ptr;
4128}
4129
4130int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4131{
4132 /*
4133 * The LVDS table header is (mostly) described in
4134 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4135 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4136 * straps are not being used for the panel, this specifies the frequency
4137 * at which modes should be set up in the dual link style.
4138 *
4139 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 4140 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 4141 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4142 * numbers for use by INIT_SUB which controlled panel init and power,
4143 * and finally a dword of ms to sleep between power off and on
4144 * operations.
4145 *
4146 * In the BIT versions, the table following the header serves as an
4147 * integrated config and xlat table: the records in the table are
4148 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4149 * two bytes - the first as a config byte, the second for indexing the
4150 * fp mode table pointed to by the BIT 'D' table
4151 *
4152 * DDC is not used until after card init, so selecting the correct table
4153 * entry and setting the dual link flag for EDID equipped panels,
4154 * requiring tests against the native-mode pixel clock, cannot be done
4155 * until later, when this function should be called with non-zero pxclk
4156 */
4157 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4158 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4159 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4160 struct lvdstableheader lth;
4161 uint16_t lvdsofs;
04a39c57 4162 int ret, chip_version = bios->chip_version;
6ee73861
BS		 4163
4164 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4165 if (ret)
4166 return ret;
4167
4168 switch (lth.lvds_ver) {
4169 case 0x0a: /* pre NV40 */
4170 lvdsmanufacturerindex = bios->data[
4171 bios->fp.fpxlatemanufacturertableptr +
4172 fpstrapping];
4173
4174 /* we're done if this isn't the EDID panel case */
4175 if (!pxclk)
4176 break;
4177
4178 if (chip_version < 0x25) {
4179 /* nv17 behaviour
4180 *
4181 * It seems the old style lvds script pointer is reused
4182 * to select 18/24 bit colour depth for EDID panels.
4183 */
4184 lvdsmanufacturerindex =
4185 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4186 2 : 0;
4187 if (pxclk >= bios->fp.duallink_transition_clk)
4188 lvdsmanufacturerindex++;
4189 } else if (chip_version < 0x30) {
4190 /* nv28 behaviour (off-chip encoder)
4191 *
4192 * nv28 does a complex dance of first using byte 121 of
4193 * the EDID to choose the lvdsmanufacturerindex, then
4194 * later attempting to match the EDID manufacturer and
4195 * product IDs in a table (signature 'pidt' (panel id
4196 * table?)), setting an lvdsmanufacturerindex of 0 and
4197 * an fp strap of the match index (or 0xf if none)
4198 */
4199 lvdsmanufacturerindex = 0;
4200 } else {
4201 /* nv31, nv34 behaviour */
4202 lvdsmanufacturerindex = 0;
4203 if (pxclk >= bios->fp.duallink_transition_clk)
4204 lvdsmanufacturerindex = 2;
4205 if (pxclk >= 140000)
4206 lvdsmanufacturerindex = 3;
4207 }
4208
4209 /*
4210 * nvidia set the high nibble of (cr57=f, cr58) to
4211 * lvdsmanufacturerindex in this case; we don't
4212 */
4213 break;
4214 case 0x30: /* NV4x */
4215 case 0x40: /* G80/G90 */
4216 lvdsmanufacturerindex = fpstrapping;
4217 break;
4218 default:
4219 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4220 return -ENOSYS;
4221 }
4222
4223 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4224 switch (lth.lvds_ver) {
4225 case 0x0a:
4226 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4227 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4228 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4229 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4230 *if_is_24bit = bios->data[lvdsofs] & 16;
4231 break;
4232 case 0x30:
f3bbb9cc 4233 case 0x40:
6ee73861
BS		 4234 /*
4235 * No sign of the "power off for reset" or "reset for panel
4236 * on" bits, but it's safer to assume we should
4237 */
4238 bios->fp.power_off_for_reset = true;
4239 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 4240
6ee73861
BS		 4241 /*
4242 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 4243 * over-written, and if_is_24bit isn't used
6ee73861
BS		 4244 */
4245 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 4246 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4247 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4248 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4249 break;
4250 }
4251
2eb92c80
BS		 4252 /* Dell Latitude D620 reports a too-high value for the dual-link
4253 * transition freq, causing us to program the panel incorrectly.
4254 *
4255 * It doesn't appear the VBIOS actually uses its transition freq
4256 * (90000kHz), instead it uses the "Number of LVDS channels" field
4257 * out of the panel ID structure (http://www.spwg.org/).
4258 *
4259 * For the moment, a quirk will do :)
4260 */
4261 if ((dev->pdev->device == 0x01d7) &&
4262 (dev->pdev->subsystem_vendor == 0x1028) &&
4263 (dev->pdev->subsystem_device == 0x01c2)) {
4264 bios->fp.duallink_transition_clk = 80000;
4265 }
4266
6ee73861
BS		 4267 /* set dual_link flag for EDID case */
4268 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4269 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4270
4271 *dl = bios->fp.dual_link;
4272
4273 return 0;
4274}
4275
4276static uint8_t *
4277bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
1eb38100
BS		 4278 uint16_t record, int record_len, int record_nr,
4279 bool match_link)
6ee73861
BS		 4280{
4281 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4282 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4283 uint32_t entry;
4284 uint16_t table;
4285 int i, v;
4286
1eb38100
BS		 4287 switch (dcbent->type) {
4288 case OUTPUT_TMDS:
4289 case OUTPUT_LVDS:
4290 case OUTPUT_DP:
4291 break;
4292 default:
4293 match_link = false;
4294 break;
4295 }
4296
6ee73861
BS		 4297 for (i = 0; i < record_nr; i++, record += record_len) {
4298 table = ROM16(bios->data[record]);
4299 if (!table)
4300 continue;
4301 entry = ROM32(bios->data[table]);
4302
1eb38100
BS		 4303 if (match_link) {
4304 v = (entry & 0x00c00000) >> 22;
4305 if (!(v & dcbent->sorconf.link))
4306 continue;
4307 }
4308
6ee73861
BS		 4309 v = (entry & 0x000f0000) >> 16;
4310 if (!(v & dcbent->or))
4311 continue;
4312
4313 v = (entry & 0x000000f0) >> 4;
4314 if (v != dcbent->location)
4315 continue;
4316
4317 v = (entry & 0x0000000f);
4318 if (v != dcbent->type)
4319 continue;
4320
4321 return &bios->data[table];
4322 }
4323
4324 return NULL;
4325}
4326
4327void *
4328nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
4329 int *length)
4330{
4331 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4332 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4333 uint8_t *table;
4334
4335 if (!bios->display.dp_table_ptr) {
4336 NV_ERROR(dev, "No pointer to DisplayPort table\n");
4337 return NULL;
4338 }
4339 table = &bios->data[bios->display.dp_table_ptr];
4340
c52e53fd 4341 if (table[0] != 0x20 && table[0] != 0x21) {
6ee73861
BS		 4342 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
4343 table[0]);
4344 return NULL;
4345 }
4346
4347 *length = table[4];
4348 return bios_output_config_match(dev, dcbent,
4349 bios->display.dp_table_ptr + table[1],
1eb38100 4350 table[2], table[3], table[0] >= 0x21);
6ee73861
BS		 4351}
4352
4353int
4354nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4355 uint32_t sub, int pxclk)
4356{
4357 /*
4358 * The display script table is located by the BIT 'U' table.
4359 *
4360 * It contains an array of pointers to various tables describing
4361 * a particular output type. The first 32-bits of the output
4362 * tables contains similar information to a DCB entry, and is
4363 * used to decide whether that particular table is suitable for
4364 * the output you want to access.
4365 *
4366 * The "record header length" field here seems to indicate the
4367 * offset of the first configuration entry in the output tables.
4368 * This is 10 on most cards I've seen, but 12 has been witnessed
4369 * on DP cards, and there's another script pointer within the
4370 * header.
4371 *
4372 * offset + 0 ( 8 bits): version
4373 * offset + 1 ( 8 bits): header length
4374 * offset + 2 ( 8 bits): record length
4375 * offset + 3 ( 8 bits): number of records
4376 * offset + 4 ( 8 bits): record header length
4377 * offset + 5 (16 bits): pointer to first output script table
4378 */
4379
4380 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4381 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4382 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4383 uint8_t *otable = NULL;
4384 uint16_t script;
4385 int i = 0;
4386
4387 if (!bios->display.script_table_ptr) {
4388 NV_ERROR(dev, "No pointer to output script table\n");
4389 return 1;
4390 }
4391
4392 /*
4393 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4394 * so until they are, we really don't need to care.
4395 */
4396 if (table[0] < 0x20)
4397 return 1;
4398
4399 if (table[0] != 0x20 && table[0] != 0x21) {
4400 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4401 table[0]);
4402 return 1;
4403 }
4404
4405 /*
4406 * The output script tables describing a particular output type
4407 * look as follows:
4408 *
4409 * offset + 0 (32 bits): output this table matches (hash of DCB)
4410 * offset + 4 ( 8 bits): unknown
4411 * offset + 5 ( 8 bits): number of configurations
4412 * offset + 6 (16 bits): pointer to some script
4413 * offset + 8 (16 bits): pointer to some script
4414 *
4415 * headerlen == 10
4416 * offset + 10 : configuration 0
4417 *
4418 * headerlen == 12
4419 * offset + 10 : pointer to some script
4420 * offset + 12 : configuration 0
4421 *
4422 * Each config entry is as follows:
4423 *
4424 * offset + 0 (16 bits): unknown, assumed to be a match value
4425 * offset + 2 (16 bits): pointer to script table (clock set?)
4426 * offset + 4 (16 bits): pointer to script table (reset?)
4427 *
4428 * There doesn't appear to be a count value to say how many
4429 * entries exist in each script table, instead, a 0 value in
4430 * the first 16-bit word seems to indicate both the end of the
4431 * list and the default entry. The second 16-bit word in the
4432 * script tables is a pointer to the script to execute.
4433 */
4434
ef2bb506 4435 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 4436 dcbent->type, dcbent->location, dcbent->or);
4437 otable = bios_output_config_match(dev, dcbent, table[1] +
4438 bios->display.script_table_ptr,
1eb38100 4439 table[2], table[3], table[0] >= 0x21);
6ee73861
BS		 4440 if (!otable) {
4441 NV_ERROR(dev, "Couldn't find matching output script table\n");
4442 return 1;
4443 }
4444
4445 if (pxclk < -2 || pxclk > 0) {
4446 /* Try to find matching script table entry */
4447 for (i = 0; i < otable[5]; i++) {
4448 if (ROM16(otable[table[4] + i*6]) == sub)
4449 break;
4450 }
4451
4452 if (i == otable[5]) {
4453 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4454 "using first\n",
4455 sub, dcbent->type, dcbent->or);
4456 i = 0;
4457 }
4458 }
4459
6ee73861
BS		 4460 if (pxclk == 0) {
4461 script = ROM16(otable[6]);
4462 if (!script) {
ef2bb506 4463 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4464 return 1;
4465 }
4466
4467 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 4468 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4469 } else
4470 if (pxclk == -1) {
4471 script = ROM16(otable[8]);
4472 if (!script) {
ef2bb506 4473 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4474 return 1;
4475 }
4476
4477 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 4478 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4479 } else
4480 if (pxclk == -2) {
4481 if (table[4] >= 12)
4482 script = ROM16(otable[10]);
4483 else
4484 script = 0;
4485 if (!script) {
ef2bb506 4486 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4487 return 1;
4488 }
4489
4490 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 4491 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4492 } else
4493 if (pxclk > 0) {
4494 script = ROM16(otable[table[4] + i*6 + 2]);
4495 if (script)
4496 script = clkcmptable(bios, script, pxclk);
4497 if (!script) {
4498 NV_ERROR(dev, "clock script 0 not found\n");
4499 return 1;
4500 }
4501
4502 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 4503 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4504 } else
4505 if (pxclk < 0) {
4506 script = ROM16(otable[table[4] + i*6 + 4]);
4507 if (script)
4508 script = clkcmptable(bios, script, -pxclk);
4509 if (!script) {
ef2bb506 4510 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4511 return 1;
4512 }
4513
4514 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 4515 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4516 }
4517
4518 return 0;
4519}
4520
4521
4522int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4523{
4524 /*
4525 * the pxclk parameter is in kHz
4526 *
4527 * This runs the TMDS regs setting code found on BIT bios cards
4528 *
4529 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4530 * ffs(or) == 3, use the second.
4531 */
4532
4533 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4534 struct nvbios *bios = &dev_priv->vbios;
4535 int cv = bios->chip_version;
6ee73861
BS		 4536 uint16_t clktable = 0, scriptptr;
4537 uint32_t sel_clk_binding, sel_clk;
4538
4539 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4540 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4541 dcbent->location != DCB_LOC_ON_CHIP)
4542 return 0;
4543
4544 switch (ffs(dcbent->or)) {
4545 case 1:
4546 clktable = bios->tmds.output0_script_ptr;
4547 break;
4548 case 2:
4549 case 3:
4550 clktable = bios->tmds.output1_script_ptr;
4551 break;
4552 }
4553
4554 if (!clktable) {
4555 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4556 return -EINVAL;
4557 }
4558
4559 scriptptr = clkcmptable(bios, clktable, pxclk);
4560
4561 if (!scriptptr) {
4562 NV_ERROR(dev, "TMDS output init script not found\n");
4563 return -ENOENT;
4564 }
4565
4566 /* don't let script change pll->head binding */
4567 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4568 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4569 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4570 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4571
4572 return 0;
4573}
4574
4575int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4576{
4577 /*
4578 * PLL limits table
4579 *
4580 * Version 0x10: NV30, NV31
4581 * One byte header (version), one record of 24 bytes
4582 * Version 0x11: NV36 - Not implemented
4583 * Seems to have same record style as 0x10, but 3 records rather than 1
4584 * Version 0x20: Found on Geforce 6 cards
4585 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4586 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4587 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4588 * length in general, some (integrated) have an extra configuration byte
4589 * Version 0x30: Found on Geforce 8, separates the register mapping
4590 * from the limits tables.
4591 */
4592
4593 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4594 struct nvbios *bios = &dev_priv->vbios;
4595 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4596 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4597 uint32_t crystal_strap_mask, crystal_straps;
4598
4599 if (!bios->pll_limit_tbl_ptr) {
4600 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4601 cv >= 0x40) {
4602 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4603 return -EINVAL;
4604 }
4605 } else
4606 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4607
4608 crystal_strap_mask = 1 << 6;
4609 /* open coded dev->twoHeads test */
4610 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4611 crystal_strap_mask |= 1 << 22;
4612 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4613 crystal_strap_mask;
4614
4615 switch (pll_lim_ver) {
4616 /*
4617 * We use version 0 to indicate a pre limit table bios (single stage
4618 * pll) and load the hard coded limits instead.
4619 */
4620 case 0:
4621 break;
4622 case 0x10:
4623 case 0x11:
4624 /*
4625 * Strictly v0x11 has 3 entries, but the last two don't seem
4626 * to get used.
4627 */
4628 headerlen = 1;
4629 recordlen = 0x18;
4630 entries = 1;
4631 pllindex = 0;
4632 break;
4633 case 0x20:
4634 case 0x21:
4635 case 0x30:
4636 case 0x40:
4637 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4638 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4639 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4640 break;
4641 default:
4642 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4643 "supported\n", pll_lim_ver);
4644 return -ENOSYS;
4645 }
4646
4647 /* initialize all members to zero */
4648 memset(pll_lim, 0, sizeof(struct pll_lims));
4649
4650 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4651 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4652
4653 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4654 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4655 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4656 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4657 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4658 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4659 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4660
4661 /* these values taken from nv30/31/36 */
4662 pll_lim->vco1.min_n = 0x1;
4663 if (cv == 0x36)
4664 pll_lim->vco1.min_n = 0x5;
4665 pll_lim->vco1.max_n = 0xff;
4666 pll_lim->vco1.min_m = 0x1;
4667 pll_lim->vco1.max_m = 0xd;
4668 pll_lim->vco2.min_n = 0x4;
4669 /*
4670 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4671 * table version (apart from nv35)), N2 is compared to
4672 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4673 * save a comparison
4674 */
4675 pll_lim->vco2.max_n = 0x28;
4676 if (cv == 0x30 || cv == 0x35)
4677 /* only 5 bits available for N2 on nv30/35 */
4678 pll_lim->vco2.max_n = 0x1f;
4679 pll_lim->vco2.min_m = 0x1;
4680 pll_lim->vco2.max_m = 0x4;
4681 pll_lim->max_log2p = 0x7;
4682 pll_lim->max_usable_log2p = 0x6;
4683 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4684 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4685 uint32_t reg = 0; /* default match */
4686 uint8_t *pll_rec;
4687 int i;
4688
4689 /*
4690 * First entry is default match, if nothing better. warn if
4691 * reg field nonzero
4692 */
4693 if (ROM32(bios->data[plloffs]))
4694 NV_WARN(dev, "Default PLL limit entry has non-zero "
4695 "register field\n");
4696
4697 if (limit_match > MAX_PLL_TYPES)
4698 /* we've been passed a reg as the match */
4699 reg = limit_match;
4700 else /* limit match is a pll type */
4701 for (i = 1; i < entries && !reg; i++) {
4702 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4703
4704 if (limit_match == NVPLL &&
4705 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4706 reg = cmpreg;
4707 if (limit_match == MPLL &&
4708 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4709 reg = cmpreg;
4710 if (limit_match == VPLL1 &&
4711 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4712 reg = cmpreg;
4713 if (limit_match == VPLL2 &&
4714 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4715 reg = cmpreg;
4716 }
4717
4718 for (i = 1; i < entries; i++)
4719 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4720 pllindex = i;
4721 break;
4722 }
4723
4724 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4725
4726 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4727 pllindex ? reg : 0);
4728
4729 /*
4730 * Frequencies are stored in tables in MHz, kHz are more
4731 * useful, so we convert.
4732 */
4733
4734 /* What output frequencies can each VCO generate? */
4735 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4736 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4737 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4738 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4739
4740 /* What input frequencies they accept (past the m-divider)? */
4741 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4742 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4743 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4744 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4745
4746 /* What values are accepted as multiplier and divider? */
4747 pll_lim->vco1.min_n = pll_rec[20];
4748 pll_lim->vco1.max_n = pll_rec[21];
4749 pll_lim->vco1.min_m = pll_rec[22];
4750 pll_lim->vco1.max_m = pll_rec[23];
4751 pll_lim->vco2.min_n = pll_rec[24];
4752 pll_lim->vco2.max_n = pll_rec[25];
4753 pll_lim->vco2.min_m = pll_rec[26];
4754 pll_lim->vco2.max_m = pll_rec[27];
4755
4756 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4757 if (pll_lim->max_log2p > 0x7)
4758 /* pll decoding in nv_hw.c assumes never > 7 */
4759 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4760 pll_lim->max_log2p);
4761 if (cv < 0x60)
4762 pll_lim->max_usable_log2p = 0x6;
4763 pll_lim->log2p_bias = pll_rec[30];
4764
4765 if (recordlen > 0x22)
4766 pll_lim->refclk = ROM32(pll_rec[31]);
4767
4768 if (recordlen > 0x23 && pll_rec[35])
4769 NV_WARN(dev,
4770 "Bits set in PLL configuration byte (%x)\n",
4771 pll_rec[35]);
4772
4773 /* C51 special not seen elsewhere */
4774 if (cv == 0x51 && !pll_lim->refclk) {
4775 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4776
4777 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4778 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4779 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4780 pll_lim->refclk = 200000;
4781 else
4782 pll_lim->refclk = 25000;
4783 }
4784 }
4785 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4786 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4787 uint8_t *record = NULL;
4788 int i;
4789
4790 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4791 limit_match);
4792
4793 for (i = 0; i < entries; i++, entry += recordlen) {
4794 if (ROM32(entry[3]) == limit_match) {
4795 record = &bios->data[ROM16(entry[1])];
4796 break;
4797 }
4798 }
4799
4800 if (!record) {
4801 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4802 "limits table", limit_match);
4803 return -ENOENT;
4804 }
4805
4806 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4807 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4808 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4809 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4810 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4811 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4812 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4813 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4814 pll_lim->vco1.min_n = record[16];
4815 pll_lim->vco1.max_n = record[17];
4816 pll_lim->vco1.min_m = record[18];
4817 pll_lim->vco1.max_m = record[19];
4818 pll_lim->vco2.min_n = record[20];
4819 pll_lim->vco2.max_n = record[21];
4820 pll_lim->vco2.min_m = record[22];
4821 pll_lim->vco2.max_m = record[23];
4822 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4823 pll_lim->log2p_bias = record[27];
4824 pll_lim->refclk = ROM32(record[28]);
4825 } else if (pll_lim_ver) { /* ver 0x40 */
4826 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4827 uint8_t *record = NULL;
4828 int i;
4829
4830 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4831 limit_match);
4832
4833 for (i = 0; i < entries; i++, entry += recordlen) {
4834 if (ROM32(entry[3]) == limit_match) {
4835 record = &bios->data[ROM16(entry[1])];
4836 break;
4837 }
4838 }
4839
4840 if (!record) {
4841 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4842 "limits table", limit_match);
4843 return -ENOENT;
4844 }
4845
4846 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4847 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4848 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4849 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4850 pll_lim->vco1.min_m = record[8];
4851 pll_lim->vco1.max_m = record[9];
4852 pll_lim->vco1.min_n = record[10];
4853 pll_lim->vco1.max_n = record[11];
4854 pll_lim->min_p = record[12];
4855 pll_lim->max_p = record[13];
4856 /* where did this go to?? */
1ac7b528 4857 if ((entry[0] & 0xf0) == 0x80)
6ee73861
BS		 4858 pll_lim->refclk = 27000;
4859 else
4860 pll_lim->refclk = 100000;
4861 }
4862
4863 /*
4864 * By now any valid limit table ought to have set a max frequency for
4865 * vco1, so if it's zero it's either a pre limit table bios, or one
4866 * with an empty limit table (seen on nv18)
4867 */
4868 if (!pll_lim->vco1.maxfreq) {
4869 pll_lim->vco1.minfreq = bios->fminvco;
4870 pll_lim->vco1.maxfreq = bios->fmaxvco;
4871 pll_lim->vco1.min_inputfreq = 0;
4872 pll_lim->vco1.max_inputfreq = INT_MAX;
4873 pll_lim->vco1.min_n = 0x1;
4874 pll_lim->vco1.max_n = 0xff;
4875 pll_lim->vco1.min_m = 0x1;
4876 if (crystal_straps == 0) {
4877 /* nv05 does this, nv11 doesn't, nv10 unknown */
4878 if (cv < 0x11)
4879 pll_lim->vco1.min_m = 0x7;
4880 pll_lim->vco1.max_m = 0xd;
4881 } else {
4882 if (cv < 0x11)
4883 pll_lim->vco1.min_m = 0x8;
4884 pll_lim->vco1.max_m = 0xe;
4885 }
4886 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4887 pll_lim->max_log2p = 4;
4888 else
4889 pll_lim->max_log2p = 5;
4890 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4891 }
4892
4893 if (!pll_lim->refclk)
4894 switch (crystal_straps) {
4895 case 0:
4896 pll_lim->refclk = 13500;
4897 break;
4898 case (1 << 6):
4899 pll_lim->refclk = 14318;
4900 break;
4901 case (1 << 22):
4902 pll_lim->refclk = 27000;
4903 break;
4904 case (1 << 22 | 1 << 6):
4905 pll_lim->refclk = 25000;
4906 break;
4907 }
4908
4c389f00
BS		 4909 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4910 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4911 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4912 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4913 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4914 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4915 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4916 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4917 if (pll_lim->vco2.maxfreq) {
4918 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4919 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4920 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4921 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4922 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4923 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4924 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4925 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4926 }
4927 if (!pll_lim->max_p) {
4928 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4929 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4930 } else {
4931 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4932 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4933 }
4934 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 4935
4936 return 0;
4937}
4938
4939static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4940{
4941 /*
4942 * offset + 0 (8 bits): Micro version
4943 * offset + 1 (8 bits): Minor version
4944 * offset + 2 (8 bits): Chip version
4945 * offset + 3 (8 bits): Major version
4946 */
4947
4948 bios->major_version = bios->data[offset + 3];
04a39c57 4949 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 4950 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4951 bios->data[offset + 3], bios->data[offset + 2],
4952 bios->data[offset + 1], bios->data[offset]);
4953}
4954
4955static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4956{
4957 /*
4958 * Parses the init table segment for pointers used in script execution.
4959 *
4960 * offset + 0 (16 bits): init script tables pointer
4961 * offset + 2 (16 bits): macro index table pointer
4962 * offset + 4 (16 bits): macro table pointer
4963 * offset + 6 (16 bits): condition table pointer
4964 * offset + 8 (16 bits): io condition table pointer
4965 * offset + 10 (16 bits): io flag condition table pointer
4966 * offset + 12 (16 bits): init function table pointer
4967 */
4968
4969 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4970 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4971 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4972 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4973 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4974 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4975 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4976}
4977
4978static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4979{
4980 /*
4981 * Parses the load detect values for g80 cards.
4982 *
4983 * offset + 0 (16 bits): loadval table pointer
4984 */
4985
4986 uint16_t load_table_ptr;
4987 uint8_t version, headerlen, entrylen, num_entries;
4988
4989 if (bitentry->length != 3) {
4990 NV_ERROR(dev, "Do not understand BIT A table\n");
4991 return -EINVAL;
4992 }
4993
4994 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4995
4996 if (load_table_ptr == 0x0) {
4997 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4998 return -EINVAL;
4999 }
5000
5001 version = bios->data[load_table_ptr];
5002
5003 if (version != 0x10) {
5004 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5005 version >> 4, version & 0xF);
5006 return -ENOSYS;
5007 }
5008
5009 headerlen = bios->data[load_table_ptr + 1];
5010 entrylen = bios->data[load_table_ptr + 2];
5011 num_entries = bios->data[load_table_ptr + 3];
5012
5013 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5014 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5015 return -EINVAL;
5016 }
5017
5018 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 5019 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 5020
5021 return 0;
5022}
5023
5024static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5025{
5026 /*
5027 * offset + 8 (16 bits): PLL limits table pointer
5028 *
5029 * There's more in here, but that's unknown.
5030 */
5031
5032 if (bitentry->length < 10) {
5033 NV_ERROR(dev, "Do not understand BIT C table\n");
5034 return -EINVAL;
5035 }
5036
5037 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5038
5039 return 0;
5040}
5041
5042static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5043{
5044 /*
5045 * Parses the flat panel table segment that the bit entry points to.
5046 * Starting at bitentry->offset:
5047 *
5048 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5049 * records beginning with a freq.
5050 * offset + 2 (16 bits): mode table pointer
5051 */
5052
5053 if (bitentry->length != 4) {
5054 NV_ERROR(dev, "Do not understand BIT display table\n");
5055 return -EINVAL;
5056 }
5057
5058 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5059
5060 return 0;
5061}
5062
5063static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5064{
5065 /*
5066 * Parses the init table segment that the bit entry points to.
5067 *
5068 * See parse_script_table_pointers for layout
5069 */
5070
5071 if (bitentry->length < 14) {
5072 NV_ERROR(dev, "Do not understand init table\n");
5073 return -EINVAL;
5074 }
5075
5076 parse_script_table_pointers(bios, bitentry->offset);
5077
5078 if (bitentry->length >= 16)
5079 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5080 if (bitentry->length >= 18)
5081 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5082
5083 return 0;
5084}
5085
5086static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5087{
5088 /*
5089 * BIT 'i' (info?) table
5090 *
5091 * offset + 0 (32 bits): BIOS version dword (as in B table)
5092 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5093 * offset + 13 (16 bits): pointer to table containing DAC load
5094 * detection comparison values
5095 *
5096 * There's other things in the table, purpose unknown
5097 */
5098
5099 uint16_t daccmpoffset;
5100 uint8_t dacver, dacheaderlen;
5101
5102 if (bitentry->length < 6) {
5103 NV_ERROR(dev, "BIT i table too short for needed information\n");
5104 return -EINVAL;
5105 }
5106
5107 parse_bios_version(dev, bios, bitentry->offset);
5108
5109 /*
5110 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5111 * Quadro identity crisis), other bits possibly as for BMP feature byte
5112 */
5113 bios->feature_byte = bios->data[bitentry->offset + 5];
5114 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5115
5116 if (bitentry->length < 15) {
5117 NV_WARN(dev, "BIT i table not long enough for DAC load "
5118 "detection comparison table\n");
5119 return -EINVAL;
5120 }
5121
5122 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5123
5124 /* doesn't exist on g80 */
5125 if (!daccmpoffset)
5126 return 0;
5127
5128 /*
5129 * The first value in the table, following the header, is the
5130 * comparison value, the second entry is a comparison value for
5131 * TV load detection.
5132 */
5133
5134 dacver = bios->data[daccmpoffset];
5135 dacheaderlen = bios->data[daccmpoffset + 1];
5136
5137 if (dacver != 0x00 && dacver != 0x10) {
5138 NV_WARN(dev, "DAC load detection comparison table version "
5139 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5140 return -ENOSYS;
5141 }
5142
04a39c57
BS		 5143 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5144 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 5145
5146 return 0;
5147}
5148
5149static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5150{
5151 /*
5152 * Parses the LVDS table segment that the bit entry points to.
5153 * Starting at bitentry->offset:
5154 *
5155 * offset + 0 (16 bits): LVDS strap xlate table pointer
5156 */
5157
5158 if (bitentry->length != 2) {
5159 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5160 return -EINVAL;
5161 }
5162
5163 /*
5164 * No idea if it's still called the LVDS manufacturer table, but
5165 * the concept's close enough.
5166 */
5167 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5168
5169 return 0;
5170}
5171
5172static int
5173parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5174 struct bit_entry *bitentry)
5175{
5176 /*
5177 * offset + 2 (8 bits): number of options in an
5178 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5179 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5180 * restrict option selection
5181 *
5182 * There's a bunch of bits in this table other than the RAM restrict
5183 * stuff that we don't use - their use currently unknown
5184 */
5185
6ee73861
BS		 5186 /*
5187 * Older bios versions don't have a sufficiently long table for
5188 * what we want
5189 */
5190 if (bitentry->length < 0x5)
5191 return 0;
5192
5193 if (bitentry->id[1] < 2) {
37383650
MK		 5194 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5195 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 5196 } else {
37383650
MK		 5197 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5198 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 5199 }
5200
6ee73861
BS		 5201 return 0;
5202}
5203
5204static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5205{
5206 /*
5207 * Parses the pointer to the TMDS table
5208 *
5209 * Starting at bitentry->offset:
5210 *
5211 * offset + 0 (16 bits): TMDS table pointer
5212 *
5213 * The TMDS table is typically found just before the DCB table, with a
5214 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5215 * length?)
5216 *
5217 * At offset +7 is a pointer to a script, which I don't know how to
5218 * run yet.
5219 * At offset +9 is a pointer to another script, likewise
5220 * Offset +11 has a pointer to a table where the first word is a pxclk
5221 * frequency and the second word a pointer to a script, which should be
5222 * run if the comparison pxclk frequency is less than the pxclk desired.
5223 * This repeats for decreasing comparison frequencies
5224 * Offset +13 has a pointer to a similar table
5225 * The selection of table (and possibly +7/+9 script) is dictated by
5226 * "or" from the DCB.
5227 */
5228
5229 uint16_t tmdstableptr, script1, script2;
5230
5231 if (bitentry->length != 2) {
5232 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5233 return -EINVAL;
5234 }
5235
5236 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5237
5238 if (tmdstableptr == 0x0) {
5239 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5240 return -EINVAL;
5241 }
5242
5243 /* nv50+ has v2.0, but we don't parse it atm */
5244 if (bios->data[tmdstableptr] != 0x11) {
5245 NV_WARN(dev,
5246 "TMDS table revision %d.%d not currently supported\n",
5247 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5248 return -ENOSYS;
5249 }
5250
5251 /*
5252 * These two scripts are odd: they don't seem to get run even when
5253 * they are not stubbed.
5254 */
5255 script1 = ROM16(bios->data[tmdstableptr + 7]);
5256 script2 = ROM16(bios->data[tmdstableptr + 9]);
5257 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5258 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5259
5260 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5261 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5262
5263 return 0;
5264}
5265
5266static int
5267parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5268 struct bit_entry *bitentry)
5269{
5270 /*
5271 * Parses the pointer to the G80 output script tables
5272 *
5273 * Starting at bitentry->offset:
5274 *
5275 * offset + 0 (16 bits): output script table pointer
5276 */
5277
5278 uint16_t outputscripttableptr;
5279
5280 if (bitentry->length != 3) {
5281 NV_ERROR(dev, "Do not understand BIT U table\n");
5282 return -EINVAL;
5283 }
5284
5285 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5286 bios->display.script_table_ptr = outputscripttableptr;
5287 return 0;
5288}
5289
5290static int
5291parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5292 struct bit_entry *bitentry)
5293{
5294 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
5295 return 0;
5296}
5297
5298struct bit_table {
5299 const char id;
5300 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5301};
5302
5303#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5304
5305static int
5306parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5307 struct bit_table *table)
5308{
5309 struct drm_device *dev = bios->dev;
5310 uint8_t maxentries = bios->data[bitoffset + 4];
5311 int i, offset;
5312 struct bit_entry bitentry;
5313
5314 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
5315 bitentry.id[0] = bios->data[offset];
5316
5317 if (bitentry.id[0] != table->id)
5318 continue;
5319
5320 bitentry.id[1] = bios->data[offset + 1];
5321 bitentry.length = ROM16(bios->data[offset + 2]);
5322 bitentry.offset = ROM16(bios->data[offset + 4]);
5323
5324 return table->parse_fn(dev, bios, &bitentry);
5325 }
5326
5327 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5328 return -ENOSYS;
5329}
5330
5331static int
5332parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5333{
5334 int ret;
5335
5336 /*
5337 * The only restriction on parsing order currently is having 'i' first
5338 * for use of bios->*_version or bios->feature_byte while parsing;
5339 * functions shouldn't be actually *doing* anything apart from pulling
5340 * data from the image into the bios struct, thus no interdependencies
5341 */
5342 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5343 if (ret) /* info? */
5344 return ret;
5345 if (bios->major_version >= 0x60) /* g80+ */
5346 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5347 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5348 if (ret)
5349 return ret;
5350 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5351 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5352 if (ret)
5353 return ret;
5354 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5355 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5356 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5357 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5358 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
5359
5360 return 0;
5361}
5362
5363static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5364{
5365 /*
5366 * Parses the BMP structure for useful things, but does not act on them
5367 *
5368 * offset + 5: BMP major version
5369 * offset + 6: BMP minor version
5370 * offset + 9: BMP feature byte
5371 * offset + 10: BCD encoded BIOS version
5372 *
5373 * offset + 18: init script table pointer (for bios versions < 5.10h)
5374 * offset + 20: extra init script table pointer (for bios
5375 * versions < 5.10h)
5376 *
5377 * offset + 24: memory init table pointer (used on early bios versions)
5378 * offset + 26: SDR memory sequencing setup data table
5379 * offset + 28: DDR memory sequencing setup data table
5380 *
5381 * offset + 54: index of I2C CRTC pair to use for CRT output
5382 * offset + 55: index of I2C CRTC pair to use for TV output
5383 * offset + 56: index of I2C CRTC pair to use for flat panel output
5384 * offset + 58: write CRTC index for I2C pair 0
5385 * offset + 59: read CRTC index for I2C pair 0
5386 * offset + 60: write CRTC index for I2C pair 1
5387 * offset + 61: read CRTC index for I2C pair 1
5388 *
5389 * offset + 67: maximum internal PLL frequency (single stage PLL)
5390 * offset + 71: minimum internal PLL frequency (single stage PLL)
5391 *
5392 * offset + 75: script table pointers, as described in
5393 * parse_script_table_pointers
5394 *
5395 * offset + 89: TMDS single link output A table pointer
5396 * offset + 91: TMDS single link output B table pointer
5397 * offset + 95: LVDS single link output A table pointer
5398 * offset + 105: flat panel timings table pointer
5399 * offset + 107: flat panel strapping translation table pointer
5400 * offset + 117: LVDS manufacturer panel config table pointer
5401 * offset + 119: LVDS manufacturer strapping translation table pointer
5402 *
5403 * offset + 142: PLL limits table pointer
5404 *
5405 * offset + 156: minimum pixel clock for LVDS dual link
5406 */
5407
5408 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5409 uint16_t bmplength;
5410 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5411
5412 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 5413 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5414 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5415 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5416 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 5417 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 5418 bios->fmaxvco = 256000;
5419 bios->fminvco = 128000;
5420 bios->fp.duallink_transition_clk = 90000;
5421
5422 bmp_version_major = bmp[5];
5423 bmp_version_minor = bmp[6];
5424
5425 NV_TRACE(dev, "BMP version %d.%d\n",
5426 bmp_version_major, bmp_version_minor);
5427
5428 /*
5429 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5430 * pointer on early versions
5431 */
5432 if (bmp_version_major < 5)
5433 *(uint16_t *)&bios->data[0x36] = 0;
5434
5435 /*
5436 * Seems that the minor version was 1 for all major versions prior
5437 * to 5. Version 6 could theoretically exist, but I suspect BIT
5438 * happened instead.
5439 */
5440 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5441 NV_ERROR(dev, "You have an unsupported BMP version. "
5442 "Please send in your bios\n");
5443 return -ENOSYS;
5444 }
5445
5446 if (bmp_version_major == 0)
5447 /* nothing that's currently useful in this version */
5448 return 0;
5449 else if (bmp_version_major == 1)
5450 bmplength = 44; /* exact for 1.01 */
5451 else if (bmp_version_major == 2)
5452 bmplength = 48; /* exact for 2.01 */
5453 else if (bmp_version_major == 3)
5454 bmplength = 54;
5455 /* guessed - mem init tables added in this version */
5456 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5457 /* don't know if 5.0 exists... */
5458 bmplength = 62;
5459 /* guessed - BMP I2C indices added in version 4*/
5460 else if (bmp_version_minor < 0x6)
5461 bmplength = 67; /* exact for 5.01 */
5462 else if (bmp_version_minor < 0x10)
5463 bmplength = 75; /* exact for 5.06 */
5464 else if (bmp_version_minor == 0x10)
5465 bmplength = 89; /* exact for 5.10h */
5466 else if (bmp_version_minor < 0x14)
5467 bmplength = 118; /* exact for 5.11h */
5468 else if (bmp_version_minor < 0x24)
5469 /*
5470 * Not sure of version where pll limits came in;
5471 * certainly exist by 0x24 though.
5472 */
5473 /* length not exact: this is long enough to get lvds members */
5474 bmplength = 123;
5475 else if (bmp_version_minor < 0x27)
5476 /*
5477 * Length not exact: this is long enough to get pll limit
5478 * member
5479 */
5480 bmplength = 144;
5481 else
5482 /*
5483 * Length not exact: this is long enough to get dual link
5484 * transition clock.
5485 */
5486 bmplength = 158;
5487
5488 /* checksum */
5489 if (nv_cksum(bmp, 8)) {
5490 NV_ERROR(dev, "Bad BMP checksum\n");
5491 return -EINVAL;
5492 }
5493
5494 /*
5495 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5496 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5497 * (not nv10gl), bit 5 that the flat panel tables are present, and
5498 * bit 6 a tv bios.
5499 */
5500 bios->feature_byte = bmp[9];
5501
5502 parse_bios_version(dev, bios, offset + 10);
5503
5504 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5505 bios->old_style_init = true;
5506 legacy_scripts_offset = 18;
5507 if (bmp_version_major < 2)
5508 legacy_scripts_offset -= 4;
5509 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5510 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5511
5512 if (bmp_version_major > 2) { /* appears in BMP 3 */
5513 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5514 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5515 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5516 }
5517
5518 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5519 if (bmplength > 61)
5520 legacy_i2c_offset = offset + 54;
5521 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5522 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5523 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3af76454
FJ		 5524 if (bios->data[legacy_i2c_offset + 4])
5525 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5526 if (bios->data[legacy_i2c_offset + 5])
5527 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5528 if (bios->data[legacy_i2c_offset + 6])
5529 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5530 if (bios->data[legacy_i2c_offset + 7])
5531 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 5532
5533 if (bmplength > 74) {
5534 bios->fmaxvco = ROM32(bmp[67]);
5535 bios->fminvco = ROM32(bmp[71]);
5536 }
5537 if (bmplength > 88)
5538 parse_script_table_pointers(bios, offset + 75);
5539 if (bmplength > 94) {
5540 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5541 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5542 /*
5543 * Never observed in use with lvds scripts, but is reused for
5544 * 18/24 bit panel interface default for EDID equipped panels
5545 * (if_is_24bit not set directly to avoid any oscillation).
5546 */
5547 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5548 }
5549 if (bmplength > 108) {
5550 bios->fp.fptablepointer = ROM16(bmp[105]);
5551 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5552 bios->fp.xlatwidth = 1;
5553 }
5554 if (bmplength > 120) {
5555 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5556 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5557 }
5558 if (bmplength > 143)
5559 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5560
5561 if (bmplength > 157)
5562 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5563
5564 return 0;
5565}
5566
5567static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5568{
5569 int i, j;
5570
5571 for (i = 0; i <= (n - len); i++) {
5572 for (j = 0; j < len; j++)
5573 if (data[i + j] != str[j])
5574 break;
5575 if (j == len)
5576 return i;
5577 }
5578
5579 return 0;
5580}
5581
6ee73861
BS		 5582static struct dcb_gpio_entry *
5583new_gpio_entry(struct nvbios *bios)
5584{
7f245b20 5585 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861
BS		 5586
5587 return &gpio->entry[gpio->entries++];
5588}
5589
5590struct dcb_gpio_entry *
5591nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5592{
5593 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5594 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5595 int i;
5596
7f245b20
BS		 5597 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5598 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5599 continue;
5600
7f245b20 5601 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5602 }
5603
5604 return NULL;
5605}
5606
5607static void
5608parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5609{
5610 struct dcb_gpio_entry *gpio;
5611 uint16_t ent = ROM16(bios->data[offset]);
5612 uint8_t line = ent & 0x1f,
5613 tag = ent >> 5 & 0x3f,
5614 flags = ent >> 11 & 0x1f;
5615
5616 if (tag == 0x3f)
5617 return;
5618
5619 gpio = new_gpio_entry(bios);
5620
5621 gpio->tag = tag;
5622 gpio->line = line;
5623 gpio->invert = flags != 4;
2535d71c 5624 gpio->entry = ent;
6ee73861
BS		 5625}
5626
5627static void
5628parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5629{
02faec09 5630 uint32_t entry = ROM32(bios->data[offset]);
6ee73861 5631 struct dcb_gpio_entry *gpio;
6ee73861 5632
02faec09 5633 if ((entry & 0x0000ff00) == 0x0000ff00)
6ee73861
BS		 5634 return;
5635
5636 gpio = new_gpio_entry(bios);
02faec09
BS		 5637 gpio->tag = (entry & 0x0000ff00) >> 8;
5638 gpio->line = (entry & 0x0000001f) >> 0;
5639 gpio->state_default = (entry & 0x01000000) >> 24;
5640 gpio->state[0] = (entry & 0x18000000) >> 27;
5641 gpio->state[1] = (entry & 0x60000000) >> 29;
5642 gpio->entry = entry;
6ee73861
BS		 5643}
5644
5645static void
5646parse_dcb_gpio_table(struct nvbios *bios)
5647{
5648 struct drm_device *dev = bios->dev;
7f245b20 5649 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr;
6ee73861
BS		 5650 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5651 int header_len = gpio_table[1],
5652 entries = gpio_table[2],
5653 entry_len = gpio_table[3];
5654 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5655 int i;
5656
7f245b20 5657 if (bios->dcb.version >= 0x40) {
6ee73861
BS		 5658 if (gpio_table_ptr && entry_len != 4) {
5659 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5660 return;
5661 }
5662
5663 parse_entry = parse_dcb40_gpio_entry;
5664
7f245b20 5665 } else if (bios->dcb.version >= 0x30) {
6ee73861
BS		 5666 if (gpio_table_ptr && entry_len != 2) {
5667 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5668 return;
5669 }
5670
5671 parse_entry = parse_dcb30_gpio_entry;
5672
7f245b20 5673 } else if (bios->dcb.version >= 0x22) {
6ee73861
BS		 5674 /*
5675 * DCBs older than v3.0 don't really have a GPIO
5676 * table, instead they keep some GPIO info at fixed
5677 * locations.
5678 */
5679 uint16_t dcbptr = ROM16(bios->data[0x36]);
5680 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5681
5682 if (tvdac_gpio[0] & 1) {
5683 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5684
5685 gpio->tag = DCB_GPIO_TVDAC0;
5686 gpio->line = tvdac_gpio[1] >> 4;
5687 gpio->invert = tvdac_gpio[0] & 2;
5688 }
5689 }
5690
5691 if (!gpio_table_ptr)
5692 return;
5693
5694 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5695 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5696 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5697 }
5698
5699 for (i = 0; i < entries; i++)
5700 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5701}
5702
5703struct dcb_connector_table_entry *
5704nouveau_bios_connector_entry(struct drm_device *dev, int index)
5705{
5706 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5707 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5708 struct dcb_connector_table_entry *cte;
5709
7f245b20 5710 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5711 return NULL;
5712
7f245b20 5713 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5714 if (cte->type == 0xff)
5715 return NULL;
5716
5717 return cte;
5718}
5719
f66fa771
BS		 5720static enum dcb_connector_type
5721divine_connector_type(struct nvbios *bios, int index)
5722{
5723 struct dcb_table *dcb = &bios->dcb;
5724 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5725 int i;
5726
5727 for (i = 0; i < dcb->entries; i++) {
5728 if (dcb->entry[i].connector == index)
5729 encoders |= (1 << dcb->entry[i].type);
5730 }
5731
5732 if (encoders & (1 << OUTPUT_DP)) {
5733 if (encoders & (1 << OUTPUT_TMDS))
5734 type = DCB_CONNECTOR_DP;
5735 else
5736 type = DCB_CONNECTOR_eDP;
5737 } else
5738 if (encoders & (1 << OUTPUT_TMDS)) {
5739 if (encoders & (1 << OUTPUT_ANALOG))
5740 type = DCB_CONNECTOR_DVI_I;
5741 else
5742 type = DCB_CONNECTOR_DVI_D;
5743 } else
5744 if (encoders & (1 << OUTPUT_ANALOG)) {
5745 type = DCB_CONNECTOR_VGA;
5746 } else
5747 if (encoders & (1 << OUTPUT_LVDS)) {
5748 type = DCB_CONNECTOR_LVDS;
5749 } else
5750 if (encoders & (1 << OUTPUT_TV)) {
5751 type = DCB_CONNECTOR_TV_0;
5752 }
5753
5754 return type;
5755}
5756
53c44c3a
BS		 5757static void
5758apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5759{
5760 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5761 struct drm_device *dev = bios->dev;
5762
5763 /* Gigabyte NX85T */
5764 if ((dev->pdev->device == 0x0421) &&
5765 (dev->pdev->subsystem_vendor == 0x1458) &&
5766 (dev->pdev->subsystem_device == 0x344c)) {
5767 if (cte->type == DCB_CONNECTOR_HDMI_1)
5768 cte->type = DCB_CONNECTOR_DVI_I;
5769 }
5770}
5771
6ee73861
BS		 5772static void
5773parse_dcb_connector_table(struct nvbios *bios)
5774{
5775 struct drm_device *dev = bios->dev;
7f245b20 5776 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5777 struct dcb_connector_table_entry *cte;
7f245b20 5778 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5779 uint8_t *entry;
5780 int i;
5781
7f245b20 5782 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5783 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5784 return;
5785 }
5786
5787 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5788 conntab[0], conntab[1], conntab[2], conntab[3]);
5789 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5790 (conntab[3] != 2 && conntab[3] != 4)) {
5791 NV_ERROR(dev, " Unknown! Please report.\n");
5792 return;
5793 }
5794
5795 ct->entries = conntab[2];
5796
5797 entry = conntab + conntab[1];
5798 cte = &ct->entry[0];
5799 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 5800 cte->index = i;
6ee73861
BS		 5801 if (conntab[3] == 2)
5802 cte->entry = ROM16(entry[0]);
5803 else
5804 cte->entry = ROM32(entry[0]);
f66fa771 5805
6ee73861 5806 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 5807 cte->index2 = (cte->entry & 0x00000f00) >> 8;
6ee73861
BS		 5808 switch (cte->entry & 0x00033000) {
5809 case 0x00001000:
5810 cte->gpio_tag = 0x07;
5811 break;
5812 case 0x00002000:
5813 cte->gpio_tag = 0x08;
5814 break;
5815 case 0x00010000:
5816 cte->gpio_tag = 0x51;
5817 break;
5818 case 0x00020000:
5819 cte->gpio_tag = 0x52;
5820 break;
5821 default:
5822 cte->gpio_tag = 0xff;
5823 break;
5824 }
5825
5826 if (cte->type == 0xff)
5827 continue;
5828
53c44c3a
BS		 5829 apply_dcb_connector_quirks(bios, i);
5830
6ee73861
BS		 5831 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5832 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 5833
5834 /* check for known types, fallback to guessing the type
5835 * from attached encoders if we hit an unknown.
5836 */
5837 switch (cte->type) {
5838 case DCB_CONNECTOR_VGA:
5839 case DCB_CONNECTOR_TV_0:
5840 case DCB_CONNECTOR_TV_1:
5841 case DCB_CONNECTOR_TV_3:
5842 case DCB_CONNECTOR_DVI_I:
5843 case DCB_CONNECTOR_DVI_D:
5844 case DCB_CONNECTOR_LVDS:
5845 case DCB_CONNECTOR_DP:
5846 case DCB_CONNECTOR_eDP:
5847 case DCB_CONNECTOR_HDMI_0:
5848 case DCB_CONNECTOR_HDMI_1:
5849 break;
5850 default:
5851 cte->type = divine_connector_type(bios, cte->index);
da647d5b 5852 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 5853 break;
5854 }
5855
da647d5b
BS		 5856 if (nouveau_override_conntype) {
5857 int type = divine_connector_type(bios, cte->index);
5858 if (type != cte->type)
5859 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
5860 }
5861
6ee73861
BS		 5862 }
5863}
5864
7f245b20 5865static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5866{
5867 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5868
5869 memset(entry, 0, sizeof(struct dcb_entry));
5870 entry->index = dcb->entries++;
5871
5872 return entry;
5873}
5874
7f245b20 5875static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads)
6ee73861
BS		 5876{
5877 struct dcb_entry *entry = new_dcb_entry(dcb);
5878
5879 entry->type = 0;
5880 entry->i2c_index = i2c;
5881 entry->heads = heads;
5882 entry->location = DCB_LOC_ON_CHIP;
5883 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5884}
5885
7f245b20 5886static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5887{
5888 struct dcb_entry *entry = new_dcb_entry(dcb);
5889
5890 entry->type = 2;
5891 entry->i2c_index = LEGACY_I2C_PANEL;
5892 entry->heads = twoHeads ? 3 : 1;
5893 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5894 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5895 entry->duallink_possible = false; /* SiI164 and co. are single link */
5896
5897#if 0
5898 /*
5899 * For dvi-a either crtc probably works, but my card appears to only
5900 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5901 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5902 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5903 * the monitor picks up the mode res ok and lights up, but no pixel
5904 * data appears, so the board manufacturer probably connected up the
5905 * sync lines, but missed the video traces / components
5906 *
5907 * with this introduction, dvi-a left as an exercise for the reader.
5908 */
5909 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5910#endif
5911}
5912
7f245b20 5913static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5914{
5915 struct dcb_entry *entry = new_dcb_entry(dcb);
5916
5917 entry->type = 1;
5918 entry->i2c_index = LEGACY_I2C_TV;
5919 entry->heads = twoHeads ? 3 : 1;
5920 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5921}
5922
5923static bool
7f245b20 5924parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5925 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5926{
5927 entry->type = conn & 0xf;
5928 entry->i2c_index = (conn >> 4) & 0xf;
5929 entry->heads = (conn >> 8) & 0xf;
7f245b20 5930 if (dcb->version >= 0x40)
6ee73861
BS		 5931 entry->connector = (conn >> 12) & 0xf;
5932 entry->bus = (conn >> 16) & 0xf;
5933 entry->location = (conn >> 20) & 0x3;
5934 entry->or = (conn >> 24) & 0xf;
6ee73861
BS		 5935
5936 switch (entry->type) {
5937 case OUTPUT_ANALOG:
5938 /*
5939 * Although the rest of a CRT conf dword is usually
5940 * zeros, mac biosen have stuff there so we must mask
5941 */
7f245b20 5942 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5943 (conf & 0xffff) * 10 :
5944 (conf & 0xff) * 10000;
5945 break;
5946 case OUTPUT_LVDS:
5947 {
5948 uint32_t mask;
5949 if (conf & 0x1)
5950 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5951 if (dcb->version < 0x22) {
6ee73861
BS		 5952 mask = ~0xd;
5953 /*
5954 * The laptop in bug 14567 lies and claims to not use
5955 * straps when it does, so assume all DCB 2.0 laptops
5956 * use straps, until a broken EDID using one is produced
5957 */
5958 entry->lvdsconf.use_straps_for_mode = true;
5959 /*
5960 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5961 * mean the same thing (probably wrong, but might work)
5962 */
5963 if (conf & 0x4 || conf & 0x8)
5964 entry->lvdsconf.use_power_scripts = true;
5965 } else {
a6ed76d7
BS		 5966 mask = ~0x7;
5967 if (conf & 0x2)
5968 entry->lvdsconf.use_acpi_for_edid = true;
6ee73861
BS		 5969 if (conf & 0x4)
5970 entry->lvdsconf.use_power_scripts = true;
c5875470 5971 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6ee73861
BS		 5972 }
5973 if (conf & mask) {
5974 /*
5975 * Until we even try to use these on G8x, it's
5976 * useless reporting unknown bits. They all are.
5977 */
7f245b20 5978 if (dcb->version >= 0x40)
6ee73861
BS		 5979 break;
5980
5981 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5982 "please report\n");
5983 }
5984 break;
5985 }
5986 case OUTPUT_TV:
5987 {
7f245b20 5988 if (dcb->version >= 0x30)
6ee73861
BS		 5989 entry->tvconf.has_component_output = conf & (0x8 << 4);
5990 else
5991 entry->tvconf.has_component_output = false;
5992
5993 break;
5994 }
5995 case OUTPUT_DP:
5996 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5997 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5998 switch ((conf & 0x0f000000) >> 24) {
5999 case 0xf:
6000 entry->dpconf.link_nr = 4;
6001 break;
6002 case 0x3:
6003 entry->dpconf.link_nr = 2;
6004 break;
6005 default:
6006 entry->dpconf.link_nr = 1;
6007 break;
6008 }
6009 break;
6010 case OUTPUT_TMDS:
4a9f822f
FJ		 6011 if (dcb->version >= 0x22)
6012 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
6013 else if (dcb->version >= 0x30)
6014 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
6015 else if (dcb->version >= 0x40)
6016 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
6017
6ee73861
BS		 6018 break;
6019 case 0xe:
6020 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 6021 dcb->entries--;
6ee73861 6022 return false;
e7cc51c5
BS		 6023 default:
6024 break;
6ee73861
BS		 6025 }
6026
23484874
BS		 6027 if (dcb->version < 0x40) {
6028 /* Normal entries consist of a single bit, but dual link has
6029 * the next most significant bit set too
6030 */
6031 entry->duallink_possible =
6032 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
6033 } else {
6034 entry->duallink_possible = (entry->sorconf.link == 3);
6035 }
6036
6ee73861
BS		 6037 /* unsure what DCB version introduces this, 3.0? */
6038 if (conf & 0x100000)
6039 entry->i2c_upper_default = true;
6040
6041 return true;
6042}
6043
6044static bool
7f245b20 6045parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6046 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6047{
b0d2de86
BS		 6048 switch (conn & 0x0000000f) {
6049 case 0:
6050 entry->type = OUTPUT_ANALOG;
6051 break;
6052 case 1:
6053 entry->type = OUTPUT_TV;
6054 break;
6055 case 2:
6056 case 3:
6ee73861 6057 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 6058 break;
6059 case 4:
6060 switch ((conn & 0x000000f0) >> 4) {
6061 case 0:
6ee73861 6062 entry->type = OUTPUT_TMDS;
b0d2de86
BS		 6063 break;
6064 case 1:
6065 entry->type = OUTPUT_LVDS;
6066 break;
6067 default:
6068 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
6069 (conn & 0x000000f0) >> 4);
6070 return false;
6071 }
6072 break;
6073 default:
6074 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
6075 return false;
6ee73861 6076 }
b0d2de86
BS		 6077
6078 entry->i2c_index = (conn & 0x0003c000) >> 14;
6079 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
6080 entry->or = entry->heads; /* same as heads, hopefully safe enough */
6081 entry->location = (conn & 0x01e00000) >> 21;
6082 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 6083 entry->duallink_possible = false;
6084
6085 switch (entry->type) {
6086 case OUTPUT_ANALOG:
6087 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
6088 break;
b0d2de86
BS		 6089 case OUTPUT_TV:
6090 entry->tvconf.has_component_output = false;
6ee73861 6091 break;
b0d2de86
BS		 6092 case OUTPUT_LVDS:
6093 if ((conn & 0x00003f00) != 0x10)
6094 entry->lvdsconf.use_straps_for_mode = true;
6095 entry->lvdsconf.use_power_scripts = true;
6096 break;
6097 default:
6ee73861
BS		 6098 break;
6099 }
6100
6101 return true;
6102}
6103
7f245b20 6104static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6105 uint32_t conn, uint32_t conf)
6106{
7f245b20 6107 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 6108 bool ret;
6109
7f245b20
BS		 6110 if (dcb->version >= 0x20)
6111 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 6112 else
7f245b20 6113 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 6114 if (!ret)
6115 return ret;
6116
7f245b20
BS		 6117 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6118 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 6119
6120 return true;
6121}
6122
6123static
7f245b20 6124void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 6125{
6126 /*
6127 * DCB v2.0 lists each output combination separately.
6128 * Here we merge compatible entries to have fewer outputs, with
6129 * more options
6130 */
6131
6132 int i, newentries = 0;
6133
6134 for (i = 0; i < dcb->entries; i++) {
6135 struct dcb_entry *ient = &dcb->entry[i];
6136 int j;
6137
6138 for (j = i + 1; j < dcb->entries; j++) {
6139 struct dcb_entry *jent = &dcb->entry[j];
6140
6141 if (jent->type == 100) /* already merged entry */
6142 continue;
6143
6144 /* merge heads field when all other fields the same */
6145 if (jent->i2c_index == ient->i2c_index &&
6146 jent->type == ient->type &&
6147 jent->location == ient->location &&
6148 jent->or == ient->or) {
6149 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
6150 i, j);
6151 ient->heads |= jent->heads;
6152 jent->type = 100; /* dummy value */
6153 }
6154 }
6155 }
6156
6157 /* Compact entries merged into others out of dcb */
6158 for (i = 0; i < dcb->entries; i++) {
6159 if (dcb->entry[i].type == 100)
6160 continue;
6161
6162 if (newentries != i) {
6163 dcb->entry[newentries] = dcb->entry[i];
6164 dcb->entry[newentries].index = newentries;
6165 }
6166 newentries++;
6167 }
6168
6169 dcb->entries = newentries;
6170}
6171
df4cf1b7
BS		 6172static bool
6173apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6174{
6175 /* Dell Precision M6300
6176 * DCB entry 2: 02025312 00000010
6177 * DCB entry 3: 02026312 00000020
6178 *
6179 * Identical, except apparently a different connector on a
6180 * different SOR link. Not a clue how we're supposed to know
6181 * which one is in use if it even shares an i2c line...
6182 *
6183 * Ignore the connector on the second SOR link to prevent
6184 * nasty problems until this is sorted (assuming it's not a
6185 * VBIOS bug).
6186 */
6187 if ((dev->pdev->device == 0x040d) &&
6188 (dev->pdev->subsystem_vendor == 0x1028) &&
6189 (dev->pdev->subsystem_device == 0x019b)) {
6190 if (*conn == 0x02026312 && *conf == 0x00000020)
6191 return false;
6192 }
6193
6194 return true;
6195}
6196
ed42f824
BS		 6197static int
6198parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6ee73861 6199{
ed42f824 6200 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 6201 struct dcb_table *dcb = &bios->dcb;
ed42f824 6202 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 6203 uint8_t *dcbtable;
6204 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
6205 bool configblock = true;
6206 int recordlength = 8, confofs = 4;
6207 int i;
6208
6ee73861 6209 /* get the offset from 0x36 */
ed42f824
BS		 6210 if (dev_priv->card_type > NV_04) {
6211 dcbptr = ROM16(bios->data[0x36]);
6212 if (dcbptr == 0x0000)
6213 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
6214 }
6ee73861 6215
ed42f824 6216 /* this situation likely means a really old card, pre DCB */
6ee73861 6217 if (dcbptr == 0x0) {
ed42f824 6218 NV_INFO(dev, "Assuming a CRT output exists\n");
6ee73861
BS		 6219 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
6220
ed42f824 6221 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6ee73861
BS		 6222 fabricate_tv_output(dcb, twoHeads);
6223
6224 return 0;
6225 }
6226
6227 dcbtable = &bios->data[dcbptr];
6228
6229 /* get DCB version */
7f245b20 6230 dcb->version = dcbtable[0];
6ee73861 6231 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 6232 dcb->version >> 4, dcb->version & 0xf);
6ee73861 6233
7f245b20 6234 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 6235 uint32_t sig;
6236
7f245b20 6237 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 6238 headerlen = dcbtable[1];
6239 entries = dcbtable[2];
6240 recordlength = dcbtable[3];
6241 i2ctabptr = ROM16(dcbtable[4]);
6242 sig = ROM32(dcbtable[6]);
7f245b20
BS		 6243 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
6244 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 6245 } else {
6246 i2ctabptr = ROM16(dcbtable[2]);
6247 sig = ROM32(dcbtable[4]);
6248 headerlen = 8;
6249 }
6250
6251 if (sig != 0x4edcbdcb) {
6252 NV_ERROR(dev, "Bad Display Configuration Block "
6253 "signature (%08X)\n", sig);
6254 return -EINVAL;
6255 }
7f245b20 6256 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 6257 char sig[8] = { 0 };
6258
6259 strncpy(sig, (char *)&dcbtable[-7], 7);
6260 i2ctabptr = ROM16(dcbtable[2]);
6261 recordlength = 10;
6262 confofs = 6;
6263
6264 if (strcmp(sig, "DEV_REC")) {
6265 NV_ERROR(dev, "Bad Display Configuration Block "
6266 "signature (%s)\n", sig);
6267 return -EINVAL;
6268 }
6269 } else {
6270 /*
6271 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
6272 * has the same single (crt) entry, even when tv-out present, so
6273 * the conclusion is this version cannot really be used.
6274 * v1.2 tables (some NV6/10, and NV15+) normally have the same
6275 * 5 entries, which are not specific to the card and so no use.
6276 * v1.2 does have an I2C table that read_dcb_i2c_table can
6277 * handle, but cards exist (nv11 in #14821) with a bad i2c table
6278 * pointer, so use the indices parsed in parse_bmp_structure.
6279 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
6280 */
6281 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
6282 "adding all possible outputs\n");
6283 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
6284
6285 /*
6286 * Attempt to detect TV before DVI because the test
6287 * for the former is more accurate and it rules the
6288 * latter out.
6289 */
6290 if (nv04_tv_identify(dev,
6291 bios->legacy.i2c_indices.tv) >= 0)
6292 fabricate_tv_output(dcb, twoHeads);
6293
6294 else if (bios->tmds.output0_script_ptr ||
6295 bios->tmds.output1_script_ptr)
6296 fabricate_dvi_i_output(dcb, twoHeads);
6297
6298 return 0;
6299 }
6300
6301 if (!i2ctabptr)
6302 NV_WARN(dev, "No pointer to DCB I2C port table\n");
6303 else {
7f245b20
BS		 6304 dcb->i2c_table = &bios->data[i2ctabptr];
6305 if (dcb->version >= 0x30)
6306 dcb->i2c_default_indices = dcb->i2c_table[4];
4a9f822f
FJ		 6307
6308 /*
6309 * Parse the "management" I2C bus, used for hardware
6310 * monitoring and some external TMDS transmitters.
6311 */
6312 if (dcb->version >= 0x22) {
6313 int idx = (dcb->version >= 0x40 ?
6314 dcb->i2c_default_indices & 0xf :
6315 2);
6316
6317 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6318 idx, &dcb->i2c[idx]);
6319 }
6ee73861
BS		 6320 }
6321
6ee73861
BS		 6322 if (entries > DCB_MAX_NUM_ENTRIES)
6323 entries = DCB_MAX_NUM_ENTRIES;
6324
6325 for (i = 0; i < entries; i++) {
6326 uint32_t connection, config = 0;
6327
6328 connection = ROM32(dcbtable[headerlen + recordlength * i]);
6329 if (configblock)
6330 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
6331
6332 /* seen on an NV11 with DCB v1.5 */
6333 if (connection == 0x00000000)
6334 break;
6335
6336 /* seen on an NV17 with DCB v2.0 */
6337 if (connection == 0xffffffff)
6338 break;
6339
6340 if ((connection & 0x0000000f) == 0x0000000f)
6341 continue;
6342
df4cf1b7
BS		 6343 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config))
6344 continue;
6345
6ee73861
BS		 6346 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
6347 dcb->entries, connection, config);
6348
7f245b20 6349 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 6350 break;
6351 }
6352
6353 /*
6354 * apart for v2.1+ not being known for requiring merging, this
6355 * guarantees dcbent->index is the index of the entry in the rom image
6356 */
7f245b20 6357 if (dcb->version < 0x21)
6ee73861
BS		 6358 merge_like_dcb_entries(dev, dcb);
6359
54abb5dd
BS		 6360 if (!dcb->entries)
6361 return -ENXIO;
6362
6363 parse_dcb_gpio_table(bios);
6364 parse_dcb_connector_table(bios);
6365 return 0;
6ee73861
BS		 6366}
6367
6368static void
6369fixup_legacy_connector(struct nvbios *bios)
6370{
7f245b20 6371 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 6372 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 6373
6374 /*
6375 * DCB 3.0 also has the table in most cases, but there are some cards
6376 * where the table is filled with stub entries, and the DCB entriy
6377 * indices are all 0. We don't need the connector indices on pre-G80
6378 * chips (yet?) so limit the use to DCB 4.0 and above.
6379 */
7f245b20 6380 if (dcb->version >= 0x40)
6ee73861
BS		 6381 return;
6382
dc5bc4ed
BS		 6383 dcb->connector.entries = 0;
6384
6ee73861
BS		 6385 /*
6386 * No known connector info before v3.0, so make it up. the rule here
6387 * is: anything on the same i2c bus is considered to be on the same
6388 * connector. any output without an associated i2c bus is assigned
6389 * its own unique connector index.
6390 */
6391 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 6392 /*
6393 * Ignore the I2C index for on-chip TV-out, as there
6394 * are cards with bogus values (nv31m in bug 23212),
6395 * and it's otherwise useless.
6396 */
6397 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 6398 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 6399 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 6400 i2c = dcb->entry[i].i2c_index;
6401
6402 if (i2c_conn[i2c]) {
6403 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 6404 continue;
6405 }
6406
dc5bc4ed
BS		 6407 dcb->entry[i].connector = dcb->connector.entries++;
6408 if (i2c != 0xf)
6409 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 6410 }
6411
dc5bc4ed
BS		 6412 /* Fake the connector table as well as just connector indices */
6413 for (i = 0; i < dcb->connector.entries; i++) {
6414 dcb->connector.entry[i].index = i;
6415 dcb->connector.entry[i].type = divine_connector_type(bios, i);
6416 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 6417 }
6418}
6419
6420static void
6421fixup_legacy_i2c(struct nvbios *bios)
6422{
7f245b20 6423 struct dcb_table *dcb = &bios->dcb;
6ee73861
BS		 6424 int i;
6425
6426 for (i = 0; i < dcb->entries; i++) {
6427 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
6428 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
6429 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
6430 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
6431 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
6432 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
6433 }
6434}
6435
6436static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6437{
6438 /*
6439 * The header following the "HWSQ" signature has the number of entries,
6440 * and the entry size
6441 *
6442 * An entry consists of a dword to write to the sequencer control reg
6443 * (0x00001304), followed by the ucode bytes, written sequentially,
6444 * starting at reg 0x00001400
6445 */
6446
6447 uint8_t bytes_to_write;
6448 uint16_t hwsq_entry_offset;
6449 int i;
6450
6451 if (bios->data[hwsq_offset] <= entry) {
6452 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6453 "requested entry\n");
6454 return -ENOENT;
6455 }
6456
6457 bytes_to_write = bios->data[hwsq_offset + 1];
6458
6459 if (bytes_to_write != 36) {
6460 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6461 return -EINVAL;
6462 }
6463
6464 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6465
6466 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6467
6468 /* set sequencer control */
6469 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6470 bytes_to_write -= 4;
6471
6472 /* write ucode */
6473 for (i = 0; i < bytes_to_write; i += 4)
6474 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6475
6476 /* twiddle NV_PBUS_DEBUG_4 */
6477 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6478
6479 return 0;
6480}
6481
6482static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6483 struct nvbios *bios)
6484{
6485 /*
6486 * BMP based cards, from NV17, need a microcode loading to correctly
6487 * control the GPIO etc for LVDS panels
6488 *
6489 * BIT based cards seem to do this directly in the init scripts
6490 *
6491 * The microcode entries are found by the "HWSQ" signature.
6492 */
6493
6494 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6495 const int sz = sizeof(hwsq_signature);
6496 int hwsq_offset;
6497
6498 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6499 if (!hwsq_offset)
6500 return 0;
6501
6502 /* always use entry 0? */
6503 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6504}
6505
6506uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6507{
6508 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6509 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6510 const uint8_t edid_sig[] = {
6511 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6512 uint16_t offset = 0;
6513 uint16_t newoffset;
6514 int searchlen = NV_PROM_SIZE;
6515
6516 if (bios->fp.edid)
6517 return bios->fp.edid;
6518
6519 while (searchlen) {
6520 newoffset = findstr(&bios->data[offset], searchlen,
6521 edid_sig, 8);
6522 if (!newoffset)
6523 return NULL;
6524 offset += newoffset;
6525 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6526 break;
6527
6528 searchlen -= offset;
6529 offset++;
6530 }
6531
6532 NV_TRACE(dev, "Found EDID in BIOS\n");
6533
6534 return bios->fp.edid = &bios->data[offset];
6535}
6536
6537void
6538nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6539 struct dcb_entry *dcbent)
6540{
6541 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6542 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6543 struct init_exec iexec = { true, false };
6544
d9184fa9 6545 mutex_lock(&bios->lock);
6ee73861
BS		 6546 bios->display.output = dcbent;
6547 parse_init_table(bios, table, &iexec);
6548 bios->display.output = NULL;
d9184fa9 6549 mutex_unlock(&bios->lock);
6ee73861
BS		 6550}
6551
6552static bool NVInitVBIOS(struct drm_device *dev)
6553{
6554 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6555 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6556
6557 memset(bios, 0, sizeof(struct nvbios));
d9184fa9 6558 mutex_init(&bios->lock);
6ee73861
BS		 6559 bios->dev = dev;
6560
6561 if (!NVShadowVBIOS(dev, bios->data))
6562 return false;
6563
6564 bios->length = NV_PROM_SIZE;
6565 return true;
6566}
6567
6568static int nouveau_parse_vbios_struct(struct drm_device *dev)
6569{
6570 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6571 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6572 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6573 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6574 int offset;
6575
6576 offset = findstr(bios->data, bios->length,
6577 bit_signature, sizeof(bit_signature));
6578 if (offset) {
6579 NV_TRACE(dev, "BIT BIOS found\n");
6580 return parse_bit_structure(bios, offset + 6);
6581 }
6582
6583 offset = findstr(bios->data, bios->length,
6584 bmp_signature, sizeof(bmp_signature));
6585 if (offset) {
6586 NV_TRACE(dev, "BMP BIOS found\n");
6587 return parse_bmp_structure(dev, bios, offset);
6588 }
6589
6590 NV_ERROR(dev, "No known BIOS signature found\n");
6591 return -ENODEV;
6592}
6593
6594int
6595nouveau_run_vbios_init(struct drm_device *dev)
6596{
6597 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6598 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6599 int i, ret = 0;
6600
946fd35f
FJ		 6601 /* Reset the BIOS head to 0. */
6602 bios->state.crtchead = 0;
6ee73861
BS		 6603
6604 if (bios->major_version < 5) /* BMP only */
6605 load_nv17_hw_sequencer_ucode(dev, bios);
6606
6607 if (bios->execute) {
6608 bios->fp.last_script_invoc = 0;
6609 bios->fp.lvds_init_run = false;
6610 }
6611
6612 parse_init_tables(bios);
6613
6614 /*
6615 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6616 * parser will run this right after the init tables, the binary
6617 * driver appears to run it at some point later.
6618 */
6619 if (bios->some_script_ptr) {
6620 struct init_exec iexec = {true, false};
6621
6622 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6623 bios->some_script_ptr);
6624 parse_init_table(bios, bios->some_script_ptr, &iexec);
6625 }
6626
6627 if (dev_priv->card_type >= NV_50) {
7f245b20 6628 for (i = 0; i < bios->dcb.entries; i++) {
6ee73861 6629 nouveau_bios_run_display_table(dev,
7f245b20 6630 &bios->dcb.entry[i],
6ee73861
BS		 6631 0, 0);
6632 }
6633 }
6634
6ee73861
BS		 6635 return ret;
6636}
6637
6638static void
6639nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6640{
6641 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6642 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6643 struct dcb_i2c_entry *entry;
6644 int i;
6645
7f245b20 6646 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6647 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6648 nouveau_i2c_fini(dev, entry);
6649}
6650
d13102c6
BS		 6651static bool
6652nouveau_bios_posted(struct drm_device *dev)
6653{
6654 struct drm_nouveau_private *dev_priv = dev->dev_private;
d13102c6
BS		 6655 unsigned htotal;
6656
6657 if (dev_priv->chipset >= NV_50) {
6658 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6659 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6660 return false;
6661 return true;
6662 }
6663
d13102c6
BS		 6664 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6665 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6666 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6667 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6668 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
03cd06ca 6669
d13102c6
BS		 6670 return (htotal != 0);
6671}
6672
6ee73861
BS		 6673int
6674nouveau_bios_init(struct drm_device *dev)
6675{
6676 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6677 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6678 int ret;
6679
6ee73861
BS		 6680 if (!NVInitVBIOS(dev))
6681 return -ENODEV;
6682
6683 ret = nouveau_parse_vbios_struct(dev);
6684 if (ret)
6685 return ret;
6686
6687 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6688 if (ret)
6689 return ret;
6690
6691 fixup_legacy_i2c(bios);
6692 fixup_legacy_connector(bios);
6693
6694 if (!bios->major_version) /* we don't run version 0 bios */
6695 return 0;
6696
6ee73861
BS		 6697 /* init script execution disabled */
6698 bios->execute = false;
6699
6700 /* ... unless card isn't POSTed already */
d13102c6 6701 if (!nouveau_bios_posted(dev)) {
67eda20e
FJ		 6702 NV_INFO(dev, "Adaptor not initialised, "
6703 "running VBIOS init tables.\n");
6ee73861
BS		 6704 bios->execute = true;
6705 }
6706
6ee73861 6707 ret = nouveau_run_vbios_init(dev);
04a39c57 6708 if (ret)
6ee73861 6709 return ret;
6ee73861
BS		 6710
6711 /* feature_byte on BMP is poor, but init always sets CR4B */
6ee73861
BS		 6712 if (bios->major_version < 5)
6713 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6714
6715 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6716 if (bios->is_mobile || bios->major_version >= 5)
6717 ret = parse_fp_mode_table(dev, bios);
6ee73861
BS		 6718
6719 /* allow subsequent scripts to execute */
6720 bios->execute = true;
6721
6722 return 0;
6723}
6724
6725void
6726nouveau_bios_takedown(struct drm_device *dev)
6727{
6728 nouveau_bios_i2c_devices_takedown(dev);
6729}
Clone of davem's net-next-2.6 tree