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6ee73861 BS |
1 | /* |
2 | * Copyright 2005-2006 Erik Waling | |
3 | * Copyright 2006 Stephane Marchesin | |
4 | * Copyright 2007-2009 Stuart Bennett | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
20 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF | |
21 | * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
22 | * SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "drmP.h" | |
26 | #define NV_DEBUG_NOTRACE | |
27 | #include "nouveau_drv.h" | |
28 | #include "nouveau_hw.h" | |
25908b77 | 29 | #include "nouveau_encoder.h" |
6ee73861 | 30 | |
67eda20e FJ |
31 | #include <linux/io-mapping.h> |
32 | ||
6ee73861 BS |
33 | /* these defines are made up */ |
34 | #define NV_CIO_CRE_44_HEADA 0x0 | |
35 | #define NV_CIO_CRE_44_HEADB 0x3 | |
36 | #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ | |
37 | #define LEGACY_I2C_CRT 0x80 | |
38 | #define LEGACY_I2C_PANEL 0x81 | |
39 | #define LEGACY_I2C_TV 0x82 | |
40 | ||
41 | #define EDID1_LEN 128 | |
42 | ||
43 | #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) | |
44 | #define LOG_OLD_VALUE(x) | |
45 | ||
46 | #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) | |
47 | #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) | |
48 | ||
49 | struct init_exec { | |
50 | bool execute; | |
51 | bool repeat; | |
52 | }; | |
53 | ||
54 | static bool nv_cksum(const uint8_t *data, unsigned int length) | |
55 | { | |
56 | /* | |
57 | * There's a few checksums in the BIOS, so here's a generic checking | |
58 | * function. | |
59 | */ | |
60 | int i; | |
61 | uint8_t sum = 0; | |
62 | ||
63 | for (i = 0; i < length; i++) | |
64 | sum += data[i]; | |
65 | ||
66 | if (sum) | |
67 | return true; | |
68 | ||
69 | return false; | |
70 | } | |
71 | ||
72 | static int | |
73 | score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) | |
74 | { | |
75 | if (!(data[0] == 0x55 && data[1] == 0xAA)) { | |
76 | NV_TRACEWARN(dev, "... BIOS signature not found\n"); | |
77 | return 0; | |
78 | } | |
79 | ||
80 | if (nv_cksum(data, data[2] * 512)) { | |
81 | NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); | |
82 | /* if a ro image is somewhat bad, it's probably all rubbish */ | |
83 | return writeable ? 2 : 1; | |
84 | } else | |
85 | NV_TRACE(dev, "... appears to be valid\n"); | |
86 | ||
87 | return 3; | |
88 | } | |
89 | ||
90 | static void load_vbios_prom(struct drm_device *dev, uint8_t *data) | |
91 | { | |
92 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
93 | uint32_t pci_nv_20, save_pci_nv_20; | |
94 | int pcir_ptr; | |
95 | int i; | |
96 | ||
97 | if (dev_priv->card_type >= NV_50) | |
98 | pci_nv_20 = 0x88050; | |
99 | else | |
100 | pci_nv_20 = NV_PBUS_PCI_NV_20; | |
101 | ||
102 | /* enable ROM access */ | |
103 | save_pci_nv_20 = nvReadMC(dev, pci_nv_20); | |
104 | nvWriteMC(dev, pci_nv_20, | |
105 | save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); | |
106 | ||
107 | /* bail if no rom signature */ | |
108 | if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || | |
109 | nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) | |
110 | goto out; | |
111 | ||
112 | /* additional check (see note below) - read PCI record header */ | |
113 | pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | | |
114 | nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; | |
115 | if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || | |
116 | nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || | |
117 | nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || | |
118 | nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') | |
119 | goto out; | |
120 | ||
121 | /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a | |
122 | * a good read may be obtained by waiting or re-reading (cargocult: 5x) | |
123 | * each byte. we'll hope pramin has something usable instead | |
124 | */ | |
125 | for (i = 0; i < NV_PROM_SIZE; i++) | |
126 | data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); | |
127 | ||
128 | out: | |
129 | /* disable ROM access */ | |
130 | nvWriteMC(dev, pci_nv_20, | |
131 | save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); | |
132 | } | |
133 | ||
134 | static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) | |
135 | { | |
136 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
137 | uint32_t old_bar0_pramin = 0; | |
138 | int i; | |
139 | ||
140 | if (dev_priv->card_type >= NV_50) { | |
141 | uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8; | |
142 | ||
143 | if (!vbios_vram) | |
144 | vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000; | |
145 | ||
146 | old_bar0_pramin = nv_rd32(dev, 0x1700); | |
147 | nv_wr32(dev, 0x1700, vbios_vram >> 16); | |
148 | } | |
149 | ||
150 | /* bail if no rom signature */ | |
151 | if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || | |
152 | nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) | |
153 | goto out; | |
154 | ||
155 | for (i = 0; i < NV_PROM_SIZE; i++) | |
156 | data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); | |
157 | ||
158 | out: | |
159 | if (dev_priv->card_type >= NV_50) | |
160 | nv_wr32(dev, 0x1700, old_bar0_pramin); | |
161 | } | |
162 | ||
163 | static void load_vbios_pci(struct drm_device *dev, uint8_t *data) | |
164 | { | |
165 | void __iomem *rom = NULL; | |
166 | size_t rom_len; | |
167 | int ret; | |
168 | ||
169 | ret = pci_enable_rom(dev->pdev); | |
170 | if (ret) | |
171 | return; | |
172 | ||
173 | rom = pci_map_rom(dev->pdev, &rom_len); | |
174 | if (!rom) | |
175 | goto out; | |
176 | memcpy_fromio(data, rom, rom_len); | |
177 | pci_unmap_rom(dev->pdev, rom); | |
178 | ||
179 | out: | |
180 | pci_disable_rom(dev->pdev); | |
181 | } | |
182 | ||
afeb3e11 DA |
183 | static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) |
184 | { | |
185 | int i; | |
186 | int ret; | |
187 | int size = 64 * 1024; | |
188 | ||
189 | if (!nouveau_acpi_rom_supported(dev->pdev)) | |
190 | return; | |
191 | ||
192 | for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { | |
193 | ret = nouveau_acpi_get_bios_chunk(data, | |
194 | (i * ROM_BIOS_PAGE), | |
195 | ROM_BIOS_PAGE); | |
196 | if (ret <= 0) | |
197 | break; | |
198 | } | |
199 | return; | |
200 | } | |
201 | ||
6ee73861 BS |
202 | struct methods { |
203 | const char desc[8]; | |
204 | void (*loadbios)(struct drm_device *, uint8_t *); | |
205 | const bool rw; | |
6ee73861 BS |
206 | }; |
207 | ||
41090eb4 | 208 | static struct methods shadow_methods[] = { |
6ee73861 BS |
209 | { "PRAMIN", load_vbios_pramin, true }, |
210 | { "PROM", load_vbios_prom, false }, | |
211 | { "PCIROM", load_vbios_pci, true }, | |
41090eb4 | 212 | { "ACPI", load_vbios_acpi, true }, |
6ee73861 | 213 | }; |
eae6192a | 214 | #define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods) |
6ee73861 BS |
215 | |
216 | static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) | |
217 | { | |
41090eb4 | 218 | struct methods *methods = shadow_methods; |
6ee73861 | 219 | int testscore = 3; |
eae6192a | 220 | int scores[NUM_SHADOW_METHODS], i; |
6ee73861 BS |
221 | |
222 | if (nouveau_vbios) { | |
eae6192a | 223 | for (i = 0; i < NUM_SHADOW_METHODS; i++) |
657b6245 | 224 | if (!strcasecmp(nouveau_vbios, methods[i].desc)) |
6ee73861 | 225 | break; |
6ee73861 | 226 | |
eae6192a | 227 | if (i < NUM_SHADOW_METHODS) { |
6ee73861 | 228 | NV_INFO(dev, "Attempting to use BIOS image from %s\n", |
657b6245 | 229 | methods[i].desc); |
6ee73861 | 230 | |
657b6245 MK |
231 | methods[i].loadbios(dev, data); |
232 | if (score_vbios(dev, data, methods[i].rw)) | |
6ee73861 BS |
233 | return true; |
234 | } | |
235 | ||
236 | NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); | |
237 | } | |
238 | ||
eae6192a | 239 | for (i = 0; i < NUM_SHADOW_METHODS; i++) { |
6ee73861 | 240 | NV_TRACE(dev, "Attempting to load BIOS image from %s\n", |
657b6245 | 241 | methods[i].desc); |
6ee73861 | 242 | data[0] = data[1] = 0; /* avoid reuse of previous image */ |
657b6245 MK |
243 | methods[i].loadbios(dev, data); |
244 | scores[i] = score_vbios(dev, data, methods[i].rw); | |
245 | if (scores[i] == testscore) | |
6ee73861 | 246 | return true; |
6ee73861 BS |
247 | } |
248 | ||
249 | while (--testscore > 0) { | |
eae6192a | 250 | for (i = 0; i < NUM_SHADOW_METHODS; i++) { |
657b6245 | 251 | if (scores[i] == testscore) { |
6ee73861 | 252 | NV_TRACE(dev, "Using BIOS image from %s\n", |
657b6245 MK |
253 | methods[i].desc); |
254 | methods[i].loadbios(dev, data); | |
6ee73861 BS |
255 | return true; |
256 | } | |
6ee73861 BS |
257 | } |
258 | } | |
259 | ||
260 | NV_ERROR(dev, "No valid BIOS image found\n"); | |
261 | return false; | |
262 | } | |
263 | ||
264 | struct init_tbl_entry { | |
265 | char *name; | |
266 | uint8_t id; | |
9170a824 BS |
267 | /* Return: |
268 | * > 0: success, length of opcode | |
269 | * 0: success, but abort further parsing of table (INIT_DONE etc) | |
270 | * < 0: failure, table parsing will be aborted | |
271 | */ | |
37383650 | 272 | int (*handler)(struct nvbios *, uint16_t, struct init_exec *); |
6ee73861 BS |
273 | }; |
274 | ||
275 | struct bit_entry { | |
276 | uint8_t id[2]; | |
277 | uint16_t length; | |
278 | uint16_t offset; | |
279 | }; | |
280 | ||
281 | static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); | |
282 | ||
283 | #define MACRO_INDEX_SIZE 2 | |
284 | #define MACRO_SIZE 8 | |
285 | #define CONDITION_SIZE 12 | |
286 | #define IO_FLAG_CONDITION_SIZE 9 | |
287 | #define IO_CONDITION_SIZE 5 | |
288 | #define MEM_INIT_SIZE 66 | |
289 | ||
290 | static void still_alive(void) | |
291 | { | |
292 | #if 0 | |
293 | sync(); | |
294 | msleep(2); | |
295 | #endif | |
296 | } | |
297 | ||
298 | static uint32_t | |
299 | munge_reg(struct nvbios *bios, uint32_t reg) | |
300 | { | |
301 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | |
302 | struct dcb_entry *dcbent = bios->display.output; | |
303 | ||
304 | if (dev_priv->card_type < NV_50) | |
305 | return reg; | |
306 | ||
307 | if (reg & 0x40000000) { | |
308 | BUG_ON(!dcbent); | |
309 | ||
310 | reg += (ffs(dcbent->or) - 1) * 0x800; | |
311 | if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) | |
312 | reg += 0x00000080; | |
313 | } | |
314 | ||
315 | reg &= ~0x60000000; | |
316 | return reg; | |
317 | } | |
318 | ||
319 | static int | |
320 | valid_reg(struct nvbios *bios, uint32_t reg) | |
321 | { | |
322 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | |
323 | struct drm_device *dev = bios->dev; | |
324 | ||
325 | /* C51 has misaligned regs on purpose. Marvellous */ | |
9855e584 | 326 | if (reg & 0x2 || |
04a39c57 | 327 | (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) |
9855e584 BS |
328 | NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); |
329 | ||
330 | /* warn on C51 regs that haven't been verified accessible in tracing */ | |
04a39c57 | 331 | if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && |
6ee73861 BS |
332 | reg != 0x130d && reg != 0x1311 && reg != 0x60081d) |
333 | NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", | |
334 | reg); | |
335 | ||
9855e584 BS |
336 | if (reg >= (8*1024*1024)) { |
337 | NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); | |
338 | return 0; | |
6ee73861 | 339 | } |
9855e584 BS |
340 | |
341 | return 1; | |
6ee73861 BS |
342 | } |
343 | ||
344 | static bool | |
345 | valid_idx_port(struct nvbios *bios, uint16_t port) | |
346 | { | |
347 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | |
348 | struct drm_device *dev = bios->dev; | |
349 | ||
350 | /* | |
351 | * If adding more ports here, the read/write functions below will need | |
352 | * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is | |
353 | * used for the port in question | |
354 | */ | |
355 | if (dev_priv->card_type < NV_50) { | |
356 | if (port == NV_CIO_CRX__COLOR) | |
357 | return true; | |
358 | if (port == NV_VIO_SRX) | |
359 | return true; | |
360 | } else { | |
361 | if (port == NV_CIO_CRX__COLOR) | |
362 | return true; | |
363 | } | |
364 | ||
365 | NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", | |
366 | port); | |
367 | ||
368 | return false; | |
369 | } | |
370 | ||
371 | static bool | |
372 | valid_port(struct nvbios *bios, uint16_t port) | |
373 | { | |
374 | struct drm_device *dev = bios->dev; | |
375 | ||
376 | /* | |
377 | * If adding more ports here, the read/write functions below will need | |
378 | * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is | |
379 | * used for the port in question | |
380 | */ | |
381 | if (port == NV_VIO_VSE2) | |
382 | return true; | |
383 | ||
384 | NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); | |
385 | ||
386 | return false; | |
387 | } | |
388 | ||
389 | static uint32_t | |
390 | bios_rd32(struct nvbios *bios, uint32_t reg) | |
391 | { | |
392 | uint32_t data; | |
393 | ||
394 | reg = munge_reg(bios, reg); | |
395 | if (!valid_reg(bios, reg)) | |
396 | return 0; | |
397 | ||
398 | /* | |
399 | * C51 sometimes uses regs with bit0 set in the address. For these | |
400 | * cases there should exist a translation in a BIOS table to an IO | |
401 | * port address which the BIOS uses for accessing the reg | |
402 | * | |
403 | * These only seem to appear for the power control regs to a flat panel, | |
404 | * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs | |
405 | * for 0x1308 and 0x1310 are used - hence the mask below. An S3 | |
406 | * suspend-resume mmio trace from a C51 will be required to see if this | |
407 | * is true for the power microcode in 0x14.., or whether the direct IO | |
408 | * port access method is needed | |
409 | */ | |
410 | if (reg & 0x1) | |
411 | reg &= ~0x1; | |
412 | ||
413 | data = nv_rd32(bios->dev, reg); | |
414 | ||
415 | BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); | |
416 | ||
417 | return data; | |
418 | } | |
419 | ||
420 | static void | |
421 | bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) | |
422 | { | |
423 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | |
424 | ||
425 | reg = munge_reg(bios, reg); | |
426 | if (!valid_reg(bios, reg)) | |
427 | return; | |
428 | ||
429 | /* see note in bios_rd32 */ | |
430 | if (reg & 0x1) | |
431 | reg &= 0xfffffffe; | |
432 | ||
433 | LOG_OLD_VALUE(bios_rd32(bios, reg)); | |
434 | BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); | |
435 | ||
04a39c57 | 436 | if (dev_priv->vbios.execute) { |
6ee73861 BS |
437 | still_alive(); |
438 | nv_wr32(bios->dev, reg, data); | |
439 | } | |
440 | } | |
441 | ||
442 | static uint8_t | |
443 | bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) | |
444 | { | |
445 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | |
446 | struct drm_device *dev = bios->dev; | |
447 | uint8_t data; | |
448 | ||
449 | if (!valid_idx_port(bios, port)) | |
450 | return 0; | |
451 | ||
452 | if (dev_priv->card_type < NV_50) { | |
453 | if (port == NV_VIO_SRX) | |
454 | data = NVReadVgaSeq(dev, bios->state.crtchead, index); | |
455 | else /* assume NV_CIO_CRX__COLOR */ | |
456 | data = NVReadVgaCrtc(dev, bios->state.crtchead, index); | |
457 | } else { | |
458 | uint32_t data32; | |
459 | ||
460 | data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); | |
461 | data = (data32 >> ((index & 3) << 3)) & 0xff; | |
462 | } | |
463 | ||
464 | BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " | |
465 | "Head: 0x%02X, Data: 0x%02X\n", | |
466 | port, index, bios->state.crtchead, data); | |
467 | return data; | |
468 | } | |
469 | ||
470 | static void | |
471 | bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) | |
472 | { | |
473 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | |
474 | struct drm_device *dev = bios->dev; | |
475 | ||
476 | if (!valid_idx_port(bios, port)) | |
477 | return; | |
478 | ||
479 | /* | |
480 | * The current head is maintained in the nvbios member state.crtchead. | |
481 | * We trap changes to CR44 and update the head variable and hence the | |
482 | * register set written. | |
483 | * As CR44 only exists on CRTC0, we update crtchead to head0 in advance | |
484 | * of the write, and to head1 after the write | |
485 | */ | |
486 | if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && | |
487 | data != NV_CIO_CRE_44_HEADB) | |
488 | bios->state.crtchead = 0; | |
489 | ||
490 | LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); | |
491 | BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " | |
492 | "Head: 0x%02X, Data: 0x%02X\n", | |
493 | port, index, bios->state.crtchead, data); | |
494 | ||
495 | if (bios->execute && dev_priv->card_type < NV_50) { | |
496 | still_alive(); | |
497 | if (port == NV_VIO_SRX) | |
498 | NVWriteVgaSeq(dev, bios->state.crtchead, index, data); | |
499 | else /* assume NV_CIO_CRX__COLOR */ | |
500 | NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); | |
501 | } else | |
502 | if (bios->execute) { | |
503 | uint32_t data32, shift = (index & 3) << 3; | |
504 | ||
505 | still_alive(); | |
506 | ||
507 | data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); | |
508 | data32 &= ~(0xff << shift); | |
509 | data32 |= (data << shift); | |
510 | bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); | |
511 | } | |
512 | ||
513 | if (port == NV_CIO_CRX__COLOR && | |
514 | index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) | |
515 | bios->state.crtchead = 1; | |
516 | } | |
517 | ||
518 | static uint8_t | |
519 | bios_port_rd(struct nvbios *bios, uint16_t port) | |
520 | { | |
521 | uint8_t data, head = bios->state.crtchead; | |
522 | ||
523 | if (!valid_port(bios, port)) | |
524 | return 0; | |
525 | ||
526 | data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); | |
527 | ||
528 | BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", | |
529 | port, head, data); | |
530 | ||
531 | return data; | |
532 | } | |
533 | ||
534 | static void | |
535 | bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) | |
536 | { | |
537 | int head = bios->state.crtchead; | |
538 | ||
539 | if (!valid_port(bios, port)) | |
540 | return; | |
541 | ||
542 | LOG_OLD_VALUE(bios_port_rd(bios, port)); | |
543 | BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", | |
544 | port, head, data); | |
545 | ||
546 | if (!bios->execute) | |
547 | return; | |
548 | ||
549 | still_alive(); | |
550 | NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); | |
551 | } | |
552 | ||
553 | static bool | |
554 | io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) | |
555 | { | |
556 | /* | |
557 | * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte | |
558 | * for the CRTC index; 1 byte for the mask to apply to the value | |
559 | * retrieved from the CRTC; 1 byte for the shift right to apply to the | |
560 | * masked CRTC value; 2 bytes for the offset to the flag array, to | |
561 | * which the shifted value is added; 1 byte for the mask applied to the | |
562 | * value read from the flag array; and 1 byte for the value to compare | |
563 | * against the masked byte from the flag table. | |
564 | */ | |
565 | ||
566 | uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; | |
567 | uint16_t crtcport = ROM16(bios->data[condptr]); | |
568 | uint8_t crtcindex = bios->data[condptr + 2]; | |
569 | uint8_t mask = bios->data[condptr + 3]; | |
570 | uint8_t shift = bios->data[condptr + 4]; | |
571 | uint16_t flagarray = ROM16(bios->data[condptr + 5]); | |
572 | uint8_t flagarraymask = bios->data[condptr + 7]; | |
573 | uint8_t cmpval = bios->data[condptr + 8]; | |
574 | uint8_t data; | |
575 | ||
576 | BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " | |
577 | "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " | |
578 | "Cmpval: 0x%02X\n", | |
579 | offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); | |
580 | ||
581 | data = bios_idxprt_rd(bios, crtcport, crtcindex); | |
582 | ||
583 | data = bios->data[flagarray + ((data & mask) >> shift)]; | |
584 | data &= flagarraymask; | |
585 | ||
586 | BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", | |
587 | offset, data, cmpval); | |
588 | ||
589 | return (data == cmpval); | |
590 | } | |
591 | ||
592 | static bool | |
593 | bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) | |
594 | { | |
595 | /* | |
596 | * The condition table entry has 4 bytes for the address of the | |
597 | * register to check, 4 bytes for a mask to apply to the register and | |
598 | * 4 for a test comparison value | |
599 | */ | |
600 | ||
601 | uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; | |
602 | uint32_t reg = ROM32(bios->data[condptr]); | |
603 | uint32_t mask = ROM32(bios->data[condptr + 4]); | |
604 | uint32_t cmpval = ROM32(bios->data[condptr + 8]); | |
605 | uint32_t data; | |
606 | ||
607 | BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", | |
608 | offset, cond, reg, mask); | |
609 | ||
610 | data = bios_rd32(bios, reg) & mask; | |
611 | ||
612 | BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", | |
613 | offset, data, cmpval); | |
614 | ||
615 | return (data == cmpval); | |
616 | } | |
617 | ||
618 | static bool | |
619 | io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) | |
620 | { | |
621 | /* | |
622 | * The IO condition entry has 2 bytes for the IO port address; 1 byte | |
623 | * for the index to write to io_port; 1 byte for the mask to apply to | |
624 | * the byte read from io_port+1; and 1 byte for the value to compare | |
625 | * against the masked byte. | |
626 | */ | |
627 | ||
628 | uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; | |
629 | uint16_t io_port = ROM16(bios->data[condptr]); | |
630 | uint8_t port_index = bios->data[condptr + 2]; | |
631 | uint8_t mask = bios->data[condptr + 3]; | |
632 | uint8_t cmpval = bios->data[condptr + 4]; | |
633 | ||
634 | uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; | |
635 | ||
636 | BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", | |
637 | offset, data, cmpval); | |
638 | ||
639 | return (data == cmpval); | |
640 | } | |
641 | ||
642 | static int | |
643 | nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) | |
644 | { | |
645 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
646 | uint32_t reg0 = nv_rd32(dev, reg + 0); | |
647 | uint32_t reg1 = nv_rd32(dev, reg + 4); | |
648 | struct nouveau_pll_vals pll; | |
649 | struct pll_lims pll_limits; | |
650 | int ret; | |
651 | ||
652 | ret = get_pll_limits(dev, reg, &pll_limits); | |
653 | if (ret) | |
654 | return ret; | |
655 | ||
656 | clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); | |
657 | if (!clk) | |
658 | return -ERANGE; | |
659 | ||
660 | reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); | |
661 | reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; | |
662 | ||
04a39c57 | 663 | if (dev_priv->vbios.execute) { |
6ee73861 BS |
664 | still_alive(); |
665 | nv_wr32(dev, reg + 4, reg1); | |
666 | nv_wr32(dev, reg + 0, reg0); | |
667 | } | |
668 | ||
669 | return 0; | |
670 | } | |
671 | ||
672 | static int | |
673 | setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) | |
674 | { | |
675 | struct drm_device *dev = bios->dev; | |
676 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
677 | /* clk in kHz */ | |
678 | struct pll_lims pll_lim; | |
679 | struct nouveau_pll_vals pllvals; | |
680 | int ret; | |
681 | ||
682 | if (dev_priv->card_type >= NV_50) | |
683 | return nv50_pll_set(dev, reg, clk); | |
684 | ||
685 | /* high regs (such as in the mac g5 table) are not -= 4 */ | |
686 | ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); | |
687 | if (ret) | |
688 | return ret; | |
689 | ||
690 | clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); | |
691 | if (!clk) | |
692 | return -ERANGE; | |
693 | ||
694 | if (bios->execute) { | |
695 | still_alive(); | |
696 | nouveau_hw_setpll(dev, reg, &pllvals); | |
697 | } | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
702 | static int dcb_entry_idx_from_crtchead(struct drm_device *dev) | |
703 | { | |
704 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 705 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
706 | |
707 | /* | |
708 | * For the results of this function to be correct, CR44 must have been | |
709 | * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, | |
710 | * and the DCB table parsed, before the script calling the function is | |
711 | * run. run_digital_op_script is example of how to do such setup | |
712 | */ | |
713 | ||
714 | uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); | |
715 | ||
7f245b20 | 716 | if (dcb_entry > bios->dcb.entries) { |
6ee73861 BS |
717 | NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " |
718 | "(%02X)\n", dcb_entry); | |
719 | dcb_entry = 0x7f; /* unused / invalid marker */ | |
720 | } | |
721 | ||
722 | return dcb_entry; | |
723 | } | |
724 | ||
f8b0be1a BS |
725 | static int |
726 | read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c) | |
727 | { | |
728 | uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4; | |
729 | int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES; | |
730 | int recordoffset = 0, rdofs = 1, wrofs = 0; | |
731 | uint8_t port_type = 0; | |
732 | ||
733 | if (!i2ctable) | |
734 | return -EINVAL; | |
735 | ||
736 | if (dcb_version >= 0x30) { | |
737 | if (i2ctable[0] != dcb_version) /* necessary? */ | |
738 | NV_WARN(dev, | |
739 | "DCB I2C table version mismatch (%02X vs %02X)\n", | |
740 | i2ctable[0], dcb_version); | |
741 | dcb_i2c_ver = i2ctable[0]; | |
742 | headerlen = i2ctable[1]; | |
743 | if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES) | |
744 | i2c_entries = i2ctable[2]; | |
745 | else | |
746 | NV_WARN(dev, | |
747 | "DCB I2C table has more entries than indexable " | |
748 | "(%d entries, max %d)\n", i2ctable[2], | |
749 | DCB_MAX_NUM_I2C_ENTRIES); | |
750 | entry_len = i2ctable[3]; | |
751 | /* [4] is i2c_default_indices, read in parse_dcb_table() */ | |
752 | } | |
753 | /* | |
754 | * It's your own fault if you call this function on a DCB 1.1 BIOS -- | |
755 | * the test below is for DCB 1.2 | |
756 | */ | |
757 | if (dcb_version < 0x14) { | |
758 | recordoffset = 2; | |
759 | rdofs = 0; | |
760 | wrofs = 1; | |
761 | } | |
762 | ||
763 | if (index == 0xf) | |
764 | return 0; | |
765 | if (index >= i2c_entries) { | |
766 | NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", | |
767 | index, i2ctable[2]); | |
768 | return -ENOENT; | |
769 | } | |
770 | if (i2ctable[headerlen + entry_len * index + 3] == 0xff) { | |
771 | NV_ERROR(dev, "DCB I2C entry invalid\n"); | |
772 | return -EINVAL; | |
773 | } | |
774 | ||
775 | if (dcb_i2c_ver >= 0x30) { | |
776 | port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index]; | |
777 | ||
778 | /* | |
779 | * Fixup for chips using same address offset for read and | |
780 | * write. | |
781 | */ | |
782 | if (port_type == 4) /* seen on C51 */ | |
783 | rdofs = wrofs = 1; | |
784 | if (port_type >= 5) /* G80+ */ | |
785 | rdofs = wrofs = 0; | |
786 | } | |
787 | ||
788 | if (dcb_i2c_ver >= 0x40) { | |
789 | if (port_type != 5 && port_type != 6) | |
790 | NV_WARN(dev, "DCB I2C table has port type %d\n", port_type); | |
791 | ||
792 | i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]); | |
793 | } | |
794 | ||
795 | i2c->port_type = port_type; | |
796 | i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index]; | |
797 | i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index]; | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
6ee73861 BS |
802 | static struct nouveau_i2c_chan * |
803 | init_i2c_device_find(struct drm_device *dev, int i2c_index) | |
804 | { | |
805 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 806 | struct dcb_table *dcb = &dev_priv->vbios.dcb; |
6ee73861 BS |
807 | |
808 | if (i2c_index == 0xff) { | |
809 | /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ | |
810 | int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; | |
7f245b20 | 811 | int default_indices = dcb->i2c_default_indices; |
6ee73861 | 812 | |
7f245b20 | 813 | if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) |
6ee73861 BS |
814 | shift = 4; |
815 | ||
816 | i2c_index = (default_indices >> shift) & 0xf; | |
817 | } | |
818 | if (i2c_index == 0x80) /* g80+ */ | |
7f245b20 | 819 | i2c_index = dcb->i2c_default_indices & 0xf; |
04f542c0 BS |
820 | else |
821 | if (i2c_index == 0x81) | |
822 | i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4; | |
6ee73861 | 823 | |
75047944 | 824 | if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) { |
f8b0be1a BS |
825 | NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index); |
826 | return NULL; | |
827 | } | |
828 | ||
829 | /* Make sure i2c table entry has been parsed, it may not | |
830 | * have been if this is a bus not referenced by a DCB encoder | |
831 | */ | |
832 | read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, | |
833 | i2c_index, &dcb->i2c[i2c_index]); | |
834 | ||
6ee73861 BS |
835 | return nouveau_i2c_find(dev, i2c_index); |
836 | } | |
837 | ||
7f245b20 BS |
838 | static uint32_t |
839 | get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) | |
6ee73861 BS |
840 | { |
841 | /* | |
842 | * For mlv < 0x80, it is an index into a table of TMDS base addresses. | |
843 | * For mlv == 0x80 use the "or" value of the dcb_entry indexed by | |
844 | * CR58 for CR57 = 0 to index a table of offsets to the basic | |
845 | * 0x6808b0 address. | |
846 | * For mlv == 0x81 use the "or" value of the dcb_entry indexed by | |
847 | * CR58 for CR57 = 0 to index a table of offsets to the basic | |
848 | * 0x6808b0 address, and then flip the offset by 8. | |
849 | */ | |
850 | ||
851 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 852 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
853 | const int pramdac_offset[13] = { |
854 | 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; | |
855 | const uint32_t pramdac_table[4] = { | |
856 | 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; | |
857 | ||
858 | if (mlv >= 0x80) { | |
859 | int dcb_entry, dacoffset; | |
860 | ||
861 | /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ | |
862 | dcb_entry = dcb_entry_idx_from_crtchead(dev); | |
863 | if (dcb_entry == 0x7f) | |
864 | return 0; | |
7f245b20 | 865 | dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; |
6ee73861 BS |
866 | if (mlv == 0x81) |
867 | dacoffset ^= 8; | |
868 | return 0x6808b0 + dacoffset; | |
869 | } else { | |
df31ef4d | 870 | if (mlv >= ARRAY_SIZE(pramdac_table)) { |
6ee73861 BS |
871 | NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", |
872 | mlv); | |
873 | return 0; | |
874 | } | |
875 | return pramdac_table[mlv]; | |
876 | } | |
877 | } | |
878 | ||
37383650 | 879 | static int |
6ee73861 BS |
880 | init_io_restrict_prog(struct nvbios *bios, uint16_t offset, |
881 | struct init_exec *iexec) | |
882 | { | |
883 | /* | |
884 | * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') | |
885 | * | |
886 | * offset (8 bit): opcode | |
887 | * offset + 1 (16 bit): CRTC port | |
888 | * offset + 3 (8 bit): CRTC index | |
889 | * offset + 4 (8 bit): mask | |
890 | * offset + 5 (8 bit): shift | |
891 | * offset + 6 (8 bit): count | |
892 | * offset + 7 (32 bit): register | |
893 | * offset + 11 (32 bit): configuration 1 | |
894 | * ... | |
895 | * | |
896 | * Starting at offset + 11 there are "count" 32 bit values. | |
897 | * To find out which value to use read index "CRTC index" on "CRTC | |
898 | * port", AND this value with "mask" and then bit shift right "shift" | |
899 | * bits. Read the appropriate value using this index and write to | |
900 | * "register" | |
901 | */ | |
902 | ||
903 | uint16_t crtcport = ROM16(bios->data[offset + 1]); | |
904 | uint8_t crtcindex = bios->data[offset + 3]; | |
905 | uint8_t mask = bios->data[offset + 4]; | |
906 | uint8_t shift = bios->data[offset + 5]; | |
907 | uint8_t count = bios->data[offset + 6]; | |
908 | uint32_t reg = ROM32(bios->data[offset + 7]); | |
909 | uint8_t config; | |
910 | uint32_t configval; | |
37383650 | 911 | int len = 11 + count * 4; |
6ee73861 BS |
912 | |
913 | if (!iexec->execute) | |
37383650 | 914 | return len; |
6ee73861 BS |
915 | |
916 | BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " | |
917 | "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", | |
918 | offset, crtcport, crtcindex, mask, shift, count, reg); | |
919 | ||
920 | config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; | |
921 | if (config > count) { | |
922 | NV_ERROR(bios->dev, | |
923 | "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", | |
924 | offset, config, count); | |
309b8c89 | 925 | return len; |
6ee73861 BS |
926 | } |
927 | ||
928 | configval = ROM32(bios->data[offset + 11 + config * 4]); | |
929 | ||
930 | BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); | |
931 | ||
932 | bios_wr32(bios, reg, configval); | |
933 | ||
37383650 | 934 | return len; |
6ee73861 BS |
935 | } |
936 | ||
37383650 | 937 | static int |
6ee73861 BS |
938 | init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
939 | { | |
940 | /* | |
941 | * INIT_REPEAT opcode: 0x33 ('3') | |
942 | * | |
943 | * offset (8 bit): opcode | |
944 | * offset + 1 (8 bit): count | |
945 | * | |
946 | * Execute script following this opcode up to INIT_REPEAT_END | |
947 | * "count" times | |
948 | */ | |
949 | ||
950 | uint8_t count = bios->data[offset + 1]; | |
951 | uint8_t i; | |
952 | ||
953 | /* no iexec->execute check by design */ | |
954 | ||
955 | BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", | |
956 | offset, count); | |
957 | ||
958 | iexec->repeat = true; | |
959 | ||
960 | /* | |
961 | * count - 1, as the script block will execute once when we leave this | |
962 | * opcode -- this is compatible with bios behaviour as: | |
963 | * a) the block is always executed at least once, even if count == 0 | |
964 | * b) the bios interpreter skips to the op following INIT_END_REPEAT, | |
965 | * while we don't | |
966 | */ | |
967 | for (i = 0; i < count - 1; i++) | |
968 | parse_init_table(bios, offset + 2, iexec); | |
969 | ||
970 | iexec->repeat = false; | |
971 | ||
37383650 | 972 | return 2; |
6ee73861 BS |
973 | } |
974 | ||
37383650 | 975 | static int |
6ee73861 BS |
976 | init_io_restrict_pll(struct nvbios *bios, uint16_t offset, |
977 | struct init_exec *iexec) | |
978 | { | |
979 | /* | |
980 | * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') | |
981 | * | |
982 | * offset (8 bit): opcode | |
983 | * offset + 1 (16 bit): CRTC port | |
984 | * offset + 3 (8 bit): CRTC index | |
985 | * offset + 4 (8 bit): mask | |
986 | * offset + 5 (8 bit): shift | |
987 | * offset + 6 (8 bit): IO flag condition index | |
988 | * offset + 7 (8 bit): count | |
989 | * offset + 8 (32 bit): register | |
990 | * offset + 12 (16 bit): frequency 1 | |
991 | * ... | |
992 | * | |
993 | * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). | |
994 | * Set PLL register "register" to coefficients for frequency n, | |
995 | * selected by reading index "CRTC index" of "CRTC port" ANDed with | |
996 | * "mask" and shifted right by "shift". | |
997 | * | |
998 | * If "IO flag condition index" > 0, and condition met, double | |
999 | * frequency before setting it. | |
1000 | */ | |
1001 | ||
1002 | uint16_t crtcport = ROM16(bios->data[offset + 1]); | |
1003 | uint8_t crtcindex = bios->data[offset + 3]; | |
1004 | uint8_t mask = bios->data[offset + 4]; | |
1005 | uint8_t shift = bios->data[offset + 5]; | |
1006 | int8_t io_flag_condition_idx = bios->data[offset + 6]; | |
1007 | uint8_t count = bios->data[offset + 7]; | |
1008 | uint32_t reg = ROM32(bios->data[offset + 8]); | |
1009 | uint8_t config; | |
1010 | uint16_t freq; | |
37383650 | 1011 | int len = 12 + count * 2; |
6ee73861 BS |
1012 | |
1013 | if (!iexec->execute) | |
37383650 | 1014 | return len; |
6ee73861 BS |
1015 | |
1016 | BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " | |
1017 | "Shift: 0x%02X, IO Flag Condition: 0x%02X, " | |
1018 | "Count: 0x%02X, Reg: 0x%08X\n", | |
1019 | offset, crtcport, crtcindex, mask, shift, | |
1020 | io_flag_condition_idx, count, reg); | |
1021 | ||
1022 | config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; | |
1023 | if (config > count) { | |
1024 | NV_ERROR(bios->dev, | |
1025 | "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", | |
1026 | offset, config, count); | |
309b8c89 | 1027 | return len; |
6ee73861 BS |
1028 | } |
1029 | ||
1030 | freq = ROM16(bios->data[offset + 12 + config * 2]); | |
1031 | ||
1032 | if (io_flag_condition_idx > 0) { | |
1033 | if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { | |
1034 | BIOSLOG(bios, "0x%04X: Condition fulfilled -- " | |
1035 | "frequency doubled\n", offset); | |
1036 | freq *= 2; | |
1037 | } else | |
1038 | BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " | |
1039 | "frequency unchanged\n", offset); | |
1040 | } | |
1041 | ||
1042 | BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", | |
1043 | offset, reg, config, freq); | |
1044 | ||
1045 | setPLL(bios, reg, freq * 10); | |
1046 | ||
37383650 | 1047 | return len; |
6ee73861 BS |
1048 | } |
1049 | ||
37383650 | 1050 | static int |
6ee73861 BS |
1051 | init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1052 | { | |
1053 | /* | |
1054 | * INIT_END_REPEAT opcode: 0x36 ('6') | |
1055 | * | |
1056 | * offset (8 bit): opcode | |
1057 | * | |
1058 | * Marks the end of the block for INIT_REPEAT to repeat | |
1059 | */ | |
1060 | ||
1061 | /* no iexec->execute check by design */ | |
1062 | ||
1063 | /* | |
1064 | * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when | |
1065 | * we're not in repeat mode | |
1066 | */ | |
1067 | if (iexec->repeat) | |
37383650 | 1068 | return 0; |
6ee73861 | 1069 | |
37383650 | 1070 | return 1; |
6ee73861 BS |
1071 | } |
1072 | ||
37383650 | 1073 | static int |
6ee73861 BS |
1074 | init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1075 | { | |
1076 | /* | |
1077 | * INIT_COPY opcode: 0x37 ('7') | |
1078 | * | |
1079 | * offset (8 bit): opcode | |
1080 | * offset + 1 (32 bit): register | |
1081 | * offset + 5 (8 bit): shift | |
1082 | * offset + 6 (8 bit): srcmask | |
1083 | * offset + 7 (16 bit): CRTC port | |
1084 | * offset + 9 (8 bit): CRTC index | |
1085 | * offset + 10 (8 bit): mask | |
1086 | * | |
1087 | * Read index "CRTC index" on "CRTC port", AND with "mask", OR with | |
1088 | * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC | |
1089 | * port | |
1090 | */ | |
1091 | ||
1092 | uint32_t reg = ROM32(bios->data[offset + 1]); | |
1093 | uint8_t shift = bios->data[offset + 5]; | |
1094 | uint8_t srcmask = bios->data[offset + 6]; | |
1095 | uint16_t crtcport = ROM16(bios->data[offset + 7]); | |
1096 | uint8_t crtcindex = bios->data[offset + 9]; | |
1097 | uint8_t mask = bios->data[offset + 10]; | |
1098 | uint32_t data; | |
1099 | uint8_t crtcdata; | |
1100 | ||
1101 | if (!iexec->execute) | |
37383650 | 1102 | return 11; |
6ee73861 BS |
1103 | |
1104 | BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " | |
1105 | "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", | |
1106 | offset, reg, shift, srcmask, crtcport, crtcindex, mask); | |
1107 | ||
1108 | data = bios_rd32(bios, reg); | |
1109 | ||
1110 | if (shift < 0x80) | |
1111 | data >>= shift; | |
1112 | else | |
1113 | data <<= (0x100 - shift); | |
1114 | ||
1115 | data &= srcmask; | |
1116 | ||
1117 | crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; | |
1118 | crtcdata |= (uint8_t)data; | |
1119 | bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); | |
1120 | ||
37383650 | 1121 | return 11; |
6ee73861 BS |
1122 | } |
1123 | ||
37383650 | 1124 | static int |
6ee73861 BS |
1125 | init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1126 | { | |
1127 | /* | |
1128 | * INIT_NOT opcode: 0x38 ('8') | |
1129 | * | |
1130 | * offset (8 bit): opcode | |
1131 | * | |
1132 | * Invert the current execute / no-execute condition (i.e. "else") | |
1133 | */ | |
1134 | if (iexec->execute) | |
1135 | BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); | |
1136 | else | |
1137 | BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); | |
1138 | ||
1139 | iexec->execute = !iexec->execute; | |
37383650 | 1140 | return 1; |
6ee73861 BS |
1141 | } |
1142 | ||
37383650 | 1143 | static int |
6ee73861 BS |
1144 | init_io_flag_condition(struct nvbios *bios, uint16_t offset, |
1145 | struct init_exec *iexec) | |
1146 | { | |
1147 | /* | |
1148 | * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') | |
1149 | * | |
1150 | * offset (8 bit): opcode | |
1151 | * offset + 1 (8 bit): condition number | |
1152 | * | |
1153 | * Check condition "condition number" in the IO flag condition table. | |
1154 | * If condition not met skip subsequent opcodes until condition is | |
1155 | * inverted (INIT_NOT), or we hit INIT_RESUME | |
1156 | */ | |
1157 | ||
1158 | uint8_t cond = bios->data[offset + 1]; | |
1159 | ||
1160 | if (!iexec->execute) | |
37383650 | 1161 | return 2; |
6ee73861 BS |
1162 | |
1163 | if (io_flag_condition_met(bios, offset, cond)) | |
1164 | BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); | |
1165 | else { | |
1166 | BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); | |
1167 | iexec->execute = false; | |
1168 | } | |
1169 | ||
37383650 | 1170 | return 2; |
6ee73861 BS |
1171 | } |
1172 | ||
25908b77 BS |
1173 | static int |
1174 | init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) | |
1175 | { | |
1176 | /* | |
1177 | * INIT_DP_CONDITION opcode: 0x3A ('') | |
1178 | * | |
1179 | * offset (8 bit): opcode | |
1180 | * offset + 1 (8 bit): "sub" opcode | |
1181 | * offset + 2 (8 bit): unknown | |
1182 | * | |
1183 | */ | |
1184 | ||
1185 | struct bit_displayport_encoder_table *dpe = NULL; | |
1186 | struct dcb_entry *dcb = bios->display.output; | |
1187 | struct drm_device *dev = bios->dev; | |
1188 | uint8_t cond = bios->data[offset + 1]; | |
1189 | int dummy; | |
1190 | ||
1191 | BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); | |
1192 | ||
1193 | if (!iexec->execute) | |
1194 | return 3; | |
1195 | ||
1196 | dpe = nouveau_bios_dp_table(dev, dcb, &dummy); | |
1197 | if (!dpe) { | |
1198 | NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset); | |
309b8c89 | 1199 | return 3; |
25908b77 BS |
1200 | } |
1201 | ||
1202 | switch (cond) { | |
1203 | case 0: | |
1204 | { | |
1205 | struct dcb_connector_table_entry *ent = | |
1206 | &bios->dcb.connector.entry[dcb->connector]; | |
1207 | ||
1208 | if (ent->type != DCB_CONNECTOR_eDP) | |
1209 | iexec->execute = false; | |
1210 | } | |
1211 | break; | |
1212 | case 1: | |
1213 | case 2: | |
1214 | if (!(dpe->unknown & cond)) | |
1215 | iexec->execute = false; | |
1216 | break; | |
1217 | case 5: | |
1218 | { | |
1219 | struct nouveau_i2c_chan *auxch; | |
1220 | int ret; | |
1221 | ||
1222 | auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); | |
309b8c89 BS |
1223 | if (!auxch) { |
1224 | NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset); | |
1225 | return 3; | |
1226 | } | |
25908b77 BS |
1227 | |
1228 | ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); | |
309b8c89 BS |
1229 | if (ret) { |
1230 | NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret); | |
1231 | return 3; | |
1232 | } | |
25908b77 BS |
1233 | |
1234 | if (cond & 1) | |
1235 | iexec->execute = false; | |
1236 | } | |
1237 | break; | |
1238 | default: | |
1239 | NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); | |
1240 | break; | |
1241 | } | |
1242 | ||
1243 | if (iexec->execute) | |
1244 | BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); | |
1245 | else | |
1246 | BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); | |
1247 | ||
1248 | return 3; | |
1249 | } | |
1250 | ||
1251 | static int | |
1252 | init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) | |
1253 | { | |
1254 | /* | |
1255 | * INIT_3B opcode: 0x3B ('') | |
1256 | * | |
1257 | * offset (8 bit): opcode | |
1258 | * offset + 1 (8 bit): crtc index | |
1259 | * | |
1260 | */ | |
1261 | ||
1262 | uint8_t or = ffs(bios->display.output->or) - 1; | |
1263 | uint8_t index = bios->data[offset + 1]; | |
1264 | uint8_t data; | |
1265 | ||
1266 | if (!iexec->execute) | |
1267 | return 2; | |
1268 | ||
1269 | data = bios_idxprt_rd(bios, 0x3d4, index); | |
1270 | bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); | |
1271 | return 2; | |
1272 | } | |
1273 | ||
1274 | static int | |
1275 | init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) | |
1276 | { | |
1277 | /* | |
1278 | * INIT_3C opcode: 0x3C ('') | |
1279 | * | |
1280 | * offset (8 bit): opcode | |
1281 | * offset + 1 (8 bit): crtc index | |
1282 | * | |
1283 | */ | |
1284 | ||
1285 | uint8_t or = ffs(bios->display.output->or) - 1; | |
1286 | uint8_t index = bios->data[offset + 1]; | |
1287 | uint8_t data; | |
1288 | ||
1289 | if (!iexec->execute) | |
1290 | return 2; | |
1291 | ||
1292 | data = bios_idxprt_rd(bios, 0x3d4, index); | |
1293 | bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); | |
1294 | return 2; | |
1295 | } | |
1296 | ||
37383650 | 1297 | static int |
6ee73861 BS |
1298 | init_idx_addr_latched(struct nvbios *bios, uint16_t offset, |
1299 | struct init_exec *iexec) | |
1300 | { | |
1301 | /* | |
1302 | * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') | |
1303 | * | |
1304 | * offset (8 bit): opcode | |
1305 | * offset + 1 (32 bit): control register | |
1306 | * offset + 5 (32 bit): data register | |
1307 | * offset + 9 (32 bit): mask | |
1308 | * offset + 13 (32 bit): data | |
1309 | * offset + 17 (8 bit): count | |
1310 | * offset + 18 (8 bit): address 1 | |
1311 | * offset + 19 (8 bit): data 1 | |
1312 | * ... | |
1313 | * | |
1314 | * For each of "count" address and data pairs, write "data n" to | |
1315 | * "data register", read the current value of "control register", | |
1316 | * and write it back once ANDed with "mask", ORed with "data", | |
1317 | * and ORed with "address n" | |
1318 | */ | |
1319 | ||
1320 | uint32_t controlreg = ROM32(bios->data[offset + 1]); | |
1321 | uint32_t datareg = ROM32(bios->data[offset + 5]); | |
1322 | uint32_t mask = ROM32(bios->data[offset + 9]); | |
1323 | uint32_t data = ROM32(bios->data[offset + 13]); | |
1324 | uint8_t count = bios->data[offset + 17]; | |
37383650 | 1325 | int len = 18 + count * 2; |
6ee73861 BS |
1326 | uint32_t value; |
1327 | int i; | |
1328 | ||
1329 | if (!iexec->execute) | |
37383650 | 1330 | return len; |
6ee73861 BS |
1331 | |
1332 | BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " | |
1333 | "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", | |
1334 | offset, controlreg, datareg, mask, data, count); | |
1335 | ||
1336 | for (i = 0; i < count; i++) { | |
1337 | uint8_t instaddress = bios->data[offset + 18 + i * 2]; | |
1338 | uint8_t instdata = bios->data[offset + 19 + i * 2]; | |
1339 | ||
1340 | BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", | |
1341 | offset, instaddress, instdata); | |
1342 | ||
1343 | bios_wr32(bios, datareg, instdata); | |
1344 | value = bios_rd32(bios, controlreg) & mask; | |
1345 | value |= data; | |
1346 | value |= instaddress; | |
1347 | bios_wr32(bios, controlreg, value); | |
1348 | } | |
1349 | ||
37383650 | 1350 | return len; |
6ee73861 BS |
1351 | } |
1352 | ||
37383650 | 1353 | static int |
6ee73861 BS |
1354 | init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, |
1355 | struct init_exec *iexec) | |
1356 | { | |
1357 | /* | |
1358 | * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') | |
1359 | * | |
1360 | * offset (8 bit): opcode | |
1361 | * offset + 1 (16 bit): CRTC port | |
1362 | * offset + 3 (8 bit): CRTC index | |
1363 | * offset + 4 (8 bit): mask | |
1364 | * offset + 5 (8 bit): shift | |
1365 | * offset + 6 (8 bit): count | |
1366 | * offset + 7 (32 bit): register | |
1367 | * offset + 11 (32 bit): frequency 1 | |
1368 | * ... | |
1369 | * | |
1370 | * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). | |
1371 | * Set PLL register "register" to coefficients for frequency n, | |
1372 | * selected by reading index "CRTC index" of "CRTC port" ANDed with | |
1373 | * "mask" and shifted right by "shift". | |
1374 | */ | |
1375 | ||
1376 | uint16_t crtcport = ROM16(bios->data[offset + 1]); | |
1377 | uint8_t crtcindex = bios->data[offset + 3]; | |
1378 | uint8_t mask = bios->data[offset + 4]; | |
1379 | uint8_t shift = bios->data[offset + 5]; | |
1380 | uint8_t count = bios->data[offset + 6]; | |
1381 | uint32_t reg = ROM32(bios->data[offset + 7]); | |
37383650 | 1382 | int len = 11 + count * 4; |
6ee73861 BS |
1383 | uint8_t config; |
1384 | uint32_t freq; | |
1385 | ||
1386 | if (!iexec->execute) | |
37383650 | 1387 | return len; |
6ee73861 BS |
1388 | |
1389 | BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " | |
1390 | "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", | |
1391 | offset, crtcport, crtcindex, mask, shift, count, reg); | |
1392 | ||
1393 | if (!reg) | |
37383650 | 1394 | return len; |
6ee73861 BS |
1395 | |
1396 | config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; | |
1397 | if (config > count) { | |
1398 | NV_ERROR(bios->dev, | |
1399 | "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", | |
1400 | offset, config, count); | |
309b8c89 | 1401 | return len; |
6ee73861 BS |
1402 | } |
1403 | ||
1404 | freq = ROM32(bios->data[offset + 11 + config * 4]); | |
1405 | ||
1406 | BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", | |
1407 | offset, reg, config, freq); | |
1408 | ||
1409 | setPLL(bios, reg, freq); | |
1410 | ||
37383650 | 1411 | return len; |
6ee73861 BS |
1412 | } |
1413 | ||
37383650 | 1414 | static int |
6ee73861 BS |
1415 | init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1416 | { | |
1417 | /* | |
1418 | * INIT_PLL2 opcode: 0x4B ('K') | |
1419 | * | |
1420 | * offset (8 bit): opcode | |
1421 | * offset + 1 (32 bit): register | |
1422 | * offset + 5 (32 bit): freq | |
1423 | * | |
1424 | * Set PLL register "register" to coefficients for frequency "freq" | |
1425 | */ | |
1426 | ||
1427 | uint32_t reg = ROM32(bios->data[offset + 1]); | |
1428 | uint32_t freq = ROM32(bios->data[offset + 5]); | |
1429 | ||
1430 | if (!iexec->execute) | |
37383650 | 1431 | return 9; |
6ee73861 BS |
1432 | |
1433 | BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", | |
1434 | offset, reg, freq); | |
1435 | ||
1436 | setPLL(bios, reg, freq); | |
37383650 | 1437 | return 9; |
6ee73861 BS |
1438 | } |
1439 | ||
37383650 | 1440 | static int |
6ee73861 BS |
1441 | init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1442 | { | |
1443 | /* | |
1444 | * INIT_I2C_BYTE opcode: 0x4C ('L') | |
1445 | * | |
1446 | * offset (8 bit): opcode | |
1447 | * offset + 1 (8 bit): DCB I2C table entry index | |
1448 | * offset + 2 (8 bit): I2C slave address | |
1449 | * offset + 3 (8 bit): count | |
1450 | * offset + 4 (8 bit): I2C register 1 | |
1451 | * offset + 5 (8 bit): mask 1 | |
1452 | * offset + 6 (8 bit): data 1 | |
1453 | * ... | |
1454 | * | |
1455 | * For each of "count" registers given by "I2C register n" on the device | |
1456 | * addressed by "I2C slave address" on the I2C bus given by | |
1457 | * "DCB I2C table entry index", read the register, AND the result with | |
1458 | * "mask n" and OR it with "data n" before writing it back to the device | |
1459 | */ | |
1460 | ||
309b8c89 | 1461 | struct drm_device *dev = bios->dev; |
6ee73861 | 1462 | uint8_t i2c_index = bios->data[offset + 1]; |
893887ed | 1463 | uint8_t i2c_address = bios->data[offset + 2] >> 1; |
6ee73861 BS |
1464 | uint8_t count = bios->data[offset + 3]; |
1465 | struct nouveau_i2c_chan *chan; | |
893887ed BS |
1466 | int len = 4 + count * 3; |
1467 | int ret, i; | |
6ee73861 BS |
1468 | |
1469 | if (!iexec->execute) | |
37383650 | 1470 | return len; |
6ee73861 BS |
1471 | |
1472 | BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " | |
1473 | "Count: 0x%02X\n", | |
1474 | offset, i2c_index, i2c_address, count); | |
1475 | ||
309b8c89 BS |
1476 | chan = init_i2c_device_find(dev, i2c_index); |
1477 | if (!chan) { | |
1478 | NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); | |
1479 | return len; | |
1480 | } | |
6ee73861 BS |
1481 | |
1482 | for (i = 0; i < count; i++) { | |
893887ed | 1483 | uint8_t reg = bios->data[offset + 4 + i * 3]; |
6ee73861 BS |
1484 | uint8_t mask = bios->data[offset + 5 + i * 3]; |
1485 | uint8_t data = bios->data[offset + 6 + i * 3]; | |
893887ed | 1486 | union i2c_smbus_data val; |
6ee73861 | 1487 | |
893887ed BS |
1488 | ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, |
1489 | I2C_SMBUS_READ, reg, | |
1490 | I2C_SMBUS_BYTE_DATA, &val); | |
309b8c89 BS |
1491 | if (ret < 0) { |
1492 | NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret); | |
1493 | return len; | |
1494 | } | |
6ee73861 BS |
1495 | |
1496 | BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " | |
1497 | "Mask: 0x%02X, Data: 0x%02X\n", | |
893887ed | 1498 | offset, reg, val.byte, mask, data); |
6ee73861 | 1499 | |
893887ed BS |
1500 | if (!bios->execute) |
1501 | continue; | |
6ee73861 | 1502 | |
893887ed BS |
1503 | val.byte &= mask; |
1504 | val.byte |= data; | |
1505 | ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, | |
1506 | I2C_SMBUS_WRITE, reg, | |
1507 | I2C_SMBUS_BYTE_DATA, &val); | |
309b8c89 BS |
1508 | if (ret < 0) { |
1509 | NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); | |
1510 | return len; | |
1511 | } | |
6ee73861 BS |
1512 | } |
1513 | ||
37383650 | 1514 | return len; |
6ee73861 BS |
1515 | } |
1516 | ||
37383650 | 1517 | static int |
6ee73861 BS |
1518 | init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1519 | { | |
1520 | /* | |
1521 | * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') | |
1522 | * | |
1523 | * offset (8 bit): opcode | |
1524 | * offset + 1 (8 bit): DCB I2C table entry index | |
1525 | * offset + 2 (8 bit): I2C slave address | |
1526 | * offset + 3 (8 bit): count | |
1527 | * offset + 4 (8 bit): I2C register 1 | |
1528 | * offset + 5 (8 bit): data 1 | |
1529 | * ... | |
1530 | * | |
1531 | * For each of "count" registers given by "I2C register n" on the device | |
1532 | * addressed by "I2C slave address" on the I2C bus given by | |
1533 | * "DCB I2C table entry index", set the register to "data n" | |
1534 | */ | |
1535 | ||
309b8c89 | 1536 | struct drm_device *dev = bios->dev; |
6ee73861 | 1537 | uint8_t i2c_index = bios->data[offset + 1]; |
893887ed | 1538 | uint8_t i2c_address = bios->data[offset + 2] >> 1; |
6ee73861 BS |
1539 | uint8_t count = bios->data[offset + 3]; |
1540 | struct nouveau_i2c_chan *chan; | |
893887ed BS |
1541 | int len = 4 + count * 2; |
1542 | int ret, i; | |
6ee73861 BS |
1543 | |
1544 | if (!iexec->execute) | |
37383650 | 1545 | return len; |
6ee73861 BS |
1546 | |
1547 | BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " | |
1548 | "Count: 0x%02X\n", | |
1549 | offset, i2c_index, i2c_address, count); | |
1550 | ||
309b8c89 BS |
1551 | chan = init_i2c_device_find(dev, i2c_index); |
1552 | if (!chan) { | |
1553 | NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); | |
1554 | return len; | |
1555 | } | |
6ee73861 BS |
1556 | |
1557 | for (i = 0; i < count; i++) { | |
893887ed BS |
1558 | uint8_t reg = bios->data[offset + 4 + i * 2]; |
1559 | union i2c_smbus_data val; | |
1560 | ||
1561 | val.byte = bios->data[offset + 5 + i * 2]; | |
6ee73861 BS |
1562 | |
1563 | BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", | |
893887ed BS |
1564 | offset, reg, val.byte); |
1565 | ||
1566 | if (!bios->execute) | |
1567 | continue; | |
1568 | ||
1569 | ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, | |
1570 | I2C_SMBUS_WRITE, reg, | |
1571 | I2C_SMBUS_BYTE_DATA, &val); | |
309b8c89 BS |
1572 | if (ret < 0) { |
1573 | NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); | |
1574 | return len; | |
1575 | } | |
6ee73861 BS |
1576 | } |
1577 | ||
37383650 | 1578 | return len; |
6ee73861 BS |
1579 | } |
1580 | ||
37383650 | 1581 | static int |
6ee73861 BS |
1582 | init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1583 | { | |
1584 | /* | |
1585 | * INIT_ZM_I2C opcode: 0x4E ('N') | |
1586 | * | |
1587 | * offset (8 bit): opcode | |
1588 | * offset + 1 (8 bit): DCB I2C table entry index | |
1589 | * offset + 2 (8 bit): I2C slave address | |
1590 | * offset + 3 (8 bit): count | |
1591 | * offset + 4 (8 bit): data 1 | |
1592 | * ... | |
1593 | * | |
1594 | * Send "count" bytes ("data n") to the device addressed by "I2C slave | |
1595 | * address" on the I2C bus given by "DCB I2C table entry index" | |
1596 | */ | |
1597 | ||
309b8c89 | 1598 | struct drm_device *dev = bios->dev; |
6ee73861 | 1599 | uint8_t i2c_index = bios->data[offset + 1]; |
893887ed | 1600 | uint8_t i2c_address = bios->data[offset + 2] >> 1; |
6ee73861 | 1601 | uint8_t count = bios->data[offset + 3]; |
37383650 | 1602 | int len = 4 + count; |
6ee73861 BS |
1603 | struct nouveau_i2c_chan *chan; |
1604 | struct i2c_msg msg; | |
1605 | uint8_t data[256]; | |
309b8c89 | 1606 | int ret, i; |
6ee73861 BS |
1607 | |
1608 | if (!iexec->execute) | |
37383650 | 1609 | return len; |
6ee73861 BS |
1610 | |
1611 | BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " | |
1612 | "Count: 0x%02X\n", | |
1613 | offset, i2c_index, i2c_address, count); | |
1614 | ||
309b8c89 BS |
1615 | chan = init_i2c_device_find(dev, i2c_index); |
1616 | if (!chan) { | |
1617 | NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); | |
1618 | return len; | |
1619 | } | |
6ee73861 BS |
1620 | |
1621 | for (i = 0; i < count; i++) { | |
1622 | data[i] = bios->data[offset + 4 + i]; | |
1623 | ||
1624 | BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); | |
1625 | } | |
1626 | ||
1627 | if (bios->execute) { | |
1628 | msg.addr = i2c_address; | |
1629 | msg.flags = 0; | |
1630 | msg.len = count; | |
1631 | msg.buf = data; | |
309b8c89 BS |
1632 | ret = i2c_transfer(&chan->adapter, &msg, 1); |
1633 | if (ret != 1) { | |
1634 | NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); | |
1635 | return len; | |
1636 | } | |
6ee73861 BS |
1637 | } |
1638 | ||
37383650 | 1639 | return len; |
6ee73861 BS |
1640 | } |
1641 | ||
37383650 | 1642 | static int |
6ee73861 BS |
1643 | init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1644 | { | |
1645 | /* | |
1646 | * INIT_TMDS opcode: 0x4F ('O') (non-canon name) | |
1647 | * | |
1648 | * offset (8 bit): opcode | |
1649 | * offset + 1 (8 bit): magic lookup value | |
1650 | * offset + 2 (8 bit): TMDS address | |
1651 | * offset + 3 (8 bit): mask | |
1652 | * offset + 4 (8 bit): data | |
1653 | * | |
1654 | * Read the data reg for TMDS address "TMDS address", AND it with mask | |
1655 | * and OR it with data, then write it back | |
1656 | * "magic lookup value" determines which TMDS base address register is | |
1657 | * used -- see get_tmds_index_reg() | |
1658 | */ | |
1659 | ||
309b8c89 | 1660 | struct drm_device *dev = bios->dev; |
6ee73861 BS |
1661 | uint8_t mlv = bios->data[offset + 1]; |
1662 | uint32_t tmdsaddr = bios->data[offset + 2]; | |
1663 | uint8_t mask = bios->data[offset + 3]; | |
1664 | uint8_t data = bios->data[offset + 4]; | |
1665 | uint32_t reg, value; | |
1666 | ||
1667 | if (!iexec->execute) | |
37383650 | 1668 | return 5; |
6ee73861 BS |
1669 | |
1670 | BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " | |
1671 | "Mask: 0x%02X, Data: 0x%02X\n", | |
1672 | offset, mlv, tmdsaddr, mask, data); | |
1673 | ||
1674 | reg = get_tmds_index_reg(bios->dev, mlv); | |
309b8c89 BS |
1675 | if (!reg) { |
1676 | NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); | |
1677 | return 5; | |
1678 | } | |
6ee73861 BS |
1679 | |
1680 | bios_wr32(bios, reg, | |
1681 | tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); | |
1682 | value = (bios_rd32(bios, reg + 4) & mask) | data; | |
1683 | bios_wr32(bios, reg + 4, value); | |
1684 | bios_wr32(bios, reg, tmdsaddr); | |
1685 | ||
37383650 | 1686 | return 5; |
6ee73861 BS |
1687 | } |
1688 | ||
37383650 | 1689 | static int |
6ee73861 BS |
1690 | init_zm_tmds_group(struct nvbios *bios, uint16_t offset, |
1691 | struct init_exec *iexec) | |
1692 | { | |
1693 | /* | |
1694 | * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) | |
1695 | * | |
1696 | * offset (8 bit): opcode | |
1697 | * offset + 1 (8 bit): magic lookup value | |
1698 | * offset + 2 (8 bit): count | |
1699 | * offset + 3 (8 bit): addr 1 | |
1700 | * offset + 4 (8 bit): data 1 | |
1701 | * ... | |
1702 | * | |
1703 | * For each of "count" TMDS address and data pairs write "data n" to | |
1704 | * "addr n". "magic lookup value" determines which TMDS base address | |
1705 | * register is used -- see get_tmds_index_reg() | |
1706 | */ | |
1707 | ||
309b8c89 | 1708 | struct drm_device *dev = bios->dev; |
6ee73861 BS |
1709 | uint8_t mlv = bios->data[offset + 1]; |
1710 | uint8_t count = bios->data[offset + 2]; | |
37383650 | 1711 | int len = 3 + count * 2; |
6ee73861 BS |
1712 | uint32_t reg; |
1713 | int i; | |
1714 | ||
1715 | if (!iexec->execute) | |
37383650 | 1716 | return len; |
6ee73861 BS |
1717 | |
1718 | BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", | |
1719 | offset, mlv, count); | |
1720 | ||
1721 | reg = get_tmds_index_reg(bios->dev, mlv); | |
309b8c89 BS |
1722 | if (!reg) { |
1723 | NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); | |
1724 | return len; | |
1725 | } | |
6ee73861 BS |
1726 | |
1727 | for (i = 0; i < count; i++) { | |
1728 | uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; | |
1729 | uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; | |
1730 | ||
1731 | bios_wr32(bios, reg + 4, tmdsdata); | |
1732 | bios_wr32(bios, reg, tmdsaddr); | |
1733 | } | |
1734 | ||
37383650 | 1735 | return len; |
6ee73861 BS |
1736 | } |
1737 | ||
37383650 | 1738 | static int |
6ee73861 BS |
1739 | init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, |
1740 | struct init_exec *iexec) | |
1741 | { | |
1742 | /* | |
1743 | * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') | |
1744 | * | |
1745 | * offset (8 bit): opcode | |
1746 | * offset + 1 (8 bit): CRTC index1 | |
1747 | * offset + 2 (8 bit): CRTC index2 | |
1748 | * offset + 3 (8 bit): baseaddr | |
1749 | * offset + 4 (8 bit): count | |
1750 | * offset + 5 (8 bit): data 1 | |
1751 | * ... | |
1752 | * | |
1753 | * For each of "count" address and data pairs, write "baseaddr + n" to | |
1754 | * "CRTC index1" and "data n" to "CRTC index2" | |
1755 | * Once complete, restore initial value read from "CRTC index1" | |
1756 | */ | |
1757 | uint8_t crtcindex1 = bios->data[offset + 1]; | |
1758 | uint8_t crtcindex2 = bios->data[offset + 2]; | |
1759 | uint8_t baseaddr = bios->data[offset + 3]; | |
1760 | uint8_t count = bios->data[offset + 4]; | |
37383650 | 1761 | int len = 5 + count; |
6ee73861 BS |
1762 | uint8_t oldaddr, data; |
1763 | int i; | |
1764 | ||
1765 | if (!iexec->execute) | |
37383650 | 1766 | return len; |
6ee73861 BS |
1767 | |
1768 | BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " | |
1769 | "BaseAddr: 0x%02X, Count: 0x%02X\n", | |
1770 | offset, crtcindex1, crtcindex2, baseaddr, count); | |
1771 | ||
1772 | oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); | |
1773 | ||
1774 | for (i = 0; i < count; i++) { | |
1775 | bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, | |
1776 | baseaddr + i); | |
1777 | data = bios->data[offset + 5 + i]; | |
1778 | bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); | |
1779 | } | |
1780 | ||
1781 | bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); | |
1782 | ||
37383650 | 1783 | return len; |
6ee73861 BS |
1784 | } |
1785 | ||
37383650 | 1786 | static int |
6ee73861 BS |
1787 | init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1788 | { | |
1789 | /* | |
1790 | * INIT_CR opcode: 0x52 ('R') | |
1791 | * | |
1792 | * offset (8 bit): opcode | |
1793 | * offset + 1 (8 bit): CRTC index | |
1794 | * offset + 2 (8 bit): mask | |
1795 | * offset + 3 (8 bit): data | |
1796 | * | |
1797 | * Assign the value of at "CRTC index" ANDed with mask and ORed with | |
1798 | * data back to "CRTC index" | |
1799 | */ | |
1800 | ||
1801 | uint8_t crtcindex = bios->data[offset + 1]; | |
1802 | uint8_t mask = bios->data[offset + 2]; | |
1803 | uint8_t data = bios->data[offset + 3]; | |
1804 | uint8_t value; | |
1805 | ||
1806 | if (!iexec->execute) | |
37383650 | 1807 | return 4; |
6ee73861 BS |
1808 | |
1809 | BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", | |
1810 | offset, crtcindex, mask, data); | |
1811 | ||
1812 | value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; | |
1813 | value |= data; | |
1814 | bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); | |
1815 | ||
37383650 | 1816 | return 4; |
6ee73861 BS |
1817 | } |
1818 | ||
37383650 | 1819 | static int |
6ee73861 BS |
1820 | init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1821 | { | |
1822 | /* | |
1823 | * INIT_ZM_CR opcode: 0x53 ('S') | |
1824 | * | |
1825 | * offset (8 bit): opcode | |
1826 | * offset + 1 (8 bit): CRTC index | |
1827 | * offset + 2 (8 bit): value | |
1828 | * | |
1829 | * Assign "value" to CRTC register with index "CRTC index". | |
1830 | */ | |
1831 | ||
1832 | uint8_t crtcindex = ROM32(bios->data[offset + 1]); | |
1833 | uint8_t data = bios->data[offset + 2]; | |
1834 | ||
1835 | if (!iexec->execute) | |
37383650 | 1836 | return 3; |
6ee73861 BS |
1837 | |
1838 | bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); | |
1839 | ||
37383650 | 1840 | return 3; |
6ee73861 BS |
1841 | } |
1842 | ||
37383650 | 1843 | static int |
6ee73861 BS |
1844 | init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1845 | { | |
1846 | /* | |
1847 | * INIT_ZM_CR_GROUP opcode: 0x54 ('T') | |
1848 | * | |
1849 | * offset (8 bit): opcode | |
1850 | * offset + 1 (8 bit): count | |
1851 | * offset + 2 (8 bit): CRTC index 1 | |
1852 | * offset + 3 (8 bit): value 1 | |
1853 | * ... | |
1854 | * | |
1855 | * For "count", assign "value n" to CRTC register with index | |
1856 | * "CRTC index n". | |
1857 | */ | |
1858 | ||
1859 | uint8_t count = bios->data[offset + 1]; | |
37383650 | 1860 | int len = 2 + count * 2; |
6ee73861 BS |
1861 | int i; |
1862 | ||
1863 | if (!iexec->execute) | |
37383650 | 1864 | return len; |
6ee73861 BS |
1865 | |
1866 | for (i = 0; i < count; i++) | |
1867 | init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); | |
1868 | ||
37383650 | 1869 | return len; |
6ee73861 BS |
1870 | } |
1871 | ||
37383650 | 1872 | static int |
6ee73861 BS |
1873 | init_condition_time(struct nvbios *bios, uint16_t offset, |
1874 | struct init_exec *iexec) | |
1875 | { | |
1876 | /* | |
1877 | * INIT_CONDITION_TIME opcode: 0x56 ('V') | |
1878 | * | |
1879 | * offset (8 bit): opcode | |
1880 | * offset + 1 (8 bit): condition number | |
1881 | * offset + 2 (8 bit): retries / 50 | |
1882 | * | |
1883 | * Check condition "condition number" in the condition table. | |
1884 | * Bios code then sleeps for 2ms if the condition is not met, and | |
1885 | * repeats up to "retries" times, but on one C51 this has proved | |
1886 | * insufficient. In mmiotraces the driver sleeps for 20ms, so we do | |
1887 | * this, and bail after "retries" times, or 2s, whichever is less. | |
1888 | * If still not met after retries, clear execution flag for this table. | |
1889 | */ | |
1890 | ||
1891 | uint8_t cond = bios->data[offset + 1]; | |
1892 | uint16_t retries = bios->data[offset + 2] * 50; | |
1893 | unsigned cnt; | |
1894 | ||
1895 | if (!iexec->execute) | |
37383650 | 1896 | return 3; |
6ee73861 BS |
1897 | |
1898 | if (retries > 100) | |
1899 | retries = 100; | |
1900 | ||
1901 | BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", | |
1902 | offset, cond, retries); | |
1903 | ||
1904 | if (!bios->execute) /* avoid 2s delays when "faking" execution */ | |
1905 | retries = 1; | |
1906 | ||
1907 | for (cnt = 0; cnt < retries; cnt++) { | |
1908 | if (bios_condition_met(bios, offset, cond)) { | |
1909 | BIOSLOG(bios, "0x%04X: Condition met, continuing\n", | |
1910 | offset); | |
1911 | break; | |
1912 | } else { | |
1913 | BIOSLOG(bios, "0x%04X: " | |
1914 | "Condition not met, sleeping for 20ms\n", | |
1915 | offset); | |
1916 | msleep(20); | |
1917 | } | |
1918 | } | |
1919 | ||
1920 | if (!bios_condition_met(bios, offset, cond)) { | |
1921 | NV_WARN(bios->dev, | |
1922 | "0x%04X: Condition still not met after %dms, " | |
1923 | "skipping following opcodes\n", offset, 20 * retries); | |
1924 | iexec->execute = false; | |
1925 | } | |
1926 | ||
37383650 | 1927 | return 3; |
6ee73861 BS |
1928 | } |
1929 | ||
37383650 | 1930 | static int |
6ee73861 BS |
1931 | init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, |
1932 | struct init_exec *iexec) | |
1933 | { | |
1934 | /* | |
1935 | * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') | |
1936 | * | |
1937 | * offset (8 bit): opcode | |
1938 | * offset + 1 (32 bit): base register | |
1939 | * offset + 5 (8 bit): count | |
1940 | * offset + 6 (32 bit): value 1 | |
1941 | * ... | |
1942 | * | |
1943 | * Starting at offset + 6 there are "count" 32 bit values. | |
1944 | * For "count" iterations set "base register" + 4 * current_iteration | |
1945 | * to "value current_iteration" | |
1946 | */ | |
1947 | ||
1948 | uint32_t basereg = ROM32(bios->data[offset + 1]); | |
1949 | uint32_t count = bios->data[offset + 5]; | |
37383650 | 1950 | int len = 6 + count * 4; |
6ee73861 BS |
1951 | int i; |
1952 | ||
1953 | if (!iexec->execute) | |
37383650 | 1954 | return len; |
6ee73861 BS |
1955 | |
1956 | BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", | |
1957 | offset, basereg, count); | |
1958 | ||
1959 | for (i = 0; i < count; i++) { | |
1960 | uint32_t reg = basereg + i * 4; | |
1961 | uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); | |
1962 | ||
1963 | bios_wr32(bios, reg, data); | |
1964 | } | |
1965 | ||
37383650 | 1966 | return len; |
6ee73861 BS |
1967 | } |
1968 | ||
37383650 | 1969 | static int |
6ee73861 BS |
1970 | init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1971 | { | |
1972 | /* | |
1973 | * INIT_SUB_DIRECT opcode: 0x5B ('[') | |
1974 | * | |
1975 | * offset (8 bit): opcode | |
1976 | * offset + 1 (16 bit): subroutine offset (in bios) | |
1977 | * | |
1978 | * Calls a subroutine that will execute commands until INIT_DONE | |
1979 | * is found. | |
1980 | */ | |
1981 | ||
1982 | uint16_t sub_offset = ROM16(bios->data[offset + 1]); | |
1983 | ||
1984 | if (!iexec->execute) | |
37383650 | 1985 | return 3; |
6ee73861 BS |
1986 | |
1987 | BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", | |
1988 | offset, sub_offset); | |
1989 | ||
1990 | parse_init_table(bios, sub_offset, iexec); | |
1991 | ||
1992 | BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); | |
1993 | ||
37383650 | 1994 | return 3; |
6ee73861 BS |
1995 | } |
1996 | ||
37383650 | 1997 | static int |
6ee73861 BS |
1998 | init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
1999 | { | |
2000 | /* | |
2001 | * INIT_COPY_NV_REG opcode: 0x5F ('_') | |
2002 | * | |
2003 | * offset (8 bit): opcode | |
2004 | * offset + 1 (32 bit): src reg | |
2005 | * offset + 5 (8 bit): shift | |
2006 | * offset + 6 (32 bit): src mask | |
2007 | * offset + 10 (32 bit): xor | |
2008 | * offset + 14 (32 bit): dst reg | |
2009 | * offset + 18 (32 bit): dst mask | |
2010 | * | |
2011 | * Shift REGVAL("src reg") right by (signed) "shift", AND result with | |
2012 | * "src mask", then XOR with "xor". Write this OR'd with | |
2013 | * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" | |
2014 | */ | |
2015 | ||
2016 | uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); | |
2017 | uint8_t shift = bios->data[offset + 5]; | |
2018 | uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); | |
2019 | uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); | |
2020 | uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); | |
2021 | uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); | |
2022 | uint32_t srcvalue, dstvalue; | |
2023 | ||
2024 | if (!iexec->execute) | |
37383650 | 2025 | return 22; |
6ee73861 BS |
2026 | |
2027 | BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " | |
2028 | "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", | |
2029 | offset, srcreg, shift, srcmask, xor, dstreg, dstmask); | |
2030 | ||
2031 | srcvalue = bios_rd32(bios, srcreg); | |
2032 | ||
2033 | if (shift < 0x80) | |
2034 | srcvalue >>= shift; | |
2035 | else | |
2036 | srcvalue <<= (0x100 - shift); | |
2037 | ||
2038 | srcvalue = (srcvalue & srcmask) ^ xor; | |
2039 | ||
2040 | dstvalue = bios_rd32(bios, dstreg) & dstmask; | |
2041 | ||
2042 | bios_wr32(bios, dstreg, dstvalue | srcvalue); | |
2043 | ||
37383650 | 2044 | return 22; |
6ee73861 BS |
2045 | } |
2046 | ||
37383650 | 2047 | static int |
6ee73861 BS |
2048 | init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2049 | { | |
2050 | /* | |
2051 | * INIT_ZM_INDEX_IO opcode: 0x62 ('b') | |
2052 | * | |
2053 | * offset (8 bit): opcode | |
2054 | * offset + 1 (16 bit): CRTC port | |
2055 | * offset + 3 (8 bit): CRTC index | |
2056 | * offset + 4 (8 bit): data | |
2057 | * | |
2058 | * Write "data" to index "CRTC index" of "CRTC port" | |
2059 | */ | |
2060 | uint16_t crtcport = ROM16(bios->data[offset + 1]); | |
2061 | uint8_t crtcindex = bios->data[offset + 3]; | |
2062 | uint8_t data = bios->data[offset + 4]; | |
2063 | ||
2064 | if (!iexec->execute) | |
37383650 | 2065 | return 5; |
6ee73861 BS |
2066 | |
2067 | bios_idxprt_wr(bios, crtcport, crtcindex, data); | |
2068 | ||
37383650 | 2069 | return 5; |
6ee73861 BS |
2070 | } |
2071 | ||
67eda20e FJ |
2072 | static inline void |
2073 | bios_md32(struct nvbios *bios, uint32_t reg, | |
2074 | uint32_t mask, uint32_t val) | |
2075 | { | |
2076 | bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val); | |
2077 | } | |
2078 | ||
2079 | static uint32_t | |
2080 | peek_fb(struct drm_device *dev, struct io_mapping *fb, | |
2081 | uint32_t off) | |
2082 | { | |
2083 | uint32_t val = 0; | |
2084 | ||
2085 | if (off < pci_resource_len(dev->pdev, 1)) { | |
2086 | uint32_t __iomem *p = io_mapping_map_atomic_wc(fb, off); | |
2087 | ||
2088 | val = ioread32(p); | |
2089 | ||
2090 | io_mapping_unmap_atomic(p); | |
2091 | } | |
2092 | ||
2093 | return val; | |
2094 | } | |
2095 | ||
2096 | static void | |
2097 | poke_fb(struct drm_device *dev, struct io_mapping *fb, | |
2098 | uint32_t off, uint32_t val) | |
2099 | { | |
2100 | if (off < pci_resource_len(dev->pdev, 1)) { | |
2101 | uint32_t __iomem *p = io_mapping_map_atomic_wc(fb, off); | |
2102 | ||
2103 | iowrite32(val, p); | |
2104 | wmb(); | |
2105 | ||
2106 | io_mapping_unmap_atomic(p); | |
2107 | } | |
2108 | } | |
2109 | ||
2110 | static inline bool | |
2111 | read_back_fb(struct drm_device *dev, struct io_mapping *fb, | |
2112 | uint32_t off, uint32_t val) | |
2113 | { | |
2114 | poke_fb(dev, fb, off, val); | |
2115 | return val == peek_fb(dev, fb, off); | |
2116 | } | |
2117 | ||
2118 | static int | |
2119 | nv04_init_compute_mem(struct nvbios *bios) | |
2120 | { | |
2121 | struct drm_device *dev = bios->dev; | |
2122 | uint32_t patt = 0xdeadbeef; | |
2123 | struct io_mapping *fb; | |
2124 | int i; | |
2125 | ||
2126 | /* Map the framebuffer aperture */ | |
2127 | fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), | |
2128 | pci_resource_len(dev->pdev, 1)); | |
2129 | if (!fb) | |
2130 | return -ENOMEM; | |
2131 | ||
2132 | /* Sequencer and refresh off */ | |
2133 | NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); | |
2134 | bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); | |
2135 | ||
2136 | bios_md32(bios, NV04_PFB_BOOT_0, ~0, | |
2137 | NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | | |
2138 | NV04_PFB_BOOT_0_RAM_WIDTH_128 | | |
2139 | NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); | |
2140 | ||
2141 | for (i = 0; i < 4; i++) | |
2142 | poke_fb(dev, fb, 4 * i, patt); | |
2143 | ||
2144 | poke_fb(dev, fb, 0x400000, patt + 1); | |
2145 | ||
2146 | if (peek_fb(dev, fb, 0) == patt + 1) { | |
2147 | bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, | |
2148 | NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); | |
2149 | bios_md32(bios, NV04_PFB_DEBUG_0, | |
2150 | NV04_PFB_DEBUG_0_REFRESH_OFF, 0); | |
2151 | ||
2152 | for (i = 0; i < 4; i++) | |
2153 | poke_fb(dev, fb, 4 * i, patt); | |
2154 | ||
2155 | if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff)) | |
2156 | bios_md32(bios, NV04_PFB_BOOT_0, | |
2157 | NV04_PFB_BOOT_0_RAM_WIDTH_128 | | |
2158 | NV04_PFB_BOOT_0_RAM_AMOUNT, | |
2159 | NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); | |
2160 | ||
2161 | } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) != | |
2162 | (patt & 0xffff0000)) { | |
2163 | bios_md32(bios, NV04_PFB_BOOT_0, | |
2164 | NV04_PFB_BOOT_0_RAM_WIDTH_128 | | |
2165 | NV04_PFB_BOOT_0_RAM_AMOUNT, | |
2166 | NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); | |
2167 | ||
2168 | } else if (peek_fb(dev, fb, 0) == patt) { | |
2169 | if (read_back_fb(dev, fb, 0x800000, patt)) | |
2170 | bios_md32(bios, NV04_PFB_BOOT_0, | |
2171 | NV04_PFB_BOOT_0_RAM_AMOUNT, | |
2172 | NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); | |
2173 | else | |
2174 | bios_md32(bios, NV04_PFB_BOOT_0, | |
2175 | NV04_PFB_BOOT_0_RAM_AMOUNT, | |
2176 | NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); | |
2177 | ||
2178 | bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, | |
2179 | NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); | |
2180 | ||
2181 | } else if (!read_back_fb(dev, fb, 0x800000, patt)) { | |
2182 | bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, | |
2183 | NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); | |
2184 | ||
2185 | } | |
2186 | ||
2187 | /* Refresh on, sequencer on */ | |
2188 | bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); | |
2189 | NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); | |
2190 | ||
2191 | io_mapping_free(fb); | |
2192 | return 0; | |
2193 | } | |
2194 | ||
2195 | static const uint8_t * | |
2196 | nv05_memory_config(struct nvbios *bios) | |
2197 | { | |
2198 | /* Defaults for BIOSes lacking a memory config table */ | |
2199 | static const uint8_t default_config_tab[][2] = { | |
2200 | { 0x24, 0x00 }, | |
2201 | { 0x28, 0x00 }, | |
2202 | { 0x24, 0x01 }, | |
2203 | { 0x1f, 0x00 }, | |
2204 | { 0x0f, 0x00 }, | |
2205 | { 0x17, 0x00 }, | |
2206 | { 0x06, 0x00 }, | |
2207 | { 0x00, 0x00 } | |
2208 | }; | |
2209 | int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & | |
2210 | NV_PEXTDEV_BOOT_0_RAMCFG) >> 2; | |
2211 | ||
2212 | if (bios->legacy.mem_init_tbl_ptr) | |
2213 | return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i]; | |
2214 | else | |
2215 | return default_config_tab[i]; | |
2216 | } | |
2217 | ||
2218 | static int | |
2219 | nv05_init_compute_mem(struct nvbios *bios) | |
2220 | { | |
2221 | struct drm_device *dev = bios->dev; | |
2222 | const uint8_t *ramcfg = nv05_memory_config(bios); | |
2223 | uint32_t patt = 0xdeadbeef; | |
2224 | struct io_mapping *fb; | |
2225 | int i, v; | |
2226 | ||
2227 | /* Map the framebuffer aperture */ | |
2228 | fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), | |
2229 | pci_resource_len(dev->pdev, 1)); | |
2230 | if (!fb) | |
2231 | return -ENOMEM; | |
2232 | ||
2233 | /* Sequencer off */ | |
2234 | NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); | |
2235 | ||
2236 | if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) | |
2237 | goto out; | |
2238 | ||
2239 | bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); | |
2240 | ||
2241 | /* If present load the hardcoded scrambling table */ | |
2242 | if (bios->legacy.mem_init_tbl_ptr) { | |
2243 | uint32_t *scramble_tab = (uint32_t *)&bios->data[ | |
2244 | bios->legacy.mem_init_tbl_ptr + 0x10]; | |
2245 | ||
2246 | for (i = 0; i < 8; i++) | |
2247 | bios_wr32(bios, NV04_PFB_SCRAMBLE(i), | |
2248 | ROM32(scramble_tab[i])); | |
2249 | } | |
2250 | ||
2251 | /* Set memory type/width/length defaults depending on the straps */ | |
2252 | bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); | |
2253 | ||
2254 | if (ramcfg[1] & 0x80) | |
2255 | bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); | |
2256 | ||
2257 | bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); | |
2258 | bios_md32(bios, NV04_PFB_CFG1, 0, 1); | |
2259 | ||
2260 | /* Probe memory bus width */ | |
2261 | for (i = 0; i < 4; i++) | |
2262 | poke_fb(dev, fb, 4 * i, patt); | |
2263 | ||
2264 | if (peek_fb(dev, fb, 0xc) != patt) | |
2265 | bios_md32(bios, NV04_PFB_BOOT_0, | |
2266 | NV04_PFB_BOOT_0_RAM_WIDTH_128, 0); | |
2267 | ||
2268 | /* Probe memory length */ | |
2269 | v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; | |
2270 | ||
2271 | if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB && | |
2272 | (!read_back_fb(dev, fb, 0x1000000, ++patt) || | |
2273 | !read_back_fb(dev, fb, 0, ++patt))) | |
2274 | bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, | |
2275 | NV04_PFB_BOOT_0_RAM_AMOUNT_16MB); | |
2276 | ||
2277 | if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB && | |
2278 | !read_back_fb(dev, fb, 0x800000, ++patt)) | |
2279 | bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, | |
2280 | NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); | |
2281 | ||
2282 | if (!read_back_fb(dev, fb, 0x400000, ++patt)) | |
2283 | bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, | |
2284 | NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); | |
2285 | ||
2286 | out: | |
2287 | /* Sequencer on */ | |
2288 | NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); | |
2289 | ||
2290 | io_mapping_free(fb); | |
2291 | return 0; | |
2292 | } | |
2293 | ||
2294 | static int | |
2295 | nv10_init_compute_mem(struct nvbios *bios) | |
2296 | { | |
2297 | struct drm_device *dev = bios->dev; | |
2298 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | |
2299 | const int mem_width[] = { 0x10, 0x00, 0x20 }; | |
2300 | const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2); | |
2301 | uint32_t patt = 0xdeadbeef; | |
2302 | struct io_mapping *fb; | |
2303 | int i, j, k; | |
2304 | ||
2305 | /* Map the framebuffer aperture */ | |
2306 | fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), | |
2307 | pci_resource_len(dev->pdev, 1)); | |
2308 | if (!fb) | |
2309 | return -ENOMEM; | |
2310 | ||
2311 | bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); | |
2312 | ||
2313 | /* Probe memory bus width */ | |
2314 | for (i = 0; i < mem_width_count; i++) { | |
2315 | bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]); | |
2316 | ||
2317 | for (j = 0; j < 4; j++) { | |
2318 | for (k = 0; k < 4; k++) | |
2319 | poke_fb(dev, fb, 0x1c, 0); | |
2320 | ||
2321 | poke_fb(dev, fb, 0x1c, patt); | |
2322 | poke_fb(dev, fb, 0x3c, 0); | |
2323 | ||
2324 | if (peek_fb(dev, fb, 0x1c) == patt) | |
2325 | goto mem_width_found; | |
2326 | } | |
2327 | } | |
2328 | ||
2329 | mem_width_found: | |
2330 | patt <<= 1; | |
2331 | ||
2332 | /* Probe amount of installed memory */ | |
2333 | for (i = 0; i < 4; i++) { | |
2334 | int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000; | |
2335 | ||
2336 | poke_fb(dev, fb, off, patt); | |
2337 | poke_fb(dev, fb, 0, 0); | |
2338 | ||
2339 | peek_fb(dev, fb, 0); | |
2340 | peek_fb(dev, fb, 0); | |
2341 | peek_fb(dev, fb, 0); | |
2342 | peek_fb(dev, fb, 0); | |
2343 | ||
2344 | if (peek_fb(dev, fb, off) == patt) | |
2345 | goto amount_found; | |
2346 | } | |
2347 | ||
2348 | /* IC missing - disable the upper half memory space. */ | |
2349 | bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0); | |
2350 | ||
2351 | amount_found: | |
2352 | io_mapping_free(fb); | |
2353 | return 0; | |
2354 | } | |
2355 | ||
2356 | static int | |
2357 | nv20_init_compute_mem(struct nvbios *bios) | |
2358 | { | |
2359 | struct drm_device *dev = bios->dev; | |
2360 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | |
2361 | uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900); | |
2362 | uint32_t amount, off; | |
2363 | struct io_mapping *fb; | |
2364 | ||
2365 | /* Map the framebuffer aperture */ | |
2366 | fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), | |
2367 | pci_resource_len(dev->pdev, 1)); | |
2368 | if (!fb) | |
2369 | return -ENOMEM; | |
2370 | ||
2371 | bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); | |
2372 | ||
2373 | /* Allow full addressing */ | |
2374 | bios_md32(bios, NV04_PFB_CFG0, 0, mask); | |
2375 | ||
2376 | amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); | |
2377 | for (off = amount; off > 0x2000000; off -= 0x2000000) | |
2378 | poke_fb(dev, fb, off - 4, off); | |
2379 | ||
2380 | amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); | |
2381 | if (amount != peek_fb(dev, fb, amount - 4)) | |
2382 | /* IC missing - disable the upper half memory space. */ | |
2383 | bios_md32(bios, NV04_PFB_CFG0, mask, 0); | |
2384 | ||
2385 | io_mapping_free(fb); | |
2386 | return 0; | |
2387 | } | |
2388 | ||
37383650 | 2389 | static int |
6ee73861 BS |
2390 | init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2391 | { | |
2392 | /* | |
2393 | * INIT_COMPUTE_MEM opcode: 0x63 ('c') | |
2394 | * | |
2395 | * offset (8 bit): opcode | |
2396 | * | |
67eda20e FJ |
2397 | * This opcode is meant to set the PFB memory config registers |
2398 | * appropriately so that we can correctly calculate how much VRAM it | |
2399 | * has (on nv10 and better chipsets the amount of installed VRAM is | |
2400 | * subsequently reported in NV_PFB_CSTATUS (0x10020C)). | |
6ee73861 | 2401 | * |
67eda20e FJ |
2402 | * The implementation of this opcode in general consists of several |
2403 | * parts: | |
6ee73861 | 2404 | * |
67eda20e FJ |
2405 | * 1) Determination of memory type and density. Only necessary for |
2406 | * really old chipsets, the memory type reported by the strap bits | |
2407 | * (0x101000) is assumed to be accurate on nv05 and newer. | |
6ee73861 | 2408 | * |
67eda20e FJ |
2409 | * 2) Determination of the memory bus width. Usually done by a cunning |
2410 | * combination of writes to offsets 0x1c and 0x3c in the fb, and | |
2411 | * seeing whether the written values are read back correctly. | |
6ee73861 | 2412 | * |
67eda20e FJ |
2413 | * Only necessary on nv0x-nv1x and nv34, on the other cards we can |
2414 | * trust the straps. | |
6ee73861 | 2415 | * |
67eda20e FJ |
2416 | * 3) Determination of how many of the card's RAM pads have ICs |
2417 | * attached, usually done by a cunning combination of writes to an | |
2418 | * offset slightly less than the maximum memory reported by | |
2419 | * NV_PFB_CSTATUS, then seeing if the test pattern can be read back. | |
6ee73861 | 2420 | * |
67eda20e FJ |
2421 | * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io |
2422 | * logs of the VBIOS and kmmio traces of the binary driver POSTing the | |
2423 | * card show nothing being done for this opcode. Why is it still listed | |
2424 | * in the table?! | |
6ee73861 BS |
2425 | */ |
2426 | ||
2427 | /* no iexec->execute check by design */ | |
2428 | ||
6ee73861 | 2429 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; |
67eda20e | 2430 | int ret; |
6ee73861 | 2431 | |
67eda20e FJ |
2432 | if (dev_priv->chipset >= 0x40 || |
2433 | dev_priv->chipset == 0x1a || | |
2434 | dev_priv->chipset == 0x1f) | |
2435 | ret = 0; | |
2436 | else if (dev_priv->chipset >= 0x20 && | |
2437 | dev_priv->chipset != 0x34) | |
2438 | ret = nv20_init_compute_mem(bios); | |
2439 | else if (dev_priv->chipset >= 0x10) | |
2440 | ret = nv10_init_compute_mem(bios); | |
2441 | else if (dev_priv->chipset >= 0x5) | |
2442 | ret = nv05_init_compute_mem(bios); | |
2443 | else | |
2444 | ret = nv04_init_compute_mem(bios); | |
6ee73861 | 2445 | |
67eda20e FJ |
2446 | if (ret) |
2447 | return ret; | |
6ee73861 | 2448 | |
37383650 | 2449 | return 1; |
6ee73861 BS |
2450 | } |
2451 | ||
37383650 | 2452 | static int |
6ee73861 BS |
2453 | init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2454 | { | |
2455 | /* | |
2456 | * INIT_RESET opcode: 0x65 ('e') | |
2457 | * | |
2458 | * offset (8 bit): opcode | |
2459 | * offset + 1 (32 bit): register | |
2460 | * offset + 5 (32 bit): value1 | |
2461 | * offset + 9 (32 bit): value2 | |
2462 | * | |
2463 | * Assign "value1" to "register", then assign "value2" to "register" | |
2464 | */ | |
2465 | ||
2466 | uint32_t reg = ROM32(bios->data[offset + 1]); | |
2467 | uint32_t value1 = ROM32(bios->data[offset + 5]); | |
2468 | uint32_t value2 = ROM32(bios->data[offset + 9]); | |
2469 | uint32_t pci_nv_19, pci_nv_20; | |
2470 | ||
2471 | /* no iexec->execute check by design */ | |
2472 | ||
2473 | pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); | |
190a4378 FJ |
2474 | bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00); |
2475 | ||
6ee73861 BS |
2476 | bios_wr32(bios, reg, value1); |
2477 | ||
2478 | udelay(10); | |
2479 | ||
2480 | bios_wr32(bios, reg, value2); | |
2481 | bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); | |
2482 | ||
2483 | pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); | |
2484 | pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ | |
2485 | bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); | |
2486 | ||
37383650 | 2487 | return 13; |
6ee73861 BS |
2488 | } |
2489 | ||
37383650 | 2490 | static int |
6ee73861 BS |
2491 | init_configure_mem(struct nvbios *bios, uint16_t offset, |
2492 | struct init_exec *iexec) | |
2493 | { | |
2494 | /* | |
2495 | * INIT_CONFIGURE_MEM opcode: 0x66 ('f') | |
2496 | * | |
2497 | * offset (8 bit): opcode | |
2498 | * | |
2499 | * Equivalent to INIT_DONE on bios version 3 or greater. | |
2500 | * For early bios versions, sets up the memory registers, using values | |
2501 | * taken from the memory init table | |
2502 | */ | |
2503 | ||
2504 | /* no iexec->execute check by design */ | |
2505 | ||
2506 | uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); | |
2507 | uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; | |
2508 | uint32_t reg, data; | |
2509 | ||
2510 | if (bios->major_version > 2) | |
ae55321c | 2511 | return 0; |
6ee73861 BS |
2512 | |
2513 | bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( | |
2514 | bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); | |
2515 | ||
2516 | if (bios->data[meminitoffs] & 1) | |
2517 | seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; | |
2518 | ||
2519 | for (reg = ROM32(bios->data[seqtbloffs]); | |
2520 | reg != 0xffffffff; | |
2521 | reg = ROM32(bios->data[seqtbloffs += 4])) { | |
2522 | ||
2523 | switch (reg) { | |
3c7066bc FJ |
2524 | case NV04_PFB_PRE: |
2525 | data = NV04_PFB_PRE_CMD_PRECHARGE; | |
6ee73861 | 2526 | break; |
3c7066bc FJ |
2527 | case NV04_PFB_PAD: |
2528 | data = NV04_PFB_PAD_CKE_NORMAL; | |
6ee73861 | 2529 | break; |
3c7066bc FJ |
2530 | case NV04_PFB_REF: |
2531 | data = NV04_PFB_REF_CMD_REFRESH; | |
6ee73861 BS |
2532 | break; |
2533 | default: | |
2534 | data = ROM32(bios->data[meminitdata]); | |
2535 | meminitdata += 4; | |
2536 | if (data == 0xffffffff) | |
2537 | continue; | |
2538 | } | |
2539 | ||
2540 | bios_wr32(bios, reg, data); | |
2541 | } | |
2542 | ||
37383650 | 2543 | return 1; |
6ee73861 BS |
2544 | } |
2545 | ||
37383650 | 2546 | static int |
6ee73861 BS |
2547 | init_configure_clk(struct nvbios *bios, uint16_t offset, |
2548 | struct init_exec *iexec) | |
2549 | { | |
2550 | /* | |
2551 | * INIT_CONFIGURE_CLK opcode: 0x67 ('g') | |
2552 | * | |
2553 | * offset (8 bit): opcode | |
2554 | * | |
2555 | * Equivalent to INIT_DONE on bios version 3 or greater. | |
2556 | * For early bios versions, sets up the NVClk and MClk PLLs, using | |
2557 | * values taken from the memory init table | |
2558 | */ | |
2559 | ||
2560 | /* no iexec->execute check by design */ | |
2561 | ||
2562 | uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); | |
2563 | int clock; | |
2564 | ||
2565 | if (bios->major_version > 2) | |
ae55321c | 2566 | return 0; |
6ee73861 BS |
2567 | |
2568 | clock = ROM16(bios->data[meminitoffs + 4]) * 10; | |
2569 | setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); | |
2570 | ||
2571 | clock = ROM16(bios->data[meminitoffs + 2]) * 10; | |
2572 | if (bios->data[meminitoffs] & 1) /* DDR */ | |
2573 | clock *= 2; | |
2574 | setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); | |
2575 | ||
37383650 | 2576 | return 1; |
6ee73861 BS |
2577 | } |
2578 | ||
37383650 | 2579 | static int |
6ee73861 BS |
2580 | init_configure_preinit(struct nvbios *bios, uint16_t offset, |
2581 | struct init_exec *iexec) | |
2582 | { | |
2583 | /* | |
2584 | * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') | |
2585 | * | |
2586 | * offset (8 bit): opcode | |
2587 | * | |
2588 | * Equivalent to INIT_DONE on bios version 3 or greater. | |
2589 | * For early bios versions, does early init, loading ram and crystal | |
2590 | * configuration from straps into CR3C | |
2591 | */ | |
2592 | ||
2593 | /* no iexec->execute check by design */ | |
2594 | ||
2595 | uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); | |
2596 | uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6)); | |
2597 | ||
2598 | if (bios->major_version > 2) | |
ae55321c | 2599 | return 0; |
6ee73861 BS |
2600 | |
2601 | bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, | |
2602 | NV_CIO_CRE_SCRATCH4__INDEX, cr3c); | |
2603 | ||
37383650 | 2604 | return 1; |
6ee73861 BS |
2605 | } |
2606 | ||
37383650 | 2607 | static int |
6ee73861 BS |
2608 | init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2609 | { | |
2610 | /* | |
2611 | * INIT_IO opcode: 0x69 ('i') | |
2612 | * | |
2613 | * offset (8 bit): opcode | |
2614 | * offset + 1 (16 bit): CRTC port | |
2615 | * offset + 3 (8 bit): mask | |
2616 | * offset + 4 (8 bit): data | |
2617 | * | |
2618 | * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" | |
2619 | */ | |
2620 | ||
2621 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | |
2622 | uint16_t crtcport = ROM16(bios->data[offset + 1]); | |
2623 | uint8_t mask = bios->data[offset + 3]; | |
2624 | uint8_t data = bios->data[offset + 4]; | |
2625 | ||
2626 | if (!iexec->execute) | |
37383650 | 2627 | return 5; |
6ee73861 BS |
2628 | |
2629 | BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", | |
2630 | offset, crtcport, mask, data); | |
2631 | ||
2632 | /* | |
2633 | * I have no idea what this does, but NVIDIA do this magic sequence | |
2634 | * in the places where this INIT_IO happens.. | |
2635 | */ | |
2636 | if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { | |
2637 | int i; | |
2638 | ||
2639 | bios_wr32(bios, 0x614100, (bios_rd32( | |
2640 | bios, 0x614100) & 0x0fffffff) | 0x00800000); | |
2641 | ||
2642 | bios_wr32(bios, 0x00e18c, bios_rd32( | |
2643 | bios, 0x00e18c) | 0x00020000); | |
2644 | ||
2645 | bios_wr32(bios, 0x614900, (bios_rd32( | |
2646 | bios, 0x614900) & 0x0fffffff) | 0x00800000); | |
2647 | ||
2648 | bios_wr32(bios, 0x000200, bios_rd32( | |
2649 | bios, 0x000200) & ~0x40000000); | |
2650 | ||
2651 | mdelay(10); | |
2652 | ||
2653 | bios_wr32(bios, 0x00e18c, bios_rd32( | |
2654 | bios, 0x00e18c) & ~0x00020000); | |
2655 | ||
2656 | bios_wr32(bios, 0x000200, bios_rd32( | |
2657 | bios, 0x000200) | 0x40000000); | |
2658 | ||
2659 | bios_wr32(bios, 0x614100, 0x00800018); | |
2660 | bios_wr32(bios, 0x614900, 0x00800018); | |
2661 | ||
2662 | mdelay(10); | |
2663 | ||
2664 | bios_wr32(bios, 0x614100, 0x10000018); | |
2665 | bios_wr32(bios, 0x614900, 0x10000018); | |
2666 | ||
2667 | for (i = 0; i < 3; i++) | |
2668 | bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( | |
2669 | bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); | |
2670 | ||
2671 | for (i = 0; i < 2; i++) | |
2672 | bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( | |
2673 | bios, 0x614300 + (i*0x800)) & 0xfffff0f0); | |
2674 | ||
2675 | for (i = 0; i < 3; i++) | |
2676 | bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( | |
2677 | bios, 0x614380 + (i*0x800)) & 0xfffff0f0); | |
2678 | ||
2679 | for (i = 0; i < 2; i++) | |
2680 | bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( | |
2681 | bios, 0x614200 + (i*0x800)) & 0xfffffff0); | |
2682 | ||
2683 | for (i = 0; i < 2; i++) | |
2684 | bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( | |
2685 | bios, 0x614108 + (i*0x800)) & 0x0fffffff); | |
37383650 | 2686 | return 5; |
6ee73861 BS |
2687 | } |
2688 | ||
2689 | bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | | |
2690 | data); | |
37383650 | 2691 | return 5; |
6ee73861 BS |
2692 | } |
2693 | ||
37383650 | 2694 | static int |
6ee73861 BS |
2695 | init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2696 | { | |
2697 | /* | |
2698 | * INIT_SUB opcode: 0x6B ('k') | |
2699 | * | |
2700 | * offset (8 bit): opcode | |
2701 | * offset + 1 (8 bit): script number | |
2702 | * | |
2703 | * Execute script number "script number", as a subroutine | |
2704 | */ | |
2705 | ||
2706 | uint8_t sub = bios->data[offset + 1]; | |
2707 | ||
2708 | if (!iexec->execute) | |
37383650 | 2709 | return 2; |
6ee73861 BS |
2710 | |
2711 | BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); | |
2712 | ||
2713 | parse_init_table(bios, | |
2714 | ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), | |
2715 | iexec); | |
2716 | ||
2717 | BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); | |
2718 | ||
37383650 | 2719 | return 2; |
6ee73861 BS |
2720 | } |
2721 | ||
37383650 | 2722 | static int |
6ee73861 BS |
2723 | init_ram_condition(struct nvbios *bios, uint16_t offset, |
2724 | struct init_exec *iexec) | |
2725 | { | |
2726 | /* | |
2727 | * INIT_RAM_CONDITION opcode: 0x6D ('m') | |
2728 | * | |
2729 | * offset (8 bit): opcode | |
2730 | * offset + 1 (8 bit): mask | |
2731 | * offset + 2 (8 bit): cmpval | |
2732 | * | |
3c7066bc | 2733 | * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval". |
6ee73861 BS |
2734 | * If condition not met skip subsequent opcodes until condition is |
2735 | * inverted (INIT_NOT), or we hit INIT_RESUME | |
2736 | */ | |
2737 | ||
2738 | uint8_t mask = bios->data[offset + 1]; | |
2739 | uint8_t cmpval = bios->data[offset + 2]; | |
2740 | uint8_t data; | |
2741 | ||
2742 | if (!iexec->execute) | |
37383650 | 2743 | return 3; |
6ee73861 | 2744 | |
3c7066bc | 2745 | data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask; |
6ee73861 BS |
2746 | |
2747 | BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", | |
2748 | offset, data, cmpval); | |
2749 | ||
2750 | if (data == cmpval) | |
2751 | BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); | |
2752 | else { | |
2753 | BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); | |
2754 | iexec->execute = false; | |
2755 | } | |
2756 | ||
37383650 | 2757 | return 3; |
6ee73861 BS |
2758 | } |
2759 | ||
37383650 | 2760 | static int |
6ee73861 BS |
2761 | init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2762 | { | |
2763 | /* | |
2764 | * INIT_NV_REG opcode: 0x6E ('n') | |
2765 | * | |
2766 | * offset (8 bit): opcode | |
2767 | * offset + 1 (32 bit): register | |
2768 | * offset + 5 (32 bit): mask | |
2769 | * offset + 9 (32 bit): data | |
2770 | * | |
2771 | * Assign ((REGVAL("register") & "mask") | "data") to "register" | |
2772 | */ | |
2773 | ||
2774 | uint32_t reg = ROM32(bios->data[offset + 1]); | |
2775 | uint32_t mask = ROM32(bios->data[offset + 5]); | |
2776 | uint32_t data = ROM32(bios->data[offset + 9]); | |
2777 | ||
2778 | if (!iexec->execute) | |
37383650 | 2779 | return 13; |
6ee73861 BS |
2780 | |
2781 | BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", | |
2782 | offset, reg, mask, data); | |
2783 | ||
2784 | bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); | |
2785 | ||
37383650 | 2786 | return 13; |
6ee73861 BS |
2787 | } |
2788 | ||
37383650 | 2789 | static int |
6ee73861 BS |
2790 | init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2791 | { | |
2792 | /* | |
2793 | * INIT_MACRO opcode: 0x6F ('o') | |
2794 | * | |
2795 | * offset (8 bit): opcode | |
2796 | * offset + 1 (8 bit): macro number | |
2797 | * | |
2798 | * Look up macro index "macro number" in the macro index table. | |
2799 | * The macro index table entry has 1 byte for the index in the macro | |
2800 | * table, and 1 byte for the number of times to repeat the macro. | |
2801 | * The macro table entry has 4 bytes for the register address and | |
2802 | * 4 bytes for the value to write to that register | |
2803 | */ | |
2804 | ||
2805 | uint8_t macro_index_tbl_idx = bios->data[offset + 1]; | |
2806 | uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); | |
2807 | uint8_t macro_tbl_idx = bios->data[tmp]; | |
2808 | uint8_t count = bios->data[tmp + 1]; | |
2809 | uint32_t reg, data; | |
2810 | int i; | |
2811 | ||
2812 | if (!iexec->execute) | |
37383650 | 2813 | return 2; |
6ee73861 BS |
2814 | |
2815 | BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " | |
2816 | "Count: 0x%02X\n", | |
2817 | offset, macro_index_tbl_idx, macro_tbl_idx, count); | |
2818 | ||
2819 | for (i = 0; i < count; i++) { | |
2820 | uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; | |
2821 | ||
2822 | reg = ROM32(bios->data[macroentryptr]); | |
2823 | data = ROM32(bios->data[macroentryptr + 4]); | |
2824 | ||
2825 | bios_wr32(bios, reg, data); | |
2826 | } | |
2827 | ||
37383650 | 2828 | return 2; |
6ee73861 BS |
2829 | } |
2830 | ||
37383650 | 2831 | static int |
6ee73861 BS |
2832 | init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2833 | { | |
2834 | /* | |
2835 | * INIT_DONE opcode: 0x71 ('q') | |
2836 | * | |
2837 | * offset (8 bit): opcode | |
2838 | * | |
2839 | * End the current script | |
2840 | */ | |
2841 | ||
2842 | /* mild retval abuse to stop parsing this table */ | |
37383650 | 2843 | return 0; |
6ee73861 BS |
2844 | } |
2845 | ||
37383650 | 2846 | static int |
6ee73861 BS |
2847 | init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2848 | { | |
2849 | /* | |
2850 | * INIT_RESUME opcode: 0x72 ('r') | |
2851 | * | |
2852 | * offset (8 bit): opcode | |
2853 | * | |
2854 | * End the current execute / no-execute condition | |
2855 | */ | |
2856 | ||
2857 | if (iexec->execute) | |
37383650 | 2858 | return 1; |
6ee73861 BS |
2859 | |
2860 | iexec->execute = true; | |
2861 | BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); | |
2862 | ||
37383650 | 2863 | return 1; |
6ee73861 BS |
2864 | } |
2865 | ||
37383650 | 2866 | static int |
6ee73861 BS |
2867 | init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2868 | { | |
2869 | /* | |
2870 | * INIT_TIME opcode: 0x74 ('t') | |
2871 | * | |
2872 | * offset (8 bit): opcode | |
2873 | * offset + 1 (16 bit): time | |
2874 | * | |
2875 | * Sleep for "time" microseconds. | |
2876 | */ | |
2877 | ||
2878 | unsigned time = ROM16(bios->data[offset + 1]); | |
2879 | ||
2880 | if (!iexec->execute) | |
37383650 | 2881 | return 3; |
6ee73861 BS |
2882 | |
2883 | BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", | |
2884 | offset, time); | |
2885 | ||
2886 | if (time < 1000) | |
2887 | udelay(time); | |
2888 | else | |
2889 | msleep((time + 900) / 1000); | |
2890 | ||
37383650 | 2891 | return 3; |
6ee73861 BS |
2892 | } |
2893 | ||
37383650 | 2894 | static int |
6ee73861 BS |
2895 | init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2896 | { | |
2897 | /* | |
2898 | * INIT_CONDITION opcode: 0x75 ('u') | |
2899 | * | |
2900 | * offset (8 bit): opcode | |
2901 | * offset + 1 (8 bit): condition number | |
2902 | * | |
2903 | * Check condition "condition number" in the condition table. | |
2904 | * If condition not met skip subsequent opcodes until condition is | |
2905 | * inverted (INIT_NOT), or we hit INIT_RESUME | |
2906 | */ | |
2907 | ||
2908 | uint8_t cond = bios->data[offset + 1]; | |
2909 | ||
2910 | if (!iexec->execute) | |
37383650 | 2911 | return 2; |
6ee73861 BS |
2912 | |
2913 | BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); | |
2914 | ||
2915 | if (bios_condition_met(bios, offset, cond)) | |
2916 | BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); | |
2917 | else { | |
2918 | BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); | |
2919 | iexec->execute = false; | |
2920 | } | |
2921 | ||
37383650 | 2922 | return 2; |
6ee73861 BS |
2923 | } |
2924 | ||
37383650 | 2925 | static int |
6ee73861 BS |
2926 | init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2927 | { | |
2928 | /* | |
2929 | * INIT_IO_CONDITION opcode: 0x76 | |
2930 | * | |
2931 | * offset (8 bit): opcode | |
2932 | * offset + 1 (8 bit): condition number | |
2933 | * | |
2934 | * Check condition "condition number" in the io condition table. | |
2935 | * If condition not met skip subsequent opcodes until condition is | |
2936 | * inverted (INIT_NOT), or we hit INIT_RESUME | |
2937 | */ | |
2938 | ||
2939 | uint8_t cond = bios->data[offset + 1]; | |
2940 | ||
2941 | if (!iexec->execute) | |
37383650 | 2942 | return 2; |
6ee73861 BS |
2943 | |
2944 | BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); | |
2945 | ||
2946 | if (io_condition_met(bios, offset, cond)) | |
2947 | BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); | |
2948 | else { | |
2949 | BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); | |
2950 | iexec->execute = false; | |
2951 | } | |
2952 | ||
37383650 | 2953 | return 2; |
6ee73861 BS |
2954 | } |
2955 | ||
37383650 | 2956 | static int |
6ee73861 BS |
2957 | init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2958 | { | |
2959 | /* | |
2960 | * INIT_INDEX_IO opcode: 0x78 ('x') | |
2961 | * | |
2962 | * offset (8 bit): opcode | |
2963 | * offset + 1 (16 bit): CRTC port | |
2964 | * offset + 3 (8 bit): CRTC index | |
2965 | * offset + 4 (8 bit): mask | |
2966 | * offset + 5 (8 bit): data | |
2967 | * | |
2968 | * Read value at index "CRTC index" on "CRTC port", AND with "mask", | |
2969 | * OR with "data", write-back | |
2970 | */ | |
2971 | ||
2972 | uint16_t crtcport = ROM16(bios->data[offset + 1]); | |
2973 | uint8_t crtcindex = bios->data[offset + 3]; | |
2974 | uint8_t mask = bios->data[offset + 4]; | |
2975 | uint8_t data = bios->data[offset + 5]; | |
2976 | uint8_t value; | |
2977 | ||
2978 | if (!iexec->execute) | |
37383650 | 2979 | return 6; |
6ee73861 BS |
2980 | |
2981 | BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " | |
2982 | "Data: 0x%02X\n", | |
2983 | offset, crtcport, crtcindex, mask, data); | |
2984 | ||
2985 | value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; | |
2986 | bios_idxprt_wr(bios, crtcport, crtcindex, value); | |
2987 | ||
37383650 | 2988 | return 6; |
6ee73861 BS |
2989 | } |
2990 | ||
37383650 | 2991 | static int |
6ee73861 BS |
2992 | init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
2993 | { | |
2994 | /* | |
2995 | * INIT_PLL opcode: 0x79 ('y') | |
2996 | * | |
2997 | * offset (8 bit): opcode | |
2998 | * offset + 1 (32 bit): register | |
2999 | * offset + 5 (16 bit): freq | |
3000 | * | |
3001 | * Set PLL register "register" to coefficients for frequency (10kHz) | |
3002 | * "freq" | |
3003 | */ | |
3004 | ||
3005 | uint32_t reg = ROM32(bios->data[offset + 1]); | |
3006 | uint16_t freq = ROM16(bios->data[offset + 5]); | |
3007 | ||
3008 | if (!iexec->execute) | |
37383650 | 3009 | return 7; |
6ee73861 BS |
3010 | |
3011 | BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); | |
3012 | ||
3013 | setPLL(bios, reg, freq * 10); | |
3014 | ||
37383650 | 3015 | return 7; |
6ee73861 BS |
3016 | } |
3017 | ||
37383650 | 3018 | static int |
6ee73861 BS |
3019 | init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3020 | { | |
3021 | /* | |
3022 | * INIT_ZM_REG opcode: 0x7A ('z') | |
3023 | * | |
3024 | * offset (8 bit): opcode | |
3025 | * offset + 1 (32 bit): register | |
3026 | * offset + 5 (32 bit): value | |
3027 | * | |
3028 | * Assign "value" to "register" | |
3029 | */ | |
3030 | ||
3031 | uint32_t reg = ROM32(bios->data[offset + 1]); | |
3032 | uint32_t value = ROM32(bios->data[offset + 5]); | |
3033 | ||
3034 | if (!iexec->execute) | |
37383650 | 3035 | return 9; |
6ee73861 BS |
3036 | |
3037 | if (reg == 0x000200) | |
3038 | value |= 1; | |
3039 | ||
3040 | bios_wr32(bios, reg, value); | |
3041 | ||
37383650 | 3042 | return 9; |
6ee73861 BS |
3043 | } |
3044 | ||
37383650 | 3045 | static int |
6ee73861 BS |
3046 | init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, |
3047 | struct init_exec *iexec) | |
3048 | { | |
3049 | /* | |
3050 | * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') | |
3051 | * | |
3052 | * offset (8 bit): opcode | |
3053 | * offset + 1 (8 bit): PLL type | |
3054 | * offset + 2 (32 bit): frequency 0 | |
3055 | * | |
3056 | * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at | |
3057 | * ram_restrict_table_ptr. The value read from there is used to select | |
3058 | * a frequency from the table starting at 'frequency 0' to be | |
3059 | * programmed into the PLL corresponding to 'type'. | |
3060 | * | |
3061 | * The PLL limits table on cards using this opcode has a mapping of | |
3062 | * 'type' to the relevant registers. | |
3063 | */ | |
3064 | ||
3065 | struct drm_device *dev = bios->dev; | |
3066 | uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; | |
3067 | uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; | |
3068 | uint8_t type = bios->data[offset + 1]; | |
3069 | uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); | |
3070 | uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; | |
37383650 | 3071 | int len = 2 + bios->ram_restrict_group_count * 4; |
6ee73861 BS |
3072 | int i; |
3073 | ||
3074 | if (!iexec->execute) | |
37383650 | 3075 | return len; |
6ee73861 BS |
3076 | |
3077 | if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { | |
3078 | NV_ERROR(dev, "PLL limits table not version 3.x\n"); | |
37383650 | 3079 | return len; /* deliberate, allow default clocks to remain */ |
6ee73861 BS |
3080 | } |
3081 | ||
3082 | entry = pll_limits + pll_limits[1]; | |
3083 | for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { | |
3084 | if (entry[0] == type) { | |
3085 | uint32_t reg = ROM32(entry[3]); | |
3086 | ||
3087 | BIOSLOG(bios, "0x%04X: " | |
3088 | "Type %02x Reg 0x%08x Freq %dKHz\n", | |
3089 | offset, type, reg, freq); | |
3090 | ||
3091 | setPLL(bios, reg, freq); | |
37383650 | 3092 | return len; |
6ee73861 BS |
3093 | } |
3094 | } | |
3095 | ||
3096 | NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); | |
37383650 | 3097 | return len; |
6ee73861 BS |
3098 | } |
3099 | ||
37383650 | 3100 | static int |
6ee73861 BS |
3101 | init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3102 | { | |
3103 | /* | |
3104 | * INIT_8C opcode: 0x8C ('') | |
3105 | * | |
3106 | * NOP so far.... | |
3107 | * | |
3108 | */ | |
3109 | ||
37383650 | 3110 | return 1; |
6ee73861 BS |
3111 | } |
3112 | ||
37383650 | 3113 | static int |
6ee73861 BS |
3114 | init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3115 | { | |
3116 | /* | |
3117 | * INIT_8D opcode: 0x8D ('') | |
3118 | * | |
3119 | * NOP so far.... | |
3120 | * | |
3121 | */ | |
3122 | ||
37383650 | 3123 | return 1; |
6ee73861 BS |
3124 | } |
3125 | ||
37383650 | 3126 | static int |
6ee73861 BS |
3127 | init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3128 | { | |
3129 | /* | |
3130 | * INIT_GPIO opcode: 0x8E ('') | |
3131 | * | |
3132 | * offset (8 bit): opcode | |
3133 | * | |
3134 | * Loop over all entries in the DCB GPIO table, and initialise | |
3135 | * each GPIO according to various values listed in each entry | |
3136 | */ | |
3137 | ||
2535d71c | 3138 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; |
6ee73861 | 3139 | const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; |
6ee73861 BS |
3140 | int i; |
3141 | ||
2535d71c BS |
3142 | if (dev_priv->card_type != NV_50) { |
3143 | NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); | |
309b8c89 | 3144 | return 1; |
6ee73861 BS |
3145 | } |
3146 | ||
2535d71c BS |
3147 | if (!iexec->execute) |
3148 | return 1; | |
6ee73861 | 3149 | |
2535d71c BS |
3150 | for (i = 0; i < bios->dcb.gpio.entries; i++) { |
3151 | struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i]; | |
3152 | uint32_t r, s, v; | |
6ee73861 | 3153 | |
2535d71c | 3154 | BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry); |
6ee73861 | 3155 | |
73db4bed BS |
3156 | BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n", |
3157 | offset, gpio->tag, gpio->state_default); | |
3158 | if (bios->execute) | |
3159 | nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default); | |
6ee73861 | 3160 | |
45284162 BS |
3161 | /* The NVIDIA binary driver doesn't appear to actually do |
3162 | * any of this, my VBIOS does however. | |
3163 | */ | |
3164 | /* Not a clue, needs de-magicing */ | |
2535d71c BS |
3165 | r = nv50_gpio_ctl[gpio->line >> 4]; |
3166 | s = (gpio->line & 0x0f); | |
6ee73861 | 3167 | v = bios_rd32(bios, r) & ~(0x00010001 << s); |
2535d71c | 3168 | switch ((gpio->entry & 0x06000000) >> 25) { |
6ee73861 BS |
3169 | case 1: |
3170 | v |= (0x00000001 << s); | |
3171 | break; | |
3172 | case 2: | |
3173 | v |= (0x00010000 << s); | |
3174 | break; | |
3175 | default: | |
3176 | break; | |
3177 | } | |
3178 | bios_wr32(bios, r, v); | |
3179 | } | |
3180 | ||
37383650 | 3181 | return 1; |
6ee73861 BS |
3182 | } |
3183 | ||
37383650 | 3184 | static int |
6ee73861 BS |
3185 | init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, |
3186 | struct init_exec *iexec) | |
3187 | { | |
3188 | /* | |
3189 | * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') | |
3190 | * | |
3191 | * offset (8 bit): opcode | |
3192 | * offset + 1 (32 bit): reg | |
3193 | * offset + 5 (8 bit): regincrement | |
3194 | * offset + 6 (8 bit): count | |
3195 | * offset + 7 (32 bit): value 1,1 | |
3196 | * ... | |
3197 | * | |
3198 | * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at | |
3199 | * ram_restrict_table_ptr. The value read from here is 'n', and | |
3200 | * "value 1,n" gets written to "reg". This repeats "count" times and on | |
3201 | * each iteration 'm', "reg" increases by "regincrement" and | |
3202 | * "value m,n" is used. The extent of n is limited by a number read | |
3203 | * from the 'M' BIT table, herein called "blocklen" | |
3204 | */ | |
3205 | ||
3206 | uint32_t reg = ROM32(bios->data[offset + 1]); | |
3207 | uint8_t regincrement = bios->data[offset + 5]; | |
3208 | uint8_t count = bios->data[offset + 6]; | |
3209 | uint32_t strap_ramcfg, data; | |
37383650 MK |
3210 | /* previously set by 'M' BIT table */ |
3211 | uint16_t blocklen = bios->ram_restrict_group_count * 4; | |
3212 | int len = 7 + count * blocklen; | |
6ee73861 BS |
3213 | uint8_t index; |
3214 | int i; | |
3215 | ||
309b8c89 | 3216 | /* critical! to know the length of the opcode */; |
6ee73861 BS |
3217 | if (!blocklen) { |
3218 | NV_ERROR(bios->dev, | |
3219 | "0x%04X: Zero block length - has the M table " | |
3220 | "been parsed?\n", offset); | |
9170a824 | 3221 | return -EINVAL; |
6ee73861 BS |
3222 | } |
3223 | ||
309b8c89 BS |
3224 | if (!iexec->execute) |
3225 | return len; | |
3226 | ||
6ee73861 BS |
3227 | strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; |
3228 | index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; | |
3229 | ||
3230 | BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " | |
3231 | "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", | |
3232 | offset, reg, regincrement, count, strap_ramcfg, index); | |
3233 | ||
3234 | for (i = 0; i < count; i++) { | |
3235 | data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); | |
3236 | ||
3237 | bios_wr32(bios, reg, data); | |
3238 | ||
3239 | reg += regincrement; | |
3240 | } | |
3241 | ||
37383650 | 3242 | return len; |
6ee73861 BS |
3243 | } |
3244 | ||
37383650 | 3245 | static int |
6ee73861 BS |
3246 | init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3247 | { | |
3248 | /* | |
3249 | * INIT_COPY_ZM_REG opcode: 0x90 ('') | |
3250 | * | |
3251 | * offset (8 bit): opcode | |
3252 | * offset + 1 (32 bit): src reg | |
3253 | * offset + 5 (32 bit): dst reg | |
3254 | * | |
3255 | * Put contents of "src reg" into "dst reg" | |
3256 | */ | |
3257 | ||
3258 | uint32_t srcreg = ROM32(bios->data[offset + 1]); | |
3259 | uint32_t dstreg = ROM32(bios->data[offset + 5]); | |
3260 | ||
3261 | if (!iexec->execute) | |
37383650 | 3262 | return 9; |
6ee73861 BS |
3263 | |
3264 | bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); | |
3265 | ||
37383650 | 3266 | return 9; |
6ee73861 BS |
3267 | } |
3268 | ||
37383650 | 3269 | static int |
6ee73861 BS |
3270 | init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, |
3271 | struct init_exec *iexec) | |
3272 | { | |
3273 | /* | |
3274 | * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') | |
3275 | * | |
3276 | * offset (8 bit): opcode | |
3277 | * offset + 1 (32 bit): dst reg | |
3278 | * offset + 5 (8 bit): count | |
3279 | * offset + 6 (32 bit): data 1 | |
3280 | * ... | |
3281 | * | |
3282 | * For each of "count" values write "data n" to "dst reg" | |
3283 | */ | |
3284 | ||
3285 | uint32_t reg = ROM32(bios->data[offset + 1]); | |
3286 | uint8_t count = bios->data[offset + 5]; | |
37383650 | 3287 | int len = 6 + count * 4; |
6ee73861 BS |
3288 | int i; |
3289 | ||
3290 | if (!iexec->execute) | |
37383650 | 3291 | return len; |
6ee73861 BS |
3292 | |
3293 | for (i = 0; i < count; i++) { | |
3294 | uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); | |
3295 | bios_wr32(bios, reg, data); | |
3296 | } | |
3297 | ||
37383650 | 3298 | return len; |
6ee73861 BS |
3299 | } |
3300 | ||
37383650 | 3301 | static int |
6ee73861 BS |
3302 | init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3303 | { | |
3304 | /* | |
3305 | * INIT_RESERVED opcode: 0x92 ('') | |
3306 | * | |
3307 | * offset (8 bit): opcode | |
3308 | * | |
3309 | * Seemingly does nothing | |
3310 | */ | |
3311 | ||
37383650 | 3312 | return 1; |
6ee73861 BS |
3313 | } |
3314 | ||
37383650 | 3315 | static int |
6ee73861 BS |
3316 | init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3317 | { | |
3318 | /* | |
3319 | * INIT_96 opcode: 0x96 ('') | |
3320 | * | |
3321 | * offset (8 bit): opcode | |
3322 | * offset + 1 (32 bit): sreg | |
3323 | * offset + 5 (8 bit): sshift | |
3324 | * offset + 6 (8 bit): smask | |
3325 | * offset + 7 (8 bit): index | |
3326 | * offset + 8 (32 bit): reg | |
3327 | * offset + 12 (32 bit): mask | |
3328 | * offset + 16 (8 bit): shift | |
3329 | * | |
3330 | */ | |
3331 | ||
3332 | uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); | |
3333 | uint32_t reg = ROM32(bios->data[offset + 8]); | |
3334 | uint32_t mask = ROM32(bios->data[offset + 12]); | |
3335 | uint32_t val; | |
3336 | ||
3337 | val = bios_rd32(bios, ROM32(bios->data[offset + 1])); | |
3338 | if (bios->data[offset + 5] < 0x80) | |
3339 | val >>= bios->data[offset + 5]; | |
3340 | else | |
3341 | val <<= (0x100 - bios->data[offset + 5]); | |
3342 | val &= bios->data[offset + 6]; | |
3343 | ||
3344 | val = bios->data[ROM16(bios->data[xlatptr]) + val]; | |
3345 | val <<= bios->data[offset + 16]; | |
3346 | ||
3347 | if (!iexec->execute) | |
37383650 | 3348 | return 17; |
6ee73861 BS |
3349 | |
3350 | bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); | |
37383650 | 3351 | return 17; |
6ee73861 BS |
3352 | } |
3353 | ||
37383650 | 3354 | static int |
6ee73861 BS |
3355 | init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3356 | { | |
3357 | /* | |
3358 | * INIT_97 opcode: 0x97 ('') | |
3359 | * | |
3360 | * offset (8 bit): opcode | |
3361 | * offset + 1 (32 bit): register | |
3362 | * offset + 5 (32 bit): mask | |
3363 | * offset + 9 (32 bit): value | |
3364 | * | |
3365 | * Adds "value" to "register" preserving the fields specified | |
3366 | * by "mask" | |
3367 | */ | |
3368 | ||
3369 | uint32_t reg = ROM32(bios->data[offset + 1]); | |
3370 | uint32_t mask = ROM32(bios->data[offset + 5]); | |
3371 | uint32_t add = ROM32(bios->data[offset + 9]); | |
3372 | uint32_t val; | |
3373 | ||
3374 | val = bios_rd32(bios, reg); | |
3375 | val = (val & mask) | ((val + add) & ~mask); | |
3376 | ||
3377 | if (!iexec->execute) | |
37383650 | 3378 | return 13; |
6ee73861 BS |
3379 | |
3380 | bios_wr32(bios, reg, val); | |
37383650 | 3381 | return 13; |
6ee73861 BS |
3382 | } |
3383 | ||
37383650 | 3384 | static int |
6ee73861 BS |
3385 | init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3386 | { | |
3387 | /* | |
3388 | * INIT_AUXCH opcode: 0x98 ('') | |
3389 | * | |
3390 | * offset (8 bit): opcode | |
3391 | * offset + 1 (32 bit): address | |
3392 | * offset + 5 (8 bit): count | |
3393 | * offset + 6 (8 bit): mask 0 | |
3394 | * offset + 7 (8 bit): data 0 | |
3395 | * ... | |
3396 | * | |
3397 | */ | |
3398 | ||
3399 | struct drm_device *dev = bios->dev; | |
3400 | struct nouveau_i2c_chan *auxch; | |
3401 | uint32_t addr = ROM32(bios->data[offset + 1]); | |
37383650 MK |
3402 | uint8_t count = bios->data[offset + 5]; |
3403 | int len = 6 + count * 2; | |
6ee73861 BS |
3404 | int ret, i; |
3405 | ||
3406 | if (!bios->display.output) { | |
3407 | NV_ERROR(dev, "INIT_AUXCH: no active output\n"); | |
309b8c89 | 3408 | return len; |
6ee73861 BS |
3409 | } |
3410 | ||
3411 | auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); | |
3412 | if (!auxch) { | |
3413 | NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", | |
3414 | bios->display.output->i2c_index); | |
309b8c89 | 3415 | return len; |
6ee73861 BS |
3416 | } |
3417 | ||
3418 | if (!iexec->execute) | |
37383650 | 3419 | return len; |
6ee73861 BS |
3420 | |
3421 | offset += 6; | |
37383650 | 3422 | for (i = 0; i < count; i++, offset += 2) { |
6ee73861 BS |
3423 | uint8_t data; |
3424 | ||
3425 | ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); | |
3426 | if (ret) { | |
3427 | NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); | |
309b8c89 | 3428 | return len; |
6ee73861 BS |
3429 | } |
3430 | ||
3431 | data &= bios->data[offset + 0]; | |
3432 | data |= bios->data[offset + 1]; | |
3433 | ||
3434 | ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); | |
3435 | if (ret) { | |
3436 | NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); | |
309b8c89 | 3437 | return len; |
6ee73861 BS |
3438 | } |
3439 | } | |
3440 | ||
37383650 | 3441 | return len; |
6ee73861 BS |
3442 | } |
3443 | ||
37383650 | 3444 | static int |
6ee73861 BS |
3445 | init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) |
3446 | { | |
3447 | /* | |
3448 | * INIT_ZM_AUXCH opcode: 0x99 ('') | |
3449 | * | |
3450 | * offset (8 bit): opcode | |
3451 | * offset + 1 (32 bit): address | |
3452 | * offset + 5 (8 bit): count | |
3453 | * offset + 6 (8 bit): data 0 | |
3454 | * ... | |
3455 | * | |
3456 | */ | |
3457 | ||
3458 | struct drm_device *dev = bios->dev; | |
3459 | struct nouveau_i2c_chan *auxch; | |
3460 | uint32_t addr = ROM32(bios->data[offset + 1]); | |
37383650 MK |
3461 | uint8_t count = bios->data[offset + 5]; |
3462 | int len = 6 + count; | |
6ee73861 BS |
3463 | int ret, i; |
3464 | ||
3465 | if (!bios->display.output) { | |
3466 | NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); | |
309b8c89 | 3467 | return len; |
6ee73861 BS |
3468 | } |
3469 | ||
3470 | auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); | |
3471 | if (!auxch) { | |
3472 | NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", | |
3473 | bios->display.output->i2c_index); | |
309b8c89 | 3474 | return len; |
6ee73861 BS |
3475 | } |
3476 | ||
3477 | if (!iexec->execute) | |
37383650 | 3478 | return len; |
6ee73861 BS |
3479 | |
3480 | offset += 6; | |
37383650 | 3481 | for (i = 0; i < count; i++, offset++) { |
6ee73861 BS |
3482 | ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); |
3483 | if (ret) { | |
3484 | NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); | |
309b8c89 | 3485 | return len; |
6ee73861 BS |
3486 | } |
3487 | } | |
3488 | ||
37383650 | 3489 | return len; |
6ee73861 BS |
3490 | } |
3491 | ||
3492 | static struct init_tbl_entry itbl_entry[] = { | |
3493 | /* command name , id , length , offset , mult , command handler */ | |
3494 | /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ | |
37383650 MK |
3495 | { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, |
3496 | { "INIT_REPEAT" , 0x33, init_repeat }, | |
3497 | { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, | |
3498 | { "INIT_END_REPEAT" , 0x36, init_end_repeat }, | |
3499 | { "INIT_COPY" , 0x37, init_copy }, | |
3500 | { "INIT_NOT" , 0x38, init_not }, | |
3501 | { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, | |
25908b77 BS |
3502 | { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, |
3503 | { "INIT_OP_3B" , 0x3B, init_op_3b }, | |
3504 | { "INIT_OP_3C" , 0x3C, init_op_3c }, | |
37383650 MK |
3505 | { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, |
3506 | { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, | |
3507 | { "INIT_PLL2" , 0x4B, init_pll2 }, | |
3508 | { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, | |
3509 | { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, | |
3510 | { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, | |
3511 | { "INIT_TMDS" , 0x4F, init_tmds }, | |
3512 | { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, | |
3513 | { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, | |
3514 | { "INIT_CR" , 0x52, init_cr }, | |
3515 | { "INIT_ZM_CR" , 0x53, init_zm_cr }, | |
3516 | { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, | |
3517 | { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, | |
3518 | { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, | |
6ee73861 | 3519 | /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ |
37383650 MK |
3520 | { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, |
3521 | { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, | |
3522 | { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, | |
3523 | { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, | |
3524 | { "INIT_RESET" , 0x65, init_reset }, | |
3525 | { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, | |
3526 | { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, | |
3527 | { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, | |
3528 | { "INIT_IO" , 0x69, init_io }, | |
3529 | { "INIT_SUB" , 0x6B, init_sub }, | |
3530 | { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, | |
3531 | { "INIT_NV_REG" , 0x6E, init_nv_reg }, | |
3532 | { "INIT_MACRO" , 0x6F, init_macro }, | |
3533 | { "INIT_DONE" , 0x71, init_done }, | |
3534 | { "INIT_RESUME" , 0x72, init_resume }, | |
6ee73861 | 3535 | /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ |
37383650 MK |
3536 | { "INIT_TIME" , 0x74, init_time }, |
3537 | { "INIT_CONDITION" , 0x75, init_condition }, | |
3538 | { "INIT_IO_CONDITION" , 0x76, init_io_condition }, | |
3539 | { "INIT_INDEX_IO" , 0x78, init_index_io }, | |
3540 | { "INIT_PLL" , 0x79, init_pll }, | |
3541 | { "INIT_ZM_REG" , 0x7A, init_zm_reg }, | |
3542 | { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, | |
3543 | { "INIT_8C" , 0x8C, init_8c }, | |
3544 | { "INIT_8D" , 0x8D, init_8d }, | |
3545 | { "INIT_GPIO" , 0x8E, init_gpio }, | |
3546 | { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, | |
3547 | { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, | |
3548 | { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, | |
3549 | { "INIT_RESERVED" , 0x92, init_reserved }, | |
3550 | { "INIT_96" , 0x96, init_96 }, | |
3551 | { "INIT_97" , 0x97, init_97 }, | |
3552 | { "INIT_AUXCH" , 0x98, init_auxch }, | |
3553 | { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, | |
3554 | { NULL , 0 , NULL } | |
6ee73861 BS |
3555 | }; |
3556 | ||
6ee73861 BS |
3557 | #define MAX_TABLE_OPS 1000 |
3558 | ||
3559 | static int | |
3560 | parse_init_table(struct nvbios *bios, unsigned int offset, | |
3561 | struct init_exec *iexec) | |
3562 | { | |
3563 | /* | |
3564 | * Parses all commands in an init table. | |
3565 | * | |
3566 | * We start out executing all commands found in the init table. Some | |
3567 | * opcodes may change the status of iexec->execute to SKIP, which will | |
3568 | * cause the following opcodes to perform no operation until the value | |
3569 | * is changed back to EXECUTE. | |
3570 | */ | |
3571 | ||
92b96187 | 3572 | int count = 0, i, ret; |
6ee73861 BS |
3573 | uint8_t id; |
3574 | ||
3575 | /* | |
3576 | * Loop until INIT_DONE causes us to break out of the loop | |
3577 | * (or until offset > bios length just in case... ) | |
3578 | * (and no more than MAX_TABLE_OPS iterations, just in case... ) | |
3579 | */ | |
3580 | while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { | |
3581 | id = bios->data[offset]; | |
3582 | ||
3583 | /* Find matching id in itbl_entry */ | |
3584 | for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) | |
3585 | ; | |
3586 | ||
92b96187 | 3587 | if (!itbl_entry[i].name) { |
6ee73861 BS |
3588 | NV_ERROR(bios->dev, |
3589 | "0x%04X: Init table command not found: " | |
3590 | "0x%02X\n", offset, id); | |
3591 | return -ENOENT; | |
3592 | } | |
92b96187 BS |
3593 | |
3594 | BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, | |
3595 | itbl_entry[i].id, itbl_entry[i].name); | |
3596 | ||
3597 | /* execute eventual command handler */ | |
3598 | ret = (*itbl_entry[i].handler)(bios, offset, iexec); | |
3599 | if (ret < 0) { | |
3600 | NV_ERROR(bios->dev, "0x%04X: Failed parsing init " | |
3601 | "table opcode: %s %d\n", offset, | |
3602 | itbl_entry[i].name, ret); | |
3603 | } | |
3604 | ||
3605 | if (ret <= 0) | |
3606 | break; | |
3607 | ||
3608 | /* | |
3609 | * Add the offset of the current command including all data | |
3610 | * of that command. The offset will then be pointing on the | |
3611 | * next op code. | |
3612 | */ | |
3613 | offset += ret; | |
6ee73861 BS |
3614 | } |
3615 | ||
3616 | if (offset >= bios->length) | |
3617 | NV_WARN(bios->dev, | |
3618 | "Offset 0x%04X greater than known bios image length. " | |
3619 | "Corrupt image?\n", offset); | |
3620 | if (count >= MAX_TABLE_OPS) | |
3621 | NV_WARN(bios->dev, | |
3622 | "More than %d opcodes to a table is unlikely, " | |
3623 | "is the bios image corrupt?\n", MAX_TABLE_OPS); | |
3624 | ||
3625 | return 0; | |
3626 | } | |
3627 | ||
3628 | static void | |
3629 | parse_init_tables(struct nvbios *bios) | |
3630 | { | |
3631 | /* Loops and calls parse_init_table() for each present table. */ | |
3632 | ||
3633 | int i = 0; | |
3634 | uint16_t table; | |
3635 | struct init_exec iexec = {true, false}; | |
3636 | ||
3637 | if (bios->old_style_init) { | |
3638 | if (bios->init_script_tbls_ptr) | |
3639 | parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); | |
3640 | if (bios->extra_init_script_tbl_ptr) | |
3641 | parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); | |
3642 | ||
3643 | return; | |
3644 | } | |
3645 | ||
3646 | while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { | |
3647 | NV_INFO(bios->dev, | |
3648 | "Parsing VBIOS init table %d at offset 0x%04X\n", | |
3649 | i / 2, table); | |
3650 | BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); | |
3651 | ||
3652 | parse_init_table(bios, table, &iexec); | |
3653 | i += 2; | |
3654 | } | |
3655 | } | |
3656 | ||
3657 | static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) | |
3658 | { | |
3659 | int compare_record_len, i = 0; | |
3660 | uint16_t compareclk, scriptptr = 0; | |
3661 | ||
3662 | if (bios->major_version < 5) /* pre BIT */ | |
3663 | compare_record_len = 3; | |
3664 | else | |
3665 | compare_record_len = 4; | |
3666 | ||
3667 | do { | |
3668 | compareclk = ROM16(bios->data[clktable + compare_record_len * i]); | |
3669 | if (pxclk >= compareclk * 10) { | |
3670 | if (bios->major_version < 5) { | |
3671 | uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; | |
3672 | scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); | |
3673 | } else | |
3674 | scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); | |
3675 | break; | |
3676 | } | |
3677 | i++; | |
3678 | } while (compareclk); | |
3679 | ||
3680 | return scriptptr; | |
3681 | } | |
3682 | ||
3683 | static void | |
3684 | run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, | |
3685 | struct dcb_entry *dcbent, int head, bool dl) | |
3686 | { | |
3687 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 3688 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
3689 | struct init_exec iexec = {true, false}; |
3690 | ||
3691 | NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", | |
3692 | scriptptr); | |
3693 | bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, | |
3694 | head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); | |
3695 | /* note: if dcb entries have been merged, index may be misleading */ | |
3696 | NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); | |
3697 | parse_init_table(bios, scriptptr, &iexec); | |
3698 | ||
3699 | nv04_dfp_bind_head(dev, dcbent, head, dl); | |
3700 | } | |
3701 | ||
3702 | static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) | |
3703 | { | |
3704 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 3705 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
3706 | uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); |
3707 | uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); | |
3708 | ||
3709 | if (!bios->fp.xlated_entry || !sub || !scriptofs) | |
3710 | return -EINVAL; | |
3711 | ||
3712 | run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); | |
3713 | ||
3714 | if (script == LVDS_PANEL_OFF) { | |
3715 | /* off-on delay in ms */ | |
3716 | msleep(ROM16(bios->data[bios->fp.xlated_entry + 7])); | |
3717 | } | |
3718 | #ifdef __powerpc__ | |
3719 | /* Powerbook specific quirks */ | |
3d9aefb8 FJ |
3720 | if ((dev->pci_device & 0xffff) == 0x0179 || |
3721 | (dev->pci_device & 0xffff) == 0x0189 || | |
3722 | (dev->pci_device & 0xffff) == 0x0329) { | |
3723 | if (script == LVDS_RESET) { | |
3724 | nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); | |
3725 | ||
3726 | } else if (script == LVDS_PANEL_ON) { | |
3727 | bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, | |
3728 | bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) | |
3729 | | (1 << 31)); | |
3730 | bios_wr32(bios, NV_PCRTC_GPIO_EXT, | |
3731 | bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1); | |
3732 | ||
3733 | } else if (script == LVDS_PANEL_OFF) { | |
3734 | bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL, | |
3735 | bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL) | |
3736 | & ~(1 << 31)); | |
3737 | bios_wr32(bios, NV_PCRTC_GPIO_EXT, | |
3738 | bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3); | |
6ee73861 BS |
3739 | } |
3740 | } | |
3741 | #endif | |
3742 | ||
3743 | return 0; | |
3744 | } | |
3745 | ||
3746 | static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) | |
3747 | { | |
3748 | /* | |
3749 | * The BIT LVDS table's header has the information to setup the | |
3750 | * necessary registers. Following the standard 4 byte header are: | |
3751 | * A bitmask byte and a dual-link transition pxclk value for use in | |
3752 | * selecting the init script when not using straps; 4 script pointers | |
3753 | * for panel power, selected by output and on/off; and 8 table pointers | |
3754 | * for panel init, the needed one determined by output, and bits in the | |
3755 | * conf byte. These tables are similar to the TMDS tables, consisting | |
3756 | * of a list of pxclks and script pointers. | |
3757 | */ | |
3758 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 3759 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
3760 | unsigned int outputset = (dcbent->or == 4) ? 1 : 0; |
3761 | uint16_t scriptptr = 0, clktable; | |
6ee73861 BS |
3762 | |
3763 | /* | |
3764 | * For now we assume version 3.0 table - g80 support will need some | |
3765 | * changes | |
3766 | */ | |
3767 | ||
3768 | switch (script) { | |
3769 | case LVDS_INIT: | |
3770 | return -ENOSYS; | |
3771 | case LVDS_BACKLIGHT_ON: | |
3772 | case LVDS_PANEL_ON: | |
3773 | scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); | |
3774 | break; | |
3775 | case LVDS_BACKLIGHT_OFF: | |
3776 | case LVDS_PANEL_OFF: | |
3777 | scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); | |
3778 | break; | |
3779 | case LVDS_RESET: | |
f3bbb9cc BS |
3780 | clktable = bios->fp.lvdsmanufacturerpointer + 15; |
3781 | if (dcbent->or == 4) | |
3782 | clktable += 8; | |
3783 | ||
6ee73861 BS |
3784 | if (dcbent->lvdsconf.use_straps_for_mode) { |
3785 | if (bios->fp.dual_link) | |
f3bbb9cc BS |
3786 | clktable += 4; |
3787 | if (bios->fp.if_is_24bit) | |
3788 | clktable += 2; | |
6ee73861 BS |
3789 | } else { |
3790 | /* using EDID */ | |
f3bbb9cc | 3791 | int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; |
6ee73861 BS |
3792 | |
3793 | if (bios->fp.dual_link) { | |
f3bbb9cc BS |
3794 | clktable += 4; |
3795 | cmpval_24bit <<= 1; | |
6ee73861 | 3796 | } |
f3bbb9cc BS |
3797 | |
3798 | if (bios->fp.strapless_is_24bit & cmpval_24bit) | |
3799 | clktable += 2; | |
6ee73861 BS |
3800 | } |
3801 | ||
f3bbb9cc | 3802 | clktable = ROM16(bios->data[clktable]); |
6ee73861 BS |
3803 | if (!clktable) { |
3804 | NV_ERROR(dev, "Pixel clock comparison table not found\n"); | |
3805 | return -ENOENT; | |
3806 | } | |
3807 | scriptptr = clkcmptable(bios, clktable, pxclk); | |
3808 | } | |
3809 | ||
3810 | if (!scriptptr) { | |
3811 | NV_ERROR(dev, "LVDS output init script not found\n"); | |
3812 | return -ENOENT; | |
3813 | } | |
3814 | run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); | |
3815 | ||
3816 | return 0; | |
3817 | } | |
3818 | ||
3819 | int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) | |
3820 | { | |
3821 | /* | |
3822 | * LVDS operations are multiplexed in an effort to present a single API | |
3823 | * which works with two vastly differing underlying structures. | |
3824 | * This acts as the demux | |
3825 | */ | |
3826 | ||
3827 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 3828 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
3829 | uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; |
3830 | uint32_t sel_clk_binding, sel_clk; | |
3831 | int ret; | |
3832 | ||
3833 | if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || | |
3834 | (lvds_ver >= 0x30 && script == LVDS_INIT)) | |
3835 | return 0; | |
3836 | ||
3837 | if (!bios->fp.lvds_init_run) { | |
3838 | bios->fp.lvds_init_run = true; | |
3839 | call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); | |
3840 | } | |
3841 | ||
3842 | if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) | |
3843 | call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); | |
3844 | if (script == LVDS_RESET && bios->fp.power_off_for_reset) | |
3845 | call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); | |
3846 | ||
3847 | NV_TRACE(dev, "Calling LVDS script %d:\n", script); | |
3848 | ||
3849 | /* don't let script change pll->head binding */ | |
3850 | sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; | |
3851 | ||
3852 | if (lvds_ver < 0x30) | |
3853 | ret = call_lvds_manufacturer_script(dev, dcbent, head, script); | |
3854 | else | |
3855 | ret = run_lvds_table(dev, dcbent, head, script, pxclk); | |
3856 | ||
3857 | bios->fp.last_script_invoc = (script << 1 | head); | |
3858 | ||
3859 | sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; | |
3860 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); | |
3861 | /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ | |
3862 | nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); | |
3863 | ||
3864 | return ret; | |
3865 | } | |
3866 | ||
3867 | struct lvdstableheader { | |
3868 | uint8_t lvds_ver, headerlen, recordlen; | |
3869 | }; | |
3870 | ||
3871 | static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) | |
3872 | { | |
3873 | /* | |
3874 | * BMP version (0xa) LVDS table has a simple header of version and | |
3875 | * record length. The BIT LVDS table has the typical BIT table header: | |
3876 | * version byte, header length byte, record length byte, and a byte for | |
3877 | * the maximum number of records that can be held in the table. | |
3878 | */ | |
3879 | ||
3880 | uint8_t lvds_ver, headerlen, recordlen; | |
3881 | ||
3882 | memset(lth, 0, sizeof(struct lvdstableheader)); | |
3883 | ||
3884 | if (bios->fp.lvdsmanufacturerpointer == 0x0) { | |
3885 | NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); | |
3886 | return -EINVAL; | |
3887 | } | |
3888 | ||
3889 | lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; | |
3890 | ||
3891 | switch (lvds_ver) { | |
3892 | case 0x0a: /* pre NV40 */ | |
3893 | headerlen = 2; | |
3894 | recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; | |
3895 | break; | |
3896 | case 0x30: /* NV4x */ | |
3897 | headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; | |
3898 | if (headerlen < 0x1f) { | |
3899 | NV_ERROR(dev, "LVDS table header not understood\n"); | |
3900 | return -EINVAL; | |
3901 | } | |
3902 | recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; | |
3903 | break; | |
3904 | case 0x40: /* G80/G90 */ | |
3905 | headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; | |
3906 | if (headerlen < 0x7) { | |
3907 | NV_ERROR(dev, "LVDS table header not understood\n"); | |
3908 | return -EINVAL; | |
3909 | } | |
3910 | recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; | |
3911 | break; | |
3912 | default: | |
3913 | NV_ERROR(dev, | |
3914 | "LVDS table revision %d.%d not currently supported\n", | |
3915 | lvds_ver >> 4, lvds_ver & 0xf); | |
3916 | return -ENOSYS; | |
3917 | } | |
3918 | ||
3919 | lth->lvds_ver = lvds_ver; | |
3920 | lth->headerlen = headerlen; | |
3921 | lth->recordlen = recordlen; | |
3922 | ||
3923 | return 0; | |
3924 | } | |
3925 | ||
3926 | static int | |
3927 | get_fp_strap(struct drm_device *dev, struct nvbios *bios) | |
3928 | { | |
3929 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
3930 | ||
3931 | /* | |
3932 | * The fp strap is normally dictated by the "User Strap" in | |
3933 | * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the | |
3934 | * Internal_Flags struct at 0x48 is set, the user strap gets overriden | |
3935 | * by the PCI subsystem ID during POST, but not before the previous user | |
3936 | * strap has been committed to CR58 for CR57=0xf on head A, which may be | |
3937 | * read and used instead | |
3938 | */ | |
3939 | ||
3940 | if (bios->major_version < 5 && bios->data[0x48] & 0x4) | |
3941 | return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; | |
3942 | ||
3943 | if (dev_priv->card_type >= NV_50) | |
3944 | return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; | |
3945 | else | |
3946 | return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; | |
3947 | } | |
3948 | ||
3949 | static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) | |
3950 | { | |
3951 | uint8_t *fptable; | |
3952 | uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; | |
3953 | int ret, ofs, fpstrapping; | |
3954 | struct lvdstableheader lth; | |
3955 | ||
3956 | if (bios->fp.fptablepointer == 0x0) { | |
3957 | /* Apple cards don't have the fp table; the laptops use DDC */ | |
3958 | /* The table is also missing on some x86 IGPs */ | |
3959 | #ifndef __powerpc__ | |
3960 | NV_ERROR(dev, "Pointer to flat panel table invalid\n"); | |
3961 | #endif | |
04a39c57 | 3962 | bios->digital_min_front_porch = 0x4b; |
6ee73861 BS |
3963 | return 0; |
3964 | } | |
3965 | ||
3966 | fptable = &bios->data[bios->fp.fptablepointer]; | |
3967 | fptable_ver = fptable[0]; | |
3968 | ||
3969 | switch (fptable_ver) { | |
3970 | /* | |
3971 | * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no | |
3972 | * version field, and miss one of the spread spectrum/PWM bytes. | |
3973 | * This could affect early GF2Go parts (not seen any appropriate ROMs | |
3974 | * though). Here we assume that a version of 0x05 matches this case | |
3975 | * (combining with a BMP version check would be better), as the | |
3976 | * common case for the panel type field is 0x0005, and that is in | |
3977 | * fact what we are reading the first byte of. | |
3978 | */ | |
3979 | case 0x05: /* some NV10, 11, 15, 16 */ | |
3980 | recordlen = 42; | |
3981 | ofs = -1; | |
3982 | break; | |
3983 | case 0x10: /* some NV15/16, and NV11+ */ | |
3984 | recordlen = 44; | |
3985 | ofs = 0; | |
3986 | break; | |
3987 | case 0x20: /* NV40+ */ | |
3988 | headerlen = fptable[1]; | |
3989 | recordlen = fptable[2]; | |
3990 | fpentries = fptable[3]; | |
3991 | /* | |
3992 | * fptable[4] is the minimum | |
3993 | * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap | |
3994 | */ | |
04a39c57 | 3995 | bios->digital_min_front_porch = fptable[4]; |
6ee73861 BS |
3996 | ofs = -7; |
3997 | break; | |
3998 | default: | |
3999 | NV_ERROR(dev, | |
4000 | "FP table revision %d.%d not currently supported\n", | |
4001 | fptable_ver >> 4, fptable_ver & 0xf); | |
4002 | return -ENOSYS; | |
4003 | } | |
4004 | ||
4005 | if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ | |
4006 | return 0; | |
4007 | ||
4008 | ret = parse_lvds_manufacturer_table_header(dev, bios, <h); | |
4009 | if (ret) | |
4010 | return ret; | |
4011 | ||
4012 | if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { | |
4013 | bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + | |
4014 | lth.headerlen + 1; | |
4015 | bios->fp.xlatwidth = lth.recordlen; | |
4016 | } | |
4017 | if (bios->fp.fpxlatetableptr == 0x0) { | |
4018 | NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); | |
4019 | return -EINVAL; | |
4020 | } | |
4021 | ||
4022 | fpstrapping = get_fp_strap(dev, bios); | |
4023 | ||
4024 | fpindex = bios->data[bios->fp.fpxlatetableptr + | |
4025 | fpstrapping * bios->fp.xlatwidth]; | |
4026 | ||
4027 | if (fpindex > fpentries) { | |
4028 | NV_ERROR(dev, "Bad flat panel table index\n"); | |
4029 | return -ENOENT; | |
4030 | } | |
4031 | ||
4032 | /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ | |
4033 | if (lth.lvds_ver > 0x10) | |
04a39c57 | 4034 | bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; |
6ee73861 BS |
4035 | |
4036 | /* | |
4037 | * If either the strap or xlated fpindex value are 0xf there is no | |
4038 | * panel using a strap-derived bios mode present. this condition | |
4039 | * includes, but is different from, the DDC panel indicator above | |
4040 | */ | |
4041 | if (fpstrapping == 0xf || fpindex == 0xf) | |
4042 | return 0; | |
4043 | ||
4044 | bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + | |
4045 | recordlen * fpindex + ofs; | |
4046 | ||
4047 | NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", | |
4048 | ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, | |
4049 | ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, | |
4050 | ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); | |
4051 | ||
4052 | return 0; | |
4053 | } | |
4054 | ||
4055 | bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) | |
4056 | { | |
4057 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 4058 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
4059 | uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; |
4060 | ||
4061 | if (!mode) /* just checking whether we can produce a mode */ | |
4062 | return bios->fp.mode_ptr; | |
4063 | ||
4064 | memset(mode, 0, sizeof(struct drm_display_mode)); | |
4065 | /* | |
4066 | * For version 1.0 (version in byte 0): | |
4067 | * bytes 1-2 are "panel type", including bits on whether Colour/mono, | |
4068 | * single/dual link, and type (TFT etc.) | |
4069 | * bytes 3-6 are bits per colour in RGBX | |
4070 | */ | |
4071 | mode->clock = ROM16(mode_entry[7]) * 10; | |
4072 | /* bytes 9-10 is HActive */ | |
4073 | mode->hdisplay = ROM16(mode_entry[11]) + 1; | |
4074 | /* | |
4075 | * bytes 13-14 is HValid Start | |
4076 | * bytes 15-16 is HValid End | |
4077 | */ | |
4078 | mode->hsync_start = ROM16(mode_entry[17]) + 1; | |
4079 | mode->hsync_end = ROM16(mode_entry[19]) + 1; | |
4080 | mode->htotal = ROM16(mode_entry[21]) + 1; | |
4081 | /* bytes 23-24, 27-30 similarly, but vertical */ | |
4082 | mode->vdisplay = ROM16(mode_entry[25]) + 1; | |
4083 | mode->vsync_start = ROM16(mode_entry[31]) + 1; | |
4084 | mode->vsync_end = ROM16(mode_entry[33]) + 1; | |
4085 | mode->vtotal = ROM16(mode_entry[35]) + 1; | |
4086 | mode->flags |= (mode_entry[37] & 0x10) ? | |
4087 | DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; | |
4088 | mode->flags |= (mode_entry[37] & 0x1) ? | |
4089 | DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; | |
4090 | /* | |
4091 | * bytes 38-39 relate to spread spectrum settings | |
4092 | * bytes 40-43 are something to do with PWM | |
4093 | */ | |
4094 | ||
4095 | mode->status = MODE_OK; | |
4096 | mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | |
4097 | drm_mode_set_name(mode); | |
4098 | return bios->fp.mode_ptr; | |
4099 | } | |
4100 | ||
4101 | int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) | |
4102 | { | |
4103 | /* | |
4104 | * The LVDS table header is (mostly) described in | |
4105 | * parse_lvds_manufacturer_table_header(): the BIT header additionally | |
4106 | * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if | |
4107 | * straps are not being used for the panel, this specifies the frequency | |
4108 | * at which modes should be set up in the dual link style. | |
4109 | * | |
4110 | * Following the header, the BMP (ver 0xa) table has several records, | |
3ad2f3fb | 4111 | * indexed by a separate xlat table, indexed in turn by the fp strap in |
6ee73861 BS |
4112 | * EXTDEV_BOOT. Each record had a config byte, followed by 6 script |
4113 | * numbers for use by INIT_SUB which controlled panel init and power, | |
4114 | * and finally a dword of ms to sleep between power off and on | |
4115 | * operations. | |
4116 | * | |
4117 | * In the BIT versions, the table following the header serves as an | |
4118 | * integrated config and xlat table: the records in the table are | |
4119 | * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has | |
4120 | * two bytes - the first as a config byte, the second for indexing the | |
4121 | * fp mode table pointed to by the BIT 'D' table | |
4122 | * | |
4123 | * DDC is not used until after card init, so selecting the correct table | |
4124 | * entry and setting the dual link flag for EDID equipped panels, | |
4125 | * requiring tests against the native-mode pixel clock, cannot be done | |
4126 | * until later, when this function should be called with non-zero pxclk | |
4127 | */ | |
4128 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 4129 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
4130 | int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; |
4131 | struct lvdstableheader lth; | |
4132 | uint16_t lvdsofs; | |
04a39c57 | 4133 | int ret, chip_version = bios->chip_version; |
6ee73861 BS |
4134 | |
4135 | ret = parse_lvds_manufacturer_table_header(dev, bios, <h); | |
4136 | if (ret) | |
4137 | return ret; | |
4138 | ||
4139 | switch (lth.lvds_ver) { | |
4140 | case 0x0a: /* pre NV40 */ | |
4141 | lvdsmanufacturerindex = bios->data[ | |
4142 | bios->fp.fpxlatemanufacturertableptr + | |
4143 | fpstrapping]; | |
4144 | ||
4145 | /* we're done if this isn't the EDID panel case */ | |
4146 | if (!pxclk) | |
4147 | break; | |
4148 | ||
4149 | if (chip_version < 0x25) { | |
4150 | /* nv17 behaviour | |
4151 | * | |
4152 | * It seems the old style lvds script pointer is reused | |
4153 | * to select 18/24 bit colour depth for EDID panels. | |
4154 | */ | |
4155 | lvdsmanufacturerindex = | |
4156 | (bios->legacy.lvds_single_a_script_ptr & 1) ? | |
4157 | 2 : 0; | |
4158 | if (pxclk >= bios->fp.duallink_transition_clk) | |
4159 | lvdsmanufacturerindex++; | |
4160 | } else if (chip_version < 0x30) { | |
4161 | /* nv28 behaviour (off-chip encoder) | |
4162 | * | |
4163 | * nv28 does a complex dance of first using byte 121 of | |
4164 | * the EDID to choose the lvdsmanufacturerindex, then | |
4165 | * later attempting to match the EDID manufacturer and | |
4166 | * product IDs in a table (signature 'pidt' (panel id | |
4167 | * table?)), setting an lvdsmanufacturerindex of 0 and | |
4168 | * an fp strap of the match index (or 0xf if none) | |
4169 | */ | |
4170 | lvdsmanufacturerindex = 0; | |
4171 | } else { | |
4172 | /* nv31, nv34 behaviour */ | |
4173 | lvdsmanufacturerindex = 0; | |
4174 | if (pxclk >= bios->fp.duallink_transition_clk) | |
4175 | lvdsmanufacturerindex = 2; | |
4176 | if (pxclk >= 140000) | |
4177 | lvdsmanufacturerindex = 3; | |
4178 | } | |
4179 | ||
4180 | /* | |
4181 | * nvidia set the high nibble of (cr57=f, cr58) to | |
4182 | * lvdsmanufacturerindex in this case; we don't | |
4183 | */ | |
4184 | break; | |
4185 | case 0x30: /* NV4x */ | |
4186 | case 0x40: /* G80/G90 */ | |
4187 | lvdsmanufacturerindex = fpstrapping; | |
4188 | break; | |
4189 | default: | |
4190 | NV_ERROR(dev, "LVDS table revision not currently supported\n"); | |
4191 | return -ENOSYS; | |
4192 | } | |
4193 | ||
4194 | lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; | |
4195 | switch (lth.lvds_ver) { | |
4196 | case 0x0a: | |
4197 | bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; | |
4198 | bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; | |
4199 | bios->fp.dual_link = bios->data[lvdsofs] & 4; | |
4200 | bios->fp.link_c_increment = bios->data[lvdsofs] & 8; | |
4201 | *if_is_24bit = bios->data[lvdsofs] & 16; | |
4202 | break; | |
4203 | case 0x30: | |
f3bbb9cc | 4204 | case 0x40: |
6ee73861 BS |
4205 | /* |
4206 | * No sign of the "power off for reset" or "reset for panel | |
4207 | * on" bits, but it's safer to assume we should | |
4208 | */ | |
4209 | bios->fp.power_off_for_reset = true; | |
4210 | bios->fp.reset_after_pclk_change = true; | |
f3bbb9cc | 4211 | |
6ee73861 BS |
4212 | /* |
4213 | * It's ok lvdsofs is wrong for nv4x edid case; dual_link is | |
f3bbb9cc | 4214 | * over-written, and if_is_24bit isn't used |
6ee73861 BS |
4215 | */ |
4216 | bios->fp.dual_link = bios->data[lvdsofs] & 1; | |
6ee73861 BS |
4217 | bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; |
4218 | bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; | |
4219 | bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; | |
4220 | break; | |
4221 | } | |
4222 | ||
2eb92c80 BS |
4223 | /* Dell Latitude D620 reports a too-high value for the dual-link |
4224 | * transition freq, causing us to program the panel incorrectly. | |
4225 | * | |
4226 | * It doesn't appear the VBIOS actually uses its transition freq | |
4227 | * (90000kHz), instead it uses the "Number of LVDS channels" field | |
4228 | * out of the panel ID structure (http://www.spwg.org/). | |
4229 | * | |
4230 | * For the moment, a quirk will do :) | |
4231 | */ | |
4232 | if ((dev->pdev->device == 0x01d7) && | |
4233 | (dev->pdev->subsystem_vendor == 0x1028) && | |
4234 | (dev->pdev->subsystem_device == 0x01c2)) { | |
4235 | bios->fp.duallink_transition_clk = 80000; | |
4236 | } | |
4237 | ||
6ee73861 BS |
4238 | /* set dual_link flag for EDID case */ |
4239 | if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) | |
4240 | bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); | |
4241 | ||
4242 | *dl = bios->fp.dual_link; | |
4243 | ||
4244 | return 0; | |
4245 | } | |
4246 | ||
4247 | static uint8_t * | |
4248 | bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, | |
1eb38100 BS |
4249 | uint16_t record, int record_len, int record_nr, |
4250 | bool match_link) | |
6ee73861 BS |
4251 | { |
4252 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 4253 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
4254 | uint32_t entry; |
4255 | uint16_t table; | |
4256 | int i, v; | |
4257 | ||
1eb38100 BS |
4258 | switch (dcbent->type) { |
4259 | case OUTPUT_TMDS: | |
4260 | case OUTPUT_LVDS: | |
4261 | case OUTPUT_DP: | |
4262 | break; | |
4263 | default: | |
4264 | match_link = false; | |
4265 | break; | |
4266 | } | |
4267 | ||
6ee73861 BS |
4268 | for (i = 0; i < record_nr; i++, record += record_len) { |
4269 | table = ROM16(bios->data[record]); | |
4270 | if (!table) | |
4271 | continue; | |
4272 | entry = ROM32(bios->data[table]); | |
4273 | ||
1eb38100 BS |
4274 | if (match_link) { |
4275 | v = (entry & 0x00c00000) >> 22; | |
4276 | if (!(v & dcbent->sorconf.link)) | |
4277 | continue; | |
4278 | } | |
4279 | ||
6ee73861 BS |
4280 | v = (entry & 0x000f0000) >> 16; |
4281 | if (!(v & dcbent->or)) | |
4282 | continue; | |
4283 | ||
4284 | v = (entry & 0x000000f0) >> 4; | |
4285 | if (v != dcbent->location) | |
4286 | continue; | |
4287 | ||
4288 | v = (entry & 0x0000000f); | |
4289 | if (v != dcbent->type) | |
4290 | continue; | |
4291 | ||
4292 | return &bios->data[table]; | |
4293 | } | |
4294 | ||
4295 | return NULL; | |
4296 | } | |
4297 | ||
4298 | void * | |
4299 | nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, | |
4300 | int *length) | |
4301 | { | |
4302 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 4303 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
4304 | uint8_t *table; |
4305 | ||
4306 | if (!bios->display.dp_table_ptr) { | |
4307 | NV_ERROR(dev, "No pointer to DisplayPort table\n"); | |
4308 | return NULL; | |
4309 | } | |
4310 | table = &bios->data[bios->display.dp_table_ptr]; | |
4311 | ||
c52e53fd | 4312 | if (table[0] != 0x20 && table[0] != 0x21) { |
6ee73861 BS |
4313 | NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", |
4314 | table[0]); | |
4315 | return NULL; | |
4316 | } | |
4317 | ||
4318 | *length = table[4]; | |
4319 | return bios_output_config_match(dev, dcbent, | |
4320 | bios->display.dp_table_ptr + table[1], | |
1eb38100 | 4321 | table[2], table[3], table[0] >= 0x21); |
6ee73861 BS |
4322 | } |
4323 | ||
4324 | int | |
4325 | nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, | |
4326 | uint32_t sub, int pxclk) | |
4327 | { | |
4328 | /* | |
4329 | * The display script table is located by the BIT 'U' table. | |
4330 | * | |
4331 | * It contains an array of pointers to various tables describing | |
4332 | * a particular output type. The first 32-bits of the output | |
4333 | * tables contains similar information to a DCB entry, and is | |
4334 | * used to decide whether that particular table is suitable for | |
4335 | * the output you want to access. | |
4336 | * | |
4337 | * The "record header length" field here seems to indicate the | |
4338 | * offset of the first configuration entry in the output tables. | |
4339 | * This is 10 on most cards I've seen, but 12 has been witnessed | |
4340 | * on DP cards, and there's another script pointer within the | |
4341 | * header. | |
4342 | * | |
4343 | * offset + 0 ( 8 bits): version | |
4344 | * offset + 1 ( 8 bits): header length | |
4345 | * offset + 2 ( 8 bits): record length | |
4346 | * offset + 3 ( 8 bits): number of records | |
4347 | * offset + 4 ( 8 bits): record header length | |
4348 | * offset + 5 (16 bits): pointer to first output script table | |
4349 | */ | |
4350 | ||
4351 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 4352 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
4353 | uint8_t *table = &bios->data[bios->display.script_table_ptr]; |
4354 | uint8_t *otable = NULL; | |
4355 | uint16_t script; | |
4356 | int i = 0; | |
4357 | ||
4358 | if (!bios->display.script_table_ptr) { | |
4359 | NV_ERROR(dev, "No pointer to output script table\n"); | |
4360 | return 1; | |
4361 | } | |
4362 | ||
4363 | /* | |
4364 | * Nothing useful has been in any of the pre-2.0 tables I've seen, | |
4365 | * so until they are, we really don't need to care. | |
4366 | */ | |
4367 | if (table[0] < 0x20) | |
4368 | return 1; | |
4369 | ||
4370 | if (table[0] != 0x20 && table[0] != 0x21) { | |
4371 | NV_ERROR(dev, "Output script table version 0x%02x unknown\n", | |
4372 | table[0]); | |
4373 | return 1; | |
4374 | } | |
4375 | ||
4376 | /* | |
4377 | * The output script tables describing a particular output type | |
4378 | * look as follows: | |
4379 | * | |
4380 | * offset + 0 (32 bits): output this table matches (hash of DCB) | |
4381 | * offset + 4 ( 8 bits): unknown | |
4382 | * offset + 5 ( 8 bits): number of configurations | |
4383 | * offset + 6 (16 bits): pointer to some script | |
4384 | * offset + 8 (16 bits): pointer to some script | |
4385 | * | |
4386 | * headerlen == 10 | |
4387 | * offset + 10 : configuration 0 | |
4388 | * | |
4389 | * headerlen == 12 | |
4390 | * offset + 10 : pointer to some script | |
4391 | * offset + 12 : configuration 0 | |
4392 | * | |
4393 | * Each config entry is as follows: | |
4394 | * | |
4395 | * offset + 0 (16 bits): unknown, assumed to be a match value | |
4396 | * offset + 2 (16 bits): pointer to script table (clock set?) | |
4397 | * offset + 4 (16 bits): pointer to script table (reset?) | |
4398 | * | |
4399 | * There doesn't appear to be a count value to say how many | |
4400 | * entries exist in each script table, instead, a 0 value in | |
4401 | * the first 16-bit word seems to indicate both the end of the | |
4402 | * list and the default entry. The second 16-bit word in the | |
4403 | * script tables is a pointer to the script to execute. | |
4404 | */ | |
4405 | ||
ef2bb506 | 4406 | NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", |
6ee73861 BS |
4407 | dcbent->type, dcbent->location, dcbent->or); |
4408 | otable = bios_output_config_match(dev, dcbent, table[1] + | |
4409 | bios->display.script_table_ptr, | |
1eb38100 | 4410 | table[2], table[3], table[0] >= 0x21); |
6ee73861 BS |
4411 | if (!otable) { |
4412 | NV_ERROR(dev, "Couldn't find matching output script table\n"); | |
4413 | return 1; | |
4414 | } | |
4415 | ||
4416 | if (pxclk < -2 || pxclk > 0) { | |
4417 | /* Try to find matching script table entry */ | |
4418 | for (i = 0; i < otable[5]; i++) { | |
4419 | if (ROM16(otable[table[4] + i*6]) == sub) | |
4420 | break; | |
4421 | } | |
4422 | ||
4423 | if (i == otable[5]) { | |
4424 | NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " | |
4425 | "using first\n", | |
4426 | sub, dcbent->type, dcbent->or); | |
4427 | i = 0; | |
4428 | } | |
4429 | } | |
4430 | ||
6ee73861 BS |
4431 | if (pxclk == 0) { |
4432 | script = ROM16(otable[6]); | |
4433 | if (!script) { | |
ef2bb506 | 4434 | NV_DEBUG_KMS(dev, "output script 0 not found\n"); |
6ee73861 BS |
4435 | return 1; |
4436 | } | |
4437 | ||
4438 | NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); | |
39c9bfb4 | 4439 | nouveau_bios_run_init_table(dev, script, dcbent); |
6ee73861 BS |
4440 | } else |
4441 | if (pxclk == -1) { | |
4442 | script = ROM16(otable[8]); | |
4443 | if (!script) { | |
ef2bb506 | 4444 | NV_DEBUG_KMS(dev, "output script 1 not found\n"); |
6ee73861 BS |
4445 | return 1; |
4446 | } | |
4447 | ||
4448 | NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); | |
39c9bfb4 | 4449 | nouveau_bios_run_init_table(dev, script, dcbent); |
6ee73861 BS |
4450 | } else |
4451 | if (pxclk == -2) { | |
4452 | if (table[4] >= 12) | |
4453 | script = ROM16(otable[10]); | |
4454 | else | |
4455 | script = 0; | |
4456 | if (!script) { | |
ef2bb506 | 4457 | NV_DEBUG_KMS(dev, "output script 2 not found\n"); |
6ee73861 BS |
4458 | return 1; |
4459 | } | |
4460 | ||
4461 | NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); | |
39c9bfb4 | 4462 | nouveau_bios_run_init_table(dev, script, dcbent); |
6ee73861 BS |
4463 | } else |
4464 | if (pxclk > 0) { | |
4465 | script = ROM16(otable[table[4] + i*6 + 2]); | |
4466 | if (script) | |
4467 | script = clkcmptable(bios, script, pxclk); | |
4468 | if (!script) { | |
4469 | NV_ERROR(dev, "clock script 0 not found\n"); | |
4470 | return 1; | |
4471 | } | |
4472 | ||
4473 | NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); | |
39c9bfb4 | 4474 | nouveau_bios_run_init_table(dev, script, dcbent); |
6ee73861 BS |
4475 | } else |
4476 | if (pxclk < 0) { | |
4477 | script = ROM16(otable[table[4] + i*6 + 4]); | |
4478 | if (script) | |
4479 | script = clkcmptable(bios, script, -pxclk); | |
4480 | if (!script) { | |
ef2bb506 | 4481 | NV_DEBUG_KMS(dev, "clock script 1 not found\n"); |
6ee73861 BS |
4482 | return 1; |
4483 | } | |
4484 | ||
4485 | NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); | |
39c9bfb4 | 4486 | nouveau_bios_run_init_table(dev, script, dcbent); |
6ee73861 BS |
4487 | } |
4488 | ||
4489 | return 0; | |
4490 | } | |
4491 | ||
4492 | ||
4493 | int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) | |
4494 | { | |
4495 | /* | |
4496 | * the pxclk parameter is in kHz | |
4497 | * | |
4498 | * This runs the TMDS regs setting code found on BIT bios cards | |
4499 | * | |
4500 | * For ffs(or) == 1 use the first table, for ffs(or) == 2 and | |
4501 | * ffs(or) == 3, use the second. | |
4502 | */ | |
4503 | ||
4504 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 BS |
4505 | struct nvbios *bios = &dev_priv->vbios; |
4506 | int cv = bios->chip_version; | |
6ee73861 BS |
4507 | uint16_t clktable = 0, scriptptr; |
4508 | uint32_t sel_clk_binding, sel_clk; | |
4509 | ||
4510 | /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ | |
4511 | if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && | |
4512 | dcbent->location != DCB_LOC_ON_CHIP) | |
4513 | return 0; | |
4514 | ||
4515 | switch (ffs(dcbent->or)) { | |
4516 | case 1: | |
4517 | clktable = bios->tmds.output0_script_ptr; | |
4518 | break; | |
4519 | case 2: | |
4520 | case 3: | |
4521 | clktable = bios->tmds.output1_script_ptr; | |
4522 | break; | |
4523 | } | |
4524 | ||
4525 | if (!clktable) { | |
4526 | NV_ERROR(dev, "Pixel clock comparison table not found\n"); | |
4527 | return -EINVAL; | |
4528 | } | |
4529 | ||
4530 | scriptptr = clkcmptable(bios, clktable, pxclk); | |
4531 | ||
4532 | if (!scriptptr) { | |
4533 | NV_ERROR(dev, "TMDS output init script not found\n"); | |
4534 | return -ENOENT; | |
4535 | } | |
4536 | ||
4537 | /* don't let script change pll->head binding */ | |
4538 | sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; | |
4539 | run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); | |
4540 | sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; | |
4541 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); | |
4542 | ||
4543 | return 0; | |
4544 | } | |
4545 | ||
4546 | int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) | |
4547 | { | |
4548 | /* | |
4549 | * PLL limits table | |
4550 | * | |
4551 | * Version 0x10: NV30, NV31 | |
4552 | * One byte header (version), one record of 24 bytes | |
4553 | * Version 0x11: NV36 - Not implemented | |
4554 | * Seems to have same record style as 0x10, but 3 records rather than 1 | |
4555 | * Version 0x20: Found on Geforce 6 cards | |
4556 | * Trivial 4 byte BIT header. 31 (0x1f) byte record length | |
4557 | * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards | |
4558 | * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record | |
4559 | * length in general, some (integrated) have an extra configuration byte | |
4560 | * Version 0x30: Found on Geforce 8, separates the register mapping | |
4561 | * from the limits tables. | |
4562 | */ | |
4563 | ||
4564 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 BS |
4565 | struct nvbios *bios = &dev_priv->vbios; |
4566 | int cv = bios->chip_version, pllindex = 0; | |
6ee73861 BS |
4567 | uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; |
4568 | uint32_t crystal_strap_mask, crystal_straps; | |
4569 | ||
4570 | if (!bios->pll_limit_tbl_ptr) { | |
4571 | if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || | |
4572 | cv >= 0x40) { | |
4573 | NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); | |
4574 | return -EINVAL; | |
4575 | } | |
4576 | } else | |
4577 | pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; | |
4578 | ||
4579 | crystal_strap_mask = 1 << 6; | |
4580 | /* open coded dev->twoHeads test */ | |
4581 | if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) | |
4582 | crystal_strap_mask |= 1 << 22; | |
4583 | crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & | |
4584 | crystal_strap_mask; | |
4585 | ||
4586 | switch (pll_lim_ver) { | |
4587 | /* | |
4588 | * We use version 0 to indicate a pre limit table bios (single stage | |
4589 | * pll) and load the hard coded limits instead. | |
4590 | */ | |
4591 | case 0: | |
4592 | break; | |
4593 | case 0x10: | |
4594 | case 0x11: | |
4595 | /* | |
4596 | * Strictly v0x11 has 3 entries, but the last two don't seem | |
4597 | * to get used. | |
4598 | */ | |
4599 | headerlen = 1; | |
4600 | recordlen = 0x18; | |
4601 | entries = 1; | |
4602 | pllindex = 0; | |
4603 | break; | |
4604 | case 0x20: | |
4605 | case 0x21: | |
4606 | case 0x30: | |
4607 | case 0x40: | |
4608 | headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; | |
4609 | recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; | |
4610 | entries = bios->data[bios->pll_limit_tbl_ptr + 3]; | |
4611 | break; | |
4612 | default: | |
4613 | NV_ERROR(dev, "PLL limits table revision 0x%X not currently " | |
4614 | "supported\n", pll_lim_ver); | |
4615 | return -ENOSYS; | |
4616 | } | |
4617 | ||
4618 | /* initialize all members to zero */ | |
4619 | memset(pll_lim, 0, sizeof(struct pll_lims)); | |
4620 | ||
4621 | if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { | |
4622 | uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; | |
4623 | ||
4624 | pll_lim->vco1.minfreq = ROM32(pll_rec[0]); | |
4625 | pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); | |
4626 | pll_lim->vco2.minfreq = ROM32(pll_rec[8]); | |
4627 | pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); | |
4628 | pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); | |
4629 | pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); | |
4630 | pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; | |
4631 | ||
4632 | /* these values taken from nv30/31/36 */ | |
4633 | pll_lim->vco1.min_n = 0x1; | |
4634 | if (cv == 0x36) | |
4635 | pll_lim->vco1.min_n = 0x5; | |
4636 | pll_lim->vco1.max_n = 0xff; | |
4637 | pll_lim->vco1.min_m = 0x1; | |
4638 | pll_lim->vco1.max_m = 0xd; | |
4639 | pll_lim->vco2.min_n = 0x4; | |
4640 | /* | |
4641 | * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this | |
4642 | * table version (apart from nv35)), N2 is compared to | |
4643 | * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and | |
4644 | * save a comparison | |
4645 | */ | |
4646 | pll_lim->vco2.max_n = 0x28; | |
4647 | if (cv == 0x30 || cv == 0x35) | |
4648 | /* only 5 bits available for N2 on nv30/35 */ | |
4649 | pll_lim->vco2.max_n = 0x1f; | |
4650 | pll_lim->vco2.min_m = 0x1; | |
4651 | pll_lim->vco2.max_m = 0x4; | |
4652 | pll_lim->max_log2p = 0x7; | |
4653 | pll_lim->max_usable_log2p = 0x6; | |
4654 | } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { | |
4655 | uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; | |
4656 | uint32_t reg = 0; /* default match */ | |
4657 | uint8_t *pll_rec; | |
4658 | int i; | |
4659 | ||
4660 | /* | |
4661 | * First entry is default match, if nothing better. warn if | |
4662 | * reg field nonzero | |
4663 | */ | |
4664 | if (ROM32(bios->data[plloffs])) | |
4665 | NV_WARN(dev, "Default PLL limit entry has non-zero " | |
4666 | "register field\n"); | |
4667 | ||
4668 | if (limit_match > MAX_PLL_TYPES) | |
4669 | /* we've been passed a reg as the match */ | |
4670 | reg = limit_match; | |
4671 | else /* limit match is a pll type */ | |
4672 | for (i = 1; i < entries && !reg; i++) { | |
4673 | uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]); | |
4674 | ||
4675 | if (limit_match == NVPLL && | |
4676 | (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000)) | |
4677 | reg = cmpreg; | |
4678 | if (limit_match == MPLL && | |
4679 | (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020)) | |
4680 | reg = cmpreg; | |
4681 | if (limit_match == VPLL1 && | |
4682 | (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010)) | |
4683 | reg = cmpreg; | |
4684 | if (limit_match == VPLL2 && | |
4685 | (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018)) | |
4686 | reg = cmpreg; | |
4687 | } | |
4688 | ||
4689 | for (i = 1; i < entries; i++) | |
4690 | if (ROM32(bios->data[plloffs + recordlen * i]) == reg) { | |
4691 | pllindex = i; | |
4692 | break; | |
4693 | } | |
4694 | ||
4695 | pll_rec = &bios->data[plloffs + recordlen * pllindex]; | |
4696 | ||
4697 | BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", | |
4698 | pllindex ? reg : 0); | |
4699 | ||
4700 | /* | |
4701 | * Frequencies are stored in tables in MHz, kHz are more | |
4702 | * useful, so we convert. | |
4703 | */ | |
4704 | ||
4705 | /* What output frequencies can each VCO generate? */ | |
4706 | pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; | |
4707 | pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; | |
4708 | pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; | |
4709 | pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; | |
4710 | ||
4711 | /* What input frequencies they accept (past the m-divider)? */ | |
4712 | pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; | |
4713 | pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; | |
4714 | pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; | |
4715 | pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; | |
4716 | ||
4717 | /* What values are accepted as multiplier and divider? */ | |
4718 | pll_lim->vco1.min_n = pll_rec[20]; | |
4719 | pll_lim->vco1.max_n = pll_rec[21]; | |
4720 | pll_lim->vco1.min_m = pll_rec[22]; | |
4721 | pll_lim->vco1.max_m = pll_rec[23]; | |
4722 | pll_lim->vco2.min_n = pll_rec[24]; | |
4723 | pll_lim->vco2.max_n = pll_rec[25]; | |
4724 | pll_lim->vco2.min_m = pll_rec[26]; | |
4725 | pll_lim->vco2.max_m = pll_rec[27]; | |
4726 | ||
4727 | pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; | |
4728 | if (pll_lim->max_log2p > 0x7) | |
4729 | /* pll decoding in nv_hw.c assumes never > 7 */ | |
4730 | NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", | |
4731 | pll_lim->max_log2p); | |
4732 | if (cv < 0x60) | |
4733 | pll_lim->max_usable_log2p = 0x6; | |
4734 | pll_lim->log2p_bias = pll_rec[30]; | |
4735 | ||
4736 | if (recordlen > 0x22) | |
4737 | pll_lim->refclk = ROM32(pll_rec[31]); | |
4738 | ||
4739 | if (recordlen > 0x23 && pll_rec[35]) | |
4740 | NV_WARN(dev, | |
4741 | "Bits set in PLL configuration byte (%x)\n", | |
4742 | pll_rec[35]); | |
4743 | ||
4744 | /* C51 special not seen elsewhere */ | |
4745 | if (cv == 0x51 && !pll_lim->refclk) { | |
4746 | uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); | |
4747 | ||
4748 | if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) || | |
4749 | ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { | |
4750 | if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) | |
4751 | pll_lim->refclk = 200000; | |
4752 | else | |
4753 | pll_lim->refclk = 25000; | |
4754 | } | |
4755 | } | |
4756 | } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ | |
4757 | uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; | |
4758 | uint8_t *record = NULL; | |
4759 | int i; | |
4760 | ||
4761 | BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", | |
4762 | limit_match); | |
4763 | ||
4764 | for (i = 0; i < entries; i++, entry += recordlen) { | |
4765 | if (ROM32(entry[3]) == limit_match) { | |
4766 | record = &bios->data[ROM16(entry[1])]; | |
4767 | break; | |
4768 | } | |
4769 | } | |
4770 | ||
4771 | if (!record) { | |
4772 | NV_ERROR(dev, "Register 0x%08x not found in PLL " | |
4773 | "limits table", limit_match); | |
4774 | return -ENOENT; | |
4775 | } | |
4776 | ||
4777 | pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; | |
4778 | pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; | |
4779 | pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; | |
4780 | pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; | |
4781 | pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; | |
4782 | pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; | |
4783 | pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; | |
4784 | pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; | |
4785 | pll_lim->vco1.min_n = record[16]; | |
4786 | pll_lim->vco1.max_n = record[17]; | |
4787 | pll_lim->vco1.min_m = record[18]; | |
4788 | pll_lim->vco1.max_m = record[19]; | |
4789 | pll_lim->vco2.min_n = record[20]; | |
4790 | pll_lim->vco2.max_n = record[21]; | |
4791 | pll_lim->vco2.min_m = record[22]; | |
4792 | pll_lim->vco2.max_m = record[23]; | |
4793 | pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; | |
4794 | pll_lim->log2p_bias = record[27]; | |
4795 | pll_lim->refclk = ROM32(record[28]); | |
4796 | } else if (pll_lim_ver) { /* ver 0x40 */ | |
4797 | uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; | |
4798 | uint8_t *record = NULL; | |
4799 | int i; | |
4800 | ||
4801 | BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", | |
4802 | limit_match); | |
4803 | ||
4804 | for (i = 0; i < entries; i++, entry += recordlen) { | |
4805 | if (ROM32(entry[3]) == limit_match) { | |
4806 | record = &bios->data[ROM16(entry[1])]; | |
4807 | break; | |
4808 | } | |
4809 | } | |
4810 | ||
4811 | if (!record) { | |
4812 | NV_ERROR(dev, "Register 0x%08x not found in PLL " | |
4813 | "limits table", limit_match); | |
4814 | return -ENOENT; | |
4815 | } | |
4816 | ||
4817 | pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; | |
4818 | pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; | |
4819 | pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; | |
4820 | pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; | |
4821 | pll_lim->vco1.min_m = record[8]; | |
4822 | pll_lim->vco1.max_m = record[9]; | |
4823 | pll_lim->vco1.min_n = record[10]; | |
4824 | pll_lim->vco1.max_n = record[11]; | |
4825 | pll_lim->min_p = record[12]; | |
4826 | pll_lim->max_p = record[13]; | |
4827 | /* where did this go to?? */ | |
4828 | if (limit_match == 0x00614100 || limit_match == 0x00614900) | |
4829 | pll_lim->refclk = 27000; | |
4830 | else | |
4831 | pll_lim->refclk = 100000; | |
4832 | } | |
4833 | ||
4834 | /* | |
4835 | * By now any valid limit table ought to have set a max frequency for | |
4836 | * vco1, so if it's zero it's either a pre limit table bios, or one | |
4837 | * with an empty limit table (seen on nv18) | |
4838 | */ | |
4839 | if (!pll_lim->vco1.maxfreq) { | |
4840 | pll_lim->vco1.minfreq = bios->fminvco; | |
4841 | pll_lim->vco1.maxfreq = bios->fmaxvco; | |
4842 | pll_lim->vco1.min_inputfreq = 0; | |
4843 | pll_lim->vco1.max_inputfreq = INT_MAX; | |
4844 | pll_lim->vco1.min_n = 0x1; | |
4845 | pll_lim->vco1.max_n = 0xff; | |
4846 | pll_lim->vco1.min_m = 0x1; | |
4847 | if (crystal_straps == 0) { | |
4848 | /* nv05 does this, nv11 doesn't, nv10 unknown */ | |
4849 | if (cv < 0x11) | |
4850 | pll_lim->vco1.min_m = 0x7; | |
4851 | pll_lim->vco1.max_m = 0xd; | |
4852 | } else { | |
4853 | if (cv < 0x11) | |
4854 | pll_lim->vco1.min_m = 0x8; | |
4855 | pll_lim->vco1.max_m = 0xe; | |
4856 | } | |
4857 | if (cv < 0x17 || cv == 0x1a || cv == 0x20) | |
4858 | pll_lim->max_log2p = 4; | |
4859 | else | |
4860 | pll_lim->max_log2p = 5; | |
4861 | pll_lim->max_usable_log2p = pll_lim->max_log2p; | |
4862 | } | |
4863 | ||
4864 | if (!pll_lim->refclk) | |
4865 | switch (crystal_straps) { | |
4866 | case 0: | |
4867 | pll_lim->refclk = 13500; | |
4868 | break; | |
4869 | case (1 << 6): | |
4870 | pll_lim->refclk = 14318; | |
4871 | break; | |
4872 | case (1 << 22): | |
4873 | pll_lim->refclk = 27000; | |
4874 | break; | |
4875 | case (1 << 22 | 1 << 6): | |
4876 | pll_lim->refclk = 25000; | |
4877 | break; | |
4878 | } | |
4879 | ||
4c389f00 BS |
4880 | NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); |
4881 | NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); | |
4882 | NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); | |
4883 | NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); | |
4884 | NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); | |
4885 | NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); | |
4886 | NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); | |
4887 | NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); | |
4888 | if (pll_lim->vco2.maxfreq) { | |
4889 | NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); | |
4890 | NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); | |
4891 | NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); | |
4892 | NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); | |
4893 | NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); | |
4894 | NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); | |
4895 | NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); | |
4896 | NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); | |
4897 | } | |
4898 | if (!pll_lim->max_p) { | |
4899 | NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); | |
4900 | NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); | |
4901 | } else { | |
4902 | NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); | |
4903 | NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); | |
4904 | } | |
4905 | NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); | |
6ee73861 BS |
4906 | |
4907 | return 0; | |
4908 | } | |
4909 | ||
4910 | static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) | |
4911 | { | |
4912 | /* | |
4913 | * offset + 0 (8 bits): Micro version | |
4914 | * offset + 1 (8 bits): Minor version | |
4915 | * offset + 2 (8 bits): Chip version | |
4916 | * offset + 3 (8 bits): Major version | |
4917 | */ | |
4918 | ||
4919 | bios->major_version = bios->data[offset + 3]; | |
04a39c57 | 4920 | bios->chip_version = bios->data[offset + 2]; |
6ee73861 BS |
4921 | NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", |
4922 | bios->data[offset + 3], bios->data[offset + 2], | |
4923 | bios->data[offset + 1], bios->data[offset]); | |
4924 | } | |
4925 | ||
4926 | static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) | |
4927 | { | |
4928 | /* | |
4929 | * Parses the init table segment for pointers used in script execution. | |
4930 | * | |
4931 | * offset + 0 (16 bits): init script tables pointer | |
4932 | * offset + 2 (16 bits): macro index table pointer | |
4933 | * offset + 4 (16 bits): macro table pointer | |
4934 | * offset + 6 (16 bits): condition table pointer | |
4935 | * offset + 8 (16 bits): io condition table pointer | |
4936 | * offset + 10 (16 bits): io flag condition table pointer | |
4937 | * offset + 12 (16 bits): init function table pointer | |
4938 | */ | |
4939 | ||
4940 | bios->init_script_tbls_ptr = ROM16(bios->data[offset]); | |
4941 | bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); | |
4942 | bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); | |
4943 | bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); | |
4944 | bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); | |
4945 | bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); | |
4946 | bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); | |
4947 | } | |
4948 | ||
4949 | static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) | |
4950 | { | |
4951 | /* | |
4952 | * Parses the load detect values for g80 cards. | |
4953 | * | |
4954 | * offset + 0 (16 bits): loadval table pointer | |
4955 | */ | |
4956 | ||
4957 | uint16_t load_table_ptr; | |
4958 | uint8_t version, headerlen, entrylen, num_entries; | |
4959 | ||
4960 | if (bitentry->length != 3) { | |
4961 | NV_ERROR(dev, "Do not understand BIT A table\n"); | |
4962 | return -EINVAL; | |
4963 | } | |
4964 | ||
4965 | load_table_ptr = ROM16(bios->data[bitentry->offset]); | |
4966 | ||
4967 | if (load_table_ptr == 0x0) { | |
4968 | NV_ERROR(dev, "Pointer to BIT loadval table invalid\n"); | |
4969 | return -EINVAL; | |
4970 | } | |
4971 | ||
4972 | version = bios->data[load_table_ptr]; | |
4973 | ||
4974 | if (version != 0x10) { | |
4975 | NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", | |
4976 | version >> 4, version & 0xF); | |
4977 | return -ENOSYS; | |
4978 | } | |
4979 | ||
4980 | headerlen = bios->data[load_table_ptr + 1]; | |
4981 | entrylen = bios->data[load_table_ptr + 2]; | |
4982 | num_entries = bios->data[load_table_ptr + 3]; | |
4983 | ||
4984 | if (headerlen != 4 || entrylen != 4 || num_entries != 2) { | |
4985 | NV_ERROR(dev, "Do not understand BIT loadval table\n"); | |
4986 | return -EINVAL; | |
4987 | } | |
4988 | ||
4989 | /* First entry is normal dac, 2nd tv-out perhaps? */ | |
04a39c57 | 4990 | bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; |
6ee73861 BS |
4991 | |
4992 | return 0; | |
4993 | } | |
4994 | ||
4995 | static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) | |
4996 | { | |
4997 | /* | |
4998 | * offset + 8 (16 bits): PLL limits table pointer | |
4999 | * | |
5000 | * There's more in here, but that's unknown. | |
5001 | */ | |
5002 | ||
5003 | if (bitentry->length < 10) { | |
5004 | NV_ERROR(dev, "Do not understand BIT C table\n"); | |
5005 | return -EINVAL; | |
5006 | } | |
5007 | ||
5008 | bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); | |
5009 | ||
5010 | return 0; | |
5011 | } | |
5012 | ||
5013 | static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) | |
5014 | { | |
5015 | /* | |
5016 | * Parses the flat panel table segment that the bit entry points to. | |
5017 | * Starting at bitentry->offset: | |
5018 | * | |
5019 | * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte | |
5020 | * records beginning with a freq. | |
5021 | * offset + 2 (16 bits): mode table pointer | |
5022 | */ | |
5023 | ||
5024 | if (bitentry->length != 4) { | |
5025 | NV_ERROR(dev, "Do not understand BIT display table\n"); | |
5026 | return -EINVAL; | |
5027 | } | |
5028 | ||
5029 | bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); | |
5030 | ||
5031 | return 0; | |
5032 | } | |
5033 | ||
5034 | static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) | |
5035 | { | |
5036 | /* | |
5037 | * Parses the init table segment that the bit entry points to. | |
5038 | * | |
5039 | * See parse_script_table_pointers for layout | |
5040 | */ | |
5041 | ||
5042 | if (bitentry->length < 14) { | |
5043 | NV_ERROR(dev, "Do not understand init table\n"); | |
5044 | return -EINVAL; | |
5045 | } | |
5046 | ||
5047 | parse_script_table_pointers(bios, bitentry->offset); | |
5048 | ||
5049 | if (bitentry->length >= 16) | |
5050 | bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); | |
5051 | if (bitentry->length >= 18) | |
5052 | bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); | |
5053 | ||
5054 | return 0; | |
5055 | } | |
5056 | ||
5057 | static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) | |
5058 | { | |
5059 | /* | |
5060 | * BIT 'i' (info?) table | |
5061 | * | |
5062 | * offset + 0 (32 bits): BIOS version dword (as in B table) | |
5063 | * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) | |
5064 | * offset + 13 (16 bits): pointer to table containing DAC load | |
5065 | * detection comparison values | |
5066 | * | |
5067 | * There's other things in the table, purpose unknown | |
5068 | */ | |
5069 | ||
5070 | uint16_t daccmpoffset; | |
5071 | uint8_t dacver, dacheaderlen; | |
5072 | ||
5073 | if (bitentry->length < 6) { | |
5074 | NV_ERROR(dev, "BIT i table too short for needed information\n"); | |
5075 | return -EINVAL; | |
5076 | } | |
5077 | ||
5078 | parse_bios_version(dev, bios, bitentry->offset); | |
5079 | ||
5080 | /* | |
5081 | * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's | |
5082 | * Quadro identity crisis), other bits possibly as for BMP feature byte | |
5083 | */ | |
5084 | bios->feature_byte = bios->data[bitentry->offset + 5]; | |
5085 | bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; | |
5086 | ||
5087 | if (bitentry->length < 15) { | |
5088 | NV_WARN(dev, "BIT i table not long enough for DAC load " | |
5089 | "detection comparison table\n"); | |
5090 | return -EINVAL; | |
5091 | } | |
5092 | ||
5093 | daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); | |
5094 | ||
5095 | /* doesn't exist on g80 */ | |
5096 | if (!daccmpoffset) | |
5097 | return 0; | |
5098 | ||
5099 | /* | |
5100 | * The first value in the table, following the header, is the | |
5101 | * comparison value, the second entry is a comparison value for | |
5102 | * TV load detection. | |
5103 | */ | |
5104 | ||
5105 | dacver = bios->data[daccmpoffset]; | |
5106 | dacheaderlen = bios->data[daccmpoffset + 1]; | |
5107 | ||
5108 | if (dacver != 0x00 && dacver != 0x10) { | |
5109 | NV_WARN(dev, "DAC load detection comparison table version " | |
5110 | "%d.%d not known\n", dacver >> 4, dacver & 0xf); | |
5111 | return -ENOSYS; | |
5112 | } | |
5113 | ||
04a39c57 BS |
5114 | bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); |
5115 | bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); | |
6ee73861 BS |
5116 | |
5117 | return 0; | |
5118 | } | |
5119 | ||
5120 | static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) | |
5121 | { | |
5122 | /* | |
5123 | * Parses the LVDS table segment that the bit entry points to. | |
5124 | * Starting at bitentry->offset: | |
5125 | * | |
5126 | * offset + 0 (16 bits): LVDS strap xlate table pointer | |
5127 | */ | |
5128 | ||
5129 | if (bitentry->length != 2) { | |
5130 | NV_ERROR(dev, "Do not understand BIT LVDS table\n"); | |
5131 | return -EINVAL; | |
5132 | } | |
5133 | ||
5134 | /* | |
5135 | * No idea if it's still called the LVDS manufacturer table, but | |
5136 | * the concept's close enough. | |
5137 | */ | |
5138 | bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); | |
5139 | ||
5140 | return 0; | |
5141 | } | |
5142 | ||
5143 | static int | |
5144 | parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, | |
5145 | struct bit_entry *bitentry) | |
5146 | { | |
5147 | /* | |
5148 | * offset + 2 (8 bits): number of options in an | |
5149 | * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set | |
5150 | * offset + 3 (16 bits): pointer to strap xlate table for RAM | |
5151 | * restrict option selection | |
5152 | * | |
5153 | * There's a bunch of bits in this table other than the RAM restrict | |
5154 | * stuff that we don't use - their use currently unknown | |
5155 | */ | |
5156 | ||
6ee73861 BS |
5157 | /* |
5158 | * Older bios versions don't have a sufficiently long table for | |
5159 | * what we want | |
5160 | */ | |
5161 | if (bitentry->length < 0x5) | |
5162 | return 0; | |
5163 | ||
5164 | if (bitentry->id[1] < 2) { | |
37383650 MK |
5165 | bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; |
5166 | bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); | |
6ee73861 | 5167 | } else { |
37383650 MK |
5168 | bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; |
5169 | bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); | |
6ee73861 BS |
5170 | } |
5171 | ||
6ee73861 BS |
5172 | return 0; |
5173 | } | |
5174 | ||
5175 | static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) | |
5176 | { | |
5177 | /* | |
5178 | * Parses the pointer to the TMDS table | |
5179 | * | |
5180 | * Starting at bitentry->offset: | |
5181 | * | |
5182 | * offset + 0 (16 bits): TMDS table pointer | |
5183 | * | |
5184 | * The TMDS table is typically found just before the DCB table, with a | |
5185 | * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being | |
5186 | * length?) | |
5187 | * | |
5188 | * At offset +7 is a pointer to a script, which I don't know how to | |
5189 | * run yet. | |
5190 | * At offset +9 is a pointer to another script, likewise | |
5191 | * Offset +11 has a pointer to a table where the first word is a pxclk | |
5192 | * frequency and the second word a pointer to a script, which should be | |
5193 | * run if the comparison pxclk frequency is less than the pxclk desired. | |
5194 | * This repeats for decreasing comparison frequencies | |
5195 | * Offset +13 has a pointer to a similar table | |
5196 | * The selection of table (and possibly +7/+9 script) is dictated by | |
5197 | * "or" from the DCB. | |
5198 | */ | |
5199 | ||
5200 | uint16_t tmdstableptr, script1, script2; | |
5201 | ||
5202 | if (bitentry->length != 2) { | |
5203 | NV_ERROR(dev, "Do not understand BIT TMDS table\n"); | |
5204 | return -EINVAL; | |
5205 | } | |
5206 | ||
5207 | tmdstableptr = ROM16(bios->data[bitentry->offset]); | |
5208 | ||
5209 | if (tmdstableptr == 0x0) { | |
5210 | NV_ERROR(dev, "Pointer to TMDS table invalid\n"); | |
5211 | return -EINVAL; | |
5212 | } | |
5213 | ||
5214 | /* nv50+ has v2.0, but we don't parse it atm */ | |
5215 | if (bios->data[tmdstableptr] != 0x11) { | |
5216 | NV_WARN(dev, | |
5217 | "TMDS table revision %d.%d not currently supported\n", | |
5218 | bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); | |
5219 | return -ENOSYS; | |
5220 | } | |
5221 | ||
5222 | /* | |
5223 | * These two scripts are odd: they don't seem to get run even when | |
5224 | * they are not stubbed. | |
5225 | */ | |
5226 | script1 = ROM16(bios->data[tmdstableptr + 7]); | |
5227 | script2 = ROM16(bios->data[tmdstableptr + 9]); | |
5228 | if (bios->data[script1] != 'q' || bios->data[script2] != 'q') | |
5229 | NV_WARN(dev, "TMDS table script pointers not stubbed\n"); | |
5230 | ||
5231 | bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); | |
5232 | bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); | |
5233 | ||
5234 | return 0; | |
5235 | } | |
5236 | ||
5237 | static int | |
5238 | parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, | |
5239 | struct bit_entry *bitentry) | |
5240 | { | |
5241 | /* | |
5242 | * Parses the pointer to the G80 output script tables | |
5243 | * | |
5244 | * Starting at bitentry->offset: | |
5245 | * | |
5246 | * offset + 0 (16 bits): output script table pointer | |
5247 | */ | |
5248 | ||
5249 | uint16_t outputscripttableptr; | |
5250 | ||
5251 | if (bitentry->length != 3) { | |
5252 | NV_ERROR(dev, "Do not understand BIT U table\n"); | |
5253 | return -EINVAL; | |
5254 | } | |
5255 | ||
5256 | outputscripttableptr = ROM16(bios->data[bitentry->offset]); | |
5257 | bios->display.script_table_ptr = outputscripttableptr; | |
5258 | return 0; | |
5259 | } | |
5260 | ||
5261 | static int | |
5262 | parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios, | |
5263 | struct bit_entry *bitentry) | |
5264 | { | |
5265 | bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]); | |
5266 | return 0; | |
5267 | } | |
5268 | ||
5269 | struct bit_table { | |
5270 | const char id; | |
5271 | int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); | |
5272 | }; | |
5273 | ||
5274 | #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) | |
5275 | ||
5276 | static int | |
5277 | parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, | |
5278 | struct bit_table *table) | |
5279 | { | |
5280 | struct drm_device *dev = bios->dev; | |
5281 | uint8_t maxentries = bios->data[bitoffset + 4]; | |
5282 | int i, offset; | |
5283 | struct bit_entry bitentry; | |
5284 | ||
5285 | for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) { | |
5286 | bitentry.id[0] = bios->data[offset]; | |
5287 | ||
5288 | if (bitentry.id[0] != table->id) | |
5289 | continue; | |
5290 | ||
5291 | bitentry.id[1] = bios->data[offset + 1]; | |
5292 | bitentry.length = ROM16(bios->data[offset + 2]); | |
5293 | bitentry.offset = ROM16(bios->data[offset + 4]); | |
5294 | ||
5295 | return table->parse_fn(dev, bios, &bitentry); | |
5296 | } | |
5297 | ||
5298 | NV_INFO(dev, "BIT table '%c' not found\n", table->id); | |
5299 | return -ENOSYS; | |
5300 | } | |
5301 | ||
5302 | static int | |
5303 | parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) | |
5304 | { | |
5305 | int ret; | |
5306 | ||
5307 | /* | |
5308 | * The only restriction on parsing order currently is having 'i' first | |
5309 | * for use of bios->*_version or bios->feature_byte while parsing; | |
5310 | * functions shouldn't be actually *doing* anything apart from pulling | |
5311 | * data from the image into the bios struct, thus no interdependencies | |
5312 | */ | |
5313 | ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); | |
5314 | if (ret) /* info? */ | |
5315 | return ret; | |
5316 | if (bios->major_version >= 0x60) /* g80+ */ | |
5317 | parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); | |
5318 | ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); | |
5319 | if (ret) | |
5320 | return ret; | |
5321 | parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); | |
5322 | ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); | |
5323 | if (ret) | |
5324 | return ret; | |
5325 | parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ | |
5326 | parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); | |
5327 | parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); | |
5328 | parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); | |
5329 | parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport)); | |
5330 | ||
5331 | return 0; | |
5332 | } | |
5333 | ||
5334 | static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) | |
5335 | { | |
5336 | /* | |
5337 | * Parses the BMP structure for useful things, but does not act on them | |
5338 | * | |
5339 | * offset + 5: BMP major version | |
5340 | * offset + 6: BMP minor version | |
5341 | * offset + 9: BMP feature byte | |
5342 | * offset + 10: BCD encoded BIOS version | |
5343 | * | |
5344 | * offset + 18: init script table pointer (for bios versions < 5.10h) | |
5345 | * offset + 20: extra init script table pointer (for bios | |
5346 | * versions < 5.10h) | |
5347 | * | |
5348 | * offset + 24: memory init table pointer (used on early bios versions) | |
5349 | * offset + 26: SDR memory sequencing setup data table | |
5350 | * offset + 28: DDR memory sequencing setup data table | |
5351 | * | |
5352 | * offset + 54: index of I2C CRTC pair to use for CRT output | |
5353 | * offset + 55: index of I2C CRTC pair to use for TV output | |
5354 | * offset + 56: index of I2C CRTC pair to use for flat panel output | |
5355 | * offset + 58: write CRTC index for I2C pair 0 | |
5356 | * offset + 59: read CRTC index for I2C pair 0 | |
5357 | * offset + 60: write CRTC index for I2C pair 1 | |
5358 | * offset + 61: read CRTC index for I2C pair 1 | |
5359 | * | |
5360 | * offset + 67: maximum internal PLL frequency (single stage PLL) | |
5361 | * offset + 71: minimum internal PLL frequency (single stage PLL) | |
5362 | * | |
5363 | * offset + 75: script table pointers, as described in | |
5364 | * parse_script_table_pointers | |
5365 | * | |
5366 | * offset + 89: TMDS single link output A table pointer | |
5367 | * offset + 91: TMDS single link output B table pointer | |
5368 | * offset + 95: LVDS single link output A table pointer | |
5369 | * offset + 105: flat panel timings table pointer | |
5370 | * offset + 107: flat panel strapping translation table pointer | |
5371 | * offset + 117: LVDS manufacturer panel config table pointer | |
5372 | * offset + 119: LVDS manufacturer strapping translation table pointer | |
5373 | * | |
5374 | * offset + 142: PLL limits table pointer | |
5375 | * | |
5376 | * offset + 156: minimum pixel clock for LVDS dual link | |
5377 | */ | |
5378 | ||
5379 | uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; | |
5380 | uint16_t bmplength; | |
5381 | uint16_t legacy_scripts_offset, legacy_i2c_offset; | |
5382 | ||
5383 | /* load needed defaults in case we can't parse this info */ | |
7f245b20 BS |
5384 | bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; |
5385 | bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; | |
5386 | bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; | |
5387 | bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; | |
04a39c57 | 5388 | bios->digital_min_front_porch = 0x4b; |
6ee73861 BS |
5389 | bios->fmaxvco = 256000; |
5390 | bios->fminvco = 128000; | |
5391 | bios->fp.duallink_transition_clk = 90000; | |
5392 | ||
5393 | bmp_version_major = bmp[5]; | |
5394 | bmp_version_minor = bmp[6]; | |
5395 | ||
5396 | NV_TRACE(dev, "BMP version %d.%d\n", | |
5397 | bmp_version_major, bmp_version_minor); | |
5398 | ||
5399 | /* | |
5400 | * Make sure that 0x36 is blank and can't be mistaken for a DCB | |
5401 | * pointer on early versions | |
5402 | */ | |
5403 | if (bmp_version_major < 5) | |
5404 | *(uint16_t *)&bios->data[0x36] = 0; | |
5405 | ||
5406 | /* | |
5407 | * Seems that the minor version was 1 for all major versions prior | |
5408 | * to 5. Version 6 could theoretically exist, but I suspect BIT | |
5409 | * happened instead. | |
5410 | */ | |
5411 | if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { | |
5412 | NV_ERROR(dev, "You have an unsupported BMP version. " | |
5413 | "Please send in your bios\n"); | |
5414 | return -ENOSYS; | |
5415 | } | |
5416 | ||
5417 | if (bmp_version_major == 0) | |
5418 | /* nothing that's currently useful in this version */ | |
5419 | return 0; | |
5420 | else if (bmp_version_major == 1) | |
5421 | bmplength = 44; /* exact for 1.01 */ | |
5422 | else if (bmp_version_major == 2) | |
5423 | bmplength = 48; /* exact for 2.01 */ | |
5424 | else if (bmp_version_major == 3) | |
5425 | bmplength = 54; | |
5426 | /* guessed - mem init tables added in this version */ | |
5427 | else if (bmp_version_major == 4 || bmp_version_minor < 0x1) | |
5428 | /* don't know if 5.0 exists... */ | |
5429 | bmplength = 62; | |
5430 | /* guessed - BMP I2C indices added in version 4*/ | |
5431 | else if (bmp_version_minor < 0x6) | |
5432 | bmplength = 67; /* exact for 5.01 */ | |
5433 | else if (bmp_version_minor < 0x10) | |
5434 | bmplength = 75; /* exact for 5.06 */ | |
5435 | else if (bmp_version_minor == 0x10) | |
5436 | bmplength = 89; /* exact for 5.10h */ | |
5437 | else if (bmp_version_minor < 0x14) | |
5438 | bmplength = 118; /* exact for 5.11h */ | |
5439 | else if (bmp_version_minor < 0x24) | |
5440 | /* | |
5441 | * Not sure of version where pll limits came in; | |
5442 | * certainly exist by 0x24 though. | |
5443 | */ | |
5444 | /* length not exact: this is long enough to get lvds members */ | |
5445 | bmplength = 123; | |
5446 | else if (bmp_version_minor < 0x27) | |
5447 | /* | |
5448 | * Length not exact: this is long enough to get pll limit | |
5449 | * member | |
5450 | */ | |
5451 | bmplength = 144; | |
5452 | else | |
5453 | /* | |
5454 | * Length not exact: this is long enough to get dual link | |
5455 | * transition clock. | |
5456 | */ | |
5457 | bmplength = 158; | |
5458 | ||
5459 | /* checksum */ | |
5460 | if (nv_cksum(bmp, 8)) { | |
5461 | NV_ERROR(dev, "Bad BMP checksum\n"); | |
5462 | return -EINVAL; | |
5463 | } | |
5464 | ||
5465 | /* | |
5466 | * Bit 4 seems to indicate either a mobile bios or a quadro card -- | |
5467 | * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl | |
5468 | * (not nv10gl), bit 5 that the flat panel tables are present, and | |
5469 | * bit 6 a tv bios. | |
5470 | */ | |
5471 | bios->feature_byte = bmp[9]; | |
5472 | ||
5473 | parse_bios_version(dev, bios, offset + 10); | |
5474 | ||
5475 | if (bmp_version_major < 5 || bmp_version_minor < 0x10) | |
5476 | bios->old_style_init = true; | |
5477 | legacy_scripts_offset = 18; | |
5478 | if (bmp_version_major < 2) | |
5479 | legacy_scripts_offset -= 4; | |
5480 | bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); | |
5481 | bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); | |
5482 | ||
5483 | if (bmp_version_major > 2) { /* appears in BMP 3 */ | |
5484 | bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); | |
5485 | bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); | |
5486 | bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); | |
5487 | } | |
5488 | ||
5489 | legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ | |
5490 | if (bmplength > 61) | |
5491 | legacy_i2c_offset = offset + 54; | |
5492 | bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; | |
5493 | bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; | |
5494 | bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; | |
3af76454 FJ |
5495 | if (bios->data[legacy_i2c_offset + 4]) |
5496 | bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; | |
5497 | if (bios->data[legacy_i2c_offset + 5]) | |
5498 | bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; | |
5499 | if (bios->data[legacy_i2c_offset + 6]) | |
5500 | bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; | |
5501 | if (bios->data[legacy_i2c_offset + 7]) | |
5502 | bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; | |
6ee73861 BS |
5503 | |
5504 | if (bmplength > 74) { | |
5505 | bios->fmaxvco = ROM32(bmp[67]); | |
5506 | bios->fminvco = ROM32(bmp[71]); | |
5507 | } | |
5508 | if (bmplength > 88) | |
5509 | parse_script_table_pointers(bios, offset + 75); | |
5510 | if (bmplength > 94) { | |
5511 | bios->tmds.output0_script_ptr = ROM16(bmp[89]); | |
5512 | bios->tmds.output1_script_ptr = ROM16(bmp[91]); | |
5513 | /* | |
5514 | * Never observed in use with lvds scripts, but is reused for | |
5515 | * 18/24 bit panel interface default for EDID equipped panels | |
5516 | * (if_is_24bit not set directly to avoid any oscillation). | |
5517 | */ | |
5518 | bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); | |
5519 | } | |
5520 | if (bmplength > 108) { | |
5521 | bios->fp.fptablepointer = ROM16(bmp[105]); | |
5522 | bios->fp.fpxlatetableptr = ROM16(bmp[107]); | |
5523 | bios->fp.xlatwidth = 1; | |
5524 | } | |
5525 | if (bmplength > 120) { | |
5526 | bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); | |
5527 | bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); | |
5528 | } | |
5529 | if (bmplength > 143) | |
5530 | bios->pll_limit_tbl_ptr = ROM16(bmp[142]); | |
5531 | ||
5532 | if (bmplength > 157) | |
5533 | bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; | |
5534 | ||
5535 | return 0; | |
5536 | } | |
5537 | ||
5538 | static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) | |
5539 | { | |
5540 | int i, j; | |
5541 | ||
5542 | for (i = 0; i <= (n - len); i++) { | |
5543 | for (j = 0; j < len; j++) | |
5544 | if (data[i + j] != str[j]) | |
5545 | break; | |
5546 | if (j == len) | |
5547 | return i; | |
5548 | } | |
5549 | ||
5550 | return 0; | |
5551 | } | |
5552 | ||
6ee73861 BS |
5553 | static struct dcb_gpio_entry * |
5554 | new_gpio_entry(struct nvbios *bios) | |
5555 | { | |
7f245b20 | 5556 | struct dcb_gpio_table *gpio = &bios->dcb.gpio; |
6ee73861 BS |
5557 | |
5558 | return &gpio->entry[gpio->entries++]; | |
5559 | } | |
5560 | ||
5561 | struct dcb_gpio_entry * | |
5562 | nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) | |
5563 | { | |
5564 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 5565 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
5566 | int i; |
5567 | ||
7f245b20 BS |
5568 | for (i = 0; i < bios->dcb.gpio.entries; i++) { |
5569 | if (bios->dcb.gpio.entry[i].tag != tag) | |
6ee73861 BS |
5570 | continue; |
5571 | ||
7f245b20 | 5572 | return &bios->dcb.gpio.entry[i]; |
6ee73861 BS |
5573 | } |
5574 | ||
5575 | return NULL; | |
5576 | } | |
5577 | ||
5578 | static void | |
5579 | parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) | |
5580 | { | |
5581 | struct dcb_gpio_entry *gpio; | |
5582 | uint16_t ent = ROM16(bios->data[offset]); | |
5583 | uint8_t line = ent & 0x1f, | |
5584 | tag = ent >> 5 & 0x3f, | |
5585 | flags = ent >> 11 & 0x1f; | |
5586 | ||
5587 | if (tag == 0x3f) | |
5588 | return; | |
5589 | ||
5590 | gpio = new_gpio_entry(bios); | |
5591 | ||
5592 | gpio->tag = tag; | |
5593 | gpio->line = line; | |
5594 | gpio->invert = flags != 4; | |
2535d71c | 5595 | gpio->entry = ent; |
6ee73861 BS |
5596 | } |
5597 | ||
5598 | static void | |
5599 | parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) | |
5600 | { | |
02faec09 | 5601 | uint32_t entry = ROM32(bios->data[offset]); |
6ee73861 | 5602 | struct dcb_gpio_entry *gpio; |
6ee73861 | 5603 | |
02faec09 | 5604 | if ((entry & 0x0000ff00) == 0x0000ff00) |
6ee73861 BS |
5605 | return; |
5606 | ||
5607 | gpio = new_gpio_entry(bios); | |
02faec09 BS |
5608 | gpio->tag = (entry & 0x0000ff00) >> 8; |
5609 | gpio->line = (entry & 0x0000001f) >> 0; | |
5610 | gpio->state_default = (entry & 0x01000000) >> 24; | |
5611 | gpio->state[0] = (entry & 0x18000000) >> 27; | |
5612 | gpio->state[1] = (entry & 0x60000000) >> 29; | |
5613 | gpio->entry = entry; | |
6ee73861 BS |
5614 | } |
5615 | ||
5616 | static void | |
5617 | parse_dcb_gpio_table(struct nvbios *bios) | |
5618 | { | |
5619 | struct drm_device *dev = bios->dev; | |
7f245b20 | 5620 | uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; |
6ee73861 BS |
5621 | uint8_t *gpio_table = &bios->data[gpio_table_ptr]; |
5622 | int header_len = gpio_table[1], | |
5623 | entries = gpio_table[2], | |
5624 | entry_len = gpio_table[3]; | |
5625 | void (*parse_entry)(struct nvbios *, uint16_t) = NULL; | |
5626 | int i; | |
5627 | ||
7f245b20 | 5628 | if (bios->dcb.version >= 0x40) { |
6ee73861 BS |
5629 | if (gpio_table_ptr && entry_len != 4) { |
5630 | NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); | |
5631 | return; | |
5632 | } | |
5633 | ||
5634 | parse_entry = parse_dcb40_gpio_entry; | |
5635 | ||
7f245b20 | 5636 | } else if (bios->dcb.version >= 0x30) { |
6ee73861 BS |
5637 | if (gpio_table_ptr && entry_len != 2) { |
5638 | NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); | |
5639 | return; | |
5640 | } | |
5641 | ||
5642 | parse_entry = parse_dcb30_gpio_entry; | |
5643 | ||
7f245b20 | 5644 | } else if (bios->dcb.version >= 0x22) { |
6ee73861 BS |
5645 | /* |
5646 | * DCBs older than v3.0 don't really have a GPIO | |
5647 | * table, instead they keep some GPIO info at fixed | |
5648 | * locations. | |
5649 | */ | |
5650 | uint16_t dcbptr = ROM16(bios->data[0x36]); | |
5651 | uint8_t *tvdac_gpio = &bios->data[dcbptr - 5]; | |
5652 | ||
5653 | if (tvdac_gpio[0] & 1) { | |
5654 | struct dcb_gpio_entry *gpio = new_gpio_entry(bios); | |
5655 | ||
5656 | gpio->tag = DCB_GPIO_TVDAC0; | |
5657 | gpio->line = tvdac_gpio[1] >> 4; | |
5658 | gpio->invert = tvdac_gpio[0] & 2; | |
5659 | } | |
5660 | } | |
5661 | ||
5662 | if (!gpio_table_ptr) | |
5663 | return; | |
5664 | ||
5665 | if (entries > DCB_MAX_NUM_GPIO_ENTRIES) { | |
5666 | NV_WARN(dev, "Too many entries in the DCB GPIO table.\n"); | |
5667 | entries = DCB_MAX_NUM_GPIO_ENTRIES; | |
5668 | } | |
5669 | ||
5670 | for (i = 0; i < entries; i++) | |
5671 | parse_entry(bios, gpio_table_ptr + header_len + entry_len * i); | |
5672 | } | |
5673 | ||
5674 | struct dcb_connector_table_entry * | |
5675 | nouveau_bios_connector_entry(struct drm_device *dev, int index) | |
5676 | { | |
5677 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 5678 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
5679 | struct dcb_connector_table_entry *cte; |
5680 | ||
7f245b20 | 5681 | if (index >= bios->dcb.connector.entries) |
6ee73861 BS |
5682 | return NULL; |
5683 | ||
7f245b20 | 5684 | cte = &bios->dcb.connector.entry[index]; |
6ee73861 BS |
5685 | if (cte->type == 0xff) |
5686 | return NULL; | |
5687 | ||
5688 | return cte; | |
5689 | } | |
5690 | ||
f66fa771 BS |
5691 | static enum dcb_connector_type |
5692 | divine_connector_type(struct nvbios *bios, int index) | |
5693 | { | |
5694 | struct dcb_table *dcb = &bios->dcb; | |
5695 | unsigned encoders = 0, type = DCB_CONNECTOR_NONE; | |
5696 | int i; | |
5697 | ||
5698 | for (i = 0; i < dcb->entries; i++) { | |
5699 | if (dcb->entry[i].connector == index) | |
5700 | encoders |= (1 << dcb->entry[i].type); | |
5701 | } | |
5702 | ||
5703 | if (encoders & (1 << OUTPUT_DP)) { | |
5704 | if (encoders & (1 << OUTPUT_TMDS)) | |
5705 | type = DCB_CONNECTOR_DP; | |
5706 | else | |
5707 | type = DCB_CONNECTOR_eDP; | |
5708 | } else | |
5709 | if (encoders & (1 << OUTPUT_TMDS)) { | |
5710 | if (encoders & (1 << OUTPUT_ANALOG)) | |
5711 | type = DCB_CONNECTOR_DVI_I; | |
5712 | else | |
5713 | type = DCB_CONNECTOR_DVI_D; | |
5714 | } else | |
5715 | if (encoders & (1 << OUTPUT_ANALOG)) { | |
5716 | type = DCB_CONNECTOR_VGA; | |
5717 | } else | |
5718 | if (encoders & (1 << OUTPUT_LVDS)) { | |
5719 | type = DCB_CONNECTOR_LVDS; | |
5720 | } else | |
5721 | if (encoders & (1 << OUTPUT_TV)) { | |
5722 | type = DCB_CONNECTOR_TV_0; | |
5723 | } | |
5724 | ||
5725 | return type; | |
5726 | } | |
5727 | ||
53c44c3a BS |
5728 | static void |
5729 | apply_dcb_connector_quirks(struct nvbios *bios, int idx) | |
5730 | { | |
5731 | struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; | |
5732 | struct drm_device *dev = bios->dev; | |
5733 | ||
5734 | /* Gigabyte NX85T */ | |
5735 | if ((dev->pdev->device == 0x0421) && | |
5736 | (dev->pdev->subsystem_vendor == 0x1458) && | |
5737 | (dev->pdev->subsystem_device == 0x344c)) { | |
5738 | if (cte->type == DCB_CONNECTOR_HDMI_1) | |
5739 | cte->type = DCB_CONNECTOR_DVI_I; | |
5740 | } | |
5741 | } | |
5742 | ||
6ee73861 BS |
5743 | static void |
5744 | parse_dcb_connector_table(struct nvbios *bios) | |
5745 | { | |
5746 | struct drm_device *dev = bios->dev; | |
7f245b20 | 5747 | struct dcb_connector_table *ct = &bios->dcb.connector; |
6ee73861 | 5748 | struct dcb_connector_table_entry *cte; |
7f245b20 | 5749 | uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; |
6ee73861 BS |
5750 | uint8_t *entry; |
5751 | int i; | |
5752 | ||
7f245b20 | 5753 | if (!bios->dcb.connector_table_ptr) { |
ef2bb506 | 5754 | NV_DEBUG_KMS(dev, "No DCB connector table present\n"); |
6ee73861 BS |
5755 | return; |
5756 | } | |
5757 | ||
5758 | NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n", | |
5759 | conntab[0], conntab[1], conntab[2], conntab[3]); | |
5760 | if ((conntab[0] != 0x30 && conntab[0] != 0x40) || | |
5761 | (conntab[3] != 2 && conntab[3] != 4)) { | |
5762 | NV_ERROR(dev, " Unknown! Please report.\n"); | |
5763 | return; | |
5764 | } | |
5765 | ||
5766 | ct->entries = conntab[2]; | |
5767 | ||
5768 | entry = conntab + conntab[1]; | |
5769 | cte = &ct->entry[0]; | |
5770 | for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { | |
d544d623 | 5771 | cte->index = i; |
6ee73861 BS |
5772 | if (conntab[3] == 2) |
5773 | cte->entry = ROM16(entry[0]); | |
5774 | else | |
5775 | cte->entry = ROM32(entry[0]); | |
f66fa771 | 5776 | |
6ee73861 | 5777 | cte->type = (cte->entry & 0x000000ff) >> 0; |
d544d623 | 5778 | cte->index2 = (cte->entry & 0x00000f00) >> 8; |
6ee73861 BS |
5779 | switch (cte->entry & 0x00033000) { |
5780 | case 0x00001000: | |
5781 | cte->gpio_tag = 0x07; | |
5782 | break; | |
5783 | case 0x00002000: | |
5784 | cte->gpio_tag = 0x08; | |
5785 | break; | |
5786 | case 0x00010000: | |
5787 | cte->gpio_tag = 0x51; | |
5788 | break; | |
5789 | case 0x00020000: | |
5790 | cte->gpio_tag = 0x52; | |
5791 | break; | |
5792 | default: | |
5793 | cte->gpio_tag = 0xff; | |
5794 | break; | |
5795 | } | |
5796 | ||
5797 | if (cte->type == 0xff) | |
5798 | continue; | |
5799 | ||
53c44c3a BS |
5800 | apply_dcb_connector_quirks(bios, i); |
5801 | ||
6ee73861 BS |
5802 | NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", |
5803 | i, cte->entry, cte->type, cte->index, cte->gpio_tag); | |
f66fa771 BS |
5804 | |
5805 | /* check for known types, fallback to guessing the type | |
5806 | * from attached encoders if we hit an unknown. | |
5807 | */ | |
5808 | switch (cte->type) { | |
5809 | case DCB_CONNECTOR_VGA: | |
5810 | case DCB_CONNECTOR_TV_0: | |
5811 | case DCB_CONNECTOR_TV_1: | |
5812 | case DCB_CONNECTOR_TV_3: | |
5813 | case DCB_CONNECTOR_DVI_I: | |
5814 | case DCB_CONNECTOR_DVI_D: | |
5815 | case DCB_CONNECTOR_LVDS: | |
5816 | case DCB_CONNECTOR_DP: | |
5817 | case DCB_CONNECTOR_eDP: | |
5818 | case DCB_CONNECTOR_HDMI_0: | |
5819 | case DCB_CONNECTOR_HDMI_1: | |
5820 | break; | |
5821 | default: | |
5822 | cte->type = divine_connector_type(bios, cte->index); | |
da647d5b | 5823 | NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type); |
f66fa771 BS |
5824 | break; |
5825 | } | |
5826 | ||
da647d5b BS |
5827 | if (nouveau_override_conntype) { |
5828 | int type = divine_connector_type(bios, cte->index); | |
5829 | if (type != cte->type) | |
5830 | NV_WARN(dev, " -> type 0x%02x\n", cte->type); | |
5831 | } | |
5832 | ||
6ee73861 BS |
5833 | } |
5834 | } | |
5835 | ||
7f245b20 | 5836 | static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) |
6ee73861 BS |
5837 | { |
5838 | struct dcb_entry *entry = &dcb->entry[dcb->entries]; | |
5839 | ||
5840 | memset(entry, 0, sizeof(struct dcb_entry)); | |
5841 | entry->index = dcb->entries++; | |
5842 | ||
5843 | return entry; | |
5844 | } | |
5845 | ||
7f245b20 | 5846 | static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads) |
6ee73861 BS |
5847 | { |
5848 | struct dcb_entry *entry = new_dcb_entry(dcb); | |
5849 | ||
5850 | entry->type = 0; | |
5851 | entry->i2c_index = i2c; | |
5852 | entry->heads = heads; | |
5853 | entry->location = DCB_LOC_ON_CHIP; | |
5854 | /* "or" mostly unused in early gen crt modesetting, 0 is fine */ | |
5855 | } | |
5856 | ||
7f245b20 | 5857 | static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) |
6ee73861 BS |
5858 | { |
5859 | struct dcb_entry *entry = new_dcb_entry(dcb); | |
5860 | ||
5861 | entry->type = 2; | |
5862 | entry->i2c_index = LEGACY_I2C_PANEL; | |
5863 | entry->heads = twoHeads ? 3 : 1; | |
5864 | entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ | |
5865 | entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */ | |
5866 | entry->duallink_possible = false; /* SiI164 and co. are single link */ | |
5867 | ||
5868 | #if 0 | |
5869 | /* | |
5870 | * For dvi-a either crtc probably works, but my card appears to only | |
5871 | * support dvi-d. "nvidia" still attempts to program it for dvi-a, | |
5872 | * doing the full fp output setup (program 0x6808.. fp dimension regs, | |
5873 | * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880); | |
5874 | * the monitor picks up the mode res ok and lights up, but no pixel | |
5875 | * data appears, so the board manufacturer probably connected up the | |
5876 | * sync lines, but missed the video traces / components | |
5877 | * | |
5878 | * with this introduction, dvi-a left as an exercise for the reader. | |
5879 | */ | |
5880 | fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads); | |
5881 | #endif | |
5882 | } | |
5883 | ||
7f245b20 | 5884 | static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads) |
6ee73861 BS |
5885 | { |
5886 | struct dcb_entry *entry = new_dcb_entry(dcb); | |
5887 | ||
5888 | entry->type = 1; | |
5889 | entry->i2c_index = LEGACY_I2C_TV; | |
5890 | entry->heads = twoHeads ? 3 : 1; | |
5891 | entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ | |
5892 | } | |
5893 | ||
5894 | static bool | |
7f245b20 | 5895 | parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, |
6ee73861 BS |
5896 | uint32_t conn, uint32_t conf, struct dcb_entry *entry) |
5897 | { | |
5898 | entry->type = conn & 0xf; | |
5899 | entry->i2c_index = (conn >> 4) & 0xf; | |
5900 | entry->heads = (conn >> 8) & 0xf; | |
7f245b20 | 5901 | if (dcb->version >= 0x40) |
6ee73861 BS |
5902 | entry->connector = (conn >> 12) & 0xf; |
5903 | entry->bus = (conn >> 16) & 0xf; | |
5904 | entry->location = (conn >> 20) & 0x3; | |
5905 | entry->or = (conn >> 24) & 0xf; | |
6ee73861 BS |
5906 | |
5907 | switch (entry->type) { | |
5908 | case OUTPUT_ANALOG: | |
5909 | /* | |
5910 | * Although the rest of a CRT conf dword is usually | |
5911 | * zeros, mac biosen have stuff there so we must mask | |
5912 | */ | |
7f245b20 | 5913 | entry->crtconf.maxfreq = (dcb->version < 0x30) ? |
6ee73861 BS |
5914 | (conf & 0xffff) * 10 : |
5915 | (conf & 0xff) * 10000; | |
5916 | break; | |
5917 | case OUTPUT_LVDS: | |
5918 | { | |
5919 | uint32_t mask; | |
5920 | if (conf & 0x1) | |
5921 | entry->lvdsconf.use_straps_for_mode = true; | |
7f245b20 | 5922 | if (dcb->version < 0x22) { |
6ee73861 BS |
5923 | mask = ~0xd; |
5924 | /* | |
5925 | * The laptop in bug 14567 lies and claims to not use | |
5926 | * straps when it does, so assume all DCB 2.0 laptops | |
5927 | * use straps, until a broken EDID using one is produced | |
5928 | */ | |
5929 | entry->lvdsconf.use_straps_for_mode = true; | |
5930 | /* | |
5931 | * Both 0x4 and 0x8 show up in v2.0 tables; assume they | |
5932 | * mean the same thing (probably wrong, but might work) | |
5933 | */ | |
5934 | if (conf & 0x4 || conf & 0x8) | |
5935 | entry->lvdsconf.use_power_scripts = true; | |
5936 | } else { | |
a6ed76d7 BS |
5937 | mask = ~0x7; |
5938 | if (conf & 0x2) | |
5939 | entry->lvdsconf.use_acpi_for_edid = true; | |
6ee73861 BS |
5940 | if (conf & 0x4) |
5941 | entry->lvdsconf.use_power_scripts = true; | |
c5875470 | 5942 | entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; |
6ee73861 BS |
5943 | } |
5944 | if (conf & mask) { | |
5945 | /* | |
5946 | * Until we even try to use these on G8x, it's | |
5947 | * useless reporting unknown bits. They all are. | |
5948 | */ | |
7f245b20 | 5949 | if (dcb->version >= 0x40) |
6ee73861 BS |
5950 | break; |
5951 | ||
5952 | NV_ERROR(dev, "Unknown LVDS configuration bits, " | |
5953 | "please report\n"); | |
5954 | } | |
5955 | break; | |
5956 | } | |
5957 | case OUTPUT_TV: | |
5958 | { | |
7f245b20 | 5959 | if (dcb->version >= 0x30) |
6ee73861 BS |
5960 | entry->tvconf.has_component_output = conf & (0x8 << 4); |
5961 | else | |
5962 | entry->tvconf.has_component_output = false; | |
5963 | ||
5964 | break; | |
5965 | } | |
5966 | case OUTPUT_DP: | |
5967 | entry->dpconf.sor.link = (conf & 0x00000030) >> 4; | |
5968 | entry->dpconf.link_bw = (conf & 0x00e00000) >> 21; | |
5969 | switch ((conf & 0x0f000000) >> 24) { | |
5970 | case 0xf: | |
5971 | entry->dpconf.link_nr = 4; | |
5972 | break; | |
5973 | case 0x3: | |
5974 | entry->dpconf.link_nr = 2; | |
5975 | break; | |
5976 | default: | |
5977 | entry->dpconf.link_nr = 1; | |
5978 | break; | |
5979 | } | |
5980 | break; | |
5981 | case OUTPUT_TMDS: | |
5982 | entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; | |
5983 | break; | |
5984 | case 0xe: | |
5985 | /* weird g80 mobile type that "nv" treats as a terminator */ | |
7f245b20 | 5986 | dcb->entries--; |
6ee73861 | 5987 | return false; |
e7cc51c5 BS |
5988 | default: |
5989 | break; | |
6ee73861 BS |
5990 | } |
5991 | ||
23484874 BS |
5992 | if (dcb->version < 0x40) { |
5993 | /* Normal entries consist of a single bit, but dual link has | |
5994 | * the next most significant bit set too | |
5995 | */ | |
5996 | entry->duallink_possible = | |
5997 | ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); | |
5998 | } else { | |
5999 | entry->duallink_possible = (entry->sorconf.link == 3); | |
6000 | } | |
6001 | ||
6ee73861 BS |
6002 | /* unsure what DCB version introduces this, 3.0? */ |
6003 | if (conf & 0x100000) | |
6004 | entry->i2c_upper_default = true; | |
6005 | ||
6006 | return true; | |
6007 | } | |
6008 | ||
6009 | static bool | |
7f245b20 | 6010 | parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, |
6ee73861 BS |
6011 | uint32_t conn, uint32_t conf, struct dcb_entry *entry) |
6012 | { | |
b0d2de86 BS |
6013 | switch (conn & 0x0000000f) { |
6014 | case 0: | |
6015 | entry->type = OUTPUT_ANALOG; | |
6016 | break; | |
6017 | case 1: | |
6018 | entry->type = OUTPUT_TV; | |
6019 | break; | |
6020 | case 2: | |
6021 | case 3: | |
6ee73861 | 6022 | entry->type = OUTPUT_LVDS; |
b0d2de86 BS |
6023 | break; |
6024 | case 4: | |
6025 | switch ((conn & 0x000000f0) >> 4) { | |
6026 | case 0: | |
6ee73861 | 6027 | entry->type = OUTPUT_TMDS; |
b0d2de86 BS |
6028 | break; |
6029 | case 1: | |
6030 | entry->type = OUTPUT_LVDS; | |
6031 | break; | |
6032 | default: | |
6033 | NV_ERROR(dev, "Unknown DCB subtype 4/%d\n", | |
6034 | (conn & 0x000000f0) >> 4); | |
6035 | return false; | |
6036 | } | |
6037 | break; | |
6038 | default: | |
6039 | NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); | |
6040 | return false; | |
6ee73861 | 6041 | } |
b0d2de86 BS |
6042 | |
6043 | entry->i2c_index = (conn & 0x0003c000) >> 14; | |
6044 | entry->heads = ((conn & 0x001c0000) >> 18) + 1; | |
6045 | entry->or = entry->heads; /* same as heads, hopefully safe enough */ | |
6046 | entry->location = (conn & 0x01e00000) >> 21; | |
6047 | entry->bus = (conn & 0x0e000000) >> 25; | |
6ee73861 BS |
6048 | entry->duallink_possible = false; |
6049 | ||
6050 | switch (entry->type) { | |
6051 | case OUTPUT_ANALOG: | |
6052 | entry->crtconf.maxfreq = (conf & 0xffff) * 10; | |
6053 | break; | |
b0d2de86 BS |
6054 | case OUTPUT_TV: |
6055 | entry->tvconf.has_component_output = false; | |
6ee73861 | 6056 | break; |
b0d2de86 BS |
6057 | case OUTPUT_LVDS: |
6058 | if ((conn & 0x00003f00) != 0x10) | |
6059 | entry->lvdsconf.use_straps_for_mode = true; | |
6060 | entry->lvdsconf.use_power_scripts = true; | |
6061 | break; | |
6062 | default: | |
6ee73861 BS |
6063 | break; |
6064 | } | |
6065 | ||
6066 | return true; | |
6067 | } | |
6068 | ||
7f245b20 | 6069 | static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, |
6ee73861 BS |
6070 | uint32_t conn, uint32_t conf) |
6071 | { | |
7f245b20 | 6072 | struct dcb_entry *entry = new_dcb_entry(dcb); |
6ee73861 BS |
6073 | bool ret; |
6074 | ||
7f245b20 BS |
6075 | if (dcb->version >= 0x20) |
6076 | ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); | |
6ee73861 | 6077 | else |
7f245b20 | 6078 | ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); |
6ee73861 BS |
6079 | if (!ret) |
6080 | return ret; | |
6081 | ||
7f245b20 BS |
6082 | read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, |
6083 | entry->i2c_index, &dcb->i2c[entry->i2c_index]); | |
6ee73861 BS |
6084 | |
6085 | return true; | |
6086 | } | |
6087 | ||
6088 | static | |
7f245b20 | 6089 | void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) |
6ee73861 BS |
6090 | { |
6091 | /* | |
6092 | * DCB v2.0 lists each output combination separately. | |
6093 | * Here we merge compatible entries to have fewer outputs, with | |
6094 | * more options | |
6095 | */ | |
6096 | ||
6097 | int i, newentries = 0; | |
6098 | ||
6099 | for (i = 0; i < dcb->entries; i++) { | |
6100 | struct dcb_entry *ient = &dcb->entry[i]; | |
6101 | int j; | |
6102 | ||
6103 | for (j = i + 1; j < dcb->entries; j++) { | |
6104 | struct dcb_entry *jent = &dcb->entry[j]; | |
6105 | ||
6106 | if (jent->type == 100) /* already merged entry */ | |
6107 | continue; | |
6108 | ||
6109 | /* merge heads field when all other fields the same */ | |
6110 | if (jent->i2c_index == ient->i2c_index && | |
6111 | jent->type == ient->type && | |
6112 | jent->location == ient->location && | |
6113 | jent->or == ient->or) { | |
6114 | NV_TRACE(dev, "Merging DCB entries %d and %d\n", | |
6115 | i, j); | |
6116 | ient->heads |= jent->heads; | |
6117 | jent->type = 100; /* dummy value */ | |
6118 | } | |
6119 | } | |
6120 | } | |
6121 | ||
6122 | /* Compact entries merged into others out of dcb */ | |
6123 | for (i = 0; i < dcb->entries; i++) { | |
6124 | if (dcb->entry[i].type == 100) | |
6125 | continue; | |
6126 | ||
6127 | if (newentries != i) { | |
6128 | dcb->entry[newentries] = dcb->entry[i]; | |
6129 | dcb->entry[newentries].index = newentries; | |
6130 | } | |
6131 | newentries++; | |
6132 | } | |
6133 | ||
6134 | dcb->entries = newentries; | |
6135 | } | |
6136 | ||
df4cf1b7 BS |
6137 | static bool |
6138 | apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf) | |
6139 | { | |
6140 | /* Dell Precision M6300 | |
6141 | * DCB entry 2: 02025312 00000010 | |
6142 | * DCB entry 3: 02026312 00000020 | |
6143 | * | |
6144 | * Identical, except apparently a different connector on a | |
6145 | * different SOR link. Not a clue how we're supposed to know | |
6146 | * which one is in use if it even shares an i2c line... | |
6147 | * | |
6148 | * Ignore the connector on the second SOR link to prevent | |
6149 | * nasty problems until this is sorted (assuming it's not a | |
6150 | * VBIOS bug). | |
6151 | */ | |
6152 | if ((dev->pdev->device == 0x040d) && | |
6153 | (dev->pdev->subsystem_vendor == 0x1028) && | |
6154 | (dev->pdev->subsystem_device == 0x019b)) { | |
6155 | if (*conn == 0x02026312 && *conf == 0x00000020) | |
6156 | return false; | |
6157 | } | |
6158 | ||
6159 | return true; | |
6160 | } | |
6161 | ||
ed42f824 BS |
6162 | static int |
6163 | parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) | |
6ee73861 | 6164 | { |
ed42f824 | 6165 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
7f245b20 | 6166 | struct dcb_table *dcb = &bios->dcb; |
ed42f824 | 6167 | uint16_t dcbptr = 0, i2ctabptr = 0; |
6ee73861 BS |
6168 | uint8_t *dcbtable; |
6169 | uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; | |
6170 | bool configblock = true; | |
6171 | int recordlength = 8, confofs = 4; | |
6172 | int i; | |
6173 | ||
6ee73861 | 6174 | /* get the offset from 0x36 */ |
ed42f824 BS |
6175 | if (dev_priv->card_type > NV_04) { |
6176 | dcbptr = ROM16(bios->data[0x36]); | |
6177 | if (dcbptr == 0x0000) | |
6178 | NV_WARN(dev, "No output data (DCB) found in BIOS\n"); | |
6179 | } | |
6ee73861 | 6180 | |
ed42f824 | 6181 | /* this situation likely means a really old card, pre DCB */ |
6ee73861 | 6182 | if (dcbptr == 0x0) { |
ed42f824 | 6183 | NV_INFO(dev, "Assuming a CRT output exists\n"); |
6ee73861 BS |
6184 | fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); |
6185 | ||
ed42f824 | 6186 | if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) |
6ee73861 BS |
6187 | fabricate_tv_output(dcb, twoHeads); |
6188 | ||
6189 | return 0; | |
6190 | } | |
6191 | ||
6192 | dcbtable = &bios->data[dcbptr]; | |
6193 | ||
6194 | /* get DCB version */ | |
7f245b20 | 6195 | dcb->version = dcbtable[0]; |
6ee73861 | 6196 | NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", |
7f245b20 | 6197 | dcb->version >> 4, dcb->version & 0xf); |
6ee73861 | 6198 | |
7f245b20 | 6199 | if (dcb->version >= 0x20) { /* NV17+ */ |
6ee73861 BS |
6200 | uint32_t sig; |
6201 | ||
7f245b20 | 6202 | if (dcb->version >= 0x30) { /* NV40+ */ |
6ee73861 BS |
6203 | headerlen = dcbtable[1]; |
6204 | entries = dcbtable[2]; | |
6205 | recordlength = dcbtable[3]; | |
6206 | i2ctabptr = ROM16(dcbtable[4]); | |
6207 | sig = ROM32(dcbtable[6]); | |
7f245b20 BS |
6208 | dcb->gpio_table_ptr = ROM16(dcbtable[10]); |
6209 | dcb->connector_table_ptr = ROM16(dcbtable[20]); | |
6ee73861 BS |
6210 | } else { |
6211 | i2ctabptr = ROM16(dcbtable[2]); | |
6212 | sig = ROM32(dcbtable[4]); | |
6213 | headerlen = 8; | |
6214 | } | |
6215 | ||
6216 | if (sig != 0x4edcbdcb) { | |
6217 | NV_ERROR(dev, "Bad Display Configuration Block " | |
6218 | "signature (%08X)\n", sig); | |
6219 | return -EINVAL; | |
6220 | } | |
7f245b20 | 6221 | } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ |
6ee73861 BS |
6222 | char sig[8] = { 0 }; |
6223 | ||
6224 | strncpy(sig, (char *)&dcbtable[-7], 7); | |
6225 | i2ctabptr = ROM16(dcbtable[2]); | |
6226 | recordlength = 10; | |
6227 | confofs = 6; | |
6228 | ||
6229 | if (strcmp(sig, "DEV_REC")) { | |
6230 | NV_ERROR(dev, "Bad Display Configuration Block " | |
6231 | "signature (%s)\n", sig); | |
6232 | return -EINVAL; | |
6233 | } | |
6234 | } else { | |
6235 | /* | |
6236 | * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always | |
6237 | * has the same single (crt) entry, even when tv-out present, so | |
6238 | * the conclusion is this version cannot really be used. | |
6239 | * v1.2 tables (some NV6/10, and NV15+) normally have the same | |
6240 | * 5 entries, which are not specific to the card and so no use. | |
6241 | * v1.2 does have an I2C table that read_dcb_i2c_table can | |
6242 | * handle, but cards exist (nv11 in #14821) with a bad i2c table | |
6243 | * pointer, so use the indices parsed in parse_bmp_structure. | |
6244 | * v1.1 (NV5+, maybe some NV4) is entirely unhelpful | |
6245 | */ | |
6246 | NV_TRACEWARN(dev, "No useful information in BIOS output table; " | |
6247 | "adding all possible outputs\n"); | |
6248 | fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); | |
6249 | ||
6250 | /* | |
6251 | * Attempt to detect TV before DVI because the test | |
6252 | * for the former is more accurate and it rules the | |
6253 | * latter out. | |
6254 | */ | |
6255 | if (nv04_tv_identify(dev, | |
6256 | bios->legacy.i2c_indices.tv) >= 0) | |
6257 | fabricate_tv_output(dcb, twoHeads); | |
6258 | ||
6259 | else if (bios->tmds.output0_script_ptr || | |
6260 | bios->tmds.output1_script_ptr) | |
6261 | fabricate_dvi_i_output(dcb, twoHeads); | |
6262 | ||
6263 | return 0; | |
6264 | } | |
6265 | ||
6266 | if (!i2ctabptr) | |
6267 | NV_WARN(dev, "No pointer to DCB I2C port table\n"); | |
6268 | else { | |
7f245b20 BS |
6269 | dcb->i2c_table = &bios->data[i2ctabptr]; |
6270 | if (dcb->version >= 0x30) | |
6271 | dcb->i2c_default_indices = dcb->i2c_table[4]; | |
6ee73861 BS |
6272 | } |
6273 | ||
6ee73861 BS |
6274 | if (entries > DCB_MAX_NUM_ENTRIES) |
6275 | entries = DCB_MAX_NUM_ENTRIES; | |
6276 | ||
6277 | for (i = 0; i < entries; i++) { | |
6278 | uint32_t connection, config = 0; | |
6279 | ||
6280 | connection = ROM32(dcbtable[headerlen + recordlength * i]); | |
6281 | if (configblock) | |
6282 | config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); | |
6283 | ||
6284 | /* seen on an NV11 with DCB v1.5 */ | |
6285 | if (connection == 0x00000000) | |
6286 | break; | |
6287 | ||
6288 | /* seen on an NV17 with DCB v2.0 */ | |
6289 | if (connection == 0xffffffff) | |
6290 | break; | |
6291 | ||
6292 | if ((connection & 0x0000000f) == 0x0000000f) | |
6293 | continue; | |
6294 | ||
df4cf1b7 BS |
6295 | if (!apply_dcb_encoder_quirks(dev, i, &connection, &config)) |
6296 | continue; | |
6297 | ||
6ee73861 BS |
6298 | NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", |
6299 | dcb->entries, connection, config); | |
6300 | ||
7f245b20 | 6301 | if (!parse_dcb_entry(dev, dcb, connection, config)) |
6ee73861 BS |
6302 | break; |
6303 | } | |
6304 | ||
6305 | /* | |
6306 | * apart for v2.1+ not being known for requiring merging, this | |
6307 | * guarantees dcbent->index is the index of the entry in the rom image | |
6308 | */ | |
7f245b20 | 6309 | if (dcb->version < 0x21) |
6ee73861 BS |
6310 | merge_like_dcb_entries(dev, dcb); |
6311 | ||
54abb5dd BS |
6312 | if (!dcb->entries) |
6313 | return -ENXIO; | |
6314 | ||
6315 | parse_dcb_gpio_table(bios); | |
6316 | parse_dcb_connector_table(bios); | |
6317 | return 0; | |
6ee73861 BS |
6318 | } |
6319 | ||
6320 | static void | |
6321 | fixup_legacy_connector(struct nvbios *bios) | |
6322 | { | |
7f245b20 | 6323 | struct dcb_table *dcb = &bios->dcb; |
dc5bc4ed | 6324 | int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; |
6ee73861 BS |
6325 | |
6326 | /* | |
6327 | * DCB 3.0 also has the table in most cases, but there are some cards | |
6328 | * where the table is filled with stub entries, and the DCB entriy | |
6329 | * indices are all 0. We don't need the connector indices on pre-G80 | |
6330 | * chips (yet?) so limit the use to DCB 4.0 and above. | |
6331 | */ | |
7f245b20 | 6332 | if (dcb->version >= 0x40) |
6ee73861 BS |
6333 | return; |
6334 | ||
dc5bc4ed BS |
6335 | dcb->connector.entries = 0; |
6336 | ||
6ee73861 BS |
6337 | /* |
6338 | * No known connector info before v3.0, so make it up. the rule here | |
6339 | * is: anything on the same i2c bus is considered to be on the same | |
6340 | * connector. any output without an associated i2c bus is assigned | |
6341 | * its own unique connector index. | |
6342 | */ | |
6343 | for (i = 0; i < dcb->entries; i++) { | |
6ee73861 BS |
6344 | /* |
6345 | * Ignore the I2C index for on-chip TV-out, as there | |
6346 | * are cards with bogus values (nv31m in bug 23212), | |
6347 | * and it's otherwise useless. | |
6348 | */ | |
6349 | if (dcb->entry[i].type == OUTPUT_TV && | |
dc5bc4ed | 6350 | dcb->entry[i].location == DCB_LOC_ON_CHIP) |
6ee73861 | 6351 | dcb->entry[i].i2c_index = 0xf; |
dc5bc4ed BS |
6352 | i2c = dcb->entry[i].i2c_index; |
6353 | ||
6354 | if (i2c_conn[i2c]) { | |
6355 | dcb->entry[i].connector = i2c_conn[i2c] - 1; | |
6ee73861 BS |
6356 | continue; |
6357 | } | |
6358 | ||
dc5bc4ed BS |
6359 | dcb->entry[i].connector = dcb->connector.entries++; |
6360 | if (i2c != 0xf) | |
6361 | i2c_conn[i2c] = dcb->connector.entries; | |
6ee73861 BS |
6362 | } |
6363 | ||
dc5bc4ed BS |
6364 | /* Fake the connector table as well as just connector indices */ |
6365 | for (i = 0; i < dcb->connector.entries; i++) { | |
6366 | dcb->connector.entry[i].index = i; | |
6367 | dcb->connector.entry[i].type = divine_connector_type(bios, i); | |
6368 | dcb->connector.entry[i].gpio_tag = 0xff; | |
6ee73861 BS |
6369 | } |
6370 | } | |
6371 | ||
6372 | static void | |
6373 | fixup_legacy_i2c(struct nvbios *bios) | |
6374 | { | |
7f245b20 | 6375 | struct dcb_table *dcb = &bios->dcb; |
6ee73861 BS |
6376 | int i; |
6377 | ||
6378 | for (i = 0; i < dcb->entries; i++) { | |
6379 | if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT) | |
6380 | dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt; | |
6381 | if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL) | |
6382 | dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel; | |
6383 | if (dcb->entry[i].i2c_index == LEGACY_I2C_TV) | |
6384 | dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv; | |
6385 | } | |
6386 | } | |
6387 | ||
6388 | static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) | |
6389 | { | |
6390 | /* | |
6391 | * The header following the "HWSQ" signature has the number of entries, | |
6392 | * and the entry size | |
6393 | * | |
6394 | * An entry consists of a dword to write to the sequencer control reg | |
6395 | * (0x00001304), followed by the ucode bytes, written sequentially, | |
6396 | * starting at reg 0x00001400 | |
6397 | */ | |
6398 | ||
6399 | uint8_t bytes_to_write; | |
6400 | uint16_t hwsq_entry_offset; | |
6401 | int i; | |
6402 | ||
6403 | if (bios->data[hwsq_offset] <= entry) { | |
6404 | NV_ERROR(dev, "Too few entries in HW sequencer table for " | |
6405 | "requested entry\n"); | |
6406 | return -ENOENT; | |
6407 | } | |
6408 | ||
6409 | bytes_to_write = bios->data[hwsq_offset + 1]; | |
6410 | ||
6411 | if (bytes_to_write != 36) { | |
6412 | NV_ERROR(dev, "Unknown HW sequencer entry size\n"); | |
6413 | return -EINVAL; | |
6414 | } | |
6415 | ||
6416 | NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); | |
6417 | ||
6418 | hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; | |
6419 | ||
6420 | /* set sequencer control */ | |
6421 | bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); | |
6422 | bytes_to_write -= 4; | |
6423 | ||
6424 | /* write ucode */ | |
6425 | for (i = 0; i < bytes_to_write; i += 4) | |
6426 | bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); | |
6427 | ||
6428 | /* twiddle NV_PBUS_DEBUG_4 */ | |
6429 | bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); | |
6430 | ||
6431 | return 0; | |
6432 | } | |
6433 | ||
6434 | static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, | |
6435 | struct nvbios *bios) | |
6436 | { | |
6437 | /* | |
6438 | * BMP based cards, from NV17, need a microcode loading to correctly | |
6439 | * control the GPIO etc for LVDS panels | |
6440 | * | |
6441 | * BIT based cards seem to do this directly in the init scripts | |
6442 | * | |
6443 | * The microcode entries are found by the "HWSQ" signature. | |
6444 | */ | |
6445 | ||
6446 | const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; | |
6447 | const int sz = sizeof(hwsq_signature); | |
6448 | int hwsq_offset; | |
6449 | ||
6450 | hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); | |
6451 | if (!hwsq_offset) | |
6452 | return 0; | |
6453 | ||
6454 | /* always use entry 0? */ | |
6455 | return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); | |
6456 | } | |
6457 | ||
6458 | uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) | |
6459 | { | |
6460 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 6461 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
6462 | const uint8_t edid_sig[] = { |
6463 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; | |
6464 | uint16_t offset = 0; | |
6465 | uint16_t newoffset; | |
6466 | int searchlen = NV_PROM_SIZE; | |
6467 | ||
6468 | if (bios->fp.edid) | |
6469 | return bios->fp.edid; | |
6470 | ||
6471 | while (searchlen) { | |
6472 | newoffset = findstr(&bios->data[offset], searchlen, | |
6473 | edid_sig, 8); | |
6474 | if (!newoffset) | |
6475 | return NULL; | |
6476 | offset += newoffset; | |
6477 | if (!nv_cksum(&bios->data[offset], EDID1_LEN)) | |
6478 | break; | |
6479 | ||
6480 | searchlen -= offset; | |
6481 | offset++; | |
6482 | } | |
6483 | ||
6484 | NV_TRACE(dev, "Found EDID in BIOS\n"); | |
6485 | ||
6486 | return bios->fp.edid = &bios->data[offset]; | |
6487 | } | |
6488 | ||
6489 | void | |
6490 | nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, | |
6491 | struct dcb_entry *dcbent) | |
6492 | { | |
6493 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 6494 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
6495 | struct init_exec iexec = { true, false }; |
6496 | ||
d9184fa9 | 6497 | mutex_lock(&bios->lock); |
6ee73861 BS |
6498 | bios->display.output = dcbent; |
6499 | parse_init_table(bios, table, &iexec); | |
6500 | bios->display.output = NULL; | |
d9184fa9 | 6501 | mutex_unlock(&bios->lock); |
6ee73861 BS |
6502 | } |
6503 | ||
6504 | static bool NVInitVBIOS(struct drm_device *dev) | |
6505 | { | |
6506 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 6507 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
6508 | |
6509 | memset(bios, 0, sizeof(struct nvbios)); | |
d9184fa9 | 6510 | mutex_init(&bios->lock); |
6ee73861 BS |
6511 | bios->dev = dev; |
6512 | ||
6513 | if (!NVShadowVBIOS(dev, bios->data)) | |
6514 | return false; | |
6515 | ||
6516 | bios->length = NV_PROM_SIZE; | |
6517 | return true; | |
6518 | } | |
6519 | ||
6520 | static int nouveau_parse_vbios_struct(struct drm_device *dev) | |
6521 | { | |
6522 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 6523 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
6524 | const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; |
6525 | const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; | |
6526 | int offset; | |
6527 | ||
6528 | offset = findstr(bios->data, bios->length, | |
6529 | bit_signature, sizeof(bit_signature)); | |
6530 | if (offset) { | |
6531 | NV_TRACE(dev, "BIT BIOS found\n"); | |
6532 | return parse_bit_structure(bios, offset + 6); | |
6533 | } | |
6534 | ||
6535 | offset = findstr(bios->data, bios->length, | |
6536 | bmp_signature, sizeof(bmp_signature)); | |
6537 | if (offset) { | |
6538 | NV_TRACE(dev, "BMP BIOS found\n"); | |
6539 | return parse_bmp_structure(dev, bios, offset); | |
6540 | } | |
6541 | ||
6542 | NV_ERROR(dev, "No known BIOS signature found\n"); | |
6543 | return -ENODEV; | |
6544 | } | |
6545 | ||
6546 | int | |
6547 | nouveau_run_vbios_init(struct drm_device *dev) | |
6548 | { | |
6549 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 6550 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
6551 | int i, ret = 0; |
6552 | ||
946fd35f FJ |
6553 | /* Reset the BIOS head to 0. */ |
6554 | bios->state.crtchead = 0; | |
6ee73861 BS |
6555 | |
6556 | if (bios->major_version < 5) /* BMP only */ | |
6557 | load_nv17_hw_sequencer_ucode(dev, bios); | |
6558 | ||
6559 | if (bios->execute) { | |
6560 | bios->fp.last_script_invoc = 0; | |
6561 | bios->fp.lvds_init_run = false; | |
6562 | } | |
6563 | ||
6564 | parse_init_tables(bios); | |
6565 | ||
6566 | /* | |
6567 | * Runs some additional script seen on G8x VBIOSen. The VBIOS' | |
6568 | * parser will run this right after the init tables, the binary | |
6569 | * driver appears to run it at some point later. | |
6570 | */ | |
6571 | if (bios->some_script_ptr) { | |
6572 | struct init_exec iexec = {true, false}; | |
6573 | ||
6574 | NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", | |
6575 | bios->some_script_ptr); | |
6576 | parse_init_table(bios, bios->some_script_ptr, &iexec); | |
6577 | } | |
6578 | ||
6579 | if (dev_priv->card_type >= NV_50) { | |
7f245b20 | 6580 | for (i = 0; i < bios->dcb.entries; i++) { |
6ee73861 | 6581 | nouveau_bios_run_display_table(dev, |
7f245b20 | 6582 | &bios->dcb.entry[i], |
6ee73861 BS |
6583 | 0, 0); |
6584 | } | |
6585 | } | |
6586 | ||
6ee73861 BS |
6587 | return ret; |
6588 | } | |
6589 | ||
6590 | static void | |
6591 | nouveau_bios_i2c_devices_takedown(struct drm_device *dev) | |
6592 | { | |
6593 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 6594 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
6595 | struct dcb_i2c_entry *entry; |
6596 | int i; | |
6597 | ||
7f245b20 | 6598 | entry = &bios->dcb.i2c[0]; |
6ee73861 BS |
6599 | for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) |
6600 | nouveau_i2c_fini(dev, entry); | |
6601 | } | |
6602 | ||
d13102c6 BS |
6603 | static bool |
6604 | nouveau_bios_posted(struct drm_device *dev) | |
6605 | { | |
6606 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
d13102c6 BS |
6607 | unsigned htotal; |
6608 | ||
6609 | if (dev_priv->chipset >= NV_50) { | |
6610 | if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && | |
6611 | NVReadVgaCrtc(dev, 0, 0x1a) == 0) | |
6612 | return false; | |
6613 | return true; | |
6614 | } | |
6615 | ||
d13102c6 BS |
6616 | htotal = NVReadVgaCrtc(dev, 0, 0x06); |
6617 | htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; | |
6618 | htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; | |
6619 | htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; | |
6620 | htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; | |
03cd06ca | 6621 | |
d13102c6 BS |
6622 | return (htotal != 0); |
6623 | } | |
6624 | ||
6ee73861 BS |
6625 | int |
6626 | nouveau_bios_init(struct drm_device *dev) | |
6627 | { | |
6628 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
04a39c57 | 6629 | struct nvbios *bios = &dev_priv->vbios; |
6ee73861 BS |
6630 | int ret; |
6631 | ||
6ee73861 BS |
6632 | if (!NVInitVBIOS(dev)) |
6633 | return -ENODEV; | |
6634 | ||
6635 | ret = nouveau_parse_vbios_struct(dev); | |
6636 | if (ret) | |
6637 | return ret; | |
6638 | ||
6639 | ret = parse_dcb_table(dev, bios, nv_two_heads(dev)); | |
6640 | if (ret) | |
6641 | return ret; | |
6642 | ||
6643 | fixup_legacy_i2c(bios); | |
6644 | fixup_legacy_connector(bios); | |
6645 | ||
6646 | if (!bios->major_version) /* we don't run version 0 bios */ | |
6647 | return 0; | |
6648 | ||
6ee73861 BS |
6649 | /* init script execution disabled */ |
6650 | bios->execute = false; | |
6651 | ||
6652 | /* ... unless card isn't POSTed already */ | |
d13102c6 | 6653 | if (!nouveau_bios_posted(dev)) { |
67eda20e FJ |
6654 | NV_INFO(dev, "Adaptor not initialised, " |
6655 | "running VBIOS init tables.\n"); | |
6ee73861 BS |
6656 | bios->execute = true; |
6657 | } | |
6658 | ||
6ee73861 | 6659 | ret = nouveau_run_vbios_init(dev); |
04a39c57 | 6660 | if (ret) |
6ee73861 | 6661 | return ret; |
6ee73861 BS |
6662 | |
6663 | /* feature_byte on BMP is poor, but init always sets CR4B */ | |
6ee73861 BS |
6664 | if (bios->major_version < 5) |
6665 | bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; | |
6666 | ||
6667 | /* all BIT systems need p_f_m_t for digital_min_front_porch */ | |
6668 | if (bios->is_mobile || bios->major_version >= 5) | |
6669 | ret = parse_fp_mode_table(dev, bios); | |
6ee73861 BS |
6670 | |
6671 | /* allow subsequent scripts to execute */ | |
6672 | bios->execute = true; | |
6673 | ||
6674 | return 0; | |
6675 | } | |
6676 | ||
6677 | void | |
6678 | nouveau_bios_takedown(struct drm_device *dev) | |
6679 | { | |
6680 | nouveau_bios_i2c_devices_takedown(dev); | |
6681 | } |