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drm/nouveau: Fix noaccel/nofbaccel option descriptions.
[net-next-2.6.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
29
30/* these defines are made up */
31#define NV_CIO_CRE_44_HEADA 0x0
32#define NV_CIO_CRE_44_HEADB 0x3
33#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
34#define LEGACY_I2C_CRT 0x80
35#define LEGACY_I2C_PANEL 0x81
36#define LEGACY_I2C_TV 0x82
37
38#define EDID1_LEN 128
39
40#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
41#define LOG_OLD_VALUE(x)
42
43#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
44#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
45
46struct init_exec {
47 bool execute;
48 bool repeat;
49};
50
51static bool nv_cksum(const uint8_t *data, unsigned int length)
52{
53 /*
54 * There's a few checksums in the BIOS, so here's a generic checking
55 * function.
56 */
57 int i;
58 uint8_t sum = 0;
59
60 for (i = 0; i < length; i++)
61 sum += data[i];
62
63 if (sum)
64 return true;
65
66 return false;
67}
68
69static int
70score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
71{
72 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
73 NV_TRACEWARN(dev, "... BIOS signature not found\n");
74 return 0;
75 }
76
77 if (nv_cksum(data, data[2] * 512)) {
78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable ? 2 : 1;
81 } else
82 NV_TRACE(dev, "... appears to be valid\n");
83
84 return 3;
85}
86
87static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
88{
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 uint32_t pci_nv_20, save_pci_nv_20;
91 int pcir_ptr;
92 int i;
93
94 if (dev_priv->card_type >= NV_50)
95 pci_nv_20 = 0x88050;
96 else
97 pci_nv_20 = NV_PBUS_PCI_NV_20;
98
99 /* enable ROM access */
100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
101 nvWriteMC(dev, pci_nv_20,
102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
103
104 /* bail if no rom signature */
105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
107 goto out;
108
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
116 goto out;
117
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
121 */
122 for (i = 0; i < NV_PROM_SIZE; i++)
123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
124
125out:
126 /* disable ROM access */
127 nvWriteMC(dev, pci_nv_20,
128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
129}
130
131static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
132{
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 uint32_t old_bar0_pramin = 0;
135 int i;
136
137 if (dev_priv->card_type >= NV_50) {
138 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
139
140 if (!vbios_vram)
141 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
142
143 old_bar0_pramin = nv_rd32(dev, 0x1700);
144 nv_wr32(dev, 0x1700, vbios_vram >> 16);
145 }
146
147 /* bail if no rom signature */
148 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
149 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
150 goto out;
151
152 for (i = 0; i < NV_PROM_SIZE; i++)
153 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
154
155out:
156 if (dev_priv->card_type >= NV_50)
157 nv_wr32(dev, 0x1700, old_bar0_pramin);
158}
159
160static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
161{
162 void __iomem *rom = NULL;
163 size_t rom_len;
164 int ret;
165
166 ret = pci_enable_rom(dev->pdev);
167 if (ret)
168 return;
169
170 rom = pci_map_rom(dev->pdev, &rom_len);
171 if (!rom)
172 goto out;
173 memcpy_fromio(data, rom, rom_len);
174 pci_unmap_rom(dev->pdev, rom);
175
176out:
177 pci_disable_rom(dev->pdev);
178}
179
180struct methods {
181 const char desc[8];
182 void (*loadbios)(struct drm_device *, uint8_t *);
183 const bool rw;
6ee73861
BS		 184};
185
186static struct methods nv04_methods[] = {
187 { "PROM", load_vbios_prom, false },
188 { "PRAMIN", load_vbios_pramin, true },
189 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 190};
191
192static struct methods nv50_methods[] = {
193 { "PRAMIN", load_vbios_pramin, true },
194 { "PROM", load_vbios_prom, false },
195 { "PCIROM", load_vbios_pci, true },
6ee73861
BS		 196};
197
657b6245
MK		 198#define METHODCNT 3
199
6ee73861
BS		 200static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
201{
202 struct drm_nouveau_private *dev_priv = dev->dev_private;
657b6245
MK		 203 struct methods *methods;
204 int i;
6ee73861 205 int testscore = 3;
657b6245 206 int scores[METHODCNT];
6ee73861
BS		 207
208 if (nouveau_vbios) {
657b6245
MK		 209 methods = nv04_methods;
210 for (i = 0; i < METHODCNT; i++)
211 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 212 break;
6ee73861 213
657b6245 214 if (i < METHODCNT) {
6ee73861 215 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 216 methods[i].desc);
6ee73861 217
657b6245
MK		 218 methods[i].loadbios(dev, data);
219 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 220 return true;
221 }
222
223 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
224 }
225
226 if (dev_priv->card_type < NV_50)
227 methods = nv04_methods;
228 else
229 methods = nv50_methods;
230
657b6245 231 for (i = 0; i < METHODCNT; i++) {
6ee73861 232 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 233 methods[i].desc);
6ee73861 234 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 235 methods[i].loadbios(dev, data);
236 scores[i] = score_vbios(dev, data, methods[i].rw);
237 if (scores[i] == testscore)
6ee73861 238 return true;
6ee73861
BS		 239 }
240
241 while (--testscore > 0) {
657b6245
MK		 242 for (i = 0; i < METHODCNT; i++) {
243 if (scores[i] == testscore) {
6ee73861 244 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 245 methods[i].desc);
246 methods[i].loadbios(dev, data);
6ee73861
BS		 247 return true;
248 }
6ee73861
BS		 249 }
250 }
251
252 NV_ERROR(dev, "No valid BIOS image found\n");
253 return false;
254}
255
256struct init_tbl_entry {
257 char *name;
258 uint8_t id;
37383650 259 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 260};
261
262struct bit_entry {
263 uint8_t id[2];
264 uint16_t length;
265 uint16_t offset;
266};
267
268static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *);
269
270#define MACRO_INDEX_SIZE 2
271#define MACRO_SIZE 8
272#define CONDITION_SIZE 12
273#define IO_FLAG_CONDITION_SIZE 9
274#define IO_CONDITION_SIZE 5
275#define MEM_INIT_SIZE 66
276
277static void still_alive(void)
278{
279#if 0
280 sync();
281 msleep(2);
282#endif
283}
284
285static uint32_t
286munge_reg(struct nvbios *bios, uint32_t reg)
287{
288 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
289 struct dcb_entry *dcbent = bios->display.output;
290
291 if (dev_priv->card_type < NV_50)
292 return reg;
293
294 if (reg & 0x40000000) {
295 BUG_ON(!dcbent);
296
297 reg += (ffs(dcbent->or) - 1) * 0x800;
298 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
299 reg += 0x00000080;
300 }
301
302 reg &= ~0x60000000;
303 return reg;
304}
305
306static int
307valid_reg(struct nvbios *bios, uint32_t reg)
308{
309 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
310 struct drm_device *dev = bios->dev;
311
312 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 313 if (reg & 0x2 ||
04a39c57 314 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 315 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
316
317 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 318 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 319 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
320 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
321 reg);
322
9855e584
BS		 323 if (reg >= (8*1024*1024)) {
324 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
325 return 0;
6ee73861 326 }
9855e584
BS		 327
328 return 1;
6ee73861
BS		 329}
330
331static bool
332valid_idx_port(struct nvbios *bios, uint16_t port)
333{
334 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
335 struct drm_device *dev = bios->dev;
336
337 /*
338 * If adding more ports here, the read/write functions below will need
339 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
340 * used for the port in question
341 */
342 if (dev_priv->card_type < NV_50) {
343 if (port == NV_CIO_CRX__COLOR)
344 return true;
345 if (port == NV_VIO_SRX)
346 return true;
347 } else {
348 if (port == NV_CIO_CRX__COLOR)
349 return true;
350 }
351
352 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
353 port);
354
355 return false;
356}
357
358static bool
359valid_port(struct nvbios *bios, uint16_t port)
360{
361 struct drm_device *dev = bios->dev;
362
363 /*
364 * If adding more ports here, the read/write functions below will need
365 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
366 * used for the port in question
367 */
368 if (port == NV_VIO_VSE2)
369 return true;
370
371 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
372
373 return false;
374}
375
376static uint32_t
377bios_rd32(struct nvbios *bios, uint32_t reg)
378{
379 uint32_t data;
380
381 reg = munge_reg(bios, reg);
382 if (!valid_reg(bios, reg))
383 return 0;
384
385 /*
386 * C51 sometimes uses regs with bit0 set in the address. For these
387 * cases there should exist a translation in a BIOS table to an IO
388 * port address which the BIOS uses for accessing the reg
389 *
390 * These only seem to appear for the power control regs to a flat panel,
391 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
392 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
393 * suspend-resume mmio trace from a C51 will be required to see if this
394 * is true for the power microcode in 0x14.., or whether the direct IO
395 * port access method is needed
396 */
397 if (reg & 0x1)
398 reg &= ~0x1;
399
400 data = nv_rd32(bios->dev, reg);
401
402 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
403
404 return data;
405}
406
407static void
408bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
409{
410 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
411
412 reg = munge_reg(bios, reg);
413 if (!valid_reg(bios, reg))
414 return;
415
416 /* see note in bios_rd32 */
417 if (reg & 0x1)
418 reg &= 0xfffffffe;
419
420 LOG_OLD_VALUE(bios_rd32(bios, reg));
421 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
422
04a39c57 423 if (dev_priv->vbios.execute) {
6ee73861
BS		 424 still_alive();
425 nv_wr32(bios->dev, reg, data);
426 }
427}
428
429static uint8_t
430bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
431{
432 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
433 struct drm_device *dev = bios->dev;
434 uint8_t data;
435
436 if (!valid_idx_port(bios, port))
437 return 0;
438
439 if (dev_priv->card_type < NV_50) {
440 if (port == NV_VIO_SRX)
441 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
442 else /* assume NV_CIO_CRX__COLOR */
443 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
444 } else {
445 uint32_t data32;
446
447 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
448 data = (data32 >> ((index & 3) << 3)) & 0xff;
449 }
450
451 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
452 "Head: 0x%02X, Data: 0x%02X\n",
453 port, index, bios->state.crtchead, data);
454 return data;
455}
456
457static void
458bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
459{
460 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
461 struct drm_device *dev = bios->dev;
462
463 if (!valid_idx_port(bios, port))
464 return;
465
466 /*
467 * The current head is maintained in the nvbios member state.crtchead.
468 * We trap changes to CR44 and update the head variable and hence the
469 * register set written.
470 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
471 * of the write, and to head1 after the write
472 */
473 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
474 data != NV_CIO_CRE_44_HEADB)
475 bios->state.crtchead = 0;
476
477 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
478 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
479 "Head: 0x%02X, Data: 0x%02X\n",
480 port, index, bios->state.crtchead, data);
481
482 if (bios->execute && dev_priv->card_type < NV_50) {
483 still_alive();
484 if (port == NV_VIO_SRX)
485 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
486 else /* assume NV_CIO_CRX__COLOR */
487 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
488 } else
489 if (bios->execute) {
490 uint32_t data32, shift = (index & 3) << 3;
491
492 still_alive();
493
494 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
495 data32 &= ~(0xff << shift);
496 data32 |= (data << shift);
497 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
498 }
499
500 if (port == NV_CIO_CRX__COLOR &&
501 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
502 bios->state.crtchead = 1;
503}
504
505static uint8_t
506bios_port_rd(struct nvbios *bios, uint16_t port)
507{
508 uint8_t data, head = bios->state.crtchead;
509
510 if (!valid_port(bios, port))
511 return 0;
512
513 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
514
515 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
516 port, head, data);
517
518 return data;
519}
520
521static void
522bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
523{
524 int head = bios->state.crtchead;
525
526 if (!valid_port(bios, port))
527 return;
528
529 LOG_OLD_VALUE(bios_port_rd(bios, port));
530 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
531 port, head, data);
532
533 if (!bios->execute)
534 return;
535
536 still_alive();
537 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
538}
539
540static bool
541io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
542{
543 /*
544 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
545 * for the CRTC index; 1 byte for the mask to apply to the value
546 * retrieved from the CRTC; 1 byte for the shift right to apply to the
547 * masked CRTC value; 2 bytes for the offset to the flag array, to
548 * which the shifted value is added; 1 byte for the mask applied to the
549 * value read from the flag array; and 1 byte for the value to compare
550 * against the masked byte from the flag table.
551 */
552
553 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
554 uint16_t crtcport = ROM16(bios->data[condptr]);
555 uint8_t crtcindex = bios->data[condptr + 2];
556 uint8_t mask = bios->data[condptr + 3];
557 uint8_t shift = bios->data[condptr + 4];
558 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
559 uint8_t flagarraymask = bios->data[condptr + 7];
560 uint8_t cmpval = bios->data[condptr + 8];
561 uint8_t data;
562
563 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
564 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
565 "Cmpval: 0x%02X\n",
566 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
567
568 data = bios_idxprt_rd(bios, crtcport, crtcindex);
569
570 data = bios->data[flagarray + ((data & mask) >> shift)];
571 data &= flagarraymask;
572
573 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
574 offset, data, cmpval);
575
576 return (data == cmpval);
577}
578
579static bool
580bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
581{
582 /*
583 * The condition table entry has 4 bytes for the address of the
584 * register to check, 4 bytes for a mask to apply to the register and
585 * 4 for a test comparison value
586 */
587
588 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
589 uint32_t reg = ROM32(bios->data[condptr]);
590 uint32_t mask = ROM32(bios->data[condptr + 4]);
591 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
592 uint32_t data;
593
594 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
595 offset, cond, reg, mask);
596
597 data = bios_rd32(bios, reg) & mask;
598
599 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
600 offset, data, cmpval);
601
602 return (data == cmpval);
603}
604
605static bool
606io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
607{
608 /*
609 * The IO condition entry has 2 bytes for the IO port address; 1 byte
610 * for the index to write to io_port; 1 byte for the mask to apply to
611 * the byte read from io_port+1; and 1 byte for the value to compare
612 * against the masked byte.
613 */
614
615 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
616 uint16_t io_port = ROM16(bios->data[condptr]);
617 uint8_t port_index = bios->data[condptr + 2];
618 uint8_t mask = bios->data[condptr + 3];
619 uint8_t cmpval = bios->data[condptr + 4];
620
621 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
622
623 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
624 offset, data, cmpval);
625
626 return (data == cmpval);
627}
628
629static int
630nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
631{
632 struct drm_nouveau_private *dev_priv = dev->dev_private;
633 uint32_t reg0 = nv_rd32(dev, reg + 0);
634 uint32_t reg1 = nv_rd32(dev, reg + 4);
635 struct nouveau_pll_vals pll;
636 struct pll_lims pll_limits;
637 int ret;
638
639 ret = get_pll_limits(dev, reg, &pll_limits);
640 if (ret)
641 return ret;
642
643 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
644 if (!clk)
645 return -ERANGE;
646
647 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
648 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
649
04a39c57 650 if (dev_priv->vbios.execute) {
6ee73861
BS		 651 still_alive();
652 nv_wr32(dev, reg + 4, reg1);
653 nv_wr32(dev, reg + 0, reg0);
654 }
655
656 return 0;
657}
658
659static int
660setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
661{
662 struct drm_device *dev = bios->dev;
663 struct drm_nouveau_private *dev_priv = dev->dev_private;
664 /* clk in kHz */
665 struct pll_lims pll_lim;
666 struct nouveau_pll_vals pllvals;
667 int ret;
668
669 if (dev_priv->card_type >= NV_50)
670 return nv50_pll_set(dev, reg, clk);
671
672 /* high regs (such as in the mac g5 table) are not -= 4 */
673 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
674 if (ret)
675 return ret;
676
677 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
678 if (!clk)
679 return -ERANGE;
680
681 if (bios->execute) {
682 still_alive();
683 nouveau_hw_setpll(dev, reg, &pllvals);
684 }
685
686 return 0;
687}
688
689static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
690{
691 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 692 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 693
694 /*
695 * For the results of this function to be correct, CR44 must have been
696 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
697 * and the DCB table parsed, before the script calling the function is
698 * run. run_digital_op_script is example of how to do such setup
699 */
700
701 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
702
7f245b20 703 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 704 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
705 "(%02X)\n", dcb_entry);
706 dcb_entry = 0x7f; /* unused / invalid marker */
707 }
708
709 return dcb_entry;
710}
711
712static struct nouveau_i2c_chan *
713init_i2c_device_find(struct drm_device *dev, int i2c_index)
714{
715 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 716 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 717
718 if (i2c_index == 0xff) {
719 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
720 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 721 int default_indices = dcb->i2c_default_indices;
6ee73861 722
7f245b20 723 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 724 shift = 4;
725
726 i2c_index = (default_indices >> shift) & 0xf;
727 }
728 if (i2c_index == 0x80) /* g80+ */
7f245b20 729 i2c_index = dcb->i2c_default_indices & 0xf;
6ee73861
BS		 730
731 return nouveau_i2c_find(dev, i2c_index);
732}
733
7f245b20
BS		 734static uint32_t
735get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 736{
737 /*
738 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
739 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
740 * CR58 for CR57 = 0 to index a table of offsets to the basic
741 * 0x6808b0 address.
742 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
743 * CR58 for CR57 = 0 to index a table of offsets to the basic
744 * 0x6808b0 address, and then flip the offset by 8.
745 */
746
747 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 748 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 749 const int pramdac_offset[13] = {
750 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
751 const uint32_t pramdac_table[4] = {
752 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
753
754 if (mlv >= 0x80) {
755 int dcb_entry, dacoffset;
756
757 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
758 dcb_entry = dcb_entry_idx_from_crtchead(dev);
759 if (dcb_entry == 0x7f)
760 return 0;
7f245b20 761 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 762 if (mlv == 0x81)
763 dacoffset ^= 8;
764 return 0x6808b0 + dacoffset;
765 } else {
df31ef4d 766 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 767 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
768 mlv);
769 return 0;
770 }
771 return pramdac_table[mlv];
772 }
773}
774
37383650 775static int
6ee73861
BS		 776init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
777 struct init_exec *iexec)
778{
779 /*
780 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
781 *
782 * offset (8 bit): opcode
783 * offset + 1 (16 bit): CRTC port
784 * offset + 3 (8 bit): CRTC index
785 * offset + 4 (8 bit): mask
786 * offset + 5 (8 bit): shift
787 * offset + 6 (8 bit): count
788 * offset + 7 (32 bit): register
789 * offset + 11 (32 bit): configuration 1
790 * ...
791 *
792 * Starting at offset + 11 there are "count" 32 bit values.
793 * To find out which value to use read index "CRTC index" on "CRTC
794 * port", AND this value with "mask" and then bit shift right "shift"
795 * bits. Read the appropriate value using this index and write to
796 * "register"
797 */
798
799 uint16_t crtcport = ROM16(bios->data[offset + 1]);
800 uint8_t crtcindex = bios->data[offset + 3];
801 uint8_t mask = bios->data[offset + 4];
802 uint8_t shift = bios->data[offset + 5];
803 uint8_t count = bios->data[offset + 6];
804 uint32_t reg = ROM32(bios->data[offset + 7]);
805 uint8_t config;
806 uint32_t configval;
37383650 807 int len = 11 + count * 4;
6ee73861
BS		 808
809 if (!iexec->execute)
37383650 810 return len;
6ee73861
BS		 811
812 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
813 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
814 offset, crtcport, crtcindex, mask, shift, count, reg);
815
816 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
817 if (config > count) {
818 NV_ERROR(bios->dev,
819 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
820 offset, config, count);
37383650 821 return 0;
6ee73861
BS		 822 }
823
824 configval = ROM32(bios->data[offset + 11 + config * 4]);
825
826 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
827
828 bios_wr32(bios, reg, configval);
829
37383650 830 return len;
6ee73861
BS		 831}
832
37383650 833static int
6ee73861
BS		 834init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
835{
836 /*
837 * INIT_REPEAT opcode: 0x33 ('3')
838 *
839 * offset (8 bit): opcode
840 * offset + 1 (8 bit): count
841 *
842 * Execute script following this opcode up to INIT_REPEAT_END
843 * "count" times
844 */
845
846 uint8_t count = bios->data[offset + 1];
847 uint8_t i;
848
849 /* no iexec->execute check by design */
850
851 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
852 offset, count);
853
854 iexec->repeat = true;
855
856 /*
857 * count - 1, as the script block will execute once when we leave this
858 * opcode -- this is compatible with bios behaviour as:
859 * a) the block is always executed at least once, even if count == 0
860 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
861 * while we don't
862 */
863 for (i = 0; i < count - 1; i++)
864 parse_init_table(bios, offset + 2, iexec);
865
866 iexec->repeat = false;
867
37383650 868 return 2;
6ee73861
BS		 869}
870
37383650 871static int
6ee73861
BS		 872init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
873 struct init_exec *iexec)
874{
875 /*
876 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
877 *
878 * offset (8 bit): opcode
879 * offset + 1 (16 bit): CRTC port
880 * offset + 3 (8 bit): CRTC index
881 * offset + 4 (8 bit): mask
882 * offset + 5 (8 bit): shift
883 * offset + 6 (8 bit): IO flag condition index
884 * offset + 7 (8 bit): count
885 * offset + 8 (32 bit): register
886 * offset + 12 (16 bit): frequency 1
887 * ...
888 *
889 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
890 * Set PLL register "register" to coefficients for frequency n,
891 * selected by reading index "CRTC index" of "CRTC port" ANDed with
892 * "mask" and shifted right by "shift".
893 *
894 * If "IO flag condition index" > 0, and condition met, double
895 * frequency before setting it.
896 */
897
898 uint16_t crtcport = ROM16(bios->data[offset + 1]);
899 uint8_t crtcindex = bios->data[offset + 3];
900 uint8_t mask = bios->data[offset + 4];
901 uint8_t shift = bios->data[offset + 5];
902 int8_t io_flag_condition_idx = bios->data[offset + 6];
903 uint8_t count = bios->data[offset + 7];
904 uint32_t reg = ROM32(bios->data[offset + 8]);
905 uint8_t config;
906 uint16_t freq;
37383650 907 int len = 12 + count * 2;
6ee73861
BS		 908
909 if (!iexec->execute)
37383650 910 return len;
6ee73861
BS		 911
912 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
913 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
914 "Count: 0x%02X, Reg: 0x%08X\n",
915 offset, crtcport, crtcindex, mask, shift,
916 io_flag_condition_idx, count, reg);
917
918 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
919 if (config > count) {
920 NV_ERROR(bios->dev,
921 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
922 offset, config, count);
37383650 923 return 0;
6ee73861
BS		 924 }
925
926 freq = ROM16(bios->data[offset + 12 + config * 2]);
927
928 if (io_flag_condition_idx > 0) {
929 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
930 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
931 "frequency doubled\n", offset);
932 freq *= 2;
933 } else
934 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
935 "frequency unchanged\n", offset);
936 }
937
938 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
939 offset, reg, config, freq);
940
941 setPLL(bios, reg, freq * 10);
942
37383650 943 return len;
6ee73861
BS		 944}
945
37383650 946static int
6ee73861
BS		 947init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
948{
949 /*
950 * INIT_END_REPEAT opcode: 0x36 ('6')
951 *
952 * offset (8 bit): opcode
953 *
954 * Marks the end of the block for INIT_REPEAT to repeat
955 */
956
957 /* no iexec->execute check by design */
958
959 /*
960 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
961 * we're not in repeat mode
962 */
963 if (iexec->repeat)
37383650 964 return 0;
6ee73861 965
37383650 966 return 1;
6ee73861
BS		 967}
968
37383650 969static int
6ee73861
BS		 970init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
971{
972 /*
973 * INIT_COPY opcode: 0x37 ('7')
974 *
975 * offset (8 bit): opcode
976 * offset + 1 (32 bit): register
977 * offset + 5 (8 bit): shift
978 * offset + 6 (8 bit): srcmask
979 * offset + 7 (16 bit): CRTC port
980 * offset + 9 (8 bit): CRTC index
981 * offset + 10 (8 bit): mask
982 *
983 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
984 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
985 * port
986 */
987
988 uint32_t reg = ROM32(bios->data[offset + 1]);
989 uint8_t shift = bios->data[offset + 5];
990 uint8_t srcmask = bios->data[offset + 6];
991 uint16_t crtcport = ROM16(bios->data[offset + 7]);
992 uint8_t crtcindex = bios->data[offset + 9];
993 uint8_t mask = bios->data[offset + 10];
994 uint32_t data;
995 uint8_t crtcdata;
996
997 if (!iexec->execute)
37383650 998 return 11;
6ee73861
BS		 999
1000 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1001 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1002 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1003
1004 data = bios_rd32(bios, reg);
1005
1006 if (shift < 0x80)
1007 data >>= shift;
1008 else
1009 data <<= (0x100 - shift);
1010
1011 data &= srcmask;
1012
1013 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1014 crtcdata |= (uint8_t)data;
1015 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1016
37383650 1017 return 11;
6ee73861
BS		 1018}
1019
37383650 1020static int
6ee73861
BS		 1021init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1022{
1023 /*
1024 * INIT_NOT opcode: 0x38 ('8')
1025 *
1026 * offset (8 bit): opcode
1027 *
1028 * Invert the current execute / no-execute condition (i.e. "else")
1029 */
1030 if (iexec->execute)
1031 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1032 else
1033 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1034
1035 iexec->execute = !iexec->execute;
37383650 1036 return 1;
6ee73861
BS		 1037}
1038
37383650 1039static int
6ee73861
BS		 1040init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1041 struct init_exec *iexec)
1042{
1043 /*
1044 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1045 *
1046 * offset (8 bit): opcode
1047 * offset + 1 (8 bit): condition number
1048 *
1049 * Check condition "condition number" in the IO flag condition table.
1050 * If condition not met skip subsequent opcodes until condition is
1051 * inverted (INIT_NOT), or we hit INIT_RESUME
1052 */
1053
1054 uint8_t cond = bios->data[offset + 1];
1055
1056 if (!iexec->execute)
37383650 1057 return 2;
6ee73861
BS		 1058
1059 if (io_flag_condition_met(bios, offset, cond))
1060 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1061 else {
1062 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1063 iexec->execute = false;
1064 }
1065
37383650 1066 return 2;
6ee73861
BS		 1067}
1068
37383650 1069static int
6ee73861
BS		 1070init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1071 struct init_exec *iexec)
1072{
1073 /*
1074 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1075 *
1076 * offset (8 bit): opcode
1077 * offset + 1 (32 bit): control register
1078 * offset + 5 (32 bit): data register
1079 * offset + 9 (32 bit): mask
1080 * offset + 13 (32 bit): data
1081 * offset + 17 (8 bit): count
1082 * offset + 18 (8 bit): address 1
1083 * offset + 19 (8 bit): data 1
1084 * ...
1085 *
1086 * For each of "count" address and data pairs, write "data n" to
1087 * "data register", read the current value of "control register",
1088 * and write it back once ANDed with "mask", ORed with "data",
1089 * and ORed with "address n"
1090 */
1091
1092 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1093 uint32_t datareg = ROM32(bios->data[offset + 5]);
1094 uint32_t mask = ROM32(bios->data[offset + 9]);
1095 uint32_t data = ROM32(bios->data[offset + 13]);
1096 uint8_t count = bios->data[offset + 17];
37383650 1097 int len = 18 + count * 2;
6ee73861
BS		 1098 uint32_t value;
1099 int i;
1100
1101 if (!iexec->execute)
37383650 1102 return len;
6ee73861
BS		 1103
1104 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1105 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1106 offset, controlreg, datareg, mask, data, count);
1107
1108 for (i = 0; i < count; i++) {
1109 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1110 uint8_t instdata = bios->data[offset + 19 + i * 2];
1111
1112 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1113 offset, instaddress, instdata);
1114
1115 bios_wr32(bios, datareg, instdata);
1116 value = bios_rd32(bios, controlreg) & mask;
1117 value |= data;
1118 value |= instaddress;
1119 bios_wr32(bios, controlreg, value);
1120 }
1121
37383650 1122 return len;
6ee73861
BS		 1123}
1124
37383650 1125static int
6ee73861
BS		 1126init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1127 struct init_exec *iexec)
1128{
1129 /*
1130 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1131 *
1132 * offset (8 bit): opcode
1133 * offset + 1 (16 bit): CRTC port
1134 * offset + 3 (8 bit): CRTC index
1135 * offset + 4 (8 bit): mask
1136 * offset + 5 (8 bit): shift
1137 * offset + 6 (8 bit): count
1138 * offset + 7 (32 bit): register
1139 * offset + 11 (32 bit): frequency 1
1140 * ...
1141 *
1142 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1143 * Set PLL register "register" to coefficients for frequency n,
1144 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1145 * "mask" and shifted right by "shift".
1146 */
1147
1148 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1149 uint8_t crtcindex = bios->data[offset + 3];
1150 uint8_t mask = bios->data[offset + 4];
1151 uint8_t shift = bios->data[offset + 5];
1152 uint8_t count = bios->data[offset + 6];
1153 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1154 int len = 11 + count * 4;
6ee73861
BS		 1155 uint8_t config;
1156 uint32_t freq;
1157
1158 if (!iexec->execute)
37383650 1159 return len;
6ee73861
BS		 1160
1161 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1162 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1163 offset, crtcport, crtcindex, mask, shift, count, reg);
1164
1165 if (!reg)
37383650 1166 return len;
6ee73861
BS		 1167
1168 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1169 if (config > count) {
1170 NV_ERROR(bios->dev,
1171 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1172 offset, config, count);
37383650 1173 return 0;
6ee73861
BS		 1174 }
1175
1176 freq = ROM32(bios->data[offset + 11 + config * 4]);
1177
1178 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1179 offset, reg, config, freq);
1180
1181 setPLL(bios, reg, freq);
1182
37383650 1183 return len;
6ee73861
BS		 1184}
1185
37383650 1186static int
6ee73861
BS		 1187init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1188{
1189 /*
1190 * INIT_PLL2 opcode: 0x4B ('K')
1191 *
1192 * offset (8 bit): opcode
1193 * offset + 1 (32 bit): register
1194 * offset + 5 (32 bit): freq
1195 *
1196 * Set PLL register "register" to coefficients for frequency "freq"
1197 */
1198
1199 uint32_t reg = ROM32(bios->data[offset + 1]);
1200 uint32_t freq = ROM32(bios->data[offset + 5]);
1201
1202 if (!iexec->execute)
37383650 1203 return 9;
6ee73861
BS		 1204
1205 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1206 offset, reg, freq);
1207
1208 setPLL(bios, reg, freq);
37383650 1209 return 9;
6ee73861
BS		 1210}
1211
37383650 1212static int
6ee73861
BS		 1213init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1214{
1215 /*
1216 * INIT_I2C_BYTE opcode: 0x4C ('L')
1217 *
1218 * offset (8 bit): opcode
1219 * offset + 1 (8 bit): DCB I2C table entry index
1220 * offset + 2 (8 bit): I2C slave address
1221 * offset + 3 (8 bit): count
1222 * offset + 4 (8 bit): I2C register 1
1223 * offset + 5 (8 bit): mask 1
1224 * offset + 6 (8 bit): data 1
1225 * ...
1226 *
1227 * For each of "count" registers given by "I2C register n" on the device
1228 * addressed by "I2C slave address" on the I2C bus given by
1229 * "DCB I2C table entry index", read the register, AND the result with
1230 * "mask n" and OR it with "data n" before writing it back to the device
1231 */
1232
1233 uint8_t i2c_index = bios->data[offset + 1];
1234 uint8_t i2c_address = bios->data[offset + 2];
1235 uint8_t count = bios->data[offset + 3];
37383650 1236 int len = 4 + count * 3;
6ee73861
BS		 1237 struct nouveau_i2c_chan *chan;
1238 struct i2c_msg msg;
1239 int i;
1240
1241 if (!iexec->execute)
37383650 1242 return len;
6ee73861
BS		 1243
1244 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1245 "Count: 0x%02X\n",
1246 offset, i2c_index, i2c_address, count);
1247
1248 chan = init_i2c_device_find(bios->dev, i2c_index);
1249 if (!chan)
37383650 1250 return 0;
6ee73861
BS		 1251
1252 for (i = 0; i < count; i++) {
1253 uint8_t i2c_reg = bios->data[offset + 4 + i * 3];
1254 uint8_t mask = bios->data[offset + 5 + i * 3];
1255 uint8_t data = bios->data[offset + 6 + i * 3];
1256 uint8_t value;
1257
1258 msg.addr = i2c_address;
1259 msg.flags = I2C_M_RD;
1260 msg.len = 1;
1261 msg.buf = &value;
1262 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1263 return 0;
6ee73861
BS		 1264
1265 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1266 "Mask: 0x%02X, Data: 0x%02X\n",
1267 offset, i2c_reg, value, mask, data);
1268
1269 value = (value & mask) | data;
1270
1271 if (bios->execute) {
1272 msg.addr = i2c_address;
1273 msg.flags = 0;
1274 msg.len = 1;
1275 msg.buf = &value;
1276 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1277 return 0;
6ee73861
BS		 1278 }
1279 }
1280
37383650 1281 return len;
6ee73861
BS		 1282}
1283
37383650 1284static int
6ee73861
BS		 1285init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1286{
1287 /*
1288 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1289 *
1290 * offset (8 bit): opcode
1291 * offset + 1 (8 bit): DCB I2C table entry index
1292 * offset + 2 (8 bit): I2C slave address
1293 * offset + 3 (8 bit): count
1294 * offset + 4 (8 bit): I2C register 1
1295 * offset + 5 (8 bit): data 1
1296 * ...
1297 *
1298 * For each of "count" registers given by "I2C register n" on the device
1299 * addressed by "I2C slave address" on the I2C bus given by
1300 * "DCB I2C table entry index", set the register to "data n"
1301 */
1302
1303 uint8_t i2c_index = bios->data[offset + 1];
1304 uint8_t i2c_address = bios->data[offset + 2];
1305 uint8_t count = bios->data[offset + 3];
37383650 1306 int len = 4 + count * 2;
6ee73861
BS		 1307 struct nouveau_i2c_chan *chan;
1308 struct i2c_msg msg;
1309 int i;
1310
1311 if (!iexec->execute)
37383650 1312 return len;
6ee73861
BS		 1313
1314 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1315 "Count: 0x%02X\n",
1316 offset, i2c_index, i2c_address, count);
1317
1318 chan = init_i2c_device_find(bios->dev, i2c_index);
1319 if (!chan)
37383650 1320 return 0;
6ee73861
BS		 1321
1322 for (i = 0; i < count; i++) {
1323 uint8_t i2c_reg = bios->data[offset + 4 + i * 2];
1324 uint8_t data = bios->data[offset + 5 + i * 2];
1325
1326 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1327 offset, i2c_reg, data);
1328
1329 if (bios->execute) {
1330 msg.addr = i2c_address;
1331 msg.flags = 0;
1332 msg.len = 1;
1333 msg.buf = &data;
1334 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1335 return 0;
6ee73861
BS		 1336 }
1337 }
1338
37383650 1339 return len;
6ee73861
BS		 1340}
1341
37383650 1342static int
6ee73861
BS		 1343init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1344{
1345 /*
1346 * INIT_ZM_I2C opcode: 0x4E ('N')
1347 *
1348 * offset (8 bit): opcode
1349 * offset + 1 (8 bit): DCB I2C table entry index
1350 * offset + 2 (8 bit): I2C slave address
1351 * offset + 3 (8 bit): count
1352 * offset + 4 (8 bit): data 1
1353 * ...
1354 *
1355 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1356 * address" on the I2C bus given by "DCB I2C table entry index"
1357 */
1358
1359 uint8_t i2c_index = bios->data[offset + 1];
1360 uint8_t i2c_address = bios->data[offset + 2];
1361 uint8_t count = bios->data[offset + 3];
37383650 1362 int len = 4 + count;
6ee73861
BS		 1363 struct nouveau_i2c_chan *chan;
1364 struct i2c_msg msg;
1365 uint8_t data[256];
1366 int i;
1367
1368 if (!iexec->execute)
37383650 1369 return len;
6ee73861
BS		 1370
1371 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1372 "Count: 0x%02X\n",
1373 offset, i2c_index, i2c_address, count);
1374
1375 chan = init_i2c_device_find(bios->dev, i2c_index);
1376 if (!chan)
37383650 1377 return 0;
6ee73861
BS		 1378
1379 for (i = 0; i < count; i++) {
1380 data[i] = bios->data[offset + 4 + i];
1381
1382 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1383 }
1384
1385 if (bios->execute) {
1386 msg.addr = i2c_address;
1387 msg.flags = 0;
1388 msg.len = count;
1389 msg.buf = data;
1390 if (i2c_transfer(&chan->adapter, &msg, 1) != 1)
37383650 1391 return 0;
6ee73861
BS		 1392 }
1393
37383650 1394 return len;
6ee73861
BS		 1395}
1396
37383650 1397static int
6ee73861
BS		 1398init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1399{
1400 /*
1401 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1402 *
1403 * offset (8 bit): opcode
1404 * offset + 1 (8 bit): magic lookup value
1405 * offset + 2 (8 bit): TMDS address
1406 * offset + 3 (8 bit): mask
1407 * offset + 4 (8 bit): data
1408 *
1409 * Read the data reg for TMDS address "TMDS address", AND it with mask
1410 * and OR it with data, then write it back
1411 * "magic lookup value" determines which TMDS base address register is
1412 * used -- see get_tmds_index_reg()
1413 */
1414
1415 uint8_t mlv = bios->data[offset + 1];
1416 uint32_t tmdsaddr = bios->data[offset + 2];
1417 uint8_t mask = bios->data[offset + 3];
1418 uint8_t data = bios->data[offset + 4];
1419 uint32_t reg, value;
1420
1421 if (!iexec->execute)
37383650 1422 return 5;
6ee73861
BS		 1423
1424 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1425 "Mask: 0x%02X, Data: 0x%02X\n",
1426 offset, mlv, tmdsaddr, mask, data);
1427
1428 reg = get_tmds_index_reg(bios->dev, mlv);
1429 if (!reg)
37383650 1430 return 0;
6ee73861
BS		 1431
1432 bios_wr32(bios, reg,
1433 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1434 value = (bios_rd32(bios, reg + 4) & mask) | data;
1435 bios_wr32(bios, reg + 4, value);
1436 bios_wr32(bios, reg, tmdsaddr);
1437
37383650 1438 return 5;
6ee73861
BS		 1439}
1440
37383650 1441static int
6ee73861
BS		 1442init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1443 struct init_exec *iexec)
1444{
1445 /*
1446 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1447 *
1448 * offset (8 bit): opcode
1449 * offset + 1 (8 bit): magic lookup value
1450 * offset + 2 (8 bit): count
1451 * offset + 3 (8 bit): addr 1
1452 * offset + 4 (8 bit): data 1
1453 * ...
1454 *
1455 * For each of "count" TMDS address and data pairs write "data n" to
1456 * "addr n". "magic lookup value" determines which TMDS base address
1457 * register is used -- see get_tmds_index_reg()
1458 */
1459
1460 uint8_t mlv = bios->data[offset + 1];
1461 uint8_t count = bios->data[offset + 2];
37383650 1462 int len = 3 + count * 2;
6ee73861
BS		 1463 uint32_t reg;
1464 int i;
1465
1466 if (!iexec->execute)
37383650 1467 return len;
6ee73861
BS		 1468
1469 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1470 offset, mlv, count);
1471
1472 reg = get_tmds_index_reg(bios->dev, mlv);
1473 if (!reg)
37383650 1474 return 0;
6ee73861
BS		 1475
1476 for (i = 0; i < count; i++) {
1477 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1478 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1479
1480 bios_wr32(bios, reg + 4, tmdsdata);
1481 bios_wr32(bios, reg, tmdsaddr);
1482 }
1483
37383650 1484 return len;
6ee73861
BS		 1485}
1486
37383650 1487static int
6ee73861
BS		 1488init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1489 struct init_exec *iexec)
1490{
1491 /*
1492 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1493 *
1494 * offset (8 bit): opcode
1495 * offset + 1 (8 bit): CRTC index1
1496 * offset + 2 (8 bit): CRTC index2
1497 * offset + 3 (8 bit): baseaddr
1498 * offset + 4 (8 bit): count
1499 * offset + 5 (8 bit): data 1
1500 * ...
1501 *
1502 * For each of "count" address and data pairs, write "baseaddr + n" to
1503 * "CRTC index1" and "data n" to "CRTC index2"
1504 * Once complete, restore initial value read from "CRTC index1"
1505 */
1506 uint8_t crtcindex1 = bios->data[offset + 1];
1507 uint8_t crtcindex2 = bios->data[offset + 2];
1508 uint8_t baseaddr = bios->data[offset + 3];
1509 uint8_t count = bios->data[offset + 4];
37383650 1510 int len = 5 + count;
6ee73861
BS		 1511 uint8_t oldaddr, data;
1512 int i;
1513
1514 if (!iexec->execute)
37383650 1515 return len;
6ee73861
BS		 1516
1517 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1518 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1519 offset, crtcindex1, crtcindex2, baseaddr, count);
1520
1521 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1522
1523 for (i = 0; i < count; i++) {
1524 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1525 baseaddr + i);
1526 data = bios->data[offset + 5 + i];
1527 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1528 }
1529
1530 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1531
37383650 1532 return len;
6ee73861
BS		 1533}
1534
37383650 1535static int
6ee73861
BS		 1536init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1537{
1538 /*
1539 * INIT_CR opcode: 0x52 ('R')
1540 *
1541 * offset (8 bit): opcode
1542 * offset + 1 (8 bit): CRTC index
1543 * offset + 2 (8 bit): mask
1544 * offset + 3 (8 bit): data
1545 *
1546 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1547 * data back to "CRTC index"
1548 */
1549
1550 uint8_t crtcindex = bios->data[offset + 1];
1551 uint8_t mask = bios->data[offset + 2];
1552 uint8_t data = bios->data[offset + 3];
1553 uint8_t value;
1554
1555 if (!iexec->execute)
37383650 1556 return 4;
6ee73861
BS		 1557
1558 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1559 offset, crtcindex, mask, data);
1560
1561 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1562 value |= data;
1563 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1564
37383650 1565 return 4;
6ee73861
BS		 1566}
1567
37383650 1568static int
6ee73861
BS		 1569init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1570{
1571 /*
1572 * INIT_ZM_CR opcode: 0x53 ('S')
1573 *
1574 * offset (8 bit): opcode
1575 * offset + 1 (8 bit): CRTC index
1576 * offset + 2 (8 bit): value
1577 *
1578 * Assign "value" to CRTC register with index "CRTC index".
1579 */
1580
1581 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1582 uint8_t data = bios->data[offset + 2];
1583
1584 if (!iexec->execute)
37383650 1585 return 3;
6ee73861
BS		 1586
1587 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1588
37383650 1589 return 3;
6ee73861
BS		 1590}
1591
37383650 1592static int
6ee73861
BS		 1593init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1594{
1595 /*
1596 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1597 *
1598 * offset (8 bit): opcode
1599 * offset + 1 (8 bit): count
1600 * offset + 2 (8 bit): CRTC index 1
1601 * offset + 3 (8 bit): value 1
1602 * ...
1603 *
1604 * For "count", assign "value n" to CRTC register with index
1605 * "CRTC index n".
1606 */
1607
1608 uint8_t count = bios->data[offset + 1];
37383650 1609 int len = 2 + count * 2;
6ee73861
BS		 1610 int i;
1611
1612 if (!iexec->execute)
37383650 1613 return len;
6ee73861
BS		 1614
1615 for (i = 0; i < count; i++)
1616 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1617
37383650 1618 return len;
6ee73861
BS		 1619}
1620
37383650 1621static int
6ee73861
BS		 1622init_condition_time(struct nvbios *bios, uint16_t offset,
1623 struct init_exec *iexec)
1624{
1625 /*
1626 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1627 *
1628 * offset (8 bit): opcode
1629 * offset + 1 (8 bit): condition number
1630 * offset + 2 (8 bit): retries / 50
1631 *
1632 * Check condition "condition number" in the condition table.
1633 * Bios code then sleeps for 2ms if the condition is not met, and
1634 * repeats up to "retries" times, but on one C51 this has proved
1635 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1636 * this, and bail after "retries" times, or 2s, whichever is less.
1637 * If still not met after retries, clear execution flag for this table.
1638 */
1639
1640 uint8_t cond = bios->data[offset + 1];
1641 uint16_t retries = bios->data[offset + 2] * 50;
1642 unsigned cnt;
1643
1644 if (!iexec->execute)
37383650 1645 return 3;
6ee73861
BS		 1646
1647 if (retries > 100)
1648 retries = 100;
1649
1650 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1651 offset, cond, retries);
1652
1653 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1654 retries = 1;
1655
1656 for (cnt = 0; cnt < retries; cnt++) {
1657 if (bios_condition_met(bios, offset, cond)) {
1658 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1659 offset);
1660 break;
1661 } else {
1662 BIOSLOG(bios, "0x%04X: "
1663 "Condition not met, sleeping for 20ms\n",
1664 offset);
1665 msleep(20);
1666 }
1667 }
1668
1669 if (!bios_condition_met(bios, offset, cond)) {
1670 NV_WARN(bios->dev,
1671 "0x%04X: Condition still not met after %dms, "
1672 "skipping following opcodes\n", offset, 20 * retries);
1673 iexec->execute = false;
1674 }
1675
37383650 1676 return 3;
6ee73861
BS		 1677}
1678
37383650 1679static int
6ee73861
BS		 1680init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1681 struct init_exec *iexec)
1682{
1683 /*
1684 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1685 *
1686 * offset (8 bit): opcode
1687 * offset + 1 (32 bit): base register
1688 * offset + 5 (8 bit): count
1689 * offset + 6 (32 bit): value 1
1690 * ...
1691 *
1692 * Starting at offset + 6 there are "count" 32 bit values.
1693 * For "count" iterations set "base register" + 4 * current_iteration
1694 * to "value current_iteration"
1695 */
1696
1697 uint32_t basereg = ROM32(bios->data[offset + 1]);
1698 uint32_t count = bios->data[offset + 5];
37383650 1699 int len = 6 + count * 4;
6ee73861
BS		 1700 int i;
1701
1702 if (!iexec->execute)
37383650 1703 return len;
6ee73861
BS		 1704
1705 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1706 offset, basereg, count);
1707
1708 for (i = 0; i < count; i++) {
1709 uint32_t reg = basereg + i * 4;
1710 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1711
1712 bios_wr32(bios, reg, data);
1713 }
1714
37383650 1715 return len;
6ee73861
BS		 1716}
1717
37383650 1718static int
6ee73861
BS		 1719init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1720{
1721 /*
1722 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1723 *
1724 * offset (8 bit): opcode
1725 * offset + 1 (16 bit): subroutine offset (in bios)
1726 *
1727 * Calls a subroutine that will execute commands until INIT_DONE
1728 * is found.
1729 */
1730
1731 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1732
1733 if (!iexec->execute)
37383650 1734 return 3;
6ee73861
BS		 1735
1736 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1737 offset, sub_offset);
1738
1739 parse_init_table(bios, sub_offset, iexec);
1740
1741 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1742
37383650 1743 return 3;
6ee73861
BS		 1744}
1745
37383650 1746static int
6ee73861
BS		 1747init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1748{
1749 /*
1750 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1751 *
1752 * offset (8 bit): opcode
1753 * offset + 1 (32 bit): src reg
1754 * offset + 5 (8 bit): shift
1755 * offset + 6 (32 bit): src mask
1756 * offset + 10 (32 bit): xor
1757 * offset + 14 (32 bit): dst reg
1758 * offset + 18 (32 bit): dst mask
1759 *
1760 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1761 * "src mask", then XOR with "xor". Write this OR'd with
1762 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1763 */
1764
1765 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1766 uint8_t shift = bios->data[offset + 5];
1767 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1768 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1769 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1770 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1771 uint32_t srcvalue, dstvalue;
1772
1773 if (!iexec->execute)
37383650 1774 return 22;
6ee73861
BS		 1775
1776 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1777 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1778 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1779
1780 srcvalue = bios_rd32(bios, srcreg);
1781
1782 if (shift < 0x80)
1783 srcvalue >>= shift;
1784 else
1785 srcvalue <<= (0x100 - shift);
1786
1787 srcvalue = (srcvalue & srcmask) ^ xor;
1788
1789 dstvalue = bios_rd32(bios, dstreg) & dstmask;
1790
1791 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1792
37383650 1793 return 22;
6ee73861
BS		 1794}
1795
37383650 1796static int
6ee73861
BS		 1797init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1798{
1799 /*
1800 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1801 *
1802 * offset (8 bit): opcode
1803 * offset + 1 (16 bit): CRTC port
1804 * offset + 3 (8 bit): CRTC index
1805 * offset + 4 (8 bit): data
1806 *
1807 * Write "data" to index "CRTC index" of "CRTC port"
1808 */
1809 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1810 uint8_t crtcindex = bios->data[offset + 3];
1811 uint8_t data = bios->data[offset + 4];
1812
1813 if (!iexec->execute)
37383650 1814 return 5;
6ee73861
BS		 1815
1816 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1817
37383650 1818 return 5;
6ee73861
BS		 1819}
1820
37383650 1821static int
6ee73861
BS		 1822init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1823{
1824 /*
1825 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
1826 *
1827 * offset (8 bit): opcode
1828 *
1829 * This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
1830 * that the hardware can correctly calculate how much VRAM it has
1831 * (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
1832 *
1833 * The implementation of this opcode in general consists of two parts:
1834 * 1) determination of the memory bus width
1835 * 2) determination of how many of the card's RAM pads have ICs attached
1836 *
1837 * 1) is done by a cunning combination of writes to offsets 0x1c and
1838 * 0x3c in the framebuffer, and seeing whether the written values are
1839 * read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
1840 *
1841 * 2) is done by a cunning combination of writes to an offset slightly
1842 * less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
1843 * if the test pattern can be read back. This then affects bits 12-15 of
1844 * NV_PFB_CFG0
1845 *
1846 * In this context a "cunning combination" may include multiple reads
1847 * and writes to varying locations, often alternating the test pattern
1848 * and 0, doubtless to make sure buffers are filled, residual charges
1849 * on tracks are removed etc.
1850 *
1851 * Unfortunately, the "cunning combination"s mentioned above, and the
1852 * changes to the bits in NV_PFB_CFG0 differ with nearly every bios
1853 * trace I have.
1854 *
1855 * Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
1856 * we started was correct, and use that instead
1857 */
1858
1859 /* no iexec->execute check by design */
1860
1861 /*
1862 * This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
1863 * and kmmio traces of the binary driver POSTing the card show nothing
1864 * being done for this opcode. why is it still listed in the table?!
1865 */
1866
1867 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
1868
e235c1f3 1869 if (dev_priv->card_type >= NV_40)
37383650 1870 return 1;
6ee73861
BS		 1871
1872 /*
1873 * On every card I've seen, this step gets done for us earlier in
1874 * the init scripts
1875 uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
1876 bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
1877 */
1878
1879 /*
1880 * This also has probably been done in the scripts, but an mmio trace of
1881 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
1882 */
1883 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);
1884
1885 /* write back the saved configuration value */
1886 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
1887
37383650 1888 return 1;
6ee73861
BS		 1889}
1890
37383650 1891static int
6ee73861
BS		 1892init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1893{
1894 /*
1895 * INIT_RESET opcode: 0x65 ('e')
1896 *
1897 * offset (8 bit): opcode
1898 * offset + 1 (32 bit): register
1899 * offset + 5 (32 bit): value1
1900 * offset + 9 (32 bit): value2
1901 *
1902 * Assign "value1" to "register", then assign "value2" to "register"
1903 */
1904
1905 uint32_t reg = ROM32(bios->data[offset + 1]);
1906 uint32_t value1 = ROM32(bios->data[offset + 5]);
1907 uint32_t value2 = ROM32(bios->data[offset + 9]);
1908 uint32_t pci_nv_19, pci_nv_20;
1909
1910 /* no iexec->execute check by design */
1911
1912 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
1913 bios_wr32(bios, NV_PBUS_PCI_NV_19, 0);
1914 bios_wr32(bios, reg, value1);
1915
1916 udelay(10);
1917
1918 bios_wr32(bios, reg, value2);
1919 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
1920
1921 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
1922 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
1923 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
1924
37383650 1925 return 13;
6ee73861
BS		 1926}
1927
37383650 1928static int
6ee73861
BS		 1929init_configure_mem(struct nvbios *bios, uint16_t offset,
1930 struct init_exec *iexec)
1931{
1932 /*
1933 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
1934 *
1935 * offset (8 bit): opcode
1936 *
1937 * Equivalent to INIT_DONE on bios version 3 or greater.
1938 * For early bios versions, sets up the memory registers, using values
1939 * taken from the memory init table
1940 */
1941
1942 /* no iexec->execute check by design */
1943
1944 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
1945 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
1946 uint32_t reg, data;
1947
1948 if (bios->major_version > 2)
37383650 1949 return 0;
6ee73861
BS		 1950
1951 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
1952 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
1953
1954 if (bios->data[meminitoffs] & 1)
1955 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
1956
1957 for (reg = ROM32(bios->data[seqtbloffs]);
1958 reg != 0xffffffff;
1959 reg = ROM32(bios->data[seqtbloffs += 4])) {
1960
1961 switch (reg) {
1962 case NV_PFB_PRE:
1963 data = NV_PFB_PRE_CMD_PRECHARGE;
1964 break;
1965 case NV_PFB_PAD:
1966 data = NV_PFB_PAD_CKE_NORMAL;
1967 break;
1968 case NV_PFB_REF:
1969 data = NV_PFB_REF_CMD_REFRESH;
1970 break;
1971 default:
1972 data = ROM32(bios->data[meminitdata]);
1973 meminitdata += 4;
1974 if (data == 0xffffffff)
1975 continue;
1976 }
1977
1978 bios_wr32(bios, reg, data);
1979 }
1980
37383650 1981 return 1;
6ee73861
BS		 1982}
1983
37383650 1984static int
6ee73861
BS		 1985init_configure_clk(struct nvbios *bios, uint16_t offset,
1986 struct init_exec *iexec)
1987{
1988 /*
1989 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
1990 *
1991 * offset (8 bit): opcode
1992 *
1993 * Equivalent to INIT_DONE on bios version 3 or greater.
1994 * For early bios versions, sets up the NVClk and MClk PLLs, using
1995 * values taken from the memory init table
1996 */
1997
1998 /* no iexec->execute check by design */
1999
2000 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2001 int clock;
2002
2003 if (bios->major_version > 2)
37383650 2004 return 0;
6ee73861
BS		 2005
2006 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2007 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2008
2009 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2010 if (bios->data[meminitoffs] & 1) /* DDR */
2011 clock *= 2;
2012 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2013
37383650 2014 return 1;
6ee73861
BS		 2015}
2016
37383650 2017static int
6ee73861
BS		 2018init_configure_preinit(struct nvbios *bios, uint16_t offset,
2019 struct init_exec *iexec)
2020{
2021 /*
2022 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2023 *
2024 * offset (8 bit): opcode
2025 *
2026 * Equivalent to INIT_DONE on bios version 3 or greater.
2027 * For early bios versions, does early init, loading ram and crystal
2028 * configuration from straps into CR3C
2029 */
2030
2031 /* no iexec->execute check by design */
2032
2033 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2034 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & (1 << 6));
2035
2036 if (bios->major_version > 2)
37383650 2037 return 0;
6ee73861
BS		 2038
2039 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2040 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2041
37383650 2042 return 1;
6ee73861
BS		 2043}
2044
37383650 2045static int
6ee73861
BS		 2046init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2047{
2048 /*
2049 * INIT_IO opcode: 0x69 ('i')
2050 *
2051 * offset (8 bit): opcode
2052 * offset + 1 (16 bit): CRTC port
2053 * offset + 3 (8 bit): mask
2054 * offset + 4 (8 bit): data
2055 *
2056 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2057 */
2058
2059 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2060 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2061 uint8_t mask = bios->data[offset + 3];
2062 uint8_t data = bios->data[offset + 4];
2063
2064 if (!iexec->execute)
37383650 2065 return 5;
6ee73861
BS		 2066
2067 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2068 offset, crtcport, mask, data);
2069
2070 /*
2071 * I have no idea what this does, but NVIDIA do this magic sequence
2072 * in the places where this INIT_IO happens..
2073 */
2074 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2075 int i;
2076
2077 bios_wr32(bios, 0x614100, (bios_rd32(
2078 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2079
2080 bios_wr32(bios, 0x00e18c, bios_rd32(
2081 bios, 0x00e18c) | 0x00020000);
2082
2083 bios_wr32(bios, 0x614900, (bios_rd32(
2084 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2085
2086 bios_wr32(bios, 0x000200, bios_rd32(
2087 bios, 0x000200) & ~0x40000000);
2088
2089 mdelay(10);
2090
2091 bios_wr32(bios, 0x00e18c, bios_rd32(
2092 bios, 0x00e18c) & ~0x00020000);
2093
2094 bios_wr32(bios, 0x000200, bios_rd32(
2095 bios, 0x000200) | 0x40000000);
2096
2097 bios_wr32(bios, 0x614100, 0x00800018);
2098 bios_wr32(bios, 0x614900, 0x00800018);
2099
2100 mdelay(10);
2101
2102 bios_wr32(bios, 0x614100, 0x10000018);
2103 bios_wr32(bios, 0x614900, 0x10000018);
2104
2105 for (i = 0; i < 3; i++)
2106 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2107 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2108
2109 for (i = 0; i < 2; i++)
2110 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2111 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2112
2113 for (i = 0; i < 3; i++)
2114 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2115 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2116
2117 for (i = 0; i < 2; i++)
2118 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2119 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2120
2121 for (i = 0; i < 2; i++)
2122 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2123 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2124 return 5;
6ee73861
BS		 2125 }
2126
2127 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2128 data);
37383650 2129 return 5;
6ee73861
BS		 2130}
2131
37383650 2132static int
6ee73861
BS		 2133init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2134{
2135 /*
2136 * INIT_SUB opcode: 0x6B ('k')
2137 *
2138 * offset (8 bit): opcode
2139 * offset + 1 (8 bit): script number
2140 *
2141 * Execute script number "script number", as a subroutine
2142 */
2143
2144 uint8_t sub = bios->data[offset + 1];
2145
2146 if (!iexec->execute)
37383650 2147 return 2;
6ee73861
BS		 2148
2149 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2150
2151 parse_init_table(bios,
2152 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2153 iexec);
2154
2155 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2156
37383650 2157 return 2;
6ee73861
BS		 2158}
2159
37383650 2160static int
6ee73861
BS		 2161init_ram_condition(struct nvbios *bios, uint16_t offset,
2162 struct init_exec *iexec)
2163{
2164 /*
2165 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2166 *
2167 * offset (8 bit): opcode
2168 * offset + 1 (8 bit): mask
2169 * offset + 2 (8 bit): cmpval
2170 *
2171 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".
2172 * If condition not met skip subsequent opcodes until condition is
2173 * inverted (INIT_NOT), or we hit INIT_RESUME
2174 */
2175
2176 uint8_t mask = bios->data[offset + 1];
2177 uint8_t cmpval = bios->data[offset + 2];
2178 uint8_t data;
2179
2180 if (!iexec->execute)
37383650 2181 return 3;
6ee73861
BS		 2182
2183 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;
2184
2185 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2186 offset, data, cmpval);
2187
2188 if (data == cmpval)
2189 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2190 else {
2191 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2192 iexec->execute = false;
2193 }
2194
37383650 2195 return 3;
6ee73861
BS		 2196}
2197
37383650 2198static int
6ee73861
BS		 2199init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2200{
2201 /*
2202 * INIT_NV_REG opcode: 0x6E ('n')
2203 *
2204 * offset (8 bit): opcode
2205 * offset + 1 (32 bit): register
2206 * offset + 5 (32 bit): mask
2207 * offset + 9 (32 bit): data
2208 *
2209 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2210 */
2211
2212 uint32_t reg = ROM32(bios->data[offset + 1]);
2213 uint32_t mask = ROM32(bios->data[offset + 5]);
2214 uint32_t data = ROM32(bios->data[offset + 9]);
2215
2216 if (!iexec->execute)
37383650 2217 return 13;
6ee73861
BS		 2218
2219 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2220 offset, reg, mask, data);
2221
2222 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2223
37383650 2224 return 13;
6ee73861
BS		 2225}
2226
37383650 2227static int
6ee73861
BS		 2228init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2229{
2230 /*
2231 * INIT_MACRO opcode: 0x6F ('o')
2232 *
2233 * offset (8 bit): opcode
2234 * offset + 1 (8 bit): macro number
2235 *
2236 * Look up macro index "macro number" in the macro index table.
2237 * The macro index table entry has 1 byte for the index in the macro
2238 * table, and 1 byte for the number of times to repeat the macro.
2239 * The macro table entry has 4 bytes for the register address and
2240 * 4 bytes for the value to write to that register
2241 */
2242
2243 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2244 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2245 uint8_t macro_tbl_idx = bios->data[tmp];
2246 uint8_t count = bios->data[tmp + 1];
2247 uint32_t reg, data;
2248 int i;
2249
2250 if (!iexec->execute)
37383650 2251 return 2;
6ee73861
BS		 2252
2253 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2254 "Count: 0x%02X\n",
2255 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2256
2257 for (i = 0; i < count; i++) {
2258 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2259
2260 reg = ROM32(bios->data[macroentryptr]);
2261 data = ROM32(bios->data[macroentryptr + 4]);
2262
2263 bios_wr32(bios, reg, data);
2264 }
2265
37383650 2266 return 2;
6ee73861
BS		 2267}
2268
37383650 2269static int
6ee73861
BS		 2270init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2271{
2272 /*
2273 * INIT_DONE opcode: 0x71 ('q')
2274 *
2275 * offset (8 bit): opcode
2276 *
2277 * End the current script
2278 */
2279
2280 /* mild retval abuse to stop parsing this table */
37383650 2281 return 0;
6ee73861
BS		 2282}
2283
37383650 2284static int
6ee73861
BS		 2285init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2286{
2287 /*
2288 * INIT_RESUME opcode: 0x72 ('r')
2289 *
2290 * offset (8 bit): opcode
2291 *
2292 * End the current execute / no-execute condition
2293 */
2294
2295 if (iexec->execute)
37383650 2296 return 1;
6ee73861
BS		 2297
2298 iexec->execute = true;
2299 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2300
37383650 2301 return 1;
6ee73861
BS		 2302}
2303
37383650 2304static int
6ee73861
BS		 2305init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2306{
2307 /*
2308 * INIT_TIME opcode: 0x74 ('t')
2309 *
2310 * offset (8 bit): opcode
2311 * offset + 1 (16 bit): time
2312 *
2313 * Sleep for "time" microseconds.
2314 */
2315
2316 unsigned time = ROM16(bios->data[offset + 1]);
2317
2318 if (!iexec->execute)
37383650 2319 return 3;
6ee73861
BS		 2320
2321 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2322 offset, time);
2323
2324 if (time < 1000)
2325 udelay(time);
2326 else
2327 msleep((time + 900) / 1000);
2328
37383650 2329 return 3;
6ee73861
BS		 2330}
2331
37383650 2332static int
6ee73861
BS		 2333init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2334{
2335 /*
2336 * INIT_CONDITION opcode: 0x75 ('u')
2337 *
2338 * offset (8 bit): opcode
2339 * offset + 1 (8 bit): condition number
2340 *
2341 * Check condition "condition number" in the condition table.
2342 * If condition not met skip subsequent opcodes until condition is
2343 * inverted (INIT_NOT), or we hit INIT_RESUME
2344 */
2345
2346 uint8_t cond = bios->data[offset + 1];
2347
2348 if (!iexec->execute)
37383650 2349 return 2;
6ee73861
BS		 2350
2351 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2352
2353 if (bios_condition_met(bios, offset, cond))
2354 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2355 else {
2356 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2357 iexec->execute = false;
2358 }
2359
37383650 2360 return 2;
6ee73861
BS		 2361}
2362
37383650 2363static int
6ee73861
BS		 2364init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2365{
2366 /*
2367 * INIT_IO_CONDITION opcode: 0x76
2368 *
2369 * offset (8 bit): opcode
2370 * offset + 1 (8 bit): condition number
2371 *
2372 * Check condition "condition number" in the io condition table.
2373 * If condition not met skip subsequent opcodes until condition is
2374 * inverted (INIT_NOT), or we hit INIT_RESUME
2375 */
2376
2377 uint8_t cond = bios->data[offset + 1];
2378
2379 if (!iexec->execute)
37383650 2380 return 2;
6ee73861
BS		 2381
2382 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2383
2384 if (io_condition_met(bios, offset, cond))
2385 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2386 else {
2387 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2388 iexec->execute = false;
2389 }
2390
37383650 2391 return 2;
6ee73861
BS		 2392}
2393
37383650 2394static int
6ee73861
BS		 2395init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2396{
2397 /*
2398 * INIT_INDEX_IO opcode: 0x78 ('x')
2399 *
2400 * offset (8 bit): opcode
2401 * offset + 1 (16 bit): CRTC port
2402 * offset + 3 (8 bit): CRTC index
2403 * offset + 4 (8 bit): mask
2404 * offset + 5 (8 bit): data
2405 *
2406 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2407 * OR with "data", write-back
2408 */
2409
2410 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2411 uint8_t crtcindex = bios->data[offset + 3];
2412 uint8_t mask = bios->data[offset + 4];
2413 uint8_t data = bios->data[offset + 5];
2414 uint8_t value;
2415
2416 if (!iexec->execute)
37383650 2417 return 6;
6ee73861
BS		 2418
2419 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2420 "Data: 0x%02X\n",
2421 offset, crtcport, crtcindex, mask, data);
2422
2423 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2424 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2425
37383650 2426 return 6;
6ee73861
BS		 2427}
2428
37383650 2429static int
6ee73861
BS		 2430init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2431{
2432 /*
2433 * INIT_PLL opcode: 0x79 ('y')
2434 *
2435 * offset (8 bit): opcode
2436 * offset + 1 (32 bit): register
2437 * offset + 5 (16 bit): freq
2438 *
2439 * Set PLL register "register" to coefficients for frequency (10kHz)
2440 * "freq"
2441 */
2442
2443 uint32_t reg = ROM32(bios->data[offset + 1]);
2444 uint16_t freq = ROM16(bios->data[offset + 5]);
2445
2446 if (!iexec->execute)
37383650 2447 return 7;
6ee73861
BS		 2448
2449 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2450
2451 setPLL(bios, reg, freq * 10);
2452
37383650 2453 return 7;
6ee73861
BS		 2454}
2455
37383650 2456static int
6ee73861
BS		 2457init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2458{
2459 /*
2460 * INIT_ZM_REG opcode: 0x7A ('z')
2461 *
2462 * offset (8 bit): opcode
2463 * offset + 1 (32 bit): register
2464 * offset + 5 (32 bit): value
2465 *
2466 * Assign "value" to "register"
2467 */
2468
2469 uint32_t reg = ROM32(bios->data[offset + 1]);
2470 uint32_t value = ROM32(bios->data[offset + 5]);
2471
2472 if (!iexec->execute)
37383650 2473 return 9;
6ee73861
BS		 2474
2475 if (reg == 0x000200)
2476 value |= 1;
2477
2478 bios_wr32(bios, reg, value);
2479
37383650 2480 return 9;
6ee73861
BS		 2481}
2482
37383650 2483static int
6ee73861
BS		 2484init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2485 struct init_exec *iexec)
2486{
2487 /*
2488 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2489 *
2490 * offset (8 bit): opcode
2491 * offset + 1 (8 bit): PLL type
2492 * offset + 2 (32 bit): frequency 0
2493 *
2494 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2495 * ram_restrict_table_ptr. The value read from there is used to select
2496 * a frequency from the table starting at 'frequency 0' to be
2497 * programmed into the PLL corresponding to 'type'.
2498 *
2499 * The PLL limits table on cards using this opcode has a mapping of
2500 * 'type' to the relevant registers.
2501 */
2502
2503 struct drm_device *dev = bios->dev;
2504 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2505 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2506 uint8_t type = bios->data[offset + 1];
2507 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2508 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 2509 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 2510 int i;
2511
2512 if (!iexec->execute)
37383650 2513 return len;
6ee73861
BS		 2514
2515 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2516 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 2517 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 2518 }
2519
2520 entry = pll_limits + pll_limits[1];
2521 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2522 if (entry[0] == type) {
2523 uint32_t reg = ROM32(entry[3]);
2524
2525 BIOSLOG(bios, "0x%04X: "
2526 "Type %02x Reg 0x%08x Freq %dKHz\n",
2527 offset, type, reg, freq);
2528
2529 setPLL(bios, reg, freq);
37383650 2530 return len;
6ee73861
BS		 2531 }
2532 }
2533
2534 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 2535 return len;
6ee73861
BS		 2536}
2537
37383650 2538static int
6ee73861
BS		 2539init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2540{
2541 /*
2542 * INIT_8C opcode: 0x8C ('')
2543 *
2544 * NOP so far....
2545 *
2546 */
2547
37383650 2548 return 1;
6ee73861
BS		 2549}
2550
37383650 2551static int
6ee73861
BS		 2552init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2553{
2554 /*
2555 * INIT_8D opcode: 0x8D ('')
2556 *
2557 * NOP so far....
2558 *
2559 */
2560
37383650 2561 return 1;
6ee73861
BS		 2562}
2563
37383650 2564static int
6ee73861
BS		 2565init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2566{
2567 /*
2568 * INIT_GPIO opcode: 0x8E ('')
2569 *
2570 * offset (8 bit): opcode
2571 *
2572 * Loop over all entries in the DCB GPIO table, and initialise
2573 * each GPIO according to various values listed in each entry
2574 */
2575
2576 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
2577 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
7f245b20 2578 const uint8_t *gpio_table = &bios->data[bios->dcb.gpio_table_ptr];
6ee73861
BS		 2579 const uint8_t *gpio_entry;
2580 int i;
2581
37383650
MK		 2582 if (!iexec->execute)
2583 return 1;
2584
7f245b20 2585 if (bios->dcb.version != 0x40) {
6ee73861 2586 NV_ERROR(bios->dev, "DCB table not version 4.0\n");
37383650 2587 return 0;
6ee73861
BS		 2588 }
2589
7f245b20 2590 if (!bios->dcb.gpio_table_ptr) {
6ee73861 2591 NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n");
37383650 2592 return 0;
6ee73861
BS		 2593 }
2594
2595 gpio_entry = gpio_table + gpio_table[1];
2596 for (i = 0; i < gpio_table[2]; i++, gpio_entry += gpio_table[3]) {
2597 uint32_t entry = ROM32(gpio_entry[0]), r, s, v;
2598 int line = (entry & 0x0000001f);
2599
2600 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, entry);
2601
2602 if ((entry & 0x0000ff00) == 0x0000ff00)
2603 continue;
2604
2605 r = nv50_gpio_reg[line >> 3];
2606 s = (line & 0x07) << 2;
2607 v = bios_rd32(bios, r) & ~(0x00000003 << s);
2608 if (entry & 0x01000000)
2609 v |= (((entry & 0x60000000) >> 29) ^ 2) << s;
2610 else
2611 v |= (((entry & 0x18000000) >> 27) ^ 2) << s;
2612 bios_wr32(bios, r, v);
2613
2614 r = nv50_gpio_ctl[line >> 4];
2615 s = (line & 0x0f);
2616 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2617 switch ((entry & 0x06000000) >> 25) {
2618 case 1:
2619 v |= (0x00000001 << s);
2620 break;
2621 case 2:
2622 v |= (0x00010000 << s);
2623 break;
2624 default:
2625 break;
2626 }
2627 bios_wr32(bios, r, v);
2628 }
2629
37383650 2630 return 1;
6ee73861
BS		 2631}
2632
37383650 2633static int
6ee73861
BS		 2634init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2635 struct init_exec *iexec)
2636{
2637 /*
2638 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2639 *
2640 * offset (8 bit): opcode
2641 * offset + 1 (32 bit): reg
2642 * offset + 5 (8 bit): regincrement
2643 * offset + 6 (8 bit): count
2644 * offset + 7 (32 bit): value 1,1
2645 * ...
2646 *
2647 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2648 * ram_restrict_table_ptr. The value read from here is 'n', and
2649 * "value 1,n" gets written to "reg". This repeats "count" times and on
2650 * each iteration 'm', "reg" increases by "regincrement" and
2651 * "value m,n" is used. The extent of n is limited by a number read
2652 * from the 'M' BIT table, herein called "blocklen"
2653 */
2654
2655 uint32_t reg = ROM32(bios->data[offset + 1]);
2656 uint8_t regincrement = bios->data[offset + 5];
2657 uint8_t count = bios->data[offset + 6];
2658 uint32_t strap_ramcfg, data;
37383650
MK		 2659 /* previously set by 'M' BIT table */
2660 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2661 int len = 7 + count * blocklen;
6ee73861
BS		 2662 uint8_t index;
2663 int i;
2664
6ee73861
BS		 2665
2666 if (!iexec->execute)
37383650 2667 return len;
6ee73861
BS		 2668
2669 if (!blocklen) {
2670 NV_ERROR(bios->dev,
2671 "0x%04X: Zero block length - has the M table "
2672 "been parsed?\n", offset);
37383650 2673 return 0;
6ee73861
BS		 2674 }
2675
2676 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2677 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2678
2679 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2680 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2681 offset, reg, regincrement, count, strap_ramcfg, index);
2682
2683 for (i = 0; i < count; i++) {
2684 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2685
2686 bios_wr32(bios, reg, data);
2687
2688 reg += regincrement;
2689 }
2690
37383650 2691 return len;
6ee73861
BS		 2692}
2693
37383650 2694static int
6ee73861
BS		 2695init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2696{
2697 /*
2698 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2699 *
2700 * offset (8 bit): opcode
2701 * offset + 1 (32 bit): src reg
2702 * offset + 5 (32 bit): dst reg
2703 *
2704 * Put contents of "src reg" into "dst reg"
2705 */
2706
2707 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2708 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2709
2710 if (!iexec->execute)
37383650 2711 return 9;
6ee73861
BS		 2712
2713 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2714
37383650 2715 return 9;
6ee73861
BS		 2716}
2717
37383650 2718static int
6ee73861
BS		 2719init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2720 struct init_exec *iexec)
2721{
2722 /*
2723 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2724 *
2725 * offset (8 bit): opcode
2726 * offset + 1 (32 bit): dst reg
2727 * offset + 5 (8 bit): count
2728 * offset + 6 (32 bit): data 1
2729 * ...
2730 *
2731 * For each of "count" values write "data n" to "dst reg"
2732 */
2733
2734 uint32_t reg = ROM32(bios->data[offset + 1]);
2735 uint8_t count = bios->data[offset + 5];
37383650 2736 int len = 6 + count * 4;
6ee73861
BS		 2737 int i;
2738
2739 if (!iexec->execute)
37383650 2740 return len;
6ee73861
BS		 2741
2742 for (i = 0; i < count; i++) {
2743 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
2744 bios_wr32(bios, reg, data);
2745 }
2746
37383650 2747 return len;
6ee73861
BS		 2748}
2749
37383650 2750static int
6ee73861
BS		 2751init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2752{
2753 /*
2754 * INIT_RESERVED opcode: 0x92 ('')
2755 *
2756 * offset (8 bit): opcode
2757 *
2758 * Seemingly does nothing
2759 */
2760
37383650 2761 return 1;
6ee73861
BS		 2762}
2763
37383650 2764static int
6ee73861
BS		 2765init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2766{
2767 /*
2768 * INIT_96 opcode: 0x96 ('')
2769 *
2770 * offset (8 bit): opcode
2771 * offset + 1 (32 bit): sreg
2772 * offset + 5 (8 bit): sshift
2773 * offset + 6 (8 bit): smask
2774 * offset + 7 (8 bit): index
2775 * offset + 8 (32 bit): reg
2776 * offset + 12 (32 bit): mask
2777 * offset + 16 (8 bit): shift
2778 *
2779 */
2780
2781 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
2782 uint32_t reg = ROM32(bios->data[offset + 8]);
2783 uint32_t mask = ROM32(bios->data[offset + 12]);
2784 uint32_t val;
2785
2786 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
2787 if (bios->data[offset + 5] < 0x80)
2788 val >>= bios->data[offset + 5];
2789 else
2790 val <<= (0x100 - bios->data[offset + 5]);
2791 val &= bios->data[offset + 6];
2792
2793 val = bios->data[ROM16(bios->data[xlatptr]) + val];
2794 val <<= bios->data[offset + 16];
2795
2796 if (!iexec->execute)
37383650 2797 return 17;
6ee73861
BS		 2798
2799 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 2800 return 17;
6ee73861
BS		 2801}
2802
37383650 2803static int
6ee73861
BS		 2804init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2805{
2806 /*
2807 * INIT_97 opcode: 0x97 ('')
2808 *
2809 * offset (8 bit): opcode
2810 * offset + 1 (32 bit): register
2811 * offset + 5 (32 bit): mask
2812 * offset + 9 (32 bit): value
2813 *
2814 * Adds "value" to "register" preserving the fields specified
2815 * by "mask"
2816 */
2817
2818 uint32_t reg = ROM32(bios->data[offset + 1]);
2819 uint32_t mask = ROM32(bios->data[offset + 5]);
2820 uint32_t add = ROM32(bios->data[offset + 9]);
2821 uint32_t val;
2822
2823 val = bios_rd32(bios, reg);
2824 val = (val & mask) | ((val + add) & ~mask);
2825
2826 if (!iexec->execute)
37383650 2827 return 13;
6ee73861
BS		 2828
2829 bios_wr32(bios, reg, val);
37383650 2830 return 13;
6ee73861
BS		 2831}
2832
37383650 2833static int
6ee73861
BS		 2834init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2835{
2836 /*
2837 * INIT_AUXCH opcode: 0x98 ('')
2838 *
2839 * offset (8 bit): opcode
2840 * offset + 1 (32 bit): address
2841 * offset + 5 (8 bit): count
2842 * offset + 6 (8 bit): mask 0
2843 * offset + 7 (8 bit): data 0
2844 * ...
2845 *
2846 */
2847
2848 struct drm_device *dev = bios->dev;
2849 struct nouveau_i2c_chan *auxch;
2850 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 2851 uint8_t count = bios->data[offset + 5];
2852 int len = 6 + count * 2;
6ee73861
BS		 2853 int ret, i;
2854
2855 if (!bios->display.output) {
2856 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
37383650 2857 return 0;
6ee73861
BS		 2858 }
2859
2860 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2861 if (!auxch) {
2862 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
2863 bios->display.output->i2c_index);
37383650 2864 return 0;
6ee73861
BS		 2865 }
2866
2867 if (!iexec->execute)
37383650 2868 return len;
6ee73861
BS		 2869
2870 offset += 6;
37383650 2871 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 2872 uint8_t data;
2873
2874 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
2875 if (ret) {
2876 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
37383650 2877 return 0;
6ee73861
BS		 2878 }
2879
2880 data &= bios->data[offset + 0];
2881 data |= bios->data[offset + 1];
2882
2883 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
2884 if (ret) {
2885 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
37383650 2886 return 0;
6ee73861
BS		 2887 }
2888 }
2889
37383650 2890 return len;
6ee73861
BS		 2891}
2892
37383650 2893static int
6ee73861
BS		 2894init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2895{
2896 /*
2897 * INIT_ZM_AUXCH opcode: 0x99 ('')
2898 *
2899 * offset (8 bit): opcode
2900 * offset + 1 (32 bit): address
2901 * offset + 5 (8 bit): count
2902 * offset + 6 (8 bit): data 0
2903 * ...
2904 *
2905 */
2906
2907 struct drm_device *dev = bios->dev;
2908 struct nouveau_i2c_chan *auxch;
2909 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 2910 uint8_t count = bios->data[offset + 5];
2911 int len = 6 + count;
6ee73861
BS		 2912 int ret, i;
2913
2914 if (!bios->display.output) {
2915 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
37383650 2916 return 0;
6ee73861
BS		 2917 }
2918
2919 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
2920 if (!auxch) {
2921 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
2922 bios->display.output->i2c_index);
37383650 2923 return 0;
6ee73861
BS		 2924 }
2925
2926 if (!iexec->execute)
37383650 2927 return len;
6ee73861
BS		 2928
2929 offset += 6;
37383650 2930 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 2931 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
2932 if (ret) {
2933 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
37383650 2934 return 0;
6ee73861
BS		 2935 }
2936 }
2937
37383650 2938 return len;
6ee73861
BS		 2939}
2940
2941static struct init_tbl_entry itbl_entry[] = {
2942 /* command name , id , length , offset , mult , command handler */
2943 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 2944 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
2945 { "INIT_REPEAT" , 0x33, init_repeat },
2946 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
2947 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
2948 { "INIT_COPY" , 0x37, init_copy },
2949 { "INIT_NOT" , 0x38, init_not },
2950 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
2951 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
2952 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
2953 { "INIT_PLL2" , 0x4B, init_pll2 },
2954 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
2955 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
2956 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
2957 { "INIT_TMDS" , 0x4F, init_tmds },
2958 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
2959 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
2960 { "INIT_CR" , 0x52, init_cr },
2961 { "INIT_ZM_CR" , 0x53, init_zm_cr },
2962 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
2963 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
2964 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 2965 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650
MK		 2966 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
2967 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
2968 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
2969 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
2970 { "INIT_RESET" , 0x65, init_reset },
2971 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
2972 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
2973 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
2974 { "INIT_IO" , 0x69, init_io },
2975 { "INIT_SUB" , 0x6B, init_sub },
2976 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
2977 { "INIT_NV_REG" , 0x6E, init_nv_reg },
2978 { "INIT_MACRO" , 0x6F, init_macro },
2979 { "INIT_DONE" , 0x71, init_done },
2980 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 2981 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 2982 { "INIT_TIME" , 0x74, init_time },
2983 { "INIT_CONDITION" , 0x75, init_condition },
2984 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
2985 { "INIT_INDEX_IO" , 0x78, init_index_io },
2986 { "INIT_PLL" , 0x79, init_pll },
2987 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
2988 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
2989 { "INIT_8C" , 0x8C, init_8c },
2990 { "INIT_8D" , 0x8D, init_8d },
2991 { "INIT_GPIO" , 0x8E, init_gpio },
2992 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
2993 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
2994 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
2995 { "INIT_RESERVED" , 0x92, init_reserved },
2996 { "INIT_96" , 0x96, init_96 },
2997 { "INIT_97" , 0x97, init_97 },
2998 { "INIT_AUXCH" , 0x98, init_auxch },
2999 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3000 { NULL , 0 , NULL }
6ee73861
BS		 3001};
3002
6ee73861
BS		 3003#define MAX_TABLE_OPS 1000
3004
3005static int
3006parse_init_table(struct nvbios *bios, unsigned int offset,
3007 struct init_exec *iexec)
3008{
3009 /*
3010 * Parses all commands in an init table.
3011 *
3012 * We start out executing all commands found in the init table. Some
3013 * opcodes may change the status of iexec->execute to SKIP, which will
3014 * cause the following opcodes to perform no operation until the value
3015 * is changed back to EXECUTE.
3016 */
3017
37383650 3018 int count = 0, i, res;
6ee73861
BS		 3019 uint8_t id;
3020
3021 /*
3022 * Loop until INIT_DONE causes us to break out of the loop
3023 * (or until offset > bios length just in case... )
3024 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3025 */
3026 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3027 id = bios->data[offset];
3028
3029 /* Find matching id in itbl_entry */
3030 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3031 ;
3032
3033 if (itbl_entry[i].name) {
3034 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n",
3035 offset, itbl_entry[i].id, itbl_entry[i].name);
3036
3037 /* execute eventual command handler */
37383650
MK		 3038 res = (*itbl_entry[i].handler)(bios, offset, iexec);
3039 if (!res)
3040 break;
3041 /*
3042 * Add the offset of the current command including all data
3043 * of that command. The offset will then be pointing on the
3044 * next op code.
3045 */
3046 offset += res;
6ee73861
BS		 3047 } else {
3048 NV_ERROR(bios->dev,
3049 "0x%04X: Init table command not found: "
3050 "0x%02X\n", offset, id);
3051 return -ENOENT;
3052 }
6ee73861
BS		 3053 }
3054
3055 if (offset >= bios->length)
3056 NV_WARN(bios->dev,
3057 "Offset 0x%04X greater than known bios image length. "
3058 "Corrupt image?\n", offset);
3059 if (count >= MAX_TABLE_OPS)
3060 NV_WARN(bios->dev,
3061 "More than %d opcodes to a table is unlikely, "
3062 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3063
3064 return 0;
3065}
3066
3067static void
3068parse_init_tables(struct nvbios *bios)
3069{
3070 /* Loops and calls parse_init_table() for each present table. */
3071
3072 int i = 0;
3073 uint16_t table;
3074 struct init_exec iexec = {true, false};
3075
3076 if (bios->old_style_init) {
3077 if (bios->init_script_tbls_ptr)
3078 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3079 if (bios->extra_init_script_tbl_ptr)
3080 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3081
3082 return;
3083 }
3084
3085 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3086 NV_INFO(bios->dev,
3087 "Parsing VBIOS init table %d at offset 0x%04X\n",
3088 i / 2, table);
3089 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3090
3091 parse_init_table(bios, table, &iexec);
3092 i += 2;
3093 }
3094}
3095
3096static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3097{
3098 int compare_record_len, i = 0;
3099 uint16_t compareclk, scriptptr = 0;
3100
3101 if (bios->major_version < 5) /* pre BIT */
3102 compare_record_len = 3;
3103 else
3104 compare_record_len = 4;
3105
3106 do {
3107 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3108 if (pxclk >= compareclk * 10) {
3109 if (bios->major_version < 5) {
3110 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3111 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3112 } else
3113 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3114 break;
3115 }
3116 i++;
3117 } while (compareclk);
3118
3119 return scriptptr;
3120}
3121
3122static void
3123run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3124 struct dcb_entry *dcbent, int head, bool dl)
3125{
3126 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3127 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3128 struct init_exec iexec = {true, false};
3129
3130 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3131 scriptptr);
3132 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3133 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3134 /* note: if dcb entries have been merged, index may be misleading */
3135 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3136 parse_init_table(bios, scriptptr, &iexec);
3137
3138 nv04_dfp_bind_head(dev, dcbent, head, dl);
3139}
3140
3141static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3142{
3143 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3144 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3145 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3146 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3147
3148 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3149 return -EINVAL;
3150
3151 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3152
3153 if (script == LVDS_PANEL_OFF) {
3154 /* off-on delay in ms */
3155 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3156 }
3157#ifdef __powerpc__
3158 /* Powerbook specific quirks */
3d9aefb8
FJ		 3159 if ((dev->pci_device & 0xffff) == 0x0179 ||
3160 (dev->pci_device & 0xffff) == 0x0189 ||
3161 (dev->pci_device & 0xffff) == 0x0329) {
3162 if (script == LVDS_RESET) {
3163 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3164
3165 } else if (script == LVDS_PANEL_ON) {
3166 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3167 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3168 | (1 << 31));
3169 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3170 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3171
3172 } else if (script == LVDS_PANEL_OFF) {
3173 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3174 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3175 & ~(1 << 31));
3176 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3177 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
6ee73861
BS		 3178 }
3179 }
3180#endif
3181
3182 return 0;
3183}
3184
3185static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3186{
3187 /*
3188 * The BIT LVDS table's header has the information to setup the
3189 * necessary registers. Following the standard 4 byte header are:
3190 * A bitmask byte and a dual-link transition pxclk value for use in
3191 * selecting the init script when not using straps; 4 script pointers
3192 * for panel power, selected by output and on/off; and 8 table pointers
3193 * for panel init, the needed one determined by output, and bits in the
3194 * conf byte. These tables are similar to the TMDS tables, consisting
3195 * of a list of pxclks and script pointers.
3196 */
3197 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3198 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3199 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3200 uint16_t scriptptr = 0, clktable;
3201 uint8_t clktableptr = 0;
3202
3203 /*
3204 * For now we assume version 3.0 table - g80 support will need some
3205 * changes
3206 */
3207
3208 switch (script) {
3209 case LVDS_INIT:
3210 return -ENOSYS;
3211 case LVDS_BACKLIGHT_ON:
3212 case LVDS_PANEL_ON:
3213 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3214 break;
3215 case LVDS_BACKLIGHT_OFF:
3216 case LVDS_PANEL_OFF:
3217 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3218 break;
3219 case LVDS_RESET:
3220 if (dcbent->lvdsconf.use_straps_for_mode) {
3221 if (bios->fp.dual_link)
3222 clktableptr += 2;
3223 if (bios->fp.BITbit1)
3224 clktableptr++;
3225 } else {
3226 /* using EDID */
3227 uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3228 int fallbackcmpval = (dcbent->or == 4) ? 4 : 1;
3229
3230 if (bios->fp.dual_link) {
3231 clktableptr += 2;
3232 fallbackcmpval *= 2;
3233 }
3234 if (fallbackcmpval & fallback)
3235 clktableptr++;
3236 }
3237
3238 /* adding outputset * 8 may not be correct */
3239 clktable = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]);
3240 if (!clktable) {
3241 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3242 return -ENOENT;
3243 }
3244 scriptptr = clkcmptable(bios, clktable, pxclk);
3245 }
3246
3247 if (!scriptptr) {
3248 NV_ERROR(dev, "LVDS output init script not found\n");
3249 return -ENOENT;
3250 }
3251 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3252
3253 return 0;
3254}
3255
3256int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3257{
3258 /*
3259 * LVDS operations are multiplexed in an effort to present a single API
3260 * which works with two vastly differing underlying structures.
3261 * This acts as the demux
3262 */
3263
3264 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3265 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3266 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3267 uint32_t sel_clk_binding, sel_clk;
3268 int ret;
3269
3270 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3271 (lvds_ver >= 0x30 && script == LVDS_INIT))
3272 return 0;
3273
3274 if (!bios->fp.lvds_init_run) {
3275 bios->fp.lvds_init_run = true;
3276 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3277 }
3278
3279 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3280 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3281 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3282 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3283
3284 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3285
3286 /* don't let script change pll->head binding */
3287 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3288
3289 if (lvds_ver < 0x30)
3290 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3291 else
3292 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3293
3294 bios->fp.last_script_invoc = (script << 1 | head);
3295
3296 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3297 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3298 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3299 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3300
3301 return ret;
3302}
3303
3304struct lvdstableheader {
3305 uint8_t lvds_ver, headerlen, recordlen;
3306};
3307
3308static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3309{
3310 /*
3311 * BMP version (0xa) LVDS table has a simple header of version and
3312 * record length. The BIT LVDS table has the typical BIT table header:
3313 * version byte, header length byte, record length byte, and a byte for
3314 * the maximum number of records that can be held in the table.
3315 */
3316
3317 uint8_t lvds_ver, headerlen, recordlen;
3318
3319 memset(lth, 0, sizeof(struct lvdstableheader));
3320
3321 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3322 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3323 return -EINVAL;
3324 }
3325
3326 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3327
3328 switch (lvds_ver) {
3329 case 0x0a: /* pre NV40 */
3330 headerlen = 2;
3331 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3332 break;
3333 case 0x30: /* NV4x */
3334 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3335 if (headerlen < 0x1f) {
3336 NV_ERROR(dev, "LVDS table header not understood\n");
3337 return -EINVAL;
3338 }
3339 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3340 break;
3341 case 0x40: /* G80/G90 */
3342 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3343 if (headerlen < 0x7) {
3344 NV_ERROR(dev, "LVDS table header not understood\n");
3345 return -EINVAL;
3346 }
3347 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3348 break;
3349 default:
3350 NV_ERROR(dev,
3351 "LVDS table revision %d.%d not currently supported\n",
3352 lvds_ver >> 4, lvds_ver & 0xf);
3353 return -ENOSYS;
3354 }
3355
3356 lth->lvds_ver = lvds_ver;
3357 lth->headerlen = headerlen;
3358 lth->recordlen = recordlen;
3359
3360 return 0;
3361}
3362
3363static int
3364get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3365{
3366 struct drm_nouveau_private *dev_priv = dev->dev_private;
3367
3368 /*
3369 * The fp strap is normally dictated by the "User Strap" in
3370 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3371 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3372 * by the PCI subsystem ID during POST, but not before the previous user
3373 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3374 * read and used instead
3375 */
3376
3377 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3378 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3379
3380 if (dev_priv->card_type >= NV_50)
3381 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3382 else
3383 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3384}
3385
3386static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3387{
3388 uint8_t *fptable;
3389 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3390 int ret, ofs, fpstrapping;
3391 struct lvdstableheader lth;
3392
3393 if (bios->fp.fptablepointer == 0x0) {
3394 /* Apple cards don't have the fp table; the laptops use DDC */
3395 /* The table is also missing on some x86 IGPs */
3396#ifndef __powerpc__
3397 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3398#endif
04a39c57 3399 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 3400 return 0;
3401 }
3402
3403 fptable = &bios->data[bios->fp.fptablepointer];
3404 fptable_ver = fptable[0];
3405
3406 switch (fptable_ver) {
3407 /*
3408 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3409 * version field, and miss one of the spread spectrum/PWM bytes.
3410 * This could affect early GF2Go parts (not seen any appropriate ROMs
3411 * though). Here we assume that a version of 0x05 matches this case
3412 * (combining with a BMP version check would be better), as the
3413 * common case for the panel type field is 0x0005, and that is in
3414 * fact what we are reading the first byte of.
3415 */
3416 case 0x05: /* some NV10, 11, 15, 16 */
3417 recordlen = 42;
3418 ofs = -1;
3419 break;
3420 case 0x10: /* some NV15/16, and NV11+ */
3421 recordlen = 44;
3422 ofs = 0;
3423 break;
3424 case 0x20: /* NV40+ */
3425 headerlen = fptable[1];
3426 recordlen = fptable[2];
3427 fpentries = fptable[3];
3428 /*
3429 * fptable[4] is the minimum
3430 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3431 */
04a39c57 3432 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 3433 ofs = -7;
3434 break;
3435 default:
3436 NV_ERROR(dev,
3437 "FP table revision %d.%d not currently supported\n",
3438 fptable_ver >> 4, fptable_ver & 0xf);
3439 return -ENOSYS;
3440 }
3441
3442 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3443 return 0;
3444
3445 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3446 if (ret)
3447 return ret;
3448
3449 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3450 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3451 lth.headerlen + 1;
3452 bios->fp.xlatwidth = lth.recordlen;
3453 }
3454 if (bios->fp.fpxlatetableptr == 0x0) {
3455 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3456 return -EINVAL;
3457 }
3458
3459 fpstrapping = get_fp_strap(dev, bios);
3460
3461 fpindex = bios->data[bios->fp.fpxlatetableptr +
3462 fpstrapping * bios->fp.xlatwidth];
3463
3464 if (fpindex > fpentries) {
3465 NV_ERROR(dev, "Bad flat panel table index\n");
3466 return -ENOENT;
3467 }
3468
3469 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3470 if (lth.lvds_ver > 0x10)
04a39c57 3471 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 3472
3473 /*
3474 * If either the strap or xlated fpindex value are 0xf there is no
3475 * panel using a strap-derived bios mode present. this condition
3476 * includes, but is different from, the DDC panel indicator above
3477 */
3478 if (fpstrapping == 0xf || fpindex == 0xf)
3479 return 0;
3480
3481 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3482 recordlen * fpindex + ofs;
3483
3484 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3485 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3486 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3487 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3488
3489 return 0;
3490}
3491
3492bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3493{
3494 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3495 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3496 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3497
3498 if (!mode) /* just checking whether we can produce a mode */
3499 return bios->fp.mode_ptr;
3500
3501 memset(mode, 0, sizeof(struct drm_display_mode));
3502 /*
3503 * For version 1.0 (version in byte 0):
3504 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3505 * single/dual link, and type (TFT etc.)
3506 * bytes 3-6 are bits per colour in RGBX
3507 */
3508 mode->clock = ROM16(mode_entry[7]) * 10;
3509 /* bytes 9-10 is HActive */
3510 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3511 /*
3512 * bytes 13-14 is HValid Start
3513 * bytes 15-16 is HValid End
3514 */
3515 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3516 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3517 mode->htotal = ROM16(mode_entry[21]) + 1;
3518 /* bytes 23-24, 27-30 similarly, but vertical */
3519 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3520 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3521 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3522 mode->vtotal = ROM16(mode_entry[35]) + 1;
3523 mode->flags |= (mode_entry[37] & 0x10) ?
3524 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3525 mode->flags |= (mode_entry[37] & 0x1) ?
3526 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3527 /*
3528 * bytes 38-39 relate to spread spectrum settings
3529 * bytes 40-43 are something to do with PWM
3530 */
3531
3532 mode->status = MODE_OK;
3533 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3534 drm_mode_set_name(mode);
3535 return bios->fp.mode_ptr;
3536}
3537
3538int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3539{
3540 /*
3541 * The LVDS table header is (mostly) described in
3542 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3543 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3544 * straps are not being used for the panel, this specifies the frequency
3545 * at which modes should be set up in the dual link style.
3546 *
3547 * Following the header, the BMP (ver 0xa) table has several records,
3548 * indexed by a seperate xlat table, indexed in turn by the fp strap in
3549 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3550 * numbers for use by INIT_SUB which controlled panel init and power,
3551 * and finally a dword of ms to sleep between power off and on
3552 * operations.
3553 *
3554 * In the BIT versions, the table following the header serves as an
3555 * integrated config and xlat table: the records in the table are
3556 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3557 * two bytes - the first as a config byte, the second for indexing the
3558 * fp mode table pointed to by the BIT 'D' table
3559 *
3560 * DDC is not used until after card init, so selecting the correct table
3561 * entry and setting the dual link flag for EDID equipped panels,
3562 * requiring tests against the native-mode pixel clock, cannot be done
3563 * until later, when this function should be called with non-zero pxclk
3564 */
3565 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3566 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3567 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3568 struct lvdstableheader lth;
3569 uint16_t lvdsofs;
04a39c57 3570 int ret, chip_version = bios->chip_version;
6ee73861
BS		 3571
3572 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3573 if (ret)
3574 return ret;
3575
3576 switch (lth.lvds_ver) {
3577 case 0x0a: /* pre NV40 */
3578 lvdsmanufacturerindex = bios->data[
3579 bios->fp.fpxlatemanufacturertableptr +
3580 fpstrapping];
3581
3582 /* we're done if this isn't the EDID panel case */
3583 if (!pxclk)
3584 break;
3585
3586 if (chip_version < 0x25) {
3587 /* nv17 behaviour
3588 *
3589 * It seems the old style lvds script pointer is reused
3590 * to select 18/24 bit colour depth for EDID panels.
3591 */
3592 lvdsmanufacturerindex =
3593 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3594 2 : 0;
3595 if (pxclk >= bios->fp.duallink_transition_clk)
3596 lvdsmanufacturerindex++;
3597 } else if (chip_version < 0x30) {
3598 /* nv28 behaviour (off-chip encoder)
3599 *
3600 * nv28 does a complex dance of first using byte 121 of
3601 * the EDID to choose the lvdsmanufacturerindex, then
3602 * later attempting to match the EDID manufacturer and
3603 * product IDs in a table (signature 'pidt' (panel id
3604 * table?)), setting an lvdsmanufacturerindex of 0 and
3605 * an fp strap of the match index (or 0xf if none)
3606 */
3607 lvdsmanufacturerindex = 0;
3608 } else {
3609 /* nv31, nv34 behaviour */
3610 lvdsmanufacturerindex = 0;
3611 if (pxclk >= bios->fp.duallink_transition_clk)
3612 lvdsmanufacturerindex = 2;
3613 if (pxclk >= 140000)
3614 lvdsmanufacturerindex = 3;
3615 }
3616
3617 /*
3618 * nvidia set the high nibble of (cr57=f, cr58) to
3619 * lvdsmanufacturerindex in this case; we don't
3620 */
3621 break;
3622 case 0x30: /* NV4x */
3623 case 0x40: /* G80/G90 */
3624 lvdsmanufacturerindex = fpstrapping;
3625 break;
3626 default:
3627 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3628 return -ENOSYS;
3629 }
3630
3631 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3632 switch (lth.lvds_ver) {
3633 case 0x0a:
3634 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3635 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3636 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3637 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3638 *if_is_24bit = bios->data[lvdsofs] & 16;
3639 break;
3640 case 0x30:
3641 /*
3642 * My money would be on there being a 24 bit interface bit in
3643 * this table, but I have no example of a laptop bios with a
3644 * 24 bit panel to confirm that. Hence we shout loudly if any
3645 * bit other than bit 0 is set (I've not even seen bit 1)
3646 */
3647 if (bios->data[lvdsofs] > 1)
3648 NV_ERROR(dev,
3649 "You have a very unusual laptop display; please report it\n");
3650 /*
3651 * No sign of the "power off for reset" or "reset for panel
3652 * on" bits, but it's safer to assume we should
3653 */
3654 bios->fp.power_off_for_reset = true;
3655 bios->fp.reset_after_pclk_change = true;
3656 /*
3657 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
3658 * over-written, and BITbit1 isn't used
3659 */
3660 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3661 bios->fp.BITbit1 = bios->data[lvdsofs] & 2;
3662 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3663 break;
3664 case 0x40:
3665 bios->fp.dual_link = bios->data[lvdsofs] & 1;
3666 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3667 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3668 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3669 break;
3670 }
3671
3672 /* set dual_link flag for EDID case */
3673 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3674 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3675
3676 *dl = bios->fp.dual_link;
3677
3678 return 0;
3679}
3680
3681static uint8_t *
3682bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
3683 uint16_t record, int record_len, int record_nr)
3684{
3685 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3686 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3687 uint32_t entry;
3688 uint16_t table;
3689 int i, v;
3690
3691 for (i = 0; i < record_nr; i++, record += record_len) {
3692 table = ROM16(bios->data[record]);
3693 if (!table)
3694 continue;
3695 entry = ROM32(bios->data[table]);
3696
3697 v = (entry & 0x000f0000) >> 16;
3698 if (!(v & dcbent->or))
3699 continue;
3700
3701 v = (entry & 0x000000f0) >> 4;
3702 if (v != dcbent->location)
3703 continue;
3704
3705 v = (entry & 0x0000000f);
3706 if (v != dcbent->type)
3707 continue;
3708
3709 return &bios->data[table];
3710 }
3711
3712 return NULL;
3713}
3714
3715void *
3716nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
3717 int *length)
3718{
3719 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3720 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3721 uint8_t *table;
3722
3723 if (!bios->display.dp_table_ptr) {
3724 NV_ERROR(dev, "No pointer to DisplayPort table\n");
3725 return NULL;
3726 }
3727 table = &bios->data[bios->display.dp_table_ptr];
3728
3729 if (table[0] != 0x21) {
3730 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
3731 table[0]);
3732 return NULL;
3733 }
3734
3735 *length = table[4];
3736 return bios_output_config_match(dev, dcbent,
3737 bios->display.dp_table_ptr + table[1],
3738 table[2], table[3]);
3739}
3740
3741int
3742nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
3743 uint32_t sub, int pxclk)
3744{
3745 /*
3746 * The display script table is located by the BIT 'U' table.
3747 *
3748 * It contains an array of pointers to various tables describing
3749 * a particular output type. The first 32-bits of the output
3750 * tables contains similar information to a DCB entry, and is
3751 * used to decide whether that particular table is suitable for
3752 * the output you want to access.
3753 *
3754 * The "record header length" field here seems to indicate the
3755 * offset of the first configuration entry in the output tables.
3756 * This is 10 on most cards I've seen, but 12 has been witnessed
3757 * on DP cards, and there's another script pointer within the
3758 * header.
3759 *
3760 * offset + 0 ( 8 bits): version
3761 * offset + 1 ( 8 bits): header length
3762 * offset + 2 ( 8 bits): record length
3763 * offset + 3 ( 8 bits): number of records
3764 * offset + 4 ( 8 bits): record header length
3765 * offset + 5 (16 bits): pointer to first output script table
3766 */
3767
3768 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3769 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3770 uint8_t *table = &bios->data[bios->display.script_table_ptr];
3771 uint8_t *otable = NULL;
3772 uint16_t script;
3773 int i = 0;
3774
3775 if (!bios->display.script_table_ptr) {
3776 NV_ERROR(dev, "No pointer to output script table\n");
3777 return 1;
3778 }
3779
3780 /*
3781 * Nothing useful has been in any of the pre-2.0 tables I've seen,
3782 * so until they are, we really don't need to care.
3783 */
3784 if (table[0] < 0x20)
3785 return 1;
3786
3787 if (table[0] != 0x20 && table[0] != 0x21) {
3788 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
3789 table[0]);
3790 return 1;
3791 }
3792
3793 /*
3794 * The output script tables describing a particular output type
3795 * look as follows:
3796 *
3797 * offset + 0 (32 bits): output this table matches (hash of DCB)
3798 * offset + 4 ( 8 bits): unknown
3799 * offset + 5 ( 8 bits): number of configurations
3800 * offset + 6 (16 bits): pointer to some script
3801 * offset + 8 (16 bits): pointer to some script
3802 *
3803 * headerlen == 10
3804 * offset + 10 : configuration 0
3805 *
3806 * headerlen == 12
3807 * offset + 10 : pointer to some script
3808 * offset + 12 : configuration 0
3809 *
3810 * Each config entry is as follows:
3811 *
3812 * offset + 0 (16 bits): unknown, assumed to be a match value
3813 * offset + 2 (16 bits): pointer to script table (clock set?)
3814 * offset + 4 (16 bits): pointer to script table (reset?)
3815 *
3816 * There doesn't appear to be a count value to say how many
3817 * entries exist in each script table, instead, a 0 value in
3818 * the first 16-bit word seems to indicate both the end of the
3819 * list and the default entry. The second 16-bit word in the
3820 * script tables is a pointer to the script to execute.
3821 */
3822
ef2bb506 3823 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 3824 dcbent->type, dcbent->location, dcbent->or);
3825 otable = bios_output_config_match(dev, dcbent, table[1] +
3826 bios->display.script_table_ptr,
3827 table[2], table[3]);
3828 if (!otable) {
3829 NV_ERROR(dev, "Couldn't find matching output script table\n");
3830 return 1;
3831 }
3832
3833 if (pxclk < -2 || pxclk > 0) {
3834 /* Try to find matching script table entry */
3835 for (i = 0; i < otable[5]; i++) {
3836 if (ROM16(otable[table[4] + i*6]) == sub)
3837 break;
3838 }
3839
3840 if (i == otable[5]) {
3841 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
3842 "using first\n",
3843 sub, dcbent->type, dcbent->or);
3844 i = 0;
3845 }
3846 }
3847
6ee73861
BS		 3848 if (pxclk == 0) {
3849 script = ROM16(otable[6]);
3850 if (!script) {
ef2bb506 3851 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 3852 return 1;
3853 }
3854
3855 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 3856 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3857 } else
3858 if (pxclk == -1) {
3859 script = ROM16(otable[8]);
3860 if (!script) {
ef2bb506 3861 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 3862 return 1;
3863 }
3864
3865 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 3866 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3867 } else
3868 if (pxclk == -2) {
3869 if (table[4] >= 12)
3870 script = ROM16(otable[10]);
3871 else
3872 script = 0;
3873 if (!script) {
ef2bb506 3874 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 3875 return 1;
3876 }
3877
3878 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 3879 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3880 } else
3881 if (pxclk > 0) {
3882 script = ROM16(otable[table[4] + i*6 + 2]);
3883 if (script)
3884 script = clkcmptable(bios, script, pxclk);
3885 if (!script) {
3886 NV_ERROR(dev, "clock script 0 not found\n");
3887 return 1;
3888 }
3889
3890 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 3891 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3892 } else
3893 if (pxclk < 0) {
3894 script = ROM16(otable[table[4] + i*6 + 4]);
3895 if (script)
3896 script = clkcmptable(bios, script, -pxclk);
3897 if (!script) {
ef2bb506 3898 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 3899 return 1;
3900 }
3901
3902 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 3903 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 3904 }
3905
3906 return 0;
3907}
3908
3909
3910int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
3911{
3912 /*
3913 * the pxclk parameter is in kHz
3914 *
3915 * This runs the TMDS regs setting code found on BIT bios cards
3916 *
3917 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
3918 * ffs(or) == 3, use the second.
3919 */
3920
3921 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 3922 struct nvbios *bios = &dev_priv->vbios;
3923 int cv = bios->chip_version;
6ee73861
BS		 3924 uint16_t clktable = 0, scriptptr;
3925 uint32_t sel_clk_binding, sel_clk;
3926
3927 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
3928 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
3929 dcbent->location != DCB_LOC_ON_CHIP)
3930 return 0;
3931
3932 switch (ffs(dcbent->or)) {
3933 case 1:
3934 clktable = bios->tmds.output0_script_ptr;
3935 break;
3936 case 2:
3937 case 3:
3938 clktable = bios->tmds.output1_script_ptr;
3939 break;
3940 }
3941
3942 if (!clktable) {
3943 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3944 return -EINVAL;
3945 }
3946
3947 scriptptr = clkcmptable(bios, clktable, pxclk);
3948
3949 if (!scriptptr) {
3950 NV_ERROR(dev, "TMDS output init script not found\n");
3951 return -ENOENT;
3952 }
3953
3954 /* don't let script change pll->head binding */
3955 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3956 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
3957 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3958 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3959
3960 return 0;
3961}
3962
3963int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
3964{
3965 /*
3966 * PLL limits table
3967 *
3968 * Version 0x10: NV30, NV31
3969 * One byte header (version), one record of 24 bytes
3970 * Version 0x11: NV36 - Not implemented
3971 * Seems to have same record style as 0x10, but 3 records rather than 1
3972 * Version 0x20: Found on Geforce 6 cards
3973 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
3974 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
3975 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
3976 * length in general, some (integrated) have an extra configuration byte
3977 * Version 0x30: Found on Geforce 8, separates the register mapping
3978 * from the limits tables.
3979 */
3980
3981 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 3982 struct nvbios *bios = &dev_priv->vbios;
3983 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 3984 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
3985 uint32_t crystal_strap_mask, crystal_straps;
3986
3987 if (!bios->pll_limit_tbl_ptr) {
3988 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
3989 cv >= 0x40) {
3990 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
3991 return -EINVAL;
3992 }
3993 } else
3994 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
3995
3996 crystal_strap_mask = 1 << 6;
3997 /* open coded dev->twoHeads test */
3998 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
3999 crystal_strap_mask |= 1 << 22;
4000 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4001 crystal_strap_mask;
4002
4003 switch (pll_lim_ver) {
4004 /*
4005 * We use version 0 to indicate a pre limit table bios (single stage
4006 * pll) and load the hard coded limits instead.
4007 */
4008 case 0:
4009 break;
4010 case 0x10:
4011 case 0x11:
4012 /*
4013 * Strictly v0x11 has 3 entries, but the last two don't seem
4014 * to get used.
4015 */
4016 headerlen = 1;
4017 recordlen = 0x18;
4018 entries = 1;
4019 pllindex = 0;
4020 break;
4021 case 0x20:
4022 case 0x21:
4023 case 0x30:
4024 case 0x40:
4025 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4026 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4027 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4028 break;
4029 default:
4030 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4031 "supported\n", pll_lim_ver);
4032 return -ENOSYS;
4033 }
4034
4035 /* initialize all members to zero */
4036 memset(pll_lim, 0, sizeof(struct pll_lims));
4037
4038 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4039 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4040
4041 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4042 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4043 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4044 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4045 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4046 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4047 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4048
4049 /* these values taken from nv30/31/36 */
4050 pll_lim->vco1.min_n = 0x1;
4051 if (cv == 0x36)
4052 pll_lim->vco1.min_n = 0x5;
4053 pll_lim->vco1.max_n = 0xff;
4054 pll_lim->vco1.min_m = 0x1;
4055 pll_lim->vco1.max_m = 0xd;
4056 pll_lim->vco2.min_n = 0x4;
4057 /*
4058 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4059 * table version (apart from nv35)), N2 is compared to
4060 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4061 * save a comparison
4062 */
4063 pll_lim->vco2.max_n = 0x28;
4064 if (cv == 0x30 || cv == 0x35)
4065 /* only 5 bits available for N2 on nv30/35 */
4066 pll_lim->vco2.max_n = 0x1f;
4067 pll_lim->vco2.min_m = 0x1;
4068 pll_lim->vco2.max_m = 0x4;
4069 pll_lim->max_log2p = 0x7;
4070 pll_lim->max_usable_log2p = 0x6;
4071 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4072 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4073 uint32_t reg = 0; /* default match */
4074 uint8_t *pll_rec;
4075 int i;
4076
4077 /*
4078 * First entry is default match, if nothing better. warn if
4079 * reg field nonzero
4080 */
4081 if (ROM32(bios->data[plloffs]))
4082 NV_WARN(dev, "Default PLL limit entry has non-zero "
4083 "register field\n");
4084
4085 if (limit_match > MAX_PLL_TYPES)
4086 /* we've been passed a reg as the match */
4087 reg = limit_match;
4088 else /* limit match is a pll type */
4089 for (i = 1; i < entries && !reg; i++) {
4090 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]);
4091
4092 if (limit_match == NVPLL &&
4093 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000))
4094 reg = cmpreg;
4095 if (limit_match == MPLL &&
4096 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020))
4097 reg = cmpreg;
4098 if (limit_match == VPLL1 &&
4099 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010))
4100 reg = cmpreg;
4101 if (limit_match == VPLL2 &&
4102 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018))
4103 reg = cmpreg;
4104 }
4105
4106 for (i = 1; i < entries; i++)
4107 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) {
4108 pllindex = i;
4109 break;
4110 }
4111
4112 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4113
4114 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4115 pllindex ? reg : 0);
4116
4117 /*
4118 * Frequencies are stored in tables in MHz, kHz are more
4119 * useful, so we convert.
4120 */
4121
4122 /* What output frequencies can each VCO generate? */
4123 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4124 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4125 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4126 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4127
4128 /* What input frequencies they accept (past the m-divider)? */
4129 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4130 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4131 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4132 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4133
4134 /* What values are accepted as multiplier and divider? */
4135 pll_lim->vco1.min_n = pll_rec[20];
4136 pll_lim->vco1.max_n = pll_rec[21];
4137 pll_lim->vco1.min_m = pll_rec[22];
4138 pll_lim->vco1.max_m = pll_rec[23];
4139 pll_lim->vco2.min_n = pll_rec[24];
4140 pll_lim->vco2.max_n = pll_rec[25];
4141 pll_lim->vco2.min_m = pll_rec[26];
4142 pll_lim->vco2.max_m = pll_rec[27];
4143
4144 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4145 if (pll_lim->max_log2p > 0x7)
4146 /* pll decoding in nv_hw.c assumes never > 7 */
4147 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4148 pll_lim->max_log2p);
4149 if (cv < 0x60)
4150 pll_lim->max_usable_log2p = 0x6;
4151 pll_lim->log2p_bias = pll_rec[30];
4152
4153 if (recordlen > 0x22)
4154 pll_lim->refclk = ROM32(pll_rec[31]);
4155
4156 if (recordlen > 0x23 && pll_rec[35])
4157 NV_WARN(dev,
4158 "Bits set in PLL configuration byte (%x)\n",
4159 pll_rec[35]);
4160
4161 /* C51 special not seen elsewhere */
4162 if (cv == 0x51 && !pll_lim->refclk) {
4163 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4164
4165 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) ||
4166 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) {
4167 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4168 pll_lim->refclk = 200000;
4169 else
4170 pll_lim->refclk = 25000;
4171 }
4172 }
4173 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4174 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4175 uint8_t *record = NULL;
4176 int i;
4177
4178 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4179 limit_match);
4180
4181 for (i = 0; i < entries; i++, entry += recordlen) {
4182 if (ROM32(entry[3]) == limit_match) {
4183 record = &bios->data[ROM16(entry[1])];
4184 break;
4185 }
4186 }
4187
4188 if (!record) {
4189 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4190 "limits table", limit_match);
4191 return -ENOENT;
4192 }
4193
4194 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4195 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4196 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4197 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4198 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4199 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4200 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4201 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4202 pll_lim->vco1.min_n = record[16];
4203 pll_lim->vco1.max_n = record[17];
4204 pll_lim->vco1.min_m = record[18];
4205 pll_lim->vco1.max_m = record[19];
4206 pll_lim->vco2.min_n = record[20];
4207 pll_lim->vco2.max_n = record[21];
4208 pll_lim->vco2.min_m = record[22];
4209 pll_lim->vco2.max_m = record[23];
4210 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4211 pll_lim->log2p_bias = record[27];
4212 pll_lim->refclk = ROM32(record[28]);
4213 } else if (pll_lim_ver) { /* ver 0x40 */
4214 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4215 uint8_t *record = NULL;
4216 int i;
4217
4218 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4219 limit_match);
4220
4221 for (i = 0; i < entries; i++, entry += recordlen) {
4222 if (ROM32(entry[3]) == limit_match) {
4223 record = &bios->data[ROM16(entry[1])];
4224 break;
4225 }
4226 }
4227
4228 if (!record) {
4229 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4230 "limits table", limit_match);
4231 return -ENOENT;
4232 }
4233
4234 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4235 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4236 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4237 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4238 pll_lim->vco1.min_m = record[8];
4239 pll_lim->vco1.max_m = record[9];
4240 pll_lim->vco1.min_n = record[10];
4241 pll_lim->vco1.max_n = record[11];
4242 pll_lim->min_p = record[12];
4243 pll_lim->max_p = record[13];
4244 /* where did this go to?? */
4245 if (limit_match == 0x00614100 || limit_match == 0x00614900)
4246 pll_lim->refclk = 27000;
4247 else
4248 pll_lim->refclk = 100000;
4249 }
4250
4251 /*
4252 * By now any valid limit table ought to have set a max frequency for
4253 * vco1, so if it's zero it's either a pre limit table bios, or one
4254 * with an empty limit table (seen on nv18)
4255 */
4256 if (!pll_lim->vco1.maxfreq) {
4257 pll_lim->vco1.minfreq = bios->fminvco;
4258 pll_lim->vco1.maxfreq = bios->fmaxvco;
4259 pll_lim->vco1.min_inputfreq = 0;
4260 pll_lim->vco1.max_inputfreq = INT_MAX;
4261 pll_lim->vco1.min_n = 0x1;
4262 pll_lim->vco1.max_n = 0xff;
4263 pll_lim->vco1.min_m = 0x1;
4264 if (crystal_straps == 0) {
4265 /* nv05 does this, nv11 doesn't, nv10 unknown */
4266 if (cv < 0x11)
4267 pll_lim->vco1.min_m = 0x7;
4268 pll_lim->vco1.max_m = 0xd;
4269 } else {
4270 if (cv < 0x11)
4271 pll_lim->vco1.min_m = 0x8;
4272 pll_lim->vco1.max_m = 0xe;
4273 }
4274 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4275 pll_lim->max_log2p = 4;
4276 else
4277 pll_lim->max_log2p = 5;
4278 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4279 }
4280
4281 if (!pll_lim->refclk)
4282 switch (crystal_straps) {
4283 case 0:
4284 pll_lim->refclk = 13500;
4285 break;
4286 case (1 << 6):
4287 pll_lim->refclk = 14318;
4288 break;
4289 case (1 << 22):
4290 pll_lim->refclk = 27000;
4291 break;
4292 case (1 << 22 | 1 << 6):
4293 pll_lim->refclk = 25000;
4294 break;
4295 }
4296
4297#if 0 /* for easy debugging */
4298 ErrorF("pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4299 ErrorF("pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4300 ErrorF("pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4301 ErrorF("pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4302
4303 ErrorF("pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4304 ErrorF("pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4305 ErrorF("pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4306 ErrorF("pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4307
4308 ErrorF("pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4309 ErrorF("pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4310 ErrorF("pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4311 ErrorF("pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4312 ErrorF("pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4313 ErrorF("pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4314 ErrorF("pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4315 ErrorF("pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4316
4317 ErrorF("pll.max_log2p: %d\n", pll_lim->max_log2p);
4318 ErrorF("pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4319
4320 ErrorF("pll.refclk: %d\n", pll_lim->refclk);
4321#endif
4322
4323 return 0;
4324}
4325
4326static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4327{
4328 /*
4329 * offset + 0 (8 bits): Micro version
4330 * offset + 1 (8 bits): Minor version
4331 * offset + 2 (8 bits): Chip version
4332 * offset + 3 (8 bits): Major version
4333 */
4334
4335 bios->major_version = bios->data[offset + 3];
04a39c57 4336 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 4337 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4338 bios->data[offset + 3], bios->data[offset + 2],
4339 bios->data[offset + 1], bios->data[offset]);
4340}
4341
4342static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4343{
4344 /*
4345 * Parses the init table segment for pointers used in script execution.
4346 *
4347 * offset + 0 (16 bits): init script tables pointer
4348 * offset + 2 (16 bits): macro index table pointer
4349 * offset + 4 (16 bits): macro table pointer
4350 * offset + 6 (16 bits): condition table pointer
4351 * offset + 8 (16 bits): io condition table pointer
4352 * offset + 10 (16 bits): io flag condition table pointer
4353 * offset + 12 (16 bits): init function table pointer
4354 */
4355
4356 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4357 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4358 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4359 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4360 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4361 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4362 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4363}
4364
4365static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4366{
4367 /*
4368 * Parses the load detect values for g80 cards.
4369 *
4370 * offset + 0 (16 bits): loadval table pointer
4371 */
4372
4373 uint16_t load_table_ptr;
4374 uint8_t version, headerlen, entrylen, num_entries;
4375
4376 if (bitentry->length != 3) {
4377 NV_ERROR(dev, "Do not understand BIT A table\n");
4378 return -EINVAL;
4379 }
4380
4381 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4382
4383 if (load_table_ptr == 0x0) {
4384 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
4385 return -EINVAL;
4386 }
4387
4388 version = bios->data[load_table_ptr];
4389
4390 if (version != 0x10) {
4391 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4392 version >> 4, version & 0xF);
4393 return -ENOSYS;
4394 }
4395
4396 headerlen = bios->data[load_table_ptr + 1];
4397 entrylen = bios->data[load_table_ptr + 2];
4398 num_entries = bios->data[load_table_ptr + 3];
4399
4400 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4401 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4402 return -EINVAL;
4403 }
4404
4405 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 4406 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 4407
4408 return 0;
4409}
4410
4411static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4412{
4413 /*
4414 * offset + 8 (16 bits): PLL limits table pointer
4415 *
4416 * There's more in here, but that's unknown.
4417 */
4418
4419 if (bitentry->length < 10) {
4420 NV_ERROR(dev, "Do not understand BIT C table\n");
4421 return -EINVAL;
4422 }
4423
4424 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4425
4426 return 0;
4427}
4428
4429static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4430{
4431 /*
4432 * Parses the flat panel table segment that the bit entry points to.
4433 * Starting at bitentry->offset:
4434 *
4435 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4436 * records beginning with a freq.
4437 * offset + 2 (16 bits): mode table pointer
4438 */
4439
4440 if (bitentry->length != 4) {
4441 NV_ERROR(dev, "Do not understand BIT display table\n");
4442 return -EINVAL;
4443 }
4444
4445 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4446
4447 return 0;
4448}
4449
4450static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4451{
4452 /*
4453 * Parses the init table segment that the bit entry points to.
4454 *
4455 * See parse_script_table_pointers for layout
4456 */
4457
4458 if (bitentry->length < 14) {
4459 NV_ERROR(dev, "Do not understand init table\n");
4460 return -EINVAL;
4461 }
4462
4463 parse_script_table_pointers(bios, bitentry->offset);
4464
4465 if (bitentry->length >= 16)
4466 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4467 if (bitentry->length >= 18)
4468 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4469
4470 return 0;
4471}
4472
4473static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4474{
4475 /*
4476 * BIT 'i' (info?) table
4477 *
4478 * offset + 0 (32 bits): BIOS version dword (as in B table)
4479 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4480 * offset + 13 (16 bits): pointer to table containing DAC load
4481 * detection comparison values
4482 *
4483 * There's other things in the table, purpose unknown
4484 */
4485
4486 uint16_t daccmpoffset;
4487 uint8_t dacver, dacheaderlen;
4488
4489 if (bitentry->length < 6) {
4490 NV_ERROR(dev, "BIT i table too short for needed information\n");
4491 return -EINVAL;
4492 }
4493
4494 parse_bios_version(dev, bios, bitentry->offset);
4495
4496 /*
4497 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4498 * Quadro identity crisis), other bits possibly as for BMP feature byte
4499 */
4500 bios->feature_byte = bios->data[bitentry->offset + 5];
4501 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4502
4503 if (bitentry->length < 15) {
4504 NV_WARN(dev, "BIT i table not long enough for DAC load "
4505 "detection comparison table\n");
4506 return -EINVAL;
4507 }
4508
4509 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4510
4511 /* doesn't exist on g80 */
4512 if (!daccmpoffset)
4513 return 0;
4514
4515 /*
4516 * The first value in the table, following the header, is the
4517 * comparison value, the second entry is a comparison value for
4518 * TV load detection.
4519 */
4520
4521 dacver = bios->data[daccmpoffset];
4522 dacheaderlen = bios->data[daccmpoffset + 1];
4523
4524 if (dacver != 0x00 && dacver != 0x10) {
4525 NV_WARN(dev, "DAC load detection comparison table version "
4526 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4527 return -ENOSYS;
4528 }
4529
04a39c57
BS		 4530 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4531 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 4532
4533 return 0;
4534}
4535
4536static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4537{
4538 /*
4539 * Parses the LVDS table segment that the bit entry points to.
4540 * Starting at bitentry->offset:
4541 *
4542 * offset + 0 (16 bits): LVDS strap xlate table pointer
4543 */
4544
4545 if (bitentry->length != 2) {
4546 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4547 return -EINVAL;
4548 }
4549
4550 /*
4551 * No idea if it's still called the LVDS manufacturer table, but
4552 * the concept's close enough.
4553 */
4554 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4555
4556 return 0;
4557}
4558
4559static int
4560parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4561 struct bit_entry *bitentry)
4562{
4563 /*
4564 * offset + 2 (8 bits): number of options in an
4565 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4566 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4567 * restrict option selection
4568 *
4569 * There's a bunch of bits in this table other than the RAM restrict
4570 * stuff that we don't use - their use currently unknown
4571 */
4572
6ee73861
BS		 4573 /*
4574 * Older bios versions don't have a sufficiently long table for
4575 * what we want
4576 */
4577 if (bitentry->length < 0x5)
4578 return 0;
4579
4580 if (bitentry->id[1] < 2) {
37383650
MK		 4581 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4582 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 4583 } else {
37383650
MK		 4584 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4585 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 4586 }
4587
6ee73861
BS		 4588 return 0;
4589}
4590
4591static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4592{
4593 /*
4594 * Parses the pointer to the TMDS table
4595 *
4596 * Starting at bitentry->offset:
4597 *
4598 * offset + 0 (16 bits): TMDS table pointer
4599 *
4600 * The TMDS table is typically found just before the DCB table, with a
4601 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4602 * length?)
4603 *
4604 * At offset +7 is a pointer to a script, which I don't know how to
4605 * run yet.
4606 * At offset +9 is a pointer to another script, likewise
4607 * Offset +11 has a pointer to a table where the first word is a pxclk
4608 * frequency and the second word a pointer to a script, which should be
4609 * run if the comparison pxclk frequency is less than the pxclk desired.
4610 * This repeats for decreasing comparison frequencies
4611 * Offset +13 has a pointer to a similar table
4612 * The selection of table (and possibly +7/+9 script) is dictated by
4613 * "or" from the DCB.
4614 */
4615
4616 uint16_t tmdstableptr, script1, script2;
4617
4618 if (bitentry->length != 2) {
4619 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4620 return -EINVAL;
4621 }
4622
4623 tmdstableptr = ROM16(bios->data[bitentry->offset]);
4624
4625 if (tmdstableptr == 0x0) {
4626 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4627 return -EINVAL;
4628 }
4629
4630 /* nv50+ has v2.0, but we don't parse it atm */
4631 if (bios->data[tmdstableptr] != 0x11) {
4632 NV_WARN(dev,
4633 "TMDS table revision %d.%d not currently supported\n",
4634 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4635 return -ENOSYS;
4636 }
4637
4638 /*
4639 * These two scripts are odd: they don't seem to get run even when
4640 * they are not stubbed.
4641 */
4642 script1 = ROM16(bios->data[tmdstableptr + 7]);
4643 script2 = ROM16(bios->data[tmdstableptr + 9]);
4644 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4645 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4646
4647 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4648 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4649
4650 return 0;
4651}
4652
4653static int
4654parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4655 struct bit_entry *bitentry)
4656{
4657 /*
4658 * Parses the pointer to the G80 output script tables
4659 *
4660 * Starting at bitentry->offset:
4661 *
4662 * offset + 0 (16 bits): output script table pointer
4663 */
4664
4665 uint16_t outputscripttableptr;
4666
4667 if (bitentry->length != 3) {
4668 NV_ERROR(dev, "Do not understand BIT U table\n");
4669 return -EINVAL;
4670 }
4671
4672 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4673 bios->display.script_table_ptr = outputscripttableptr;
4674 return 0;
4675}
4676
4677static int
4678parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4679 struct bit_entry *bitentry)
4680{
4681 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
4682 return 0;
4683}
4684
4685struct bit_table {
4686 const char id;
4687 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4688};
4689
4690#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4691
4692static int
4693parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4694 struct bit_table *table)
4695{
4696 struct drm_device *dev = bios->dev;
4697 uint8_t maxentries = bios->data[bitoffset + 4];
4698 int i, offset;
4699 struct bit_entry bitentry;
4700
4701 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) {
4702 bitentry.id[0] = bios->data[offset];
4703
4704 if (bitentry.id[0] != table->id)
4705 continue;
4706
4707 bitentry.id[1] = bios->data[offset + 1];
4708 bitentry.length = ROM16(bios->data[offset + 2]);
4709 bitentry.offset = ROM16(bios->data[offset + 4]);
4710
4711 return table->parse_fn(dev, bios, &bitentry);
4712 }
4713
4714 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4715 return -ENOSYS;
4716}
4717
4718static int
4719parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4720{
4721 int ret;
4722
4723 /*
4724 * The only restriction on parsing order currently is having 'i' first
4725 * for use of bios->*_version or bios->feature_byte while parsing;
4726 * functions shouldn't be actually *doing* anything apart from pulling
4727 * data from the image into the bios struct, thus no interdependencies
4728 */
4729 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4730 if (ret) /* info? */
4731 return ret;
4732 if (bios->major_version >= 0x60) /* g80+ */
4733 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4734 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4735 if (ret)
4736 return ret;
4737 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4738 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4739 if (ret)
4740 return ret;
4741 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4742 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4743 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4744 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
4745 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
4746
4747 return 0;
4748}
4749
4750static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4751{
4752 /*
4753 * Parses the BMP structure for useful things, but does not act on them
4754 *
4755 * offset + 5: BMP major version
4756 * offset + 6: BMP minor version
4757 * offset + 9: BMP feature byte
4758 * offset + 10: BCD encoded BIOS version
4759 *
4760 * offset + 18: init script table pointer (for bios versions < 5.10h)
4761 * offset + 20: extra init script table pointer (for bios
4762 * versions < 5.10h)
4763 *
4764 * offset + 24: memory init table pointer (used on early bios versions)
4765 * offset + 26: SDR memory sequencing setup data table
4766 * offset + 28: DDR memory sequencing setup data table
4767 *
4768 * offset + 54: index of I2C CRTC pair to use for CRT output
4769 * offset + 55: index of I2C CRTC pair to use for TV output
4770 * offset + 56: index of I2C CRTC pair to use for flat panel output
4771 * offset + 58: write CRTC index for I2C pair 0
4772 * offset + 59: read CRTC index for I2C pair 0
4773 * offset + 60: write CRTC index for I2C pair 1
4774 * offset + 61: read CRTC index for I2C pair 1
4775 *
4776 * offset + 67: maximum internal PLL frequency (single stage PLL)
4777 * offset + 71: minimum internal PLL frequency (single stage PLL)
4778 *
4779 * offset + 75: script table pointers, as described in
4780 * parse_script_table_pointers
4781 *
4782 * offset + 89: TMDS single link output A table pointer
4783 * offset + 91: TMDS single link output B table pointer
4784 * offset + 95: LVDS single link output A table pointer
4785 * offset + 105: flat panel timings table pointer
4786 * offset + 107: flat panel strapping translation table pointer
4787 * offset + 117: LVDS manufacturer panel config table pointer
4788 * offset + 119: LVDS manufacturer strapping translation table pointer
4789 *
4790 * offset + 142: PLL limits table pointer
4791 *
4792 * offset + 156: minimum pixel clock for LVDS dual link
4793 */
4794
4795 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
4796 uint16_t bmplength;
4797 uint16_t legacy_scripts_offset, legacy_i2c_offset;
4798
4799 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 4800 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
4801 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
4802 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
4803 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 4804 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 4805 bios->fmaxvco = 256000;
4806 bios->fminvco = 128000;
4807 bios->fp.duallink_transition_clk = 90000;
4808
4809 bmp_version_major = bmp[5];
4810 bmp_version_minor = bmp[6];
4811
4812 NV_TRACE(dev, "BMP version %d.%d\n",
4813 bmp_version_major, bmp_version_minor);
4814
4815 /*
4816 * Make sure that 0x36 is blank and can't be mistaken for a DCB
4817 * pointer on early versions
4818 */
4819 if (bmp_version_major < 5)
4820 *(uint16_t *)&bios->data[0x36] = 0;
4821
4822 /*
4823 * Seems that the minor version was 1 for all major versions prior
4824 * to 5. Version 6 could theoretically exist, but I suspect BIT
4825 * happened instead.
4826 */
4827 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
4828 NV_ERROR(dev, "You have an unsupported BMP version. "
4829 "Please send in your bios\n");
4830 return -ENOSYS;
4831 }
4832
4833 if (bmp_version_major == 0)
4834 /* nothing that's currently useful in this version */
4835 return 0;
4836 else if (bmp_version_major == 1)
4837 bmplength = 44; /* exact for 1.01 */
4838 else if (bmp_version_major == 2)
4839 bmplength = 48; /* exact for 2.01 */
4840 else if (bmp_version_major == 3)
4841 bmplength = 54;
4842 /* guessed - mem init tables added in this version */
4843 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
4844 /* don't know if 5.0 exists... */
4845 bmplength = 62;
4846 /* guessed - BMP I2C indices added in version 4*/
4847 else if (bmp_version_minor < 0x6)
4848 bmplength = 67; /* exact for 5.01 */
4849 else if (bmp_version_minor < 0x10)
4850 bmplength = 75; /* exact for 5.06 */
4851 else if (bmp_version_minor == 0x10)
4852 bmplength = 89; /* exact for 5.10h */
4853 else if (bmp_version_minor < 0x14)
4854 bmplength = 118; /* exact for 5.11h */
4855 else if (bmp_version_minor < 0x24)
4856 /*
4857 * Not sure of version where pll limits came in;
4858 * certainly exist by 0x24 though.
4859 */
4860 /* length not exact: this is long enough to get lvds members */
4861 bmplength = 123;
4862 else if (bmp_version_minor < 0x27)
4863 /*
4864 * Length not exact: this is long enough to get pll limit
4865 * member
4866 */
4867 bmplength = 144;
4868 else
4869 /*
4870 * Length not exact: this is long enough to get dual link
4871 * transition clock.
4872 */
4873 bmplength = 158;
4874
4875 /* checksum */
4876 if (nv_cksum(bmp, 8)) {
4877 NV_ERROR(dev, "Bad BMP checksum\n");
4878 return -EINVAL;
4879 }
4880
4881 /*
4882 * Bit 4 seems to indicate either a mobile bios or a quadro card --
4883 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
4884 * (not nv10gl), bit 5 that the flat panel tables are present, and
4885 * bit 6 a tv bios.
4886 */
4887 bios->feature_byte = bmp[9];
4888
4889 parse_bios_version(dev, bios, offset + 10);
4890
4891 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
4892 bios->old_style_init = true;
4893 legacy_scripts_offset = 18;
4894 if (bmp_version_major < 2)
4895 legacy_scripts_offset -= 4;
4896 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
4897 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
4898
4899 if (bmp_version_major > 2) { /* appears in BMP 3 */
4900 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
4901 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
4902 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
4903 }
4904
4905 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
4906 if (bmplength > 61)
4907 legacy_i2c_offset = offset + 54;
4908 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
4909 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
4910 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
7f245b20
BS		 4911 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
4912 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
4913 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
4914 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 4915
4916 if (bmplength > 74) {
4917 bios->fmaxvco = ROM32(bmp[67]);
4918 bios->fminvco = ROM32(bmp[71]);
4919 }
4920 if (bmplength > 88)
4921 parse_script_table_pointers(bios, offset + 75);
4922 if (bmplength > 94) {
4923 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
4924 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
4925 /*
4926 * Never observed in use with lvds scripts, but is reused for
4927 * 18/24 bit panel interface default for EDID equipped panels
4928 * (if_is_24bit not set directly to avoid any oscillation).
4929 */
4930 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
4931 }
4932 if (bmplength > 108) {
4933 bios->fp.fptablepointer = ROM16(bmp[105]);
4934 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
4935 bios->fp.xlatwidth = 1;
4936 }
4937 if (bmplength > 120) {
4938 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
4939 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
4940 }
4941 if (bmplength > 143)
4942 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
4943
4944 if (bmplength > 157)
4945 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
4946
4947 return 0;
4948}
4949
4950static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
4951{
4952 int i, j;
4953
4954 for (i = 0; i <= (n - len); i++) {
4955 for (j = 0; j < len; j++)
4956 if (data[i + j] != str[j])
4957 break;
4958 if (j == len)
4959 return i;
4960 }
4961
4962 return 0;
4963}
4964
4965static int
4966read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
4967{
4968 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
4969 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
4970 int recordoffset = 0, rdofs = 1, wrofs = 0;
4971 uint8_t port_type = 0;
4972
4973 if (!i2ctable)
4974 return -EINVAL;
4975
4976 if (dcb_version >= 0x30) {
4977 if (i2ctable[0] != dcb_version) /* necessary? */
4978 NV_WARN(dev,
4979 "DCB I2C table version mismatch (%02X vs %02X)\n",
4980 i2ctable[0], dcb_version);
4981 dcb_i2c_ver = i2ctable[0];
4982 headerlen = i2ctable[1];
4983 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
4984 i2c_entries = i2ctable[2];
4985 else
4986 NV_WARN(dev,
4987 "DCB I2C table has more entries than indexable "
761c5a69
MS		 4988 "(%d entries, max %d)\n", i2ctable[2],
4989 DCB_MAX_NUM_I2C_ENTRIES);
6ee73861
BS		 4990 entry_len = i2ctable[3];
4991 /* [4] is i2c_default_indices, read in parse_dcb_table() */
4992 }
4993 /*
4994 * It's your own fault if you call this function on a DCB 1.1 BIOS --
4995 * the test below is for DCB 1.2
4996 */
4997 if (dcb_version < 0x14) {
4998 recordoffset = 2;
4999 rdofs = 0;
5000 wrofs = 1;
5001 }
5002
5003 if (index == 0xf)
5004 return 0;
761c5a69
MS		 5005 if (index >= i2c_entries) {
5006 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
6ee73861
BS		 5007 index, i2ctable[2]);
5008 return -ENOENT;
5009 }
5010 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
5011 NV_ERROR(dev, "DCB I2C entry invalid\n");
5012 return -EINVAL;
5013 }
5014
5015 if (dcb_i2c_ver >= 0x30) {
5016 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
5017
5018 /*
5019 * Fixup for chips using same address offset for read and
5020 * write.
5021 */
5022 if (port_type == 4) /* seen on C51 */
5023 rdofs = wrofs = 1;
5024 if (port_type >= 5) /* G80+ */
5025 rdofs = wrofs = 0;
5026 }
5027
5028 if (dcb_i2c_ver >= 0x40 && port_type != 5 && port_type != 6)
5029 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
5030
5031 i2c->port_type = port_type;
5032 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
5033 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
5034
5035 return 0;
5036}
5037
5038static struct dcb_gpio_entry *
5039new_gpio_entry(struct nvbios *bios)
5040{
7f245b20 5041 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861
BS		 5042
5043 return &gpio->entry[gpio->entries++];
5044}
5045
5046struct dcb_gpio_entry *
5047nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5048{
5049 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5050 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5051 int i;
5052
7f245b20
BS		 5053 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5054 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5055 continue;
5056
7f245b20 5057 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5058 }
5059
5060 return NULL;
5061}
5062
5063static void
5064parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset)
5065{
5066 struct dcb_gpio_entry *gpio;
5067 uint16_t ent = ROM16(bios->data[offset]);
5068 uint8_t line = ent & 0x1f,
5069 tag = ent >> 5 & 0x3f,
5070 flags = ent >> 11 & 0x1f;
5071
5072 if (tag == 0x3f)
5073 return;
5074
5075 gpio = new_gpio_entry(bios);
5076
5077 gpio->tag = tag;
5078 gpio->line = line;
5079 gpio->invert = flags != 4;
5080}
5081
5082static void
5083parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset)
5084{
5085 struct dcb_gpio_entry *gpio;
5086 uint32_t ent = ROM32(bios->data[offset]);
5087 uint8_t line = ent & 0x1f,
5088 tag = ent >> 8 & 0xff;
5089
5090 if (tag == 0xff)
5091 return;
5092
5093 gpio = new_gpio_entry(bios);
5094
5095 /* Currently unused, we may need more fields parsed at some
5096 * point. */
5097 gpio->tag = tag;
5098 gpio->line = line;
5099}
5100
5101static void
5102parse_dcb_gpio_table(struct nvbios *bios)
5103{
5104 struct drm_device *dev = bios->dev;
7f245b20 5105 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr;
6ee73861
BS		 5106 uint8_t *gpio_table = &bios->data[gpio_table_ptr];
5107 int header_len = gpio_table[1],
5108 entries = gpio_table[2],
5109 entry_len = gpio_table[3];
5110 void (*parse_entry)(struct nvbios *, uint16_t) = NULL;
5111 int i;
5112
7f245b20 5113 if (bios->dcb.version >= 0x40) {
6ee73861
BS		 5114 if (gpio_table_ptr && entry_len != 4) {
5115 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5116 return;
5117 }
5118
5119 parse_entry = parse_dcb40_gpio_entry;
5120
7f245b20 5121 } else if (bios->dcb.version >= 0x30) {
6ee73861
BS		 5122 if (gpio_table_ptr && entry_len != 2) {
5123 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n");
5124 return;
5125 }
5126
5127 parse_entry = parse_dcb30_gpio_entry;
5128
7f245b20 5129 } else if (bios->dcb.version >= 0x22) {
6ee73861
BS		 5130 /*
5131 * DCBs older than v3.0 don't really have a GPIO
5132 * table, instead they keep some GPIO info at fixed
5133 * locations.
5134 */
5135 uint16_t dcbptr = ROM16(bios->data[0x36]);
5136 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5];
5137
5138 if (tvdac_gpio[0] & 1) {
5139 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5140
5141 gpio->tag = DCB_GPIO_TVDAC0;
5142 gpio->line = tvdac_gpio[1] >> 4;
5143 gpio->invert = tvdac_gpio[0] & 2;
5144 }
5145 }
5146
5147 if (!gpio_table_ptr)
5148 return;
5149
5150 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) {
5151 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n");
5152 entries = DCB_MAX_NUM_GPIO_ENTRIES;
5153 }
5154
5155 for (i = 0; i < entries; i++)
5156 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i);
5157}
5158
5159struct dcb_connector_table_entry *
5160nouveau_bios_connector_entry(struct drm_device *dev, int index)
5161{
5162 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5163 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5164 struct dcb_connector_table_entry *cte;
5165
7f245b20 5166 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5167 return NULL;
5168
7f245b20 5169 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5170 if (cte->type == 0xff)
5171 return NULL;
5172
5173 return cte;
5174}
5175
f66fa771
BS		 5176static enum dcb_connector_type
5177divine_connector_type(struct nvbios *bios, int index)
5178{
5179 struct dcb_table *dcb = &bios->dcb;
5180 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5181 int i;
5182
5183 for (i = 0; i < dcb->entries; i++) {
5184 if (dcb->entry[i].connector == index)
5185 encoders |= (1 << dcb->entry[i].type);
5186 }
5187
5188 if (encoders & (1 << OUTPUT_DP)) {
5189 if (encoders & (1 << OUTPUT_TMDS))
5190 type = DCB_CONNECTOR_DP;
5191 else
5192 type = DCB_CONNECTOR_eDP;
5193 } else
5194 if (encoders & (1 << OUTPUT_TMDS)) {
5195 if (encoders & (1 << OUTPUT_ANALOG))
5196 type = DCB_CONNECTOR_DVI_I;
5197 else
5198 type = DCB_CONNECTOR_DVI_D;
5199 } else
5200 if (encoders & (1 << OUTPUT_ANALOG)) {
5201 type = DCB_CONNECTOR_VGA;
5202 } else
5203 if (encoders & (1 << OUTPUT_LVDS)) {
5204 type = DCB_CONNECTOR_LVDS;
5205 } else
5206 if (encoders & (1 << OUTPUT_TV)) {
5207 type = DCB_CONNECTOR_TV_0;
5208 }
5209
5210 return type;
5211}
5212
6ee73861
BS		 5213static void
5214parse_dcb_connector_table(struct nvbios *bios)
5215{
5216 struct drm_device *dev = bios->dev;
7f245b20 5217 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5218 struct dcb_connector_table_entry *cte;
7f245b20 5219 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5220 uint8_t *entry;
5221 int i;
5222
7f245b20 5223 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5224 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5225 return;
5226 }
5227
5228 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5229 conntab[0], conntab[1], conntab[2], conntab[3]);
5230 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5231 (conntab[3] != 2 && conntab[3] != 4)) {
5232 NV_ERROR(dev, " Unknown! Please report.\n");
5233 return;
5234 }
5235
5236 ct->entries = conntab[2];
5237
5238 entry = conntab + conntab[1];
5239 cte = &ct->entry[0];
5240 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
5241 if (conntab[3] == 2)
5242 cte->entry = ROM16(entry[0]);
5243 else
5244 cte->entry = ROM32(entry[0]);
f66fa771 5245
6ee73861
BS		 5246 cte->type = (cte->entry & 0x000000ff) >> 0;
5247 cte->index = (cte->entry & 0x00000f00) >> 8;
5248 switch (cte->entry & 0x00033000) {
5249 case 0x00001000:
5250 cte->gpio_tag = 0x07;
5251 break;
5252 case 0x00002000:
5253 cte->gpio_tag = 0x08;
5254 break;
5255 case 0x00010000:
5256 cte->gpio_tag = 0x51;
5257 break;
5258 case 0x00020000:
5259 cte->gpio_tag = 0x52;
5260 break;
5261 default:
5262 cte->gpio_tag = 0xff;
5263 break;
5264 }
5265
5266 if (cte->type == 0xff)
5267 continue;
5268
5269 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5270 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 5271
5272 /* check for known types, fallback to guessing the type
5273 * from attached encoders if we hit an unknown.
5274 */
5275 switch (cte->type) {
5276 case DCB_CONNECTOR_VGA:
5277 case DCB_CONNECTOR_TV_0:
5278 case DCB_CONNECTOR_TV_1:
5279 case DCB_CONNECTOR_TV_3:
5280 case DCB_CONNECTOR_DVI_I:
5281 case DCB_CONNECTOR_DVI_D:
5282 case DCB_CONNECTOR_LVDS:
5283 case DCB_CONNECTOR_DP:
5284 case DCB_CONNECTOR_eDP:
5285 case DCB_CONNECTOR_HDMI_0:
5286 case DCB_CONNECTOR_HDMI_1:
5287 break;
5288 default:
5289 cte->type = divine_connector_type(bios, cte->index);
5290 NV_WARN(dev, "unknown type, using 0x%02x", cte->type);
5291 break;
5292 }
5293
6ee73861
BS		 5294 }
5295}
5296
7f245b20 5297static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5298{
5299 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5300
5301 memset(entry, 0, sizeof(struct dcb_entry));
5302 entry->index = dcb->entries++;
5303
5304 return entry;
5305}
5306
7f245b20 5307static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads)
6ee73861
BS		 5308{
5309 struct dcb_entry *entry = new_dcb_entry(dcb);
5310
5311 entry->type = 0;
5312 entry->i2c_index = i2c;
5313 entry->heads = heads;
5314 entry->location = DCB_LOC_ON_CHIP;
5315 /* "or" mostly unused in early gen crt modesetting, 0 is fine */
5316}
5317
7f245b20 5318static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5319{
5320 struct dcb_entry *entry = new_dcb_entry(dcb);
5321
5322 entry->type = 2;
5323 entry->i2c_index = LEGACY_I2C_PANEL;
5324 entry->heads = twoHeads ? 3 : 1;
5325 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5326 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
5327 entry->duallink_possible = false; /* SiI164 and co. are single link */
5328
5329#if 0
5330 /*
5331 * For dvi-a either crtc probably works, but my card appears to only
5332 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
5333 * doing the full fp output setup (program 0x6808.. fp dimension regs,
5334 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
5335 * the monitor picks up the mode res ok and lights up, but no pixel
5336 * data appears, so the board manufacturer probably connected up the
5337 * sync lines, but missed the video traces / components
5338 *
5339 * with this introduction, dvi-a left as an exercise for the reader.
5340 */
5341 fabricate_vga_output(dcb, LEGACY_I2C_PANEL, entry->heads);
5342#endif
5343}
5344
7f245b20 5345static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads)
6ee73861
BS		 5346{
5347 struct dcb_entry *entry = new_dcb_entry(dcb);
5348
5349 entry->type = 1;
5350 entry->i2c_index = LEGACY_I2C_TV;
5351 entry->heads = twoHeads ? 3 : 1;
5352 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5353}
5354
5355static bool
7f245b20 5356parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5357 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5358{
5359 entry->type = conn & 0xf;
5360 entry->i2c_index = (conn >> 4) & 0xf;
5361 entry->heads = (conn >> 8) & 0xf;
7f245b20 5362 if (dcb->version >= 0x40)
6ee73861
BS		 5363 entry->connector = (conn >> 12) & 0xf;
5364 entry->bus = (conn >> 16) & 0xf;
5365 entry->location = (conn >> 20) & 0x3;
5366 entry->or = (conn >> 24) & 0xf;
5367 /*
5368 * Normal entries consist of a single bit, but dual link has the
5369 * next most significant bit set too
5370 */
5371 entry->duallink_possible =
5372 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5373
5374 switch (entry->type) {
5375 case OUTPUT_ANALOG:
5376 /*
5377 * Although the rest of a CRT conf dword is usually
5378 * zeros, mac biosen have stuff there so we must mask
5379 */
7f245b20 5380 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5381 (conf & 0xffff) * 10 :
5382 (conf & 0xff) * 10000;
5383 break;
5384 case OUTPUT_LVDS:
5385 {
5386 uint32_t mask;
5387 if (conf & 0x1)
5388 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5389 if (dcb->version < 0x22) {
6ee73861
BS		 5390 mask = ~0xd;
5391 /*
5392 * The laptop in bug 14567 lies and claims to not use
5393 * straps when it does, so assume all DCB 2.0 laptops
5394 * use straps, until a broken EDID using one is produced
5395 */
5396 entry->lvdsconf.use_straps_for_mode = true;
5397 /*
5398 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5399 * mean the same thing (probably wrong, but might work)
5400 */
5401 if (conf & 0x4 || conf & 0x8)
5402 entry->lvdsconf.use_power_scripts = true;
5403 } else {
5404 mask = ~0x5;
5405 if (conf & 0x4)
5406 entry->lvdsconf.use_power_scripts = true;
5407 }
5408 if (conf & mask) {
5409 /*
5410 * Until we even try to use these on G8x, it's
5411 * useless reporting unknown bits. They all are.
5412 */
7f245b20 5413 if (dcb->version >= 0x40)
6ee73861
BS		 5414 break;
5415
5416 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5417 "please report\n");
5418 }
5419 break;
5420 }
5421 case OUTPUT_TV:
5422 {
7f245b20 5423 if (dcb->version >= 0x30)
6ee73861
BS		 5424 entry->tvconf.has_component_output = conf & (0x8 << 4);
5425 else
5426 entry->tvconf.has_component_output = false;
5427
5428 break;
5429 }
5430 case OUTPUT_DP:
5431 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5432 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
5433 switch ((conf & 0x0f000000) >> 24) {
5434 case 0xf:
5435 entry->dpconf.link_nr = 4;
5436 break;
5437 case 0x3:
5438 entry->dpconf.link_nr = 2;
5439 break;
5440 default:
5441 entry->dpconf.link_nr = 1;
5442 break;
5443 }
5444 break;
5445 case OUTPUT_TMDS:
5446 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5447 break;
5448 case 0xe:
5449 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 5450 dcb->entries--;
6ee73861 5451 return false;
e7cc51c5
BS		 5452 default:
5453 break;
6ee73861
BS		 5454 }
5455
5456 /* unsure what DCB version introduces this, 3.0? */
5457 if (conf & 0x100000)
5458 entry->i2c_upper_default = true;
5459
5460 return true;
5461}
5462
5463static bool
7f245b20 5464parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5465 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5466{
b0d2de86
BS		 5467 switch (conn & 0x0000000f) {
5468 case 0:
5469 entry->type = OUTPUT_ANALOG;
5470 break;
5471 case 1:
5472 entry->type = OUTPUT_TV;
5473 break;
5474 case 2:
5475 case 3:
6ee73861 5476 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 5477 break;
5478 case 4:
5479 switch ((conn & 0x000000f0) >> 4) {
5480 case 0:
6ee73861 5481 entry->type = OUTPUT_TMDS;
b0d2de86
BS		 5482 break;
5483 case 1:
5484 entry->type = OUTPUT_LVDS;
5485 break;
5486 default:
5487 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n",
5488 (conn & 0x000000f0) >> 4);
5489 return false;
5490 }
5491 break;
5492 default:
5493 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5494 return false;
6ee73861 5495 }
b0d2de86
BS		 5496
5497 entry->i2c_index = (conn & 0x0003c000) >> 14;
5498 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5499 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5500 entry->location = (conn & 0x01e00000) >> 21;
5501 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 5502 entry->duallink_possible = false;
5503
5504 switch (entry->type) {
5505 case OUTPUT_ANALOG:
5506 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5507 break;
b0d2de86
BS		 5508 case OUTPUT_TV:
5509 entry->tvconf.has_component_output = false;
6ee73861
BS		 5510 break;
5511 case OUTPUT_TMDS:
5512 /*
5513 * Invent a DVI-A output, by copying the fields of the DVI-D
5514 * output; reported to work by math_b on an NV20(!).
5515 */
5516 fabricate_vga_output(dcb, entry->i2c_index, entry->heads);
5517 break;
b0d2de86
BS		 5518 case OUTPUT_LVDS:
5519 if ((conn & 0x00003f00) != 0x10)
5520 entry->lvdsconf.use_straps_for_mode = true;
5521 entry->lvdsconf.use_power_scripts = true;
5522 break;
5523 default:
6ee73861
BS		 5524 break;
5525 }
5526
5527 return true;
5528}
5529
7f245b20 5530static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5531 uint32_t conn, uint32_t conf)
5532{
7f245b20 5533 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 5534 bool ret;
5535
7f245b20
BS		 5536 if (dcb->version >= 0x20)
5537 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 5538 else
7f245b20 5539 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 5540 if (!ret)
5541 return ret;
5542
7f245b20
BS		 5543 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
5544 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 5545
5546 return true;
5547}
5548
5549static
7f245b20 5550void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 5551{
5552 /*
5553 * DCB v2.0 lists each output combination separately.
5554 * Here we merge compatible entries to have fewer outputs, with
5555 * more options
5556 */
5557
5558 int i, newentries = 0;
5559
5560 for (i = 0; i < dcb->entries; i++) {
5561 struct dcb_entry *ient = &dcb->entry[i];
5562 int j;
5563
5564 for (j = i + 1; j < dcb->entries; j++) {
5565 struct dcb_entry *jent = &dcb->entry[j];
5566
5567 if (jent->type == 100) /* already merged entry */
5568 continue;
5569
5570 /* merge heads field when all other fields the same */
5571 if (jent->i2c_index == ient->i2c_index &&
5572 jent->type == ient->type &&
5573 jent->location == ient->location &&
5574 jent->or == ient->or) {
5575 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5576 i, j);
5577 ient->heads |= jent->heads;
5578 jent->type = 100; /* dummy value */
5579 }
5580 }
5581 }
5582
5583 /* Compact entries merged into others out of dcb */
5584 for (i = 0; i < dcb->entries; i++) {
5585 if (dcb->entry[i].type == 100)
5586 continue;
5587
5588 if (newentries != i) {
5589 dcb->entry[newentries] = dcb->entry[i];
5590 dcb->entry[newentries].index = newentries;
5591 }
5592 newentries++;
5593 }
5594
5595 dcb->entries = newentries;
5596}
5597
ed42f824
BS		 5598static int
5599parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads)
6ee73861 5600{
ed42f824 5601 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 5602 struct dcb_table *dcb = &bios->dcb;
ed42f824 5603 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 5604 uint8_t *dcbtable;
5605 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
5606 bool configblock = true;
5607 int recordlength = 8, confofs = 4;
5608 int i;
5609
6ee73861 5610 /* get the offset from 0x36 */
ed42f824
BS		 5611 if (dev_priv->card_type > NV_04) {
5612 dcbptr = ROM16(bios->data[0x36]);
5613 if (dcbptr == 0x0000)
5614 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
5615 }
6ee73861 5616
ed42f824 5617 /* this situation likely means a really old card, pre DCB */
6ee73861 5618 if (dcbptr == 0x0) {
ed42f824 5619 NV_INFO(dev, "Assuming a CRT output exists\n");
6ee73861
BS		 5620 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5621
ed42f824 5622 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6ee73861
BS		 5623 fabricate_tv_output(dcb, twoHeads);
5624
5625 return 0;
5626 }
5627
5628 dcbtable = &bios->data[dcbptr];
5629
5630 /* get DCB version */
7f245b20 5631 dcb->version = dcbtable[0];
6ee73861 5632 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 5633 dcb->version >> 4, dcb->version & 0xf);
6ee73861 5634
7f245b20 5635 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 5636 uint32_t sig;
5637
7f245b20 5638 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 5639 headerlen = dcbtable[1];
5640 entries = dcbtable[2];
5641 recordlength = dcbtable[3];
5642 i2ctabptr = ROM16(dcbtable[4]);
5643 sig = ROM32(dcbtable[6]);
7f245b20
BS		 5644 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
5645 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 5646 } else {
5647 i2ctabptr = ROM16(dcbtable[2]);
5648 sig = ROM32(dcbtable[4]);
5649 headerlen = 8;
5650 }
5651
5652 if (sig != 0x4edcbdcb) {
5653 NV_ERROR(dev, "Bad Display Configuration Block "
5654 "signature (%08X)\n", sig);
5655 return -EINVAL;
5656 }
7f245b20 5657 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 5658 char sig[8] = { 0 };
5659
5660 strncpy(sig, (char *)&dcbtable[-7], 7);
5661 i2ctabptr = ROM16(dcbtable[2]);
5662 recordlength = 10;
5663 confofs = 6;
5664
5665 if (strcmp(sig, "DEV_REC")) {
5666 NV_ERROR(dev, "Bad Display Configuration Block "
5667 "signature (%s)\n", sig);
5668 return -EINVAL;
5669 }
5670 } else {
5671 /*
5672 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
5673 * has the same single (crt) entry, even when tv-out present, so
5674 * the conclusion is this version cannot really be used.
5675 * v1.2 tables (some NV6/10, and NV15+) normally have the same
5676 * 5 entries, which are not specific to the card and so no use.
5677 * v1.2 does have an I2C table that read_dcb_i2c_table can
5678 * handle, but cards exist (nv11 in #14821) with a bad i2c table
5679 * pointer, so use the indices parsed in parse_bmp_structure.
5680 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5681 */
5682 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
5683 "adding all possible outputs\n");
5684 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1);
5685
5686 /*
5687 * Attempt to detect TV before DVI because the test
5688 * for the former is more accurate and it rules the
5689 * latter out.
5690 */
5691 if (nv04_tv_identify(dev,
5692 bios->legacy.i2c_indices.tv) >= 0)
5693 fabricate_tv_output(dcb, twoHeads);
5694
5695 else if (bios->tmds.output0_script_ptr ||
5696 bios->tmds.output1_script_ptr)
5697 fabricate_dvi_i_output(dcb, twoHeads);
5698
5699 return 0;
5700 }
5701
5702 if (!i2ctabptr)
5703 NV_WARN(dev, "No pointer to DCB I2C port table\n");
5704 else {
7f245b20
BS		 5705 dcb->i2c_table = &bios->data[i2ctabptr];
5706 if (dcb->version >= 0x30)
5707 dcb->i2c_default_indices = dcb->i2c_table[4];
6ee73861
BS		 5708 }
5709
6ee73861
BS		 5710 if (entries > DCB_MAX_NUM_ENTRIES)
5711 entries = DCB_MAX_NUM_ENTRIES;
5712
5713 for (i = 0; i < entries; i++) {
5714 uint32_t connection, config = 0;
5715
5716 connection = ROM32(dcbtable[headerlen + recordlength * i]);
5717 if (configblock)
5718 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
5719
5720 /* seen on an NV11 with DCB v1.5 */
5721 if (connection == 0x00000000)
5722 break;
5723
5724 /* seen on an NV17 with DCB v2.0 */
5725 if (connection == 0xffffffff)
5726 break;
5727
5728 if ((connection & 0x0000000f) == 0x0000000f)
5729 continue;
5730
5731 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
5732 dcb->entries, connection, config);
5733
7f245b20 5734 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 5735 break;
5736 }
5737
5738 /*
5739 * apart for v2.1+ not being known for requiring merging, this
5740 * guarantees dcbent->index is the index of the entry in the rom image
5741 */
7f245b20 5742 if (dcb->version < 0x21)
6ee73861
BS		 5743 merge_like_dcb_entries(dev, dcb);
5744
54abb5dd
BS		 5745 if (!dcb->entries)
5746 return -ENXIO;
5747
5748 parse_dcb_gpio_table(bios);
5749 parse_dcb_connector_table(bios);
5750 return 0;
6ee73861
BS		 5751}
5752
5753static void
5754fixup_legacy_connector(struct nvbios *bios)
5755{
7f245b20 5756 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 5757 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 5758
5759 /*
5760 * DCB 3.0 also has the table in most cases, but there are some cards
5761 * where the table is filled with stub entries, and the DCB entriy
5762 * indices are all 0. We don't need the connector indices on pre-G80
5763 * chips (yet?) so limit the use to DCB 4.0 and above.
5764 */
7f245b20 5765 if (dcb->version >= 0x40)
6ee73861
BS		 5766 return;
5767
dc5bc4ed
BS		 5768 dcb->connector.entries = 0;
5769
6ee73861
BS		 5770 /*
5771 * No known connector info before v3.0, so make it up. the rule here
5772 * is: anything on the same i2c bus is considered to be on the same
5773 * connector. any output without an associated i2c bus is assigned
5774 * its own unique connector index.
5775 */
5776 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 5777 /*
5778 * Ignore the I2C index for on-chip TV-out, as there
5779 * are cards with bogus values (nv31m in bug 23212),
5780 * and it's otherwise useless.
5781 */
5782 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 5783 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 5784 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 5785 i2c = dcb->entry[i].i2c_index;
5786
5787 if (i2c_conn[i2c]) {
5788 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 5789 continue;
5790 }
5791
dc5bc4ed
BS		 5792 dcb->entry[i].connector = dcb->connector.entries++;
5793 if (i2c != 0xf)
5794 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 5795 }
5796
dc5bc4ed
BS		 5797 /* Fake the connector table as well as just connector indices */
5798 for (i = 0; i < dcb->connector.entries; i++) {
5799 dcb->connector.entry[i].index = i;
5800 dcb->connector.entry[i].type = divine_connector_type(bios, i);
5801 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 5802 }
5803}
5804
5805static void
5806fixup_legacy_i2c(struct nvbios *bios)
5807{
7f245b20 5808 struct dcb_table *dcb = &bios->dcb;
6ee73861
BS		 5809 int i;
5810
5811 for (i = 0; i < dcb->entries; i++) {
5812 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
5813 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
5814 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
5815 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
5816 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
5817 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
5818 }
5819}
5820
5821static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
5822{
5823 /*
5824 * The header following the "HWSQ" signature has the number of entries,
5825 * and the entry size
5826 *
5827 * An entry consists of a dword to write to the sequencer control reg
5828 * (0x00001304), followed by the ucode bytes, written sequentially,
5829 * starting at reg 0x00001400
5830 */
5831
5832 uint8_t bytes_to_write;
5833 uint16_t hwsq_entry_offset;
5834 int i;
5835
5836 if (bios->data[hwsq_offset] <= entry) {
5837 NV_ERROR(dev, "Too few entries in HW sequencer table for "
5838 "requested entry\n");
5839 return -ENOENT;
5840 }
5841
5842 bytes_to_write = bios->data[hwsq_offset + 1];
5843
5844 if (bytes_to_write != 36) {
5845 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
5846 return -EINVAL;
5847 }
5848
5849 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
5850
5851 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
5852
5853 /* set sequencer control */
5854 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
5855 bytes_to_write -= 4;
5856
5857 /* write ucode */
5858 for (i = 0; i < bytes_to_write; i += 4)
5859 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
5860
5861 /* twiddle NV_PBUS_DEBUG_4 */
5862 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
5863
5864 return 0;
5865}
5866
5867static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
5868 struct nvbios *bios)
5869{
5870 /*
5871 * BMP based cards, from NV17, need a microcode loading to correctly
5872 * control the GPIO etc for LVDS panels
5873 *
5874 * BIT based cards seem to do this directly in the init scripts
5875 *
5876 * The microcode entries are found by the "HWSQ" signature.
5877 */
5878
5879 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
5880 const int sz = sizeof(hwsq_signature);
5881 int hwsq_offset;
5882
5883 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
5884 if (!hwsq_offset)
5885 return 0;
5886
5887 /* always use entry 0? */
5888 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
5889}
5890
5891uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
5892{
5893 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5894 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5895 const uint8_t edid_sig[] = {
5896 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
5897 uint16_t offset = 0;
5898 uint16_t newoffset;
5899 int searchlen = NV_PROM_SIZE;
5900
5901 if (bios->fp.edid)
5902 return bios->fp.edid;
5903
5904 while (searchlen) {
5905 newoffset = findstr(&bios->data[offset], searchlen,
5906 edid_sig, 8);
5907 if (!newoffset)
5908 return NULL;
5909 offset += newoffset;
5910 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
5911 break;
5912
5913 searchlen -= offset;
5914 offset++;
5915 }
5916
5917 NV_TRACE(dev, "Found EDID in BIOS\n");
5918
5919 return bios->fp.edid = &bios->data[offset];
5920}
5921
5922void
5923nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
5924 struct dcb_entry *dcbent)
5925{
5926 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5927 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5928 struct init_exec iexec = { true, false };
5929
d9184fa9 5930 mutex_lock(&bios->lock);
6ee73861
BS		 5931 bios->display.output = dcbent;
5932 parse_init_table(bios, table, &iexec);
5933 bios->display.output = NULL;
d9184fa9 5934 mutex_unlock(&bios->lock);
6ee73861
BS		 5935}
5936
5937static bool NVInitVBIOS(struct drm_device *dev)
5938{
5939 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5940 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5941
5942 memset(bios, 0, sizeof(struct nvbios));
d9184fa9 5943 mutex_init(&bios->lock);
6ee73861
BS		 5944 bios->dev = dev;
5945
5946 if (!NVShadowVBIOS(dev, bios->data))
5947 return false;
5948
5949 bios->length = NV_PROM_SIZE;
5950 return true;
5951}
5952
5953static int nouveau_parse_vbios_struct(struct drm_device *dev)
5954{
5955 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5956 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5957 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
5958 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
5959 int offset;
5960
5961 offset = findstr(bios->data, bios->length,
5962 bit_signature, sizeof(bit_signature));
5963 if (offset) {
5964 NV_TRACE(dev, "BIT BIOS found\n");
5965 return parse_bit_structure(bios, offset + 6);
5966 }
5967
5968 offset = findstr(bios->data, bios->length,
5969 bmp_signature, sizeof(bmp_signature));
5970 if (offset) {
5971 NV_TRACE(dev, "BMP BIOS found\n");
5972 return parse_bmp_structure(dev, bios, offset);
5973 }
5974
5975 NV_ERROR(dev, "No known BIOS signature found\n");
5976 return -ENODEV;
5977}
5978
5979int
5980nouveau_run_vbios_init(struct drm_device *dev)
5981{
5982 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5983 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5984 int i, ret = 0;
5985
5986 NVLockVgaCrtcs(dev, false);
5987 if (nv_two_heads(dev))
5988 NVSetOwner(dev, bios->state.crtchead);
5989
5990 if (bios->major_version < 5) /* BMP only */
5991 load_nv17_hw_sequencer_ucode(dev, bios);
5992
5993 if (bios->execute) {
5994 bios->fp.last_script_invoc = 0;
5995 bios->fp.lvds_init_run = false;
5996 }
5997
5998 parse_init_tables(bios);
5999
6000 /*
6001 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6002 * parser will run this right after the init tables, the binary
6003 * driver appears to run it at some point later.
6004 */
6005 if (bios->some_script_ptr) {
6006 struct init_exec iexec = {true, false};
6007
6008 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6009 bios->some_script_ptr);
6010 parse_init_table(bios, bios->some_script_ptr, &iexec);
6011 }
6012
6013 if (dev_priv->card_type >= NV_50) {
7f245b20 6014 for (i = 0; i < bios->dcb.entries; i++) {
6ee73861 6015 nouveau_bios_run_display_table(dev,
7f245b20 6016 &bios->dcb.entry[i],
6ee73861
BS		 6017 0, 0);
6018 }
6019 }
6020
6021 NVLockVgaCrtcs(dev, true);
6022
6023 return ret;
6024}
6025
6026static void
6027nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6028{
6029 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6030 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6031 struct dcb_i2c_entry *entry;
6032 int i;
6033
7f245b20 6034 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6035 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6036 nouveau_i2c_fini(dev, entry);
6037}
6038
6039int
6040nouveau_bios_init(struct drm_device *dev)
6041{
6042 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6043 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6044 uint32_t saved_nv_pextdev_boot_0;
6045 bool was_locked;
6046 int ret;
6047
6ee73861
BS		 6048 if (!NVInitVBIOS(dev))
6049 return -ENODEV;
6050
6051 ret = nouveau_parse_vbios_struct(dev);
6052 if (ret)
6053 return ret;
6054
6055 ret = parse_dcb_table(dev, bios, nv_two_heads(dev));
6056 if (ret)
6057 return ret;
6058
6059 fixup_legacy_i2c(bios);
6060 fixup_legacy_connector(bios);
6061
6062 if (!bios->major_version) /* we don't run version 0 bios */
6063 return 0;
6064
6065 /* these will need remembering across a suspend */
6066 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6067 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);
6068
6069 /* init script execution disabled */
6070 bios->execute = false;
6071
6072 /* ... unless card isn't POSTed already */
6073 if (dev_priv->card_type >= NV_10 &&
6074 NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6075 NVReadVgaCrtc(dev, 0, 0x1a) == 0) {
6076 NV_INFO(dev, "Adaptor not initialised\n");
6077 if (dev_priv->card_type < NV_50) {
6078 NV_ERROR(dev, "Unable to POST this chipset\n");
6079 return -ENODEV;
6080 }
6081
6082 NV_INFO(dev, "Running VBIOS init tables\n");
6083 bios->execute = true;
6084 }
6085
6086 bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
6087
6088 ret = nouveau_run_vbios_init(dev);
04a39c57 6089 if (ret)
6ee73861 6090 return ret;
6ee73861
BS		 6091
6092 /* feature_byte on BMP is poor, but init always sets CR4B */
6093 was_locked = NVLockVgaCrtcs(dev, false);
6094 if (bios->major_version < 5)
6095 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6096
6097 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6098 if (bios->is_mobile || bios->major_version >= 5)
6099 ret = parse_fp_mode_table(dev, bios);
6100 NVLockVgaCrtcs(dev, was_locked);
6101
6102 /* allow subsequent scripts to execute */
6103 bios->execute = true;
6104
6105 return 0;
6106}
6107
6108void
6109nouveau_bios_takedown(struct drm_device *dev)
6110{
6111 nouveau_bios_i2c_devices_takedown(dev);
6112}
Clone of davem's net-next-2.6 tree