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i915/intel_sdvo: remove unneeded null check
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "intel_drv.h"
2b8d33f7 35#include "drm_edid.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
50
79e53945 51
ce6feabd
ZY		 52static char *tv_format_names[] = {
53 "NTSC_M" , "NTSC_J" , "NTSC_443",
54 "PAL_B" , "PAL_D" , "PAL_G" ,
55 "PAL_H" , "PAL_I" , "PAL_M" ,
56 "PAL_N" , "PAL_NC" , "PAL_60" ,
57 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
58 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
59 "SECAM_60"
60};
61
62#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
63
79e53945 64struct intel_sdvo_priv {
f9c10a9b 65 u8 slave_addr;
e2f0ba97
JB		 66
67 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 68 int sdvo_reg;
79e53945 69
e2f0ba97
JB		 70 /* Active outputs controlled by this SDVO output */
71 uint16_t controlled_output;
79e53945 72
e2f0ba97
JB		 73 /*
74 * Capabilities of the SDVO device returned by
75 * i830_sdvo_get_capabilities()
76 */
79e53945 77 struct intel_sdvo_caps caps;
e2f0ba97
JB		 78
79 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 80 int pixel_clock_min, pixel_clock_max;
81
fb7a46f3 82 /*
83 * For multiple function SDVO device,
84 * this is for current attached outputs.
85 */
86 uint16_t attached_output;
87
e2f0ba97
JB		 88 /**
89 * This is set if we're going to treat the device as TV-out.
90 *
91 * While we have these nice friendly flags for output types that ought
92 * to decide this for us, the S-Video output on our HDMI+S-Video card
93 * shows up as RGB1 (VGA).
94 */
95 bool is_tv;
96
ce6feabd
ZY		 97 /* This is for current tv format name */
98 char *tv_format_name;
99
e2f0ba97
JB		 100 /**
101 * This is set if we treat the device as HDMI, instead of DVI.
102 */
103 bool is_hdmi;
12682a97 104
7086c87f
ML		 105 /**
106 * This is set if we detect output of sdvo device as LVDS.
107 */
108 bool is_lvds;
e2f0ba97 109
12682a97 110 /**
111 * This is sdvo flags for input timing.
112 */
113 uint8_t sdvo_flags;
114
115 /**
116 * This is sdvo fixed pannel mode pointer
117 */
118 struct drm_display_mode *sdvo_lvds_fixed_mode;
119
e2f0ba97
JB		 120 /*
121 * supported encoding mode, used to determine whether HDMI is
122 * supported
123 */
124 struct intel_sdvo_encode encode;
125
c751ce4f 126 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 127 uint8_t ddc_bus;
128
57cdaf90
KP		 129 /* Mac mini hack -- use the same DDC as the analog connector */
130 struct i2c_adapter *analog_ddc_bus;
131
14571b4c
ZW		 132};
133
134struct intel_sdvo_connector {
135 /* Mark the type of connector */
136 uint16_t output_flag;
137
138 /* This contains all current supported TV format */
139 char *tv_format_supported[TV_FORMAT_NUM];
140 int format_supported_num;
141 struct drm_property *tv_format_property;
142 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
143
144 /**
145 * Returned SDTV resolutions allowed for the current format, if the
146 * device reported it.
147 */
148 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
149
b9219c5e
ZY		 150 /* add the property for the SDVO-TV */
151 struct drm_property *left_property;
152 struct drm_property *right_property;
153 struct drm_property *top_property;
154 struct drm_property *bottom_property;
155 struct drm_property *hpos_property;
156 struct drm_property *vpos_property;
157
158 /* add the property for the SDVO-TV/LVDS */
159 struct drm_property *brightness_property;
160 struct drm_property *contrast_property;
161 struct drm_property *saturation_property;
162 struct drm_property *hue_property;
163
164 /* Add variable to record current setting for the above property */
165 u32 left_margin, right_margin, top_margin, bottom_margin;
166 /* this is to get the range of margin.*/
167 u32 max_hscan, max_vscan;
168 u32 max_hpos, cur_hpos;
169 u32 max_vpos, cur_vpos;
170 u32 cur_brightness, max_brightness;
171 u32 cur_contrast, max_contrast;
172 u32 cur_saturation, max_saturation;
173 u32 cur_hue, max_hue;
79e53945
JB		 174};
175
fb7a46f3 176static bool
d2a82a6f 177intel_sdvo_output_setup(struct intel_encoder *intel_encoder,
d2a82a6f 178 uint16_t flags);
14571b4c
ZW		 179static void
180intel_sdvo_tv_create_property(struct drm_connector *connector, int type);
181static void
182intel_sdvo_create_enhance_property(struct drm_connector *connector);
fb7a46f3 183
79e53945
JB		 184/**
185 * Writes the SDVOB or SDVOC with the given value, but always writes both
186 * SDVOB and SDVOC to work around apparent hardware issues (according to
187 * comments in the BIOS).
188 */
21d40d37 189static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val)
79e53945 190{
d2a82a6f 191 struct drm_device *dev = intel_encoder->enc.dev;
79e53945 192 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 193 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 194 u32 bval = val, cval = val;
195 int i;
196
461ed3ca
ZY		 197 if (sdvo_priv->sdvo_reg == PCH_SDVOB) {
198 I915_WRITE(sdvo_priv->sdvo_reg, val);
199 I915_READ(sdvo_priv->sdvo_reg);
200 return;
201 }
202
c751ce4f 203 if (sdvo_priv->sdvo_reg == SDVOB) {
79e53945
JB		 204 cval = I915_READ(SDVOC);
205 } else {
206 bval = I915_READ(SDVOB);
207 }
208 /*
209 * Write the registers twice for luck. Sometimes,
210 * writing them only once doesn't appear to 'stick'.
211 * The BIOS does this too. Yay, magic
212 */
213 for (i = 0; i < 2; i++)
214 {
215 I915_WRITE(SDVOB, bval);
216 I915_READ(SDVOB);
217 I915_WRITE(SDVOC, cval);
218 I915_READ(SDVOC);
219 }
220}
221
21d40d37 222static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr,
79e53945
JB		 223 u8 *ch)
224{
21d40d37 225 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 226 u8 out_buf[2];
227 u8 buf[2];
228 int ret;
229
230 struct i2c_msg msgs[] = {
231 {
f9c10a9b 232 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 233 .flags = 0,
234 .len = 1,
235 .buf = out_buf,
236 },
237 {
f9c10a9b 238 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 239 .flags = I2C_M_RD,
240 .len = 1,
241 .buf = buf,
242 }
243 };
244
245 out_buf[0] = addr;
246 out_buf[1] = 0;
247
21d40d37 248 if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2)
79e53945
JB		 249 {
250 *ch = buf[0];
251 return true;
252 }
253
8a4c47f3 254 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 255 return false;
256}
257
21d40d37 258static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr,
79e53945
JB		 259 u8 ch)
260{
21d40d37 261 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 262 u8 out_buf[2];
263 struct i2c_msg msgs[] = {
264 {
f9c10a9b 265 .addr = sdvo_priv->slave_addr >> 1,
79e53945
JB		 266 .flags = 0,
267 .len = 2,
268 .buf = out_buf,
269 }
270 };
271
272 out_buf[0] = addr;
273 out_buf[1] = ch;
274
21d40d37 275 if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1)
79e53945
JB		 276 {
277 return true;
278 }
279 return false;
280}
281
282#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
283/** Mapping of command numbers to names, for debug output */
005568be 284static const struct _sdvo_cmd_name {
e2f0ba97
JB		 285 u8 cmd;
286 char *name;
79e53945
JB		 287} sdvo_cmd_names[] = {
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
b9219c5e
ZY		 331 /* Add the op code for SDVO enhancements */
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
e2f0ba97
JB		 356 /* HDMI op code */
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 377};
378
461ed3ca
ZY		 379#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
380#define SDVO_NAME(dev_priv) (IS_SDVOB((dev_priv)->sdvo_reg) ? "SDVOB" : "SDVOC")
c751ce4f 381#define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv)
79e53945 382
21d40d37 383static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 384 void *args, int args_len)
385{
21d40d37 386 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 387 int i;
388
8a4c47f3 389 DRM_DEBUG_KMS("%s: W: %02X ",
342dc382 390 SDVO_NAME(sdvo_priv), cmd);
79e53945 391 for (i = 0; i < args_len; i++)
342dc382 392 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 393 for (; i < 8; i++)
342dc382 394 DRM_LOG_KMS(" ");
79e53945
JB		 395 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
396 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 397 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 398 break;
399 }
400 }
401 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
342dc382 402 DRM_LOG_KMS("(%02X)", cmd);
403 DRM_LOG_KMS("\n");
79e53945 404}
79e53945 405
21d40d37 406static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 407 void *args, int args_len)
408{
409 int i;
410
21d40d37 411 intel_sdvo_debug_write(intel_encoder, cmd, args, args_len);
79e53945
JB		 412
413 for (i = 0; i < args_len; i++) {
21d40d37 414 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i,
79e53945
JB		 415 ((u8*)args)[i]);
416 }
417
21d40d37 418 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 419}
420
79e53945
JB		 421static const char *cmd_status_names[] = {
422 "Power on",
423 "Success",
424 "Not supported",
425 "Invalid arg",
426 "Pending",
427 "Target not specified",
428 "Scaling not supported"
429};
430
21d40d37 431static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder,
79e53945
JB		 432 void *response, int response_len,
433 u8 status)
434{
21d40d37 435 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
33b52961 436 int i;
79e53945 437
8a4c47f3 438 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
79e53945 439 for (i = 0; i < response_len; i++)
342dc382 440 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 441 for (; i < 8; i++)
342dc382 442 DRM_LOG_KMS(" ");
79e53945 443 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 444 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 445 else
342dc382 446 DRM_LOG_KMS("(??? %d)", status);
447 DRM_LOG_KMS("\n");
79e53945 448}
79e53945 449
21d40d37 450static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder,
79e53945
JB		 451 void *response, int response_len)
452{
453 int i;
454 u8 status;
455 u8 retry = 50;
456
457 while (retry--) {
458 /* Read the command response */
459 for (i = 0; i < response_len; i++) {
21d40d37 460 intel_sdvo_read_byte(intel_encoder,
79e53945
JB		 461 SDVO_I2C_RETURN_0 + i,
462 &((u8 *)response)[i]);
463 }
464
465 /* read the return status */
21d40d37 466 intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS,
79e53945
JB		 467 &status);
468
21d40d37 469 intel_sdvo_debug_response(intel_encoder, response, response_len,
79e53945
JB		 470 status);
471 if (status != SDVO_CMD_STATUS_PENDING)
472 return status;
473
474 mdelay(50);
475 }
476
477 return status;
478}
479
b358d0a6 480static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 481{
482 if (mode->clock >= 100000)
483 return 1;
484 else if (mode->clock >= 50000)
485 return 2;
486 else
487 return 4;
488}
489
490/**
6a304caf
ZY		 491 * Try to read the response after issuie the DDC switch command. But it
492 * is noted that we must do the action of reading response and issuing DDC
493 * switch command in one I2C transaction. Otherwise when we try to start
494 * another I2C transaction after issuing the DDC bus switch, it will be
495 * switched to the internal SDVO register.
79e53945 496 */
21d40d37 497static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder,
b358d0a6 498 u8 target)
79e53945 499{
21d40d37 500 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
6a304caf
ZY		 501 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
502 struct i2c_msg msgs[] = {
503 {
504 .addr = sdvo_priv->slave_addr >> 1,
505 .flags = 0,
506 .len = 2,
507 .buf = out_buf,
508 },
509 /* the following two are to read the response */
510 {
511 .addr = sdvo_priv->slave_addr >> 1,
512 .flags = 0,
513 .len = 1,
514 .buf = cmd_buf,
515 },
516 {
517 .addr = sdvo_priv->slave_addr >> 1,
518 .flags = I2C_M_RD,
519 .len = 1,
520 .buf = ret_value,
521 },
522 };
523
21d40d37 524 intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
6a304caf
ZY		 525 &target, 1);
526 /* write the DDC switch command argument */
21d40d37 527 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target);
6a304caf
ZY		 528
529 out_buf[0] = SDVO_I2C_OPCODE;
530 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
531 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
532 cmd_buf[1] = 0;
533 ret_value[0] = 0;
534 ret_value[1] = 0;
535
21d40d37 536 ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3);
6a304caf
ZY		 537 if (ret != 3) {
538 /* failure in I2C transfer */
539 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
540 return;
541 }
542 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
543 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
544 ret_value[0]);
545 return;
546 }
547 return;
79e53945
JB		 548}
549
21d40d37 550static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1)
79e53945
JB		 551{
552 struct intel_sdvo_set_target_input_args targets = {0};
553 u8 status;
554
555 if (target_0 && target_1)
556 return SDVO_CMD_STATUS_NOTSUPP;
557
558 if (target_1)
559 targets.target_1 = 1;
560
21d40d37 561 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets,
79e53945
JB		 562 sizeof(targets));
563
21d40d37 564 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 565
566 return (status == SDVO_CMD_STATUS_SUCCESS);
567}
568
569/**
570 * Return whether each input is trained.
571 *
572 * This function is making an assumption about the layout of the response,
573 * which should be checked against the docs.
574 */
21d40d37 575static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2)
79e53945
JB		 576{
577 struct intel_sdvo_get_trained_inputs_response response;
578 u8 status;
579
21d40d37
EA		 580 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
581 status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response));
79e53945
JB		 582 if (status != SDVO_CMD_STATUS_SUCCESS)
583 return false;
584
585 *input_1 = response.input0_trained;
586 *input_2 = response.input1_trained;
587 return true;
588}
589
21d40d37 590static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder,
79e53945
JB		 591 u16 outputs)
592{
593 u8 status;
594
21d40d37 595 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
79e53945 596 sizeof(outputs));
21d40d37 597 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 598 return (status == SDVO_CMD_STATUS_SUCCESS);
599}
600
21d40d37 601static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder,
79e53945
JB		 602 int mode)
603{
604 u8 status, state = SDVO_ENCODER_STATE_ON;
605
606 switch (mode) {
607 case DRM_MODE_DPMS_ON:
608 state = SDVO_ENCODER_STATE_ON;
609 break;
610 case DRM_MODE_DPMS_STANDBY:
611 state = SDVO_ENCODER_STATE_STANDBY;
612 break;
613 case DRM_MODE_DPMS_SUSPEND:
614 state = SDVO_ENCODER_STATE_SUSPEND;
615 break;
616 case DRM_MODE_DPMS_OFF:
617 state = SDVO_ENCODER_STATE_OFF;
618 break;
619 }
620
21d40d37 621 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
79e53945 622 sizeof(state));
21d40d37 623 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 624
625 return (status == SDVO_CMD_STATUS_SUCCESS);
626}
627
21d40d37 628static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder,
79e53945
JB		 629 int *clock_min,
630 int *clock_max)
631{
632 struct intel_sdvo_pixel_clock_range clocks;
633 u8 status;
634
21d40d37 635 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
79e53945
JB		 636 NULL, 0);
637
21d40d37 638 status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks));
79e53945
JB		 639
640 if (status != SDVO_CMD_STATUS_SUCCESS)
641 return false;
642
643 /* Convert the values from units of 10 kHz to kHz. */
644 *clock_min = clocks.min * 10;
645 *clock_max = clocks.max * 10;
646
647 return true;
648}
649
21d40d37 650static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder,
79e53945
JB		 651 u16 outputs)
652{
653 u8 status;
654
21d40d37 655 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
79e53945
JB		 656 sizeof(outputs));
657
21d40d37 658 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 659 return (status == SDVO_CMD_STATUS_SUCCESS);
660}
661
21d40d37 662static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd,
79e53945
JB		 663 struct intel_sdvo_dtd *dtd)
664{
665 u8 status;
666
21d40d37
EA		 667 intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1));
668 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 669 if (status != SDVO_CMD_STATUS_SUCCESS)
670 return false;
671
21d40d37
EA		 672 intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2));
673 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 674 if (status != SDVO_CMD_STATUS_SUCCESS)
675 return false;
676
677 return true;
678}
679
21d40d37 680static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder,
79e53945
JB		 681 struct intel_sdvo_dtd *dtd)
682{
21d40d37 683 return intel_sdvo_set_timing(intel_encoder,
79e53945
JB		 684 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
685}
686
21d40d37 687static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder,
79e53945
JB		 688 struct intel_sdvo_dtd *dtd)
689{
21d40d37 690 return intel_sdvo_set_timing(intel_encoder,
79e53945
JB		 691 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
692}
693
e2f0ba97 694static bool
c751ce4f 695intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 696 uint16_t clock,
697 uint16_t width,
698 uint16_t height)
699{
700 struct intel_sdvo_preferred_input_timing_args args;
c751ce4f 701 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
e2f0ba97
JB		 702 uint8_t status;
703
e642c6f1 704 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 705 args.clock = clock;
706 args.width = width;
707 args.height = height;
e642c6f1 708 args.interlace = 0;
12682a97 709
710 if (sdvo_priv->is_lvds &&
711 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
712 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
713 args.scaled = 1;
714
c751ce4f
EA		 715 intel_sdvo_write_cmd(intel_encoder,
716 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
e2f0ba97 717 &args, sizeof(args));
c751ce4f 718 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 719 if (status != SDVO_CMD_STATUS_SUCCESS)
720 return false;
721
722 return true;
723}
724
c751ce4f 725static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 726 struct intel_sdvo_dtd *dtd)
727{
728 bool status;
729
c751ce4f 730 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
e2f0ba97
JB		 731 NULL, 0);
732
c751ce4f 733 status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
e2f0ba97
JB		 734 sizeof(dtd->part1));
735 if (status != SDVO_CMD_STATUS_SUCCESS)
736 return false;
737
c751ce4f 738 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
e2f0ba97
JB		 739 NULL, 0);
740
c751ce4f 741 status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
e2f0ba97
JB		 742 sizeof(dtd->part2));
743 if (status != SDVO_CMD_STATUS_SUCCESS)
744 return false;
745
746 return false;
747}
79e53945 748
21d40d37 749static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val)
79e53945
JB		 750{
751 u8 status;
752
21d40d37
EA		 753 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
754 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
79e53945
JB		 755 if (status != SDVO_CMD_STATUS_SUCCESS)
756 return false;
757
758 return true;
759}
760
e2f0ba97
JB		 761static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
762 struct drm_display_mode *mode)
79e53945 763{
e2f0ba97
JB		 764 uint16_t width, height;
765 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
766 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 767
768 width = mode->crtc_hdisplay;
769 height = mode->crtc_vdisplay;
770
771 /* do some mode translations */
772 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
773 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
774
775 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
776 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
777
778 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
779 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
780
e2f0ba97
JB		 781 dtd->part1.clock = mode->clock / 10;
782 dtd->part1.h_active = width & 0xff;
783 dtd->part1.h_blank = h_blank_len & 0xff;
784 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 785 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 786 dtd->part1.v_active = height & 0xff;
787 dtd->part1.v_blank = v_blank_len & 0xff;
788 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 789 ((v_blank_len >> 8) & 0xf);
790
171a9e96 791 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 792 dtd->part2.h_sync_width = h_sync_len & 0xff;
793 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 794 (v_sync_len & 0xf);
e2f0ba97 795 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 796 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
797 ((v_sync_len & 0x30) >> 4);
798
e2f0ba97 799 dtd->part2.dtd_flags = 0x18;
79e53945 800 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 801 dtd->part2.dtd_flags |= 0x2;
79e53945 802 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 803 dtd->part2.dtd_flags |= 0x4;
804
805 dtd->part2.sdvo_flags = 0;
806 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
807 dtd->part2.reserved = 0;
808}
809
810static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
811 struct intel_sdvo_dtd *dtd)
812{
e2f0ba97
JB		 813 mode->hdisplay = dtd->part1.h_active;
814 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
815 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 816 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 817 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
818 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
819 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
820 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
821
822 mode->vdisplay = dtd->part1.v_active;
823 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
824 mode->vsync_start = mode->vdisplay;
825 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 826 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 827 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
828 mode->vsync_end = mode->vsync_start +
829 (dtd->part2.v_sync_off_width & 0xf);
830 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
831 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
832 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
833
834 mode->clock = dtd->part1.clock * 10;
835
171a9e96 836 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 837 if (dtd->part2.dtd_flags & 0x2)
838 mode->flags |= DRM_MODE_FLAG_PHSYNC;
839 if (dtd->part2.dtd_flags & 0x4)
840 mode->flags |= DRM_MODE_FLAG_PVSYNC;
841}
842
c751ce4f 843static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 844 struct intel_sdvo_encode *encode)
845{
846 uint8_t status;
847
c751ce4f
EA		 848 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
849 status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode));
e2f0ba97
JB		 850 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
851 memset(encode, 0, sizeof(*encode));
852 return false;
853 }
854
855 return true;
856}
857
c751ce4f
EA		 858static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder,
859 uint8_t mode)
e2f0ba97
JB		 860{
861 uint8_t status;
862
c751ce4f
EA		 863 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);
864 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 865
866 return (status == SDVO_CMD_STATUS_SUCCESS);
867}
868
c751ce4f 869static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 870 uint8_t mode)
871{
872 uint8_t status;
873
c751ce4f
EA		 874 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
875 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 876
877 return (status == SDVO_CMD_STATUS_SUCCESS);
878}
879
880#if 0
c751ce4f 881static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
e2f0ba97
JB		 882{
883 int i, j;
884 uint8_t set_buf_index[2];
885 uint8_t av_split;
886 uint8_t buf_size;
887 uint8_t buf[48];
888 uint8_t *pos;
889
c751ce4f
EA		 890 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
891 intel_sdvo_read_response(encoder, &av_split, 1);
e2f0ba97
JB		 892
893 for (i = 0; i <= av_split; i++) {
894 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 895 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 896 set_buf_index, 2);
c751ce4f
EA		 897 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
898 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 899
900 pos = buf;
901 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 902 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 903 NULL, 0);
c751ce4f 904 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 905 pos += 8;
906 }
907 }
908}
909#endif
910
c751ce4f
EA		 911static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,
912 int index,
913 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 914{
915 uint8_t set_buf_index[2];
916
917 set_buf_index[0] = index;
918 set_buf_index[1] = 0;
919
c751ce4f
EA		 920 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX,
921 set_buf_index, 2);
e2f0ba97
JB		 922
923 for (; size > 0; size -= 8) {
c751ce4f 924 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8);
e2f0ba97
JB		 925 data += 8;
926 }
927
c751ce4f 928 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 929}
930
931static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
932{
933 uint8_t csum = 0;
934 int i;
935
936 for (i = 0; i < size; i++)
937 csum += data[i];
938
939 return 0x100 - csum;
940}
941
942#define DIP_TYPE_AVI 0x82
943#define DIP_VERSION_AVI 0x2
944#define DIP_LEN_AVI 13
945
946struct dip_infoframe {
947 uint8_t type;
948 uint8_t version;
949 uint8_t len;
950 uint8_t checksum;
951 union {
952 struct {
953 /* Packet Byte #1 */
954 uint8_t S:2;
955 uint8_t B:2;
956 uint8_t A:1;
957 uint8_t Y:2;
958 uint8_t rsvd1:1;
959 /* Packet Byte #2 */
960 uint8_t R:4;
961 uint8_t M:2;
962 uint8_t C:2;
963 /* Packet Byte #3 */
964 uint8_t SC:2;
965 uint8_t Q:2;
966 uint8_t EC:3;
967 uint8_t ITC:1;
968 /* Packet Byte #4 */
969 uint8_t VIC:7;
970 uint8_t rsvd2:1;
971 /* Packet Byte #5 */
972 uint8_t PR:4;
973 uint8_t rsvd3:4;
974 /* Packet Byte #6~13 */
975 uint16_t top_bar_end;
976 uint16_t bottom_bar_start;
977 uint16_t left_bar_end;
978 uint16_t right_bar_start;
979 } avi;
980 struct {
981 /* Packet Byte #1 */
982 uint8_t channel_count:3;
983 uint8_t rsvd1:1;
984 uint8_t coding_type:4;
985 /* Packet Byte #2 */
986 uint8_t sample_size:2; /* SS0, SS1 */
987 uint8_t sample_frequency:3;
988 uint8_t rsvd2:3;
989 /* Packet Byte #3 */
990 uint8_t coding_type_private:5;
991 uint8_t rsvd3:3;
992 /* Packet Byte #4 */
993 uint8_t channel_allocation;
994 /* Packet Byte #5 */
995 uint8_t rsvd4:3;
996 uint8_t level_shift:4;
997 uint8_t downmix_inhibit:1;
998 } audio;
999 uint8_t payload[28];
1000 } __attribute__ ((packed)) u;
1001} __attribute__((packed));
1002
c751ce4f 1003static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,
e2f0ba97
JB		 1004 struct drm_display_mode * mode)
1005{
1006 struct dip_infoframe avi_if = {
1007 .type = DIP_TYPE_AVI,
1008 .version = DIP_VERSION_AVI,
1009 .len = DIP_LEN_AVI,
1010 };
1011
1012 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1013 4 + avi_if.len);
c751ce4f
EA		 1014 intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if,
1015 4 + avi_if.len,
e2f0ba97
JB		 1016 SDVO_HBUF_TX_VSYNC);
1017}
1018
c751ce4f 1019static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder)
7026d4ac 1020{
ce6feabd
ZY		 1021
1022 struct intel_sdvo_tv_format format;
c751ce4f 1023 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
ce6feabd
ZY		 1024 uint32_t format_map, i;
1025 uint8_t status;
7026d4ac 1026
ce6feabd
ZY		 1027 for (i = 0; i < TV_FORMAT_NUM; i++)
1028 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1029 break;
1030
1031 format_map = 1 << i;
1032 memset(&format, 0, sizeof(format));
1033 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1034 sizeof(format) : sizeof(format_map));
1035
8a1837ce 1036 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format,
ce6feabd
ZY		 1037 sizeof(format));
1038
c751ce4f 1039 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
ce6feabd 1040 if (status != SDVO_CMD_STATUS_SUCCESS)
b9219c5e 1041 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
ce6feabd 1042 SDVO_NAME(sdvo_priv));
7026d4ac
ZW		 1043}
1044
e2f0ba97
JB		 1045static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1046 struct drm_display_mode *mode,
1047 struct drm_display_mode *adjusted_mode)
1048{
c751ce4f
EA		 1049 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1050 struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;
79e53945 1051
12682a97 1052 if (dev_priv->is_tv) {
e2f0ba97
JB		 1053 struct intel_sdvo_dtd output_dtd;
1054 bool success;
1055
1056 /* We need to construct preferred input timings based on our
1057 * output timings. To do that, we have to set the output
1058 * timings, even though this isn't really the right place in
1059 * the sequence to do it. Oh well.
1060 */
1061
1062
1063 /* Set output timings */
1064 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c751ce4f 1065 intel_sdvo_set_target_output(intel_encoder,
14571b4c 1066 dev_priv->attached_output);
c751ce4f 1067 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
e2f0ba97
JB		 1068
1069 /* Set the input timing to the screen. Assume always input 0. */
c751ce4f 1070 intel_sdvo_set_target_input(intel_encoder, true, false);
e2f0ba97
JB		 1071
1072
c751ce4f 1073 success = intel_sdvo_create_preferred_input_timing(intel_encoder,
e2f0ba97
JB		 1074 mode->clock / 10,
1075 mode->hdisplay,
1076 mode->vdisplay);
1077 if (success) {
1078 struct intel_sdvo_dtd input_dtd;
79e53945 1079
c751ce4f 1080 intel_sdvo_get_preferred_input_timing(intel_encoder,
e2f0ba97
JB		 1081 &input_dtd);
1082 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
12682a97 1083 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1084
1085 drm_mode_set_crtcinfo(adjusted_mode, 0);
1086
1087 mode->clock = adjusted_mode->clock;
1088
1089 adjusted_mode->clock *=
1090 intel_sdvo_get_pixel_multiplier(mode);
1091 } else {
1092 return false;
1093 }
1094 } else if (dev_priv->is_lvds) {
1095 struct intel_sdvo_dtd output_dtd;
1096 bool success;
1097
1098 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1099 /* Set output timings */
1100 intel_sdvo_get_dtd_from_mode(&output_dtd,
1101 dev_priv->sdvo_lvds_fixed_mode);
1102
c751ce4f 1103 intel_sdvo_set_target_output(intel_encoder,
14571b4c 1104 dev_priv->attached_output);
c751ce4f 1105 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
12682a97 1106
1107 /* Set the input timing to the screen. Assume always input 0. */
c751ce4f 1108 intel_sdvo_set_target_input(intel_encoder, true, false);
12682a97 1109
1110
1111 success = intel_sdvo_create_preferred_input_timing(
c751ce4f 1112 intel_encoder,
12682a97 1113 mode->clock / 10,
1114 mode->hdisplay,
1115 mode->vdisplay);
1116
1117 if (success) {
1118 struct intel_sdvo_dtd input_dtd;
1119
c751ce4f 1120 intel_sdvo_get_preferred_input_timing(intel_encoder,
12682a97 1121 &input_dtd);
1122 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1123 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
e2f0ba97 1124
7026d4ac
ZW		 1125 drm_mode_set_crtcinfo(adjusted_mode, 0);
1126
1127 mode->clock = adjusted_mode->clock;
1128
1129 adjusted_mode->clock *=
1130 intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1131 } else {
1132 return false;
1133 }
12682a97 1134
1135 } else {
1136 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1137 * SDVO device will be told of the multiplier during mode_set.
1138 */
1139 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
e2f0ba97
JB		 1140 }
1141 return true;
1142}
1143
1144static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1145 struct drm_display_mode *mode,
1146 struct drm_display_mode *adjusted_mode)
1147{
1148 struct drm_device *dev = encoder->dev;
1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150 struct drm_crtc *crtc = encoder->crtc;
1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c751ce4f
EA		 1152 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1153 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
e2f0ba97
JB		 1154 u32 sdvox = 0;
1155 int sdvo_pixel_multiply;
1156 struct intel_sdvo_in_out_map in_out;
1157 struct intel_sdvo_dtd input_dtd;
1158 u8 status;
1159
1160 if (!mode)
1161 return;
1162
1163 /* First, set the input mapping for the first input to our controlled
1164 * output. This is only correct if we're a single-input device, in
1165 * which case the first input is the output from the appropriate SDVO
1166 * channel on the motherboard. In a two-input device, the first input
1167 * will be SDVOB and the second SDVOC.
1168 */
14571b4c 1169 in_out.in0 = sdvo_priv->attached_output;
e2f0ba97
JB		 1170 in_out.in1 = 0;
1171
c751ce4f 1172 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP,
e2f0ba97 1173 &in_out, sizeof(in_out));
c751ce4f 1174 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
e2f0ba97
JB		 1175
1176 if (sdvo_priv->is_hdmi) {
c751ce4f 1177 intel_sdvo_set_avi_infoframe(intel_encoder, mode);
e2f0ba97
JB		 1178 sdvox |= SDVO_AUDIO_ENABLE;
1179 }
1180
7026d4ac
ZW		 1181 /* We have tried to get input timing in mode_fixup, and filled into
1182 adjusted_mode */
12682a97 1183 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
7026d4ac 1184 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
12682a97 1185 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1186 } else
7026d4ac 1187 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
e2f0ba97
JB		 1188
1189 /* If it's a TV, we already set the output timing in mode_fixup.
1190 * Otherwise, the output timing is equal to the input timing.
1191 */
12682a97 1192 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
e2f0ba97 1193 /* Set the output timing to the screen */
c751ce4f 1194 intel_sdvo_set_target_output(intel_encoder,
14571b4c 1195 sdvo_priv->attached_output);
c751ce4f 1196 intel_sdvo_set_output_timing(intel_encoder, &input_dtd);
e2f0ba97 1197 }
79e53945
JB		 1198
1199 /* Set the input timing to the screen. Assume always input 0. */
c751ce4f 1200 intel_sdvo_set_target_input(intel_encoder, true, false);
79e53945 1201
7026d4ac 1202 if (sdvo_priv->is_tv)
c751ce4f 1203 intel_sdvo_set_tv_format(intel_encoder);
7026d4ac 1204
e2f0ba97 1205 /* We would like to use intel_sdvo_create_preferred_input_timing() to
79e53945
JB		 1206 * provide the device with a timing it can support, if it supports that
1207 * feature. However, presumably we would need to adjust the CRTC to
1208 * output the preferred timing, and we don't support that currently.
1209 */
e2f0ba97 1210#if 0
c751ce4f 1211 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
e2f0ba97
JB		 1212 width, height);
1213 if (success) {
1214 struct intel_sdvo_dtd *input_dtd;
1215
c751ce4f
EA		 1216 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1217 intel_sdvo_set_input_timing(encoder, &input_dtd);
e2f0ba97
JB		 1218 }
1219#else
c751ce4f 1220 intel_sdvo_set_input_timing(intel_encoder, &input_dtd);
e2f0ba97 1221#endif
79e53945
JB		 1222
1223 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1224 case 1:
c751ce4f 1225 intel_sdvo_set_clock_rate_mult(intel_encoder,
79e53945
JB		 1226 SDVO_CLOCK_RATE_MULT_1X);
1227 break;
1228 case 2:
c751ce4f 1229 intel_sdvo_set_clock_rate_mult(intel_encoder,
79e53945
JB		 1230 SDVO_CLOCK_RATE_MULT_2X);
1231 break;
1232 case 4:
c751ce4f 1233 intel_sdvo_set_clock_rate_mult(intel_encoder,
79e53945
JB		 1234 SDVO_CLOCK_RATE_MULT_4X);
1235 break;
1236 }
1237
1238 /* Set the SDVO control regs. */
e2f0ba97
JB		 1239 if (IS_I965G(dev)) {
1240 sdvox |= SDVO_BORDER_ENABLE |
1241 SDVO_VSYNC_ACTIVE_HIGH |
1242 SDVO_HSYNC_ACTIVE_HIGH;
1243 } else {
c751ce4f
EA		 1244 sdvox |= I915_READ(sdvo_priv->sdvo_reg);
1245 switch (sdvo_priv->sdvo_reg) {
e2f0ba97
JB		 1246 case SDVOB:
1247 sdvox &= SDVOB_PRESERVE_MASK;
1248 break;
1249 case SDVOC:
1250 sdvox &= SDVOC_PRESERVE_MASK;
1251 break;
1252 }
1253 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1254 }
79e53945
JB		 1255 if (intel_crtc->pipe == 1)
1256 sdvox |= SDVO_PIPE_B_SELECT;
1257
1258 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1259 if (IS_I965G(dev)) {
e2f0ba97
JB		 1260 /* done in crtc_mode_set as the dpll_md reg must be written early */
1261 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1262 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945
JB		 1263 } else {
1264 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1265 }
1266
12682a97 1267 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1268 sdvox |= SDVO_STALL_SELECT;
c751ce4f 1269 intel_sdvo_write_sdvox(intel_encoder, sdvox);
79e53945
JB		 1270}
1271
1272static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1273{
1274 struct drm_device *dev = encoder->dev;
1275 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37
EA		 1276 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1277 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 1278 u32 temp;
1279
1280 if (mode != DRM_MODE_DPMS_ON) {
21d40d37 1281 intel_sdvo_set_active_outputs(intel_encoder, 0);
79e53945 1282 if (0)
21d40d37 1283 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
79e53945
JB		 1284
1285 if (mode == DRM_MODE_DPMS_OFF) {
c751ce4f 1286 temp = I915_READ(sdvo_priv->sdvo_reg);
79e53945 1287 if ((temp & SDVO_ENABLE) != 0) {
21d40d37 1288 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE);
79e53945
JB		 1289 }
1290 }
1291 } else {
1292 bool input1, input2;
1293 int i;
1294 u8 status;
1295
c751ce4f 1296 temp = I915_READ(sdvo_priv->sdvo_reg);
79e53945 1297 if ((temp & SDVO_ENABLE) == 0)
21d40d37 1298 intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE);
79e53945
JB		 1299 for (i = 0; i < 2; i++)
1300 intel_wait_for_vblank(dev);
1301
21d40d37 1302 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1,
79e53945
JB		 1303 &input2);
1304
1305
1306 /* Warn if the device reported failure to sync.
1307 * A lot of SDVO devices fail to notify of sync, but it's
1308 * a given it the status is a success, we succeeded.
1309 */
1310 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3
ZY		 1311 DRM_DEBUG_KMS("First %s output reported failure to "
1312 "sync\n", SDVO_NAME(sdvo_priv));
79e53945
JB		 1313 }
1314
1315 if (0)
21d40d37 1316 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
14571b4c 1317 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->attached_output);
79e53945
JB		 1318 }
1319 return;
1320}
1321
79e53945
JB		 1322static int intel_sdvo_mode_valid(struct drm_connector *connector,
1323 struct drm_display_mode *mode)
1324{
d2a82a6f
ZW		 1325 struct drm_encoder *encoder = intel_attached_encoder(connector);
1326 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37 1327 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
79e53945
JB		 1328
1329 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1330 return MODE_NO_DBLESCAN;
1331
1332 if (sdvo_priv->pixel_clock_min > mode->clock)
1333 return MODE_CLOCK_LOW;
1334
1335 if (sdvo_priv->pixel_clock_max < mode->clock)
1336 return MODE_CLOCK_HIGH;
1337
12682a97 1338 if (sdvo_priv->is_lvds == true) {
1339 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1340 return MODE_PANEL;
1341
1342 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1343 return MODE_PANEL;
1344
1345 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1346 return MODE_PANEL;
1347 }
1348
79e53945
JB		 1349 return MODE_OK;
1350}
1351
21d40d37 1352static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps)
79e53945
JB		 1353{
1354 u8 status;
1355
21d40d37
EA		 1356 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1357 status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps));
79e53945
JB		 1358 if (status != SDVO_CMD_STATUS_SUCCESS)
1359 return false;
1360
1361 return true;
1362}
1363
d2a82a6f
ZW		 1364/* No use! */
1365#if 0
79e53945
JB		 1366struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1367{
1368 struct drm_connector *connector = NULL;
21d40d37 1369 struct intel_encoder *iout = NULL;
79e53945
JB		 1370 struct intel_sdvo_priv *sdvo;
1371
1372 /* find the sdvo connector */
1373 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
21d40d37 1374 iout = to_intel_encoder(connector);
79e53945
JB		 1375
1376 if (iout->type != INTEL_OUTPUT_SDVO)
1377 continue;
1378
1379 sdvo = iout->dev_priv;
1380
c751ce4f 1381 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1382 return connector;
1383
c751ce4f 1384 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1385 return connector;
1386
1387 }
1388
1389 return NULL;
1390}
1391
1392int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1393{
1394 u8 response[2];
1395 u8 status;
21d40d37 1396 struct intel_encoder *intel_encoder;
8a4c47f3 1397 DRM_DEBUG_KMS("\n");
79e53945
JB		 1398
1399 if (!connector)
1400 return 0;
1401
21d40d37 1402 intel_encoder = to_intel_encoder(connector);
79e53945 1403
21d40d37
EA		 1404 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1405 status = intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945
JB		 1406
1407 if (response[0] !=0)
1408 return 1;
1409
1410 return 0;
1411}
1412
1413void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1414{
1415 u8 response[2];
1416 u8 status;
21d40d37 1417 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
79e53945 1418
21d40d37
EA		 1419 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1420 intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945
JB		 1421
1422 if (on) {
21d40d37
EA		 1423 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1424 status = intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945 1425
21d40d37 1426 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1427 } else {
1428 response[0] = 0;
1429 response[1] = 0;
21d40d37 1430 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1431 }
1432
21d40d37
EA		 1433 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1434 intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945 1435}
d2a82a6f 1436#endif
79e53945 1437
fb7a46f3 1438static bool
21d40d37 1439intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder)
fb7a46f3 1440{
21d40d37 1441 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
fb7a46f3 1442 int caps = 0;
1443
1444 if (sdvo_priv->caps.output_flags &
1445 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1446 caps++;
1447 if (sdvo_priv->caps.output_flags &
1448 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1449 caps++;
1450 if (sdvo_priv->caps.output_flags &
19e1f888 1451 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1452 caps++;
1453 if (sdvo_priv->caps.output_flags &
1454 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1455 caps++;
1456 if (sdvo_priv->caps.output_flags &
1457 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1458 caps++;
1459
1460 if (sdvo_priv->caps.output_flags &
1461 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1462 caps++;
1463
1464 if (sdvo_priv->caps.output_flags &
1465 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1466 caps++;
1467
1468 return (caps > 1);
1469}
1470
57cdaf90
KP		 1471static struct drm_connector *
1472intel_find_analog_connector(struct drm_device *dev)
1473{
1474 struct drm_connector *connector;
d2a82a6f 1475 struct drm_encoder *encoder;
21d40d37 1476 struct intel_encoder *intel_encoder;
57cdaf90 1477
d2a82a6f
ZW		 1478 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1479 intel_encoder = enc_to_intel_encoder(encoder);
1480 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
1481 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
90a78e8f 1482 if (encoder == intel_attached_encoder(connector))
d2a82a6f
ZW		 1483 return connector;
1484 }
1485 }
57cdaf90
KP		 1486 }
1487 return NULL;
1488}
1489
1490static int
1491intel_analog_is_connected(struct drm_device *dev)
1492{
1493 struct drm_connector *analog_connector;
1494 analog_connector = intel_find_analog_connector(dev);
1495
1496 if (!analog_connector)
1497 return false;
1498
1499 if (analog_connector->funcs->detect(analog_connector) ==
1500 connector_status_disconnected)
1501 return false;
1502
1503 return true;
1504}
1505
2b8d33f7 1506enum drm_connector_status
149c36a3 1507intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1508{
d2a82a6f
ZW		 1509 struct drm_encoder *encoder = intel_attached_encoder(connector);
1510 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37 1511 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
149c36a3
AJ		 1512 struct intel_connector *intel_connector = to_intel_connector(connector);
1513 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
2b8d33f7 1514 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1515 struct edid *edid = NULL;
1516
149c36a3 1517 edid = drm_get_edid(connector, intel_encoder->ddc_bus);
57cdaf90 1518
7c3f0a27 1519 /* This is only applied to SDVO cards with multiple outputs */
21d40d37 1520 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) {
7c3f0a27
ZY		 1521 uint8_t saved_ddc, temp_ddc;
1522 saved_ddc = sdvo_priv->ddc_bus;
1523 temp_ddc = sdvo_priv->ddc_bus >> 1;
1524 /*
1525 * Don't use the 1 as the argument of DDC bus switch to get
1526 * the EDID. It is used for SDVO SPD ROM.
1527 */
1528 while(temp_ddc > 1) {
1529 sdvo_priv->ddc_bus = temp_ddc;
149c36a3 1530 edid = drm_get_edid(connector, intel_encoder->ddc_bus);
7c3f0a27
ZY		 1531 if (edid) {
1532 /*
1533 * When we can get the EDID, maybe it is the
1534 * correct DDC bus. Update it.
1535 */
1536 sdvo_priv->ddc_bus = temp_ddc;
1537 break;
1538 }
1539 temp_ddc >>= 1;
1540 }
1541 if (edid == NULL)
1542 sdvo_priv->ddc_bus = saved_ddc;
1543 }
57cdaf90
KP		 1544 /* when there is no edid and no monitor is connected with VGA
1545 * port, try to use the CRT ddc to read the EDID for DVI-connector
1546 */
149c36a3 1547 if (edid == NULL && sdvo_priv->analog_ddc_bus &&
d2a82a6f 1548 !intel_analog_is_connected(connector->dev))
149c36a3
AJ		 1549 edid = drm_get_edid(connector, sdvo_priv->analog_ddc_bus);
1550
9dff6af8 1551 if (edid != NULL) {
149c36a3
AJ		 1552 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1553 bool need_digital = !!(sdvo_connector->output_flag & SDVO_TMDS_MASK);
2b8d33f7 1554
149c36a3
AJ		 1555 /* DDC bus is shared, match EDID to connector type */
1556 if (is_digital && need_digital)
1557 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
1558 else if (is_digital != need_digital)
1559 status = connector_status_disconnected;
2b8d33f7 1560
149c36a3
AJ		 1561 connector->display_info.raw_edid = NULL;
1562 } else
2b8d33f7 1563 status = connector_status_disconnected;
149c36a3
AJ		 1564
1565 kfree(edid);
2b8d33f7 1566
1567 return status;
9dff6af8
ML		 1568}
1569
79e53945
JB		 1570static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1571{
fb7a46f3 1572 uint16_t response;
79e53945 1573 u8 status;
d2a82a6f
ZW		 1574 struct drm_encoder *encoder = intel_attached_encoder(connector);
1575 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1576 struct intel_connector *intel_connector = to_intel_connector(connector);
21d40d37 1577 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
14571b4c
ZW		 1578 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1579 enum drm_connector_status ret;
79e53945 1580
21d40d37 1581 intel_sdvo_write_cmd(intel_encoder,
ce6feabd 1582 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
d09c23de
ZY		 1583 if (sdvo_priv->is_tv) {
1584 /* add 30ms delay when the output type is SDVO-TV */
1585 mdelay(30);
1586 }
21d40d37 1587 status = intel_sdvo_read_response(intel_encoder, &response, 2);
79e53945 1588
51c8b407 1589 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97
JB		 1590
1591 if (status != SDVO_CMD_STATUS_SUCCESS)
1592 return connector_status_unknown;
1593
fb7a46f3 1594 if (response == 0)
79e53945 1595 return connector_status_disconnected;
fb7a46f3 1596
14571b4c
ZW		 1597 sdvo_priv->attached_output = response;
1598
1599 if ((sdvo_connector->output_flag & response) == 0)
1600 ret = connector_status_disconnected;
149c36a3
AJ		 1601 else if (response & SDVO_TMDS_MASK)
1602 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1603 else
1604 ret = connector_status_connected;
1605
1606 /* May update encoder flag for like clock for SDVO TV, etc.*/
1607 if (ret == connector_status_connected) {
1608 sdvo_priv->is_tv = false;
1609 sdvo_priv->is_lvds = false;
1610 intel_encoder->needs_tv_clock = false;
1611
1612 if (response & SDVO_TV_MASK) {
1613 sdvo_priv->is_tv = true;
1614 intel_encoder->needs_tv_clock = true;
1615 }
1616 if (response & SDVO_LVDS_MASK)
1617 sdvo_priv->is_lvds = true;
fb7a46f3 1618 }
14571b4c
ZW		 1619
1620 return ret;
79e53945
JB		 1621}
1622
e2f0ba97 1623static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1624{
d2a82a6f
ZW		 1625 struct drm_encoder *encoder = intel_attached_encoder(connector);
1626 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37 1627 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
57cdaf90 1628 int num_modes;
79e53945
JB		 1629
1630 /* set the bus switch and get the modes */
335af9a2 1631 num_modes = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
79e53945 1632
57cdaf90
KP		 1633 /*
1634 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1635 * link between analog and digital outputs. So, if the regular SDVO
1636 * DDC fails, check to see if the analog output is disconnected, in
1637 * which case we'll look there for the digital DDC data.
e2f0ba97 1638 */
57cdaf90
KP		 1639 if (num_modes == 0 &&
1640 sdvo_priv->analog_ddc_bus &&
d2a82a6f 1641 !intel_analog_is_connected(connector->dev)) {
57cdaf90
KP		 1642 /* Switch to the analog ddc bus and try that
1643 */
335af9a2 1644 (void) intel_ddc_get_modes(connector, sdvo_priv->analog_ddc_bus);
e2f0ba97 1645 }
e2f0ba97
JB		 1646}
1647
1648/*
1649 * Set of SDVO TV modes.
1650 * Note! This is in reply order (see loop in get_tv_modes).
1651 * XXX: all 60Hz refresh?
1652 */
1653struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1654 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1655 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1657 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1658 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1660 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1661 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1662 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1663 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1664 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1665 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1666 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1667 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1669 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1670 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1672 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1673 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1674 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1675 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1676 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1678 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1679 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1680 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1681 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1682 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1683 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1684 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1685 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1686 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1687 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1688 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1690 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1691 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1692 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1693 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1694 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1696 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1697 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1698 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1699 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1700 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1701 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1702 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1703 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1705 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1706 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1707 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1708 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1709 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1710 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1711};
1712
1713static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1714{
d2a82a6f
ZW		 1715 struct drm_encoder *encoder = intel_attached_encoder(connector);
1716 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1717 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
7026d4ac 1718 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1719 uint32_t reply = 0, format_map = 0;
1720 int i;
e2f0ba97 1721 uint8_t status;
e2f0ba97 1722
e2f0ba97
JB		 1723
1724 /* Read the list of supported input resolutions for the selected TV
1725 * format.
1726 */
ce6feabd
ZY		 1727 for (i = 0; i < TV_FORMAT_NUM; i++)
1728 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1729 break;
1730
1731 format_map = (1 << i);
1732 memcpy(&tv_res, &format_map,
1733 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1734 sizeof(format_map) ? sizeof(format_map) :
1735 sizeof(struct intel_sdvo_sdtv_resolution_request));
1736
14571b4c 1737 intel_sdvo_set_target_output(intel_encoder, sdvo_priv->attached_output);
ce6feabd 1738
d2a82a6f 1739 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
7026d4ac 1740 &tv_res, sizeof(tv_res));
d2a82a6f 1741 status = intel_sdvo_read_response(intel_encoder, &reply, 3);
e2f0ba97
JB		 1742 if (status != SDVO_CMD_STATUS_SUCCESS)
1743 return;
1744
1745 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1746 if (reply & (1 << i)) {
1747 struct drm_display_mode *nmode;
1748 nmode = drm_mode_duplicate(connector->dev,
1749 &sdvo_tv_modes[i]);
1750 if (nmode)
1751 drm_mode_probed_add(connector, nmode);
1752 }
ce6feabd 1753
e2f0ba97
JB		 1754}
1755
7086c87f
ML		 1756static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1757{
d2a82a6f
ZW		 1758 struct drm_encoder *encoder = intel_attached_encoder(connector);
1759 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
7086c87f 1760 struct drm_i915_private *dev_priv = connector->dev->dev_private;
21d40d37 1761 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
12682a97 1762 struct drm_display_mode *newmode;
7086c87f
ML		 1763
1764 /*
1765 * Attempt to get the mode list from DDC.
1766 * Assume that the preferred modes are
1767 * arranged in priority order.
1768 */
335af9a2 1769 intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
7086c87f 1770 if (list_empty(&connector->probed_modes) == false)
12682a97 1771 goto end;
7086c87f
ML		 1772
1773 /* Fetch modes from VBT */
1774 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1775 newmode = drm_mode_duplicate(connector->dev,
1776 dev_priv->sdvo_lvds_vbt_mode);
1777 if (newmode != NULL) {
1778 /* Guarantee the mode is preferred */
1779 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1780 DRM_MODE_TYPE_DRIVER);
1781 drm_mode_probed_add(connector, newmode);
1782 }
1783 }
12682a97 1784
1785end:
1786 list_for_each_entry(newmode, &connector->probed_modes, head) {
1787 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1788 sdvo_priv->sdvo_lvds_fixed_mode =
1789 drm_mode_duplicate(connector->dev, newmode);
1790 break;
1791 }
1792 }
1793
7086c87f
ML		 1794}
1795
e2f0ba97
JB		 1796static int intel_sdvo_get_modes(struct drm_connector *connector)
1797{
14571b4c
ZW		 1798 struct intel_connector *intel_connector = to_intel_connector(connector);
1799 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
e2f0ba97 1800
14571b4c 1801 if (IS_TV(sdvo_connector))
e2f0ba97 1802 intel_sdvo_get_tv_modes(connector);
14571b4c 1803 else if (IS_LVDS(sdvo_connector))
7086c87f 1804 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1805 else
1806 intel_sdvo_get_ddc_modes(connector);
1807
79e53945
JB		 1808 if (list_empty(&connector->probed_modes))
1809 return 0;
1810 return 1;
1811}
1812
b9219c5e
ZY		 1813static
1814void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1815{
14571b4c
ZW		 1816 struct intel_connector *intel_connector = to_intel_connector(connector);
1817 struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv;
b9219c5e
ZY		 1818 struct drm_device *dev = connector->dev;
1819
14571b4c 1820 if (IS_TV(sdvo_priv)) {
b9219c5e
ZY		 1821 if (sdvo_priv->left_property)
1822 drm_property_destroy(dev, sdvo_priv->left_property);
1823 if (sdvo_priv->right_property)
1824 drm_property_destroy(dev, sdvo_priv->right_property);
1825 if (sdvo_priv->top_property)
1826 drm_property_destroy(dev, sdvo_priv->top_property);
1827 if (sdvo_priv->bottom_property)
1828 drm_property_destroy(dev, sdvo_priv->bottom_property);
1829 if (sdvo_priv->hpos_property)
1830 drm_property_destroy(dev, sdvo_priv->hpos_property);
1831 if (sdvo_priv->vpos_property)
1832 drm_property_destroy(dev, sdvo_priv->vpos_property);
b9219c5e
ZY		 1833 if (sdvo_priv->saturation_property)
1834 drm_property_destroy(dev,
1835 sdvo_priv->saturation_property);
1836 if (sdvo_priv->contrast_property)
1837 drm_property_destroy(dev,
1838 sdvo_priv->contrast_property);
1839 if (sdvo_priv->hue_property)
1840 drm_property_destroy(dev, sdvo_priv->hue_property);
1841 }
14571b4c 1842 if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) {
b9219c5e
ZY		 1843 if (sdvo_priv->brightness_property)
1844 drm_property_destroy(dev,
1845 sdvo_priv->brightness_property);
1846 }
1847 return;
1848}
1849
79e53945
JB		 1850static void intel_sdvo_destroy(struct drm_connector *connector)
1851{
14571b4c
ZW		 1852 struct intel_connector *intel_connector = to_intel_connector(connector);
1853 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
79e53945 1854
14571b4c 1855 if (sdvo_connector->tv_format_property)
ce6feabd 1856 drm_property_destroy(connector->dev,
14571b4c 1857 sdvo_connector->tv_format_property);
b9219c5e 1858
d2a82a6f 1859 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1860 drm_sysfs_connector_remove(connector);
1861 drm_connector_cleanup(connector);
d2a82a6f 1862 kfree(connector);
79e53945
JB		 1863}
1864
ce6feabd
ZY		 1865static int
1866intel_sdvo_set_property(struct drm_connector *connector,
1867 struct drm_property *property,
1868 uint64_t val)
1869{
d2a82a6f
ZW		 1870 struct drm_encoder *encoder = intel_attached_encoder(connector);
1871 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37 1872 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
14571b4c
ZW		 1873 struct intel_connector *intel_connector = to_intel_connector(connector);
1874 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
ce6feabd
ZY		 1875 struct drm_crtc *crtc = encoder->crtc;
1876 int ret = 0;
1877 bool changed = false;
b9219c5e
ZY		 1878 uint8_t cmd, status;
1879 uint16_t temp_value;
ce6feabd
ZY		 1880
1881 ret = drm_connector_property_set_value(connector, property, val);
1882 if (ret < 0)
1883 goto out;
1884
14571b4c 1885 if (property == sdvo_connector->tv_format_property) {
ce6feabd
ZY		 1886 if (val >= TV_FORMAT_NUM) {
1887 ret = -EINVAL;
1888 goto out;
1889 }
1890 if (sdvo_priv->tv_format_name ==
14571b4c 1891 sdvo_connector->tv_format_supported[val])
ce6feabd
ZY		 1892 goto out;
1893
14571b4c 1894 sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[val];
ce6feabd 1895 changed = true;
ce6feabd
ZY		 1896 }
1897
14571b4c 1898 if (IS_TV(sdvo_connector) || IS_LVDS(sdvo_connector)) {
b9219c5e
ZY		 1899 cmd = 0;
1900 temp_value = val;
14571b4c 1901 if (sdvo_connector->left_property == property) {
b9219c5e 1902 drm_connector_property_set_value(connector,
14571b4c
ZW		 1903 sdvo_connector->right_property, val);
1904 if (sdvo_connector->left_margin == temp_value)
b9219c5e
ZY		 1905 goto out;
1906
14571b4c
ZW		 1907 sdvo_connector->left_margin = temp_value;
1908 sdvo_connector->right_margin = temp_value;
1909 temp_value = sdvo_connector->max_hscan -
1910 sdvo_connector->left_margin;
b9219c5e 1911 cmd = SDVO_CMD_SET_OVERSCAN_H;
14571b4c 1912 } else if (sdvo_connector->right_property == property) {
b9219c5e 1913 drm_connector_property_set_value(connector,
14571b4c
ZW		 1914 sdvo_connector->left_property, val);
1915 if (sdvo_connector->right_margin == temp_value)
b9219c5e
ZY		 1916 goto out;
1917
14571b4c
ZW		 1918 sdvo_connector->left_margin = temp_value;
1919 sdvo_connector->right_margin = temp_value;
1920 temp_value = sdvo_connector->max_hscan -
1921 sdvo_connector->left_margin;
b9219c5e 1922 cmd = SDVO_CMD_SET_OVERSCAN_H;
14571b4c 1923 } else if (sdvo_connector->top_property == property) {
b9219c5e 1924 drm_connector_property_set_value(connector,
14571b4c
ZW		 1925 sdvo_connector->bottom_property, val);
1926 if (sdvo_connector->top_margin == temp_value)
b9219c5e
ZY		 1927 goto out;
1928
14571b4c
ZW		 1929 sdvo_connector->top_margin = temp_value;
1930 sdvo_connector->bottom_margin = temp_value;
1931 temp_value = sdvo_connector->max_vscan -
1932 sdvo_connector->top_margin;
b9219c5e 1933 cmd = SDVO_CMD_SET_OVERSCAN_V;
14571b4c 1934 } else if (sdvo_connector->bottom_property == property) {
b9219c5e 1935 drm_connector_property_set_value(connector,
14571b4c
ZW		 1936 sdvo_connector->top_property, val);
1937 if (sdvo_connector->bottom_margin == temp_value)
b9219c5e 1938 goto out;
14571b4c
ZW		 1939 sdvo_connector->top_margin = temp_value;
1940 sdvo_connector->bottom_margin = temp_value;
1941 temp_value = sdvo_connector->max_vscan -
1942 sdvo_connector->top_margin;
b9219c5e 1943 cmd = SDVO_CMD_SET_OVERSCAN_V;
14571b4c
ZW		 1944 } else if (sdvo_connector->hpos_property == property) {
1945 if (sdvo_connector->cur_hpos == temp_value)
b9219c5e
ZY		 1946 goto out;
1947
1948 cmd = SDVO_CMD_SET_POSITION_H;
14571b4c
ZW		 1949 sdvo_connector->cur_hpos = temp_value;
1950 } else if (sdvo_connector->vpos_property == property) {
1951 if (sdvo_connector->cur_vpos == temp_value)
b9219c5e
ZY		 1952 goto out;
1953
1954 cmd = SDVO_CMD_SET_POSITION_V;
14571b4c
ZW		 1955 sdvo_connector->cur_vpos = temp_value;
1956 } else if (sdvo_connector->saturation_property == property) {
1957 if (sdvo_connector->cur_saturation == temp_value)
b9219c5e
ZY		 1958 goto out;
1959
1960 cmd = SDVO_CMD_SET_SATURATION;
14571b4c
ZW		 1961 sdvo_connector->cur_saturation = temp_value;
1962 } else if (sdvo_connector->contrast_property == property) {
1963 if (sdvo_connector->cur_contrast == temp_value)
b9219c5e
ZY		 1964 goto out;
1965
1966 cmd = SDVO_CMD_SET_CONTRAST;
14571b4c
ZW		 1967 sdvo_connector->cur_contrast = temp_value;
1968 } else if (sdvo_connector->hue_property == property) {
1969 if (sdvo_connector->cur_hue == temp_value)
b9219c5e
ZY		 1970 goto out;
1971
1972 cmd = SDVO_CMD_SET_HUE;
14571b4c
ZW		 1973 sdvo_connector->cur_hue = temp_value;
1974 } else if (sdvo_connector->brightness_property == property) {
1975 if (sdvo_connector->cur_brightness == temp_value)
b9219c5e
ZY		 1976 goto out;
1977
1978 cmd = SDVO_CMD_SET_BRIGHTNESS;
14571b4c 1979 sdvo_connector->cur_brightness = temp_value;
b9219c5e
ZY		 1980 }
1981 if (cmd) {
21d40d37
EA		 1982 intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2);
1983 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 1984 NULL, 0);
1985 if (status != SDVO_CMD_STATUS_SUCCESS) {
1986 DRM_DEBUG_KMS("Incorrect SDVO command \n");
1987 return -EINVAL;
1988 }
1989 changed = true;
1990 }
1991 }
ce6feabd
ZY		 1992 if (changed && crtc)
1993 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1994 crtc->y, crtc->fb);
1995out:
1996 return ret;
1997}
1998
79e53945
JB		 1999static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2000 .dpms = intel_sdvo_dpms,
2001 .mode_fixup = intel_sdvo_mode_fixup,
2002 .prepare = intel_encoder_prepare,
2003 .mode_set = intel_sdvo_mode_set,
2004 .commit = intel_encoder_commit,
2005};
2006
2007static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 2008 .dpms = drm_helper_connector_dpms,
79e53945
JB		 2009 .detect = intel_sdvo_detect,
2010 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2011 .set_property = intel_sdvo_set_property,
79e53945
JB		 2012 .destroy = intel_sdvo_destroy,
2013};
2014
2015static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2016 .get_modes = intel_sdvo_get_modes,
2017 .mode_valid = intel_sdvo_mode_valid,
d2a82a6f 2018 .best_encoder = intel_attached_encoder,
79e53945
JB		 2019};
2020
b358d0a6 2021static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2022{
d2a82a6f
ZW		 2023 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2024 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2025
2026 if (intel_encoder->i2c_bus)
2027 intel_i2c_destroy(intel_encoder->i2c_bus);
2028 if (intel_encoder->ddc_bus)
2029 intel_i2c_destroy(intel_encoder->ddc_bus);
2030 if (sdvo_priv->analog_ddc_bus)
2031 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2032
2033 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
2034 drm_mode_destroy(encoder->dev,
2035 sdvo_priv->sdvo_lvds_fixed_mode);
2036
79e53945 2037 drm_encoder_cleanup(encoder);
d2a82a6f 2038 kfree(intel_encoder);
79e53945
JB		 2039}
2040
2041static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2042 .destroy = intel_sdvo_enc_destroy,
2043};
2044
2045
e2f0ba97
JB		 2046/**
2047 * Choose the appropriate DDC bus for control bus switch command for this
2048 * SDVO output based on the controlled output.
2049 *
2050 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2051 * outputs, then LVDS outputs.
2052 */
2053static void
b1083333
AJ		 2054intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2055 struct intel_sdvo_priv *sdvo, u32 reg)
e2f0ba97 2056{
b1083333 2057 struct sdvo_device_mapping *mapping;
e2f0ba97 2058
b1083333
AJ		 2059 if (IS_SDVOB(reg))
2060 mapping = &(dev_priv->sdvo_mappings[0]);
2061 else
2062 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2063
b1083333 2064 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
e2f0ba97
JB		 2065}
2066
2067static bool
14571b4c 2068intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output, int device)
e2f0ba97
JB		 2069{
2070 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2071 uint8_t status;
2072
14571b4c
ZW		 2073 if (device == 0)
2074 intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS0);
2075 else
2076 intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS1);
e2f0ba97
JB		 2077
2078 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2079 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2080 if (status != SDVO_CMD_STATUS_SUCCESS)
2081 return false;
2082 return true;
2083}
2084
21d40d37
EA		 2085static struct intel_encoder *
2086intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan)
619ac3b7
ML		 2087{
2088 struct drm_device *dev = chan->drm_dev;
d2a82a6f 2089 struct drm_encoder *encoder;
21d40d37 2090 struct intel_encoder *intel_encoder = NULL;
619ac3b7 2091
d2a82a6f
ZW		 2092 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2093 intel_encoder = enc_to_intel_encoder(encoder);
2094 if (intel_encoder->ddc_bus == &chan->adapter)
619ac3b7 2095 break;
619ac3b7 2096 }
21d40d37 2097 return intel_encoder;
619ac3b7
ML		 2098}
2099
2100static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2101 struct i2c_msg msgs[], int num)
2102{
21d40d37 2103 struct intel_encoder *intel_encoder;
619ac3b7
ML		 2104 struct intel_sdvo_priv *sdvo_priv;
2105 struct i2c_algo_bit_data *algo_data;
f9c10a9b 2106 const struct i2c_algorithm *algo;
619ac3b7
ML		 2107
2108 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
21d40d37
EA		 2109 intel_encoder =
2110 intel_sdvo_chan_to_intel_encoder(
619ac3b7 2111 (struct intel_i2c_chan *)(algo_data->data));
21d40d37 2112 if (intel_encoder == NULL)
619ac3b7
ML		 2113 return -EINVAL;
2114
21d40d37
EA		 2115 sdvo_priv = intel_encoder->dev_priv;
2116 algo = intel_encoder->i2c_bus->algo;
619ac3b7 2117
21d40d37 2118 intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus);
619ac3b7
ML		 2119 return algo->master_xfer(i2c_adap, msgs, num);
2120}
2121
2122static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2123 .master_xfer = intel_sdvo_master_xfer,
2124};
2125
714605e4 2126static u8
c751ce4f 2127intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2128{
2129 struct drm_i915_private *dev_priv = dev->dev_private;
2130 struct sdvo_device_mapping *my_mapping, *other_mapping;
2131
461ed3ca 2132 if (IS_SDVOB(sdvo_reg)) {
714605e4 2133 my_mapping = &dev_priv->sdvo_mappings[0];
2134 other_mapping = &dev_priv->sdvo_mappings[1];
2135 } else {
2136 my_mapping = &dev_priv->sdvo_mappings[1];
2137 other_mapping = &dev_priv->sdvo_mappings[0];
2138 }
2139
2140 /* If the BIOS described our SDVO device, take advantage of it. */
2141 if (my_mapping->slave_addr)
2142 return my_mapping->slave_addr;
2143
2144 /* If the BIOS only described a different SDVO device, use the
2145 * address that it isn't using.
2146 */
2147 if (other_mapping->slave_addr) {
2148 if (other_mapping->slave_addr == 0x70)
2149 return 0x72;
2150 else
2151 return 0x70;
2152 }
2153
2154 /* No SDVO device info is found for another DVO port,
2155 * so use mapping assumption we had before BIOS parsing.
2156 */
461ed3ca 2157 if (IS_SDVOB(sdvo_reg))
714605e4 2158 return 0x70;
2159 else
2160 return 0x72;
2161}
2162
fb7a46f3 2163static bool
14571b4c 2164intel_sdvo_connector_alloc (struct intel_connector **ret)
6070a4a9 2165{
14571b4c
ZW		 2166 struct intel_connector *intel_connector;
2167 struct intel_sdvo_connector *sdvo_connector;
2168
2169 *ret = kzalloc(sizeof(*intel_connector) +
2170 sizeof(*sdvo_connector), GFP_KERNEL);
2171 if (!*ret)
2172 return false;
2173
2174 intel_connector = *ret;
2175 sdvo_connector = (struct intel_sdvo_connector *)(intel_connector + 1);
2176 intel_connector->dev_priv = sdvo_connector;
2177
2178 return true;
6070a4a9
ZY		 2179}
2180
14571b4c
ZW		 2181static void
2182intel_sdvo_connector_create (struct drm_encoder *encoder,
2183 struct drm_connector *connector)
2184{
2185 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
2186 connector->connector_type);
6070a4a9 2187
14571b4c
ZW		 2188 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2189
2190 connector->interlace_allowed = 0;
2191 connector->doublescan_allowed = 0;
2192 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2193
2194 drm_mode_connector_attach_encoder(connector, encoder);
2195 drm_sysfs_connector_add(connector);
2196}
6070a4a9 2197
fb7a46f3 2198static bool
14571b4c 2199intel_sdvo_dvi_init(struct intel_encoder *intel_encoder, int device)
fb7a46f3 2200{
21d40d37
EA		 2201 struct drm_encoder *encoder = &intel_encoder->enc;
2202 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
14571b4c
ZW		 2203 struct drm_connector *connector;
2204 struct intel_connector *intel_connector;
2205 struct intel_sdvo_connector *sdvo_connector;
2206
2207 if (!intel_sdvo_connector_alloc(&intel_connector))
2208 return false;
2209
2210 sdvo_connector = intel_connector->dev_priv;
2211
2212 if (device == 0) {
2213 sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS0;
2214 sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2215 } else if (device == 1) {
2216 sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS1;
2217 sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2218 }
2219
2220 connector = &intel_connector->base;
eb1f8e4f 2221 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2222 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2223 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2224
2225 if (intel_sdvo_get_supp_encode(intel_encoder, &sdvo_priv->encode)
2226 && intel_sdvo_get_digital_encoding_mode(intel_encoder, device)
2227 && sdvo_priv->is_hdmi) {
2228 /* enable hdmi encoding mode if supported */
2229 intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI);
2230 intel_sdvo_set_colorimetry(intel_encoder,
2231 SDVO_COLORIMETRY_RGB256);
2232 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2233 }
2234 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2235 (1 << INTEL_ANALOG_CLONE_BIT);
2236
2237 intel_sdvo_connector_create(encoder, connector);
2238
2239 return true;
2240}
2241
2242static bool
2243intel_sdvo_tv_init(struct intel_encoder *intel_encoder, int type)
2244{
2245 struct drm_encoder *encoder = &intel_encoder->enc;
2246 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2247 struct drm_connector *connector;
2248 struct intel_connector *intel_connector;
2249 struct intel_sdvo_connector *sdvo_connector;
2250
2251 if (!intel_sdvo_connector_alloc(&intel_connector))
2252 return false;
2253
2254 connector = &intel_connector->base;
2255 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2256 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2257 sdvo_connector = intel_connector->dev_priv;
2258
2259 sdvo_priv->controlled_output |= type;
2260 sdvo_connector->output_flag = type;
2261
2262 sdvo_priv->is_tv = true;
2263 intel_encoder->needs_tv_clock = true;
2264 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2265
2266 intel_sdvo_connector_create(encoder, connector);
2267
2268 intel_sdvo_tv_create_property(connector, type);
2269
2270 intel_sdvo_create_enhance_property(connector);
2271
2272 return true;
2273}
2274
2275static bool
2276intel_sdvo_analog_init(struct intel_encoder *intel_encoder, int device)
2277{
2278 struct drm_encoder *encoder = &intel_encoder->enc;
2279 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2280 struct drm_connector *connector;
2281 struct intel_connector *intel_connector;
2282 struct intel_sdvo_connector *sdvo_connector;
2283
2284 if (!intel_sdvo_connector_alloc(&intel_connector))
2285 return false;
2286
2287 connector = &intel_connector->base;
eb1f8e4f 2288 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
14571b4c
ZW		 2289 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2290 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2291 sdvo_connector = intel_connector->dev_priv;
2292
2293 if (device == 0) {
2294 sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB0;
2295 sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2296 } else if (device == 1) {
2297 sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB1;
2298 sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2299 }
2300
2301 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2302 (1 << INTEL_ANALOG_CLONE_BIT);
2303
2304 intel_sdvo_connector_create(encoder, connector);
2305 return true;
2306}
2307
2308static bool
2309intel_sdvo_lvds_init(struct intel_encoder *intel_encoder, int device)
2310{
2311 struct drm_encoder *encoder = &intel_encoder->enc;
2312 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2313 struct drm_connector *connector;
2314 struct intel_connector *intel_connector;
2315 struct intel_sdvo_connector *sdvo_connector;
2316
2317 if (!intel_sdvo_connector_alloc(&intel_connector))
2318 return false;
2319
2320 connector = &intel_connector->base;
2321 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2322 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2323 sdvo_connector = intel_connector->dev_priv;
2324
2325 sdvo_priv->is_lvds = true;
2326
2327 if (device == 0) {
2328 sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS0;
2329 sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2330 } else if (device == 1) {
2331 sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS1;
2332 sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2333 }
2334
2335 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2336 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2337
2338 intel_sdvo_connector_create(encoder, connector);
2339 intel_sdvo_create_enhance_property(connector);
2340 return true;
2341}
2342
2343static bool
2344intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags)
2345{
2346 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
fb7a46f3 2347
2348 sdvo_priv->is_tv = false;
21d40d37 2349 intel_encoder->needs_tv_clock = false;
fb7a46f3 2350 sdvo_priv->is_lvds = false;
2351
14571b4c 2352 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2353
14571b4c
ZW		 2354 if (flags & SDVO_OUTPUT_TMDS0)
2355 if (!intel_sdvo_dvi_init(intel_encoder, 0))
2356 return false;
2357
2358 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2359 if (!intel_sdvo_dvi_init(intel_encoder, 1))
2360 return false;
2361
2362 /* TV has no XXX1 function block */
a1f4b7ff 2363 if (flags & SDVO_OUTPUT_SVID0)
14571b4c
ZW		 2364 if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_SVID0))
2365 return false;
2366
2367 if (flags & SDVO_OUTPUT_CVBS0)
2368 if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_CVBS0))
2369 return false;
fb7a46f3 2370
14571b4c
ZW		 2371 if (flags & SDVO_OUTPUT_RGB0)
2372 if (!intel_sdvo_analog_init(intel_encoder, 0))
2373 return false;
2374
2375 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2376 if (!intel_sdvo_analog_init(intel_encoder, 1))
2377 return false;
2378
2379 if (flags & SDVO_OUTPUT_LVDS0)
2380 if (!intel_sdvo_lvds_init(intel_encoder, 0))
2381 return false;
2382
2383 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2384 if (!intel_sdvo_lvds_init(intel_encoder, 1))
2385 return false;
fb7a46f3 2386
14571b4c 2387 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2388 unsigned char bytes[2];
2389
2390 sdvo_priv->controlled_output = 0;
2391 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
51c8b407
DA		 2392 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2393 SDVO_NAME(sdvo_priv),
2394 bytes[0], bytes[1]);
14571b4c 2395 return false;
fb7a46f3 2396 }
21d40d37 2397 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2398
14571b4c 2399 return true;
fb7a46f3 2400}
2401
14571b4c 2402static void intel_sdvo_tv_create_property(struct drm_connector *connector, int type)
ce6feabd 2403{
d2a82a6f
ZW		 2404 struct drm_encoder *encoder = intel_attached_encoder(connector);
2405 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37 2406 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
14571b4c
ZW		 2407 struct intel_connector *intel_connector = to_intel_connector(connector);
2408 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
ce6feabd
ZY		 2409 struct intel_sdvo_tv_format format;
2410 uint32_t format_map, i;
2411 uint8_t status;
2412
14571b4c 2413 intel_sdvo_set_target_output(intel_encoder, type);
ce6feabd 2414
21d40d37 2415 intel_sdvo_write_cmd(intel_encoder,
ce6feabd 2416 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
21d40d37 2417 status = intel_sdvo_read_response(intel_encoder,
ce6feabd
ZY		 2418 &format, sizeof(format));
2419 if (status != SDVO_CMD_STATUS_SUCCESS)
2420 return;
2421
2422 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2423 sizeof(format_map) : sizeof(format));
2424
2425 if (format_map == 0)
2426 return;
2427
14571b4c 2428 sdvo_connector->format_supported_num = 0;
ce6feabd
ZY		 2429 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2430 if (format_map & (1 << i)) {
14571b4c
ZW		 2431 sdvo_connector->tv_format_supported
2432 [sdvo_connector->format_supported_num++] =
ce6feabd
ZY		 2433 tv_format_names[i];
2434 }
2435
2436
14571b4c 2437 sdvo_connector->tv_format_property =
ce6feabd
ZY		 2438 drm_property_create(
2439 connector->dev, DRM_MODE_PROP_ENUM,
14571b4c 2440 "mode", sdvo_connector->format_supported_num);
ce6feabd 2441
14571b4c 2442 for (i = 0; i < sdvo_connector->format_supported_num; i++)
ce6feabd 2443 drm_property_add_enum(
14571b4c
ZW		 2444 sdvo_connector->tv_format_property, i,
2445 i, sdvo_connector->tv_format_supported[i]);
ce6feabd 2446
14571b4c 2447 sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[0];
ce6feabd 2448 drm_connector_attach_property(
14571b4c 2449 connector, sdvo_connector->tv_format_property, 0);
ce6feabd
ZY		 2450
2451}
2452
b9219c5e
ZY		 2453static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2454{
d2a82a6f
ZW		 2455 struct drm_encoder *encoder = intel_attached_encoder(connector);
2456 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
14571b4c
ZW		 2457 struct intel_connector *intel_connector = to_intel_connector(connector);
2458 struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv;
b9219c5e
ZY		 2459 struct intel_sdvo_enhancements_reply sdvo_data;
2460 struct drm_device *dev = connector->dev;
2461 uint8_t status;
2462 uint16_t response, data_value[2];
2463
21d40d37 2464 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
b9219c5e 2465 NULL, 0);
21d40d37 2466 status = intel_sdvo_read_response(intel_encoder, &sdvo_data,
b9219c5e
ZY		 2467 sizeof(sdvo_data));
2468 if (status != SDVO_CMD_STATUS_SUCCESS) {
2469 DRM_DEBUG_KMS(" incorrect response is returned\n");
2470 return;
2471 }
2472 response = *((uint16_t *)&sdvo_data);
2473 if (!response) {
2474 DRM_DEBUG_KMS("No enhancement is supported\n");
2475 return;
2476 }
14571b4c 2477 if (IS_TV(sdvo_priv)) {
b9219c5e
ZY		 2478 /* when horizontal overscan is supported, Add the left/right
2479 * property
2480 */
2481 if (sdvo_data.overscan_h) {
21d40d37 2482 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2483 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
21d40d37 2484 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2485 &data_value, 4);
2486 if (status != SDVO_CMD_STATUS_SUCCESS) {
2487 DRM_DEBUG_KMS("Incorrect SDVO max "
2488 "h_overscan\n");
2489 return;
2490 }
21d40d37 2491 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2492 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
21d40d37 2493 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2494 &response, 2);
2495 if (status != SDVO_CMD_STATUS_SUCCESS) {
2496 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2497 return;
2498 }
2499 sdvo_priv->max_hscan = data_value[0];
2500 sdvo_priv->left_margin = data_value[0] - response;
2501 sdvo_priv->right_margin = sdvo_priv->left_margin;
2502 sdvo_priv->left_property =
2503 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2504 "left_margin", 2);
2505 sdvo_priv->left_property->values[0] = 0;
2506 sdvo_priv->left_property->values[1] = data_value[0];
2507 drm_connector_attach_property(connector,
2508 sdvo_priv->left_property,
2509 sdvo_priv->left_margin);
2510 sdvo_priv->right_property =
2511 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2512 "right_margin", 2);
2513 sdvo_priv->right_property->values[0] = 0;
2514 sdvo_priv->right_property->values[1] = data_value[0];
2515 drm_connector_attach_property(connector,
2516 sdvo_priv->right_property,
2517 sdvo_priv->right_margin);
2518 DRM_DEBUG_KMS("h_overscan: max %d, "
2519 "default %d, current %d\n",
2520 data_value[0], data_value[1], response);
2521 }
2522 if (sdvo_data.overscan_v) {
21d40d37 2523 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2524 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
21d40d37 2525 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2526 &data_value, 4);
2527 if (status != SDVO_CMD_STATUS_SUCCESS) {
2528 DRM_DEBUG_KMS("Incorrect SDVO max "
2529 "v_overscan\n");
2530 return;
2531 }
21d40d37 2532 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2533 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
21d40d37 2534 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2535 &response, 2);
2536 if (status != SDVO_CMD_STATUS_SUCCESS) {
2537 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2538 return;
2539 }
2540 sdvo_priv->max_vscan = data_value[0];
2541 sdvo_priv->top_margin = data_value[0] - response;
2542 sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2543 sdvo_priv->top_property =
2544 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2545 "top_margin", 2);
2546 sdvo_priv->top_property->values[0] = 0;
2547 sdvo_priv->top_property->values[1] = data_value[0];
2548 drm_connector_attach_property(connector,
2549 sdvo_priv->top_property,
2550 sdvo_priv->top_margin);
2551 sdvo_priv->bottom_property =
2552 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2553 "bottom_margin", 2);
2554 sdvo_priv->bottom_property->values[0] = 0;
2555 sdvo_priv->bottom_property->values[1] = data_value[0];
2556 drm_connector_attach_property(connector,
2557 sdvo_priv->bottom_property,
2558 sdvo_priv->bottom_margin);
2559 DRM_DEBUG_KMS("v_overscan: max %d, "
2560 "default %d, current %d\n",
2561 data_value[0], data_value[1], response);
2562 }
2563 if (sdvo_data.position_h) {
21d40d37 2564 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2565 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
21d40d37 2566 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2567 &data_value, 4);
2568 if (status != SDVO_CMD_STATUS_SUCCESS) {
2569 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2570 return;
2571 }
21d40d37 2572 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2573 SDVO_CMD_GET_POSITION_H, NULL, 0);
21d40d37 2574 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2575 &response, 2);
2576 if (status != SDVO_CMD_STATUS_SUCCESS) {
2577 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2578 return;
2579 }
2580 sdvo_priv->max_hpos = data_value[0];
2581 sdvo_priv->cur_hpos = response;
2582 sdvo_priv->hpos_property =
2583 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2584 "hpos", 2);
2585 sdvo_priv->hpos_property->values[0] = 0;
2586 sdvo_priv->hpos_property->values[1] = data_value[0];
2587 drm_connector_attach_property(connector,
2588 sdvo_priv->hpos_property,
2589 sdvo_priv->cur_hpos);
2590 DRM_DEBUG_KMS("h_position: max %d, "
2591 "default %d, current %d\n",
2592 data_value[0], data_value[1], response);
2593 }
2594 if (sdvo_data.position_v) {
21d40d37 2595 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2596 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
21d40d37 2597 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2598 &data_value, 4);
2599 if (status != SDVO_CMD_STATUS_SUCCESS) {
2600 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2601 return;
2602 }
21d40d37 2603 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2604 SDVO_CMD_GET_POSITION_V, NULL, 0);
21d40d37 2605 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2606 &response, 2);
2607 if (status != SDVO_CMD_STATUS_SUCCESS) {
2608 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2609 return;
2610 }
2611 sdvo_priv->max_vpos = data_value[0];
2612 sdvo_priv->cur_vpos = response;
2613 sdvo_priv->vpos_property =
2614 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2615 "vpos", 2);
2616 sdvo_priv->vpos_property->values[0] = 0;
2617 sdvo_priv->vpos_property->values[1] = data_value[0];
2618 drm_connector_attach_property(connector,
2619 sdvo_priv->vpos_property,
2620 sdvo_priv->cur_vpos);
2621 DRM_DEBUG_KMS("v_position: max %d, "
2622 "default %d, current %d\n",
2623 data_value[0], data_value[1], response);
2624 }
b9219c5e 2625 if (sdvo_data.saturation) {
21d40d37 2626 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2627 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
21d40d37 2628 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2629 &data_value, 4);
2630 if (status != SDVO_CMD_STATUS_SUCCESS) {
2631 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2632 return;
2633 }
21d40d37 2634 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2635 SDVO_CMD_GET_SATURATION, NULL, 0);
21d40d37 2636 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2637 &response, 2);
2638 if (status != SDVO_CMD_STATUS_SUCCESS) {
2639 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2640 return;
2641 }
2642 sdvo_priv->max_saturation = data_value[0];
2643 sdvo_priv->cur_saturation = response;
2644 sdvo_priv->saturation_property =
2645 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2646 "saturation", 2);
2647 sdvo_priv->saturation_property->values[0] = 0;
2648 sdvo_priv->saturation_property->values[1] =
2649 data_value[0];
2650 drm_connector_attach_property(connector,
2651 sdvo_priv->saturation_property,
2652 sdvo_priv->cur_saturation);
2653 DRM_DEBUG_KMS("saturation: max %d, "
2654 "default %d, current %d\n",
2655 data_value[0], data_value[1], response);
2656 }
2657 if (sdvo_data.contrast) {
21d40d37 2658 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2659 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
21d40d37 2660 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2661 &data_value, 4);
2662 if (status != SDVO_CMD_STATUS_SUCCESS) {
2663 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2664 return;
2665 }
21d40d37 2666 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2667 SDVO_CMD_GET_CONTRAST, NULL, 0);
21d40d37 2668 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2669 &response, 2);
2670 if (status != SDVO_CMD_STATUS_SUCCESS) {
2671 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2672 return;
2673 }
2674 sdvo_priv->max_contrast = data_value[0];
2675 sdvo_priv->cur_contrast = response;
2676 sdvo_priv->contrast_property =
2677 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2678 "contrast", 2);
2679 sdvo_priv->contrast_property->values[0] = 0;
2680 sdvo_priv->contrast_property->values[1] = data_value[0];
2681 drm_connector_attach_property(connector,
2682 sdvo_priv->contrast_property,
2683 sdvo_priv->cur_contrast);
2684 DRM_DEBUG_KMS("contrast: max %d, "
2685 "default %d, current %d\n",
2686 data_value[0], data_value[1], response);
2687 }
2688 if (sdvo_data.hue) {
21d40d37 2689 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2690 SDVO_CMD_GET_MAX_HUE, NULL, 0);
21d40d37 2691 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2692 &data_value, 4);
2693 if (status != SDVO_CMD_STATUS_SUCCESS) {
2694 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2695 return;
2696 }
21d40d37 2697 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2698 SDVO_CMD_GET_HUE, NULL, 0);
21d40d37 2699 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2700 &response, 2);
2701 if (status != SDVO_CMD_STATUS_SUCCESS) {
2702 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2703 return;
2704 }
2705 sdvo_priv->max_hue = data_value[0];
2706 sdvo_priv->cur_hue = response;
2707 sdvo_priv->hue_property =
2708 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2709 "hue", 2);
2710 sdvo_priv->hue_property->values[0] = 0;
2711 sdvo_priv->hue_property->values[1] =
2712 data_value[0];
2713 drm_connector_attach_property(connector,
2714 sdvo_priv->hue_property,
2715 sdvo_priv->cur_hue);
2716 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2717 data_value[0], data_value[1], response);
2718 }
2719 }
14571b4c 2720 if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) {
b9219c5e 2721 if (sdvo_data.brightness) {
21d40d37 2722 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2723 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
21d40d37 2724 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2725 &data_value, 4);
2726 if (status != SDVO_CMD_STATUS_SUCCESS) {
2727 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2728 return;
2729 }
21d40d37 2730 intel_sdvo_write_cmd(intel_encoder,
b9219c5e 2731 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
21d40d37 2732 status = intel_sdvo_read_response(intel_encoder,
b9219c5e
ZY		 2733 &response, 2);
2734 if (status != SDVO_CMD_STATUS_SUCCESS) {
2735 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2736 return;
2737 }
2738 sdvo_priv->max_brightness = data_value[0];
2739 sdvo_priv->cur_brightness = response;
2740 sdvo_priv->brightness_property =
2741 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2742 "brightness", 2);
2743 sdvo_priv->brightness_property->values[0] = 0;
2744 sdvo_priv->brightness_property->values[1] =
2745 data_value[0];
2746 drm_connector_attach_property(connector,
2747 sdvo_priv->brightness_property,
2748 sdvo_priv->cur_brightness);
2749 DRM_DEBUG_KMS("brightness: max %d, "
2750 "default %d, current %d\n",
2751 data_value[0], data_value[1], response);
2752 }
2753 }
2754 return;
2755}
2756
c751ce4f 2757bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2758{
b01f2c3a 2759 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2760 struct intel_encoder *intel_encoder;
79e53945 2761 struct intel_sdvo_priv *sdvo_priv;
79e53945
JB		 2762 u8 ch[0x40];
2763 int i;
461ed3ca 2764 u32 i2c_reg, ddc_reg, analog_ddc_reg;
79e53945 2765
21d40d37
EA		 2766 intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2767 if (!intel_encoder) {
7d57382e 2768 return false;
79e53945
JB		 2769 }
2770
21d40d37 2771 sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1);
c751ce4f 2772 sdvo_priv->sdvo_reg = sdvo_reg;
308cd3a2 2773
21d40d37
EA		 2774 intel_encoder->dev_priv = sdvo_priv;
2775 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2776
461ed3ca
ZY		 2777 if (HAS_PCH_SPLIT(dev)) {
2778 i2c_reg = PCH_GPIOE;
2779 ddc_reg = PCH_GPIOE;
2780 analog_ddc_reg = PCH_GPIOA;
2781 } else {
2782 i2c_reg = GPIOE;
2783 ddc_reg = GPIOE;
2784 analog_ddc_reg = GPIOA;
2785 }
2786
79e53945 2787 /* setup the DDC bus. */
461ed3ca
ZY		 2788 if (IS_SDVOB(sdvo_reg))
2789 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
308cd3a2 2790 else
461ed3ca 2791 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
308cd3a2 2792
21d40d37 2793 if (!intel_encoder->i2c_bus)
ad5b2a6d 2794 goto err_inteloutput;
79e53945 2795
c751ce4f 2796 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2797
308cd3a2 2798 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2799 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2800
79e53945
JB		 2801 /* Read the regs to test if we can talk to the device */
2802 for (i = 0; i < 0x40; i++) {
21d40d37 2803 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) {
8a4c47f3 2804 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2805 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2806 goto err_i2c;
2807 }
2808 }
2809
619ac3b7 2810 /* setup the DDC bus. */
461ed3ca
ZY		 2811 if (IS_SDVOB(sdvo_reg)) {
2812 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
2813 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2814 "SDVOB/VGA DDC BUS");
b01f2c3a 2815 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2816 } else {
461ed3ca
ZY		 2817 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
2818 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2819 "SDVOC/VGA DDC BUS");
b01f2c3a 2820 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2821 }
619ac3b7 2822
21d40d37 2823 if (intel_encoder->ddc_bus == NULL)
619ac3b7
ML		 2824 goto err_i2c;
2825
308cd3a2 2826 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2827 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2828
14571b4c
ZW		 2829 /* encoder type will be decided later */
2830 drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
2831 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2832
af901ca1 2833 /* In default case sdvo lvds is false */
21d40d37 2834 intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps);
79e53945 2835
21d40d37 2836 if (intel_sdvo_output_setup(intel_encoder,
fb7a46f3 2837 sdvo_priv->caps.output_flags) != true) {
51c8b407 2838 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2839 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2840 goto err_i2c;
2841 }
2842
b1083333 2843 intel_sdvo_select_ddc_bus(dev_priv, sdvo_priv, sdvo_reg);
e2f0ba97 2844
79e53945 2845 /* Set the input timing to the screen. Assume always input 0. */
21d40d37 2846 intel_sdvo_set_target_input(intel_encoder, true, false);
79e53945 2847
21d40d37 2848 intel_sdvo_get_input_pixel_clock_range(intel_encoder,
79e53945
JB		 2849 &sdvo_priv->pixel_clock_min,
2850 &sdvo_priv->pixel_clock_max);
2851
2852
8a4c47f3 2853 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2854 "clock range %dMHz - %dMHz, "
2855 "input 1: %c, input 2: %c, "
2856 "output 1: %c, output 2: %c\n",
2857 SDVO_NAME(sdvo_priv),
2858 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2859 sdvo_priv->caps.device_rev_id,
2860 sdvo_priv->pixel_clock_min / 1000,
2861 sdvo_priv->pixel_clock_max / 1000,
2862 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2863 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2864 /* check currently supported outputs */
2865 sdvo_priv->caps.output_flags &
79e53945 2866 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
342dc382 2867 sdvo_priv->caps.output_flags &
79e53945
JB		 2868 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2869
7d57382e 2870 return true;
79e53945
JB		 2871
2872err_i2c:
57cdaf90
KP		 2873 if (sdvo_priv->analog_ddc_bus != NULL)
2874 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
21d40d37
EA		 2875 if (intel_encoder->ddc_bus != NULL)
2876 intel_i2c_destroy(intel_encoder->ddc_bus);
2877 if (intel_encoder->i2c_bus != NULL)
2878 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2879err_inteloutput:
21d40d37 2880 kfree(intel_encoder);
79e53945 2881
7d57382e 2882 return false;
79e53945 2883}
Clone of davem's net-next-2.6 tree