[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_i2c.c

/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2008,2010 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Chris Wilson <chris@chris-wilson.co.uk>
 */
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include "drmP.h"
#include "drm.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

/* Intel GPIO access functions */

#define I2C_RISEFALL_TIME 20

static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter *i2c)
{
	return container_of(i2c, struct intel_gmbus, adapter);
}

struct intel_gpio {
	struct i2c_adapter adapter;
	struct i2c_algo_bit_data algo;
	struct drm_i915_private *dev_priv;
	u32 reg;
};

void
intel_i2c_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	if (HAS_PCH_SPLIT(dev))
		I915_WRITE(PCH_GMBUS0, 0);
	else
		I915_WRITE(GMBUS0, 0);
}

static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
{
	u32 val;

	/* When using bit bashing for I2C, this bit needs to be set to 1 */
	if (!IS_PINEVIEW(dev_priv->dev))
		return;

	val = I915_READ(DSPCLK_GATE_D);
	if (enable)
		val |= DPCUNIT_CLOCK_GATE_DISABLE;
	else
		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
	I915_WRITE(DSPCLK_GATE_D, val);
}

static u32 get_reserved(struct intel_gpio *gpio)
{
	struct drm_i915_private *dev_priv = gpio->dev_priv;
	struct drm_device *dev = dev_priv->dev;
	u32 reserved = 0;

	/* On most chips, these bits must be preserved in software. */
	if (!IS_I830(dev) && !IS_845G(dev))
		reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE |
						   GPIO_CLOCK_PULLUP_DISABLE);

	return reserved;
}

static int get_clock(void *data)
{
	struct intel_gpio *gpio = data;
	struct drm_i915_private *dev_priv = gpio->dev_priv;
	u32 reserved = get_reserved(gpio);
	I915_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
	I915_WRITE(gpio->reg, reserved);
	return (I915_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
}

static int get_data(void *data)
{
	struct intel_gpio *gpio = data;
	struct drm_i915_private *dev_priv = gpio->dev_priv;
	u32 reserved = get_reserved(gpio);
	I915_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
	I915_WRITE(gpio->reg, reserved);
	return (I915_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
}

static void set_clock(void *data, int state_high)
{
	struct intel_gpio *gpio = data;
	struct drm_i915_private *dev_priv = gpio->dev_priv;
	u32 reserved = get_reserved(gpio);
	u32 clock_bits;

	if (state_high)
		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
	else
		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
			GPIO_CLOCK_VAL_MASK;

	I915_WRITE(gpio->reg, reserved | clock_bits);
	POSTING_READ(gpio->reg);
}

static void set_data(void *data, int state_high)
{
	struct intel_gpio *gpio = data;
	struct drm_i915_private *dev_priv = gpio->dev_priv;
	u32 reserved = get_reserved(gpio);
	u32 data_bits;

	if (state_high)
		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
	else
		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
			GPIO_DATA_VAL_MASK;

	I915_WRITE(gpio->reg, reserved | data_bits);
	POSTING_READ(gpio->reg);
}

static struct i2c_adapter *
intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
{
	static const int map_pin_to_reg[] = {
		0,
		GPIOB,
		GPIOA,
		GPIOC,
		GPIOD,
		GPIOE,
		GPIOF,
	};
	struct intel_gpio *gpio;

	if (pin < 1 || pin > 7)
		return NULL;

	gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
	if (gpio == NULL)
		return NULL;

	gpio->reg = map_pin_to_reg[pin];
	if (HAS_PCH_SPLIT(dev_priv->dev))
		gpio->reg += PCH_GPIOA - GPIOA;
	gpio->dev_priv = dev_priv;

	snprintf(gpio->adapter.name, I2C_NAME_SIZE, "GPIO%c", "?BACDEF?"[pin]);
	gpio->adapter.owner = THIS_MODULE;
	gpio->adapter.algo_data	= &gpio->algo;
	gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
	gpio->algo.setsda = set_data;
	gpio->algo.setscl = set_clock;
	gpio->algo.getsda = get_data;
	gpio->algo.getscl = get_clock;
	gpio->algo.udelay = I2C_RISEFALL_TIME;
	gpio->algo.timeout = usecs_to_jiffies(2200);
	gpio->algo.data = gpio;

	if (i2c_bit_add_bus(&gpio->adapter))
		goto out_free;

	return &gpio->adapter;

out_free:
	kfree(gpio);
	return NULL;
}

static int
intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
		     struct i2c_adapter *adapter,
		     struct i2c_msg *msgs,
		     int num)
{
	struct intel_gpio *gpio = container_of(adapter,
					       struct intel_gpio,
					       adapter);
	int ret;

	intel_i2c_reset(dev_priv->dev);

	intel_i2c_quirk_set(dev_priv, true);
	set_data(gpio, 1);
	set_clock(gpio, 1);
	udelay(I2C_RISEFALL_TIME);

	ret = adapter->algo->master_xfer(adapter, msgs, num);

	set_data(gpio, 1);
	set_clock(gpio, 1);
	intel_i2c_quirk_set(dev_priv, false);

	return ret;
}

static int
gmbus_xfer(struct i2c_adapter *adapter,
	   struct i2c_msg *msgs,
	   int num)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);
	struct drm_i915_private *dev_priv = adapter->algo_data;
	int i, reg_offset;

	if (bus->force_bit)
		return intel_i2c_quirk_xfer(dev_priv,
					    bus->force_bit, msgs, num);

	reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;

	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);

	for (i = 0; i < num; i++) {
		u16 len = msgs[i].len;
		u8 *buf = msgs[i].buf;

		if (msgs[i].flags & I2C_M_RD) {
			I915_WRITE(GMBUS1 + reg_offset,
				   GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
				   (len << GMBUS_BYTE_COUNT_SHIFT) |
				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
				   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
			POSTING_READ(GMBUS2+reg_offset);
			do {
				u32 val, loop = 0;

				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
					goto timeout;
				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
					return 0;

				val = I915_READ(GMBUS3 + reg_offset);
				do {
					*buf++ = val & 0xff;
					val >>= 8;
				} while (--len && ++loop < 4);
			} while (len);
		} else {
			u32 val, loop;

			val = loop = 0;
			do {
				val |= *buf++ << (8 * loop);
			} while (--len && ++loop < 4);

			I915_WRITE(GMBUS3 + reg_offset, val);
			I915_WRITE(GMBUS1 + reg_offset,
				   (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
				   (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
				   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
			POSTING_READ(GMBUS2+reg_offset);

			while (len) {
				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
					goto timeout;
				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
					return 0;

				val = loop = 0;
				do {
					val |= *buf++ << (8 * loop);
				} while (--len && ++loop < 4);

				I915_WRITE(GMBUS3 + reg_offset, val);
				POSTING_READ(GMBUS2+reg_offset);
			}
		}

		if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
			goto timeout;
		if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
			return 0;
	}

	return num;

timeout:
	DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
		 bus->reg0 & 0xff, bus->adapter.name);
	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
	bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
	if (!bus->force_bit)
		return -ENOMEM;

	return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
}

static u32 gmbus_func(struct i2c_adapter *adapter)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);

	if (bus->force_bit)
		bus->force_bit->algo->functionality(bus->force_bit);

	return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
		/* I2C_FUNC_10BIT_ADDR | */
		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
}

static const struct i2c_algorithm gmbus_algorithm = {
	.master_xfer	= gmbus_xfer,
	.functionality	= gmbus_func
};

/**
 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 * @dev: DRM device
 */
int intel_setup_gmbus(struct drm_device *dev)
{
	static const char *names[GMBUS_NUM_PORTS] = {
		"disabled",
		"ssc",
		"vga",
		"panel",
		"dpc",
		"dpb",
		"reserved"
		"dpd",
	};
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret, i;

	dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
				  GFP_KERNEL);
	if (dev_priv->gmbus == NULL)
		return -ENOMEM;

	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];

		bus->adapter.owner = THIS_MODULE;
		bus->adapter.class = I2C_CLASS_DDC;
		snprintf(bus->adapter.name,
			 I2C_NAME_SIZE,
			 "gmbus %s",
			 names[i]);

		bus->adapter.dev.parent = &dev->pdev->dev;
		bus->adapter.algo_data	= dev_priv;

		bus->adapter.algo = &gmbus_algorithm;
		ret = i2c_add_adapter(&bus->adapter);
		if (ret)
			goto err;

		/* By default use a conservative clock rate */
		bus->reg0 = i | GMBUS_RATE_100KHZ;

		/* XXX force bit banging until GMBUS is fully debugged */
		bus->force_bit = intel_gpio_create(dev_priv, i);
	}

	intel_i2c_reset(dev_priv->dev);

	return 0;

err:
	while (--i) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];
		i2c_del_adapter(&bus->adapter);
	}
	kfree(dev_priv->gmbus);
	dev_priv->gmbus = NULL;
	return ret;
}

void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	/* speed:
	 * 0x0 = 100 KHz
	 * 0x1 = 50 KHz
	 * 0x2 = 400 KHz
	 * 0x3 = 1000 Khz
	 */
	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
}

void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	if (force_bit) {
		if (bus->force_bit == NULL) {
			struct drm_i915_private *dev_priv = adapter->algo_data;
			bus->force_bit = intel_gpio_create(dev_priv,
							   bus->reg0 & 0xff);
		}
	} else {
		if (bus->force_bit) {
			i2c_del_adapter(bus->force_bit);
			kfree(bus->force_bit);
			bus->force_bit = NULL;
		}
	}
}

void intel_teardown_gmbus(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	if (dev_priv->gmbus == NULL)
		return;

	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];
		if (bus->force_bit) {
			i2c_del_adapter(bus->force_bit);
			kfree(bus->force_bit);
		}
		i2c_del_adapter(&bus->adapter);
	}

	kfree(dev_priv->gmbus);
	dev_priv->gmbus = NULL;
}
Commit	Line	Data
79e53945 JB	1	/*
79e53945 JB	2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
f899fc64	3	* Copyright © 2006-2008,2010 Intel Corporation
79e53945 JB	4	* Jesse Barnes <jesse.barnes@intel.com>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the next
	14	* paragraph) shall be included in all copies or substantial portions of the
	15	* Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	23	* DEALINGS IN THE SOFTWARE.
	24	*
	25	* Authors:
	26	* Eric Anholt <eric@anholt.net>
f899fc64	27	* Chris Wilson <chris@chris-wilson.co.uk>
79e53945 JB	28	*/
79e53945 JB	29	#include <linux/i2c.h>
79e53945 JB	30	#include <linux/i2c-algo-bit.h>
	31	#include "drmP.h"
	32	#include "drm.h"
	33	#include "intel_drv.h"
	34	#include "i915_drm.h"
	35	#include "i915_drv.h"
	36
f899fc64 CW	37	/* Intel GPIO access functions */
	38
	39	#define I2C_RISEFALL_TIME 20
	40
e957d772 CW	41	static inline struct intel_gmbus *
	42	to_intel_gmbus(struct i2c_adapter *i2c)
	43	{
	44	return container_of(i2c, struct intel_gmbus, adapter);
	45	}
	46
f899fc64 CW	47	struct intel_gpio {
	48	struct i2c_adapter adapter;
	49	struct i2c_algo_bit_data algo;
	50	struct drm_i915_private *dev_priv;
	51	u32 reg;
	52	};
	53
	54	void
	55	intel_i2c_reset(struct drm_device *dev)
0ba0e9e1 SL	56	{
0ba0e9e1 SL	57	struct drm_i915_private *dev_priv = dev->dev_private;
f899fc64 CW	58	if (HAS_PCH_SPLIT(dev))
	59	I915_WRITE(PCH_GMBUS0, 0);
	60	else
	61	I915_WRITE(GMBUS0, 0);
	62	}
	63
	64	static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
	65	{
b222f267	66	u32 val;
0ba0e9e1 SL	67
0ba0e9e1 SL	68	/* When using bit bashing for I2C, this bit needs to be set to 1 */
f899fc64	69	if (!IS_PINEVIEW(dev_priv->dev))
0ba0e9e1	70	return;
b222f267 CW	71
b222f267 CW	72	val = I915_READ(DSPCLK_GATE_D);
0ba0e9e1	73	if (enable)
b222f267	74	val \|= DPCUNIT_CLOCK_GATE_DISABLE;
0ba0e9e1	75	else
b222f267 CW	76	val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
b222f267 CW	77	I915_WRITE(DSPCLK_GATE_D, val);
0ba0e9e1 SL	78	}
0ba0e9e1 SL	79
e957d772 CW	80	static u32 get_reserved(struct intel_gpio *gpio)
	81	{
	82	struct drm_i915_private *dev_priv = gpio->dev_priv;
	83	struct drm_device *dev = dev_priv->dev;
	84	u32 reserved = 0;
	85
	86	/* On most chips, these bits must be preserved in software. */
	87	if (!IS_I830(dev) && !IS_845G(dev))
	88	reserved = I915_READ(gpio->reg) & (GPIO_DATA_PULLUP_DISABLE \|
	89	GPIO_CLOCK_PULLUP_DISABLE);
	90
	91	return reserved;
	92	}
	93
79e53945 JB	94	static int get_clock(void *data)
79e53945 JB	95	{
f899fc64 CW	96	struct intel_gpio *gpio = data;
f899fc64 CW	97	struct drm_i915_private *dev_priv = gpio->dev_priv;
e957d772 CW	98	u32 reserved = get_reserved(gpio);
	99	I915_WRITE(gpio->reg, reserved \| GPIO_CLOCK_DIR_MASK);
	100	I915_WRITE(gpio->reg, reserved);
f899fc64	101	return (I915_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
79e53945 JB	102	}
	103
	104	static int get_data(void *data)
	105	{
f899fc64 CW	106	struct intel_gpio *gpio = data;
f899fc64 CW	107	struct drm_i915_private *dev_priv = gpio->dev_priv;
e957d772 CW	108	u32 reserved = get_reserved(gpio);
	109	I915_WRITE(gpio->reg, reserved \| GPIO_DATA_DIR_MASK);
	110	I915_WRITE(gpio->reg, reserved);
f899fc64	111	return (I915_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
79e53945 JB	112	}
	113
	114	static void set_clock(void *data, int state_high)
	115	{
f899fc64 CW	116	struct intel_gpio *gpio = data;
f899fc64 CW	117	struct drm_i915_private *dev_priv = gpio->dev_priv;
e957d772 CW	118	u32 reserved = get_reserved(gpio);
e957d772 CW	119	u32 clock_bits;
79e53945 JB	120
	121	if (state_high)
	122	clock_bits = GPIO_CLOCK_DIR_IN \| GPIO_CLOCK_DIR_MASK;
	123	else
	124	clock_bits = GPIO_CLOCK_DIR_OUT \| GPIO_CLOCK_DIR_MASK \|
	125	GPIO_CLOCK_VAL_MASK;
f899fc64 CW	126
	127	I915_WRITE(gpio->reg, reserved \| clock_bits);
	128	POSTING_READ(gpio->reg);
79e53945 JB	129	}
	130
	131	static void set_data(void *data, int state_high)
	132	{
f899fc64 CW	133	struct intel_gpio *gpio = data;
f899fc64 CW	134	struct drm_i915_private *dev_priv = gpio->dev_priv;
e957d772 CW	135	u32 reserved = get_reserved(gpio);
e957d772 CW	136	u32 data_bits;
79e53945 JB	137
	138	if (state_high)
	139	data_bits = GPIO_DATA_DIR_IN \| GPIO_DATA_DIR_MASK;
	140	else
	141	data_bits = GPIO_DATA_DIR_OUT \| GPIO_DATA_DIR_MASK \|
	142	GPIO_DATA_VAL_MASK;
	143
f899fc64 CW	144	I915_WRITE(gpio->reg, reserved \| data_bits);
f899fc64 CW	145	POSTING_READ(gpio->reg);
79e53945 JB	146	}
79e53945 JB	147
f899fc64 CW	148	static struct i2c_adapter *
f899fc64 CW	149	intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
f0217c42	150	{
f899fc64 CW	151	static const int map_pin_to_reg[] = {
	152	0,
	153	GPIOB,
	154	GPIOA,
	155	GPIOC,
	156	GPIOD,
	157	GPIOE,
	158	GPIOF,
	159	};
	160	struct intel_gpio *gpio;
f0217c42	161
f899fc64 CW	162	if (pin < 1 \|\| pin > 7)
f899fc64 CW	163	return NULL;
f0217c42	164
f899fc64 CW	165	gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
	166	if (gpio == NULL)
	167	return NULL;
79e53945	168
f899fc64 CW	169	gpio->reg = map_pin_to_reg[pin];
	170	if (HAS_PCH_SPLIT(dev_priv->dev))
	171	gpio->reg += PCH_GPIOA - GPIOA;
	172	gpio->dev_priv = dev_priv;
79e53945	173
e957d772	174	snprintf(gpio->adapter.name, I2C_NAME_SIZE, "GPIO%c", "?BACDEF?"[pin]);
f899fc64 CW	175	gpio->adapter.owner = THIS_MODULE;
	176	gpio->adapter.algo_data = &gpio->algo;
	177	gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
	178	gpio->algo.setsda = set_data;
	179	gpio->algo.setscl = set_clock;
	180	gpio->algo.getsda = get_data;
	181	gpio->algo.getscl = get_clock;
	182	gpio->algo.udelay = I2C_RISEFALL_TIME;
	183	gpio->algo.timeout = usecs_to_jiffies(2200);
	184	gpio->algo.data = gpio;
	185
	186	if (i2c_bit_add_bus(&gpio->adapter))
79e53945 JB	187	goto out_free;
79e53945 JB	188
f899fc64	189	return &gpio->adapter;
79e53945 JB	190
79e53945 JB	191	out_free:
f899fc64	192	kfree(gpio);
79e53945 JB	193	return NULL;
	194	}
	195
f899fc64	196	static int
e957d772 CW	197	intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
	198	struct i2c_adapter *adapter,
	199	struct i2c_msg *msgs,
	200	int num)
f899fc64	201	{
e957d772 CW	202	struct intel_gpio *gpio = container_of(adapter,
	203	struct intel_gpio,
	204	adapter);
f899fc64 CW	205	int ret;
	206
	207	intel_i2c_reset(dev_priv->dev);
	208
	209	intel_i2c_quirk_set(dev_priv, true);
e957d772 CW	210	set_data(gpio, 1);
	211	set_clock(gpio, 1);
	212	udelay(I2C_RISEFALL_TIME);
	213
	214	ret = adapter->algo->master_xfer(adapter, msgs, num);
	215
	216	set_data(gpio, 1);
	217	set_clock(gpio, 1);
f899fc64 CW	218	intel_i2c_quirk_set(dev_priv, false);
	219
	220	return ret;
	221	}
	222
	223	static int
	224	gmbus_xfer(struct i2c_adapter *adapter,
	225	struct i2c_msg *msgs,
	226	int num)
	227	{
	228	struct intel_gmbus *bus = container_of(adapter,
	229	struct intel_gmbus,
	230	adapter);
	231	struct drm_i915_private *dev_priv = adapter->algo_data;
e957d772	232	int i, reg_offset;
f899fc64	233
e957d772 CW	234	if (bus->force_bit)
	235	return intel_i2c_quirk_xfer(dev_priv,
	236	bus->force_bit, msgs, num);
f899fc64 CW	237
	238	reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
	239
e957d772	240	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
f899fc64 CW	241
	242	for (i = 0; i < num; i++) {
	243	u16 len = msgs[i].len;
	244	u8 *buf = msgs[i].buf;
	245
	246	if (msgs[i].flags & I2C_M_RD) {
	247	I915_WRITE(GMBUS1 + reg_offset,
	248	GMBUS_CYCLE_WAIT \| (i + 1 == num ? GMBUS_CYCLE_STOP : 0) \|
	249	(len << GMBUS_BYTE_COUNT_SHIFT) \|
	250	(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) \|
	251	GMBUS_SLAVE_READ \| GMBUS_SW_RDY);
e957d772	252	POSTING_READ(GMBUS2+reg_offset);
f899fc64 CW	253	do {
	254	u32 val, loop = 0;
	255
	256	if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER \| GMBUS_HW_RDY), 50))
	257	goto timeout;
	258	if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
	259	return 0;
	260
	261	val = I915_READ(GMBUS3 + reg_offset);
	262	do {
	263	*buf++ = val & 0xff;
	264	val >>= 8;
	265	} while (--len && ++loop < 4);
	266	} while (len);
	267	} else {
e957d772	268	u32 val, loop;
f899fc64	269
e957d772	270	val = loop = 0;
f899fc64	271	do {
e957d772 CW	272	val \|= buf++ << (8 loop);
e957d772 CW	273	} while (--len && ++loop < 4);
f899fc64 CW	274
	275	I915_WRITE(GMBUS3 + reg_offset, val);
	276	I915_WRITE(GMBUS1 + reg_offset,
e957d772	277	(i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) \|
f899fc64 CW	278	(msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) \|
	279	(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) \|
	280	GMBUS_SLAVE_WRITE \| GMBUS_SW_RDY);
e957d772 CW	281	POSTING_READ(GMBUS2+reg_offset);
	282
	283	while (len) {
	284	if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER \| GMBUS_HW_RDY), 50))
	285	goto timeout;
	286	if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
	287	return 0;
	288
	289	val = loop = 0;
	290	do {
	291	val \|= buf++ << (8 loop);
	292	} while (--len && ++loop < 4);
	293
	294	I915_WRITE(GMBUS3 + reg_offset, val);
	295	POSTING_READ(GMBUS2+reg_offset);
	296	}
f899fc64 CW	297	}
	298
	299	if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER \| GMBUS_HW_WAIT_PHASE), 50))
	300	goto timeout;
	301	if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
	302	return 0;
	303	}
	304
	305	return num;
	306
	307	timeout:
e957d772 CW	308	DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
e957d772 CW	309	bus->reg0 & 0xff, bus->adapter.name);
f899fc64	310	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
e957d772 CW	311	bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
e957d772 CW	312	if (!bus->force_bit)
f899fc64 CW	313	return -ENOMEM;
f899fc64 CW	314
e957d772	315	return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
f899fc64 CW	316	}
	317
	318	static u32 gmbus_func(struct i2c_adapter *adapter)
	319	{
e957d772 CW	320	struct intel_gmbus *bus = container_of(adapter,
	321	struct intel_gmbus,
	322	adapter);
	323
	324	if (bus->force_bit)
	325	bus->force_bit->algo->functionality(bus->force_bit);
	326
f899fc64 CW	327	return (I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \|
	328	/* I2C_FUNC_10BIT_ADDR \| */
	329	I2C_FUNC_SMBUS_READ_BLOCK_DATA \|
	330	I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
	331	}
	332
	333	static const struct i2c_algorithm gmbus_algorithm = {
	334	.master_xfer = gmbus_xfer,
	335	.functionality = gmbus_func
	336	};
	337
79e53945	338	/**
f899fc64 CW	339	* intel_gmbus_setup - instantiate all Intel i2c GMBuses
f899fc64 CW	340	* @dev: DRM device
79e53945	341	*/
f899fc64 CW	342	int intel_setup_gmbus(struct drm_device *dev)
f899fc64 CW	343	{
e957d772	344	static const char *names[GMBUS_NUM_PORTS] = {
f899fc64 CW	345	"disabled",
	346	"ssc",
	347	"vga",
	348	"panel",
	349	"dpc",
	350	"dpb",
f899fc64	351	"reserved"
e957d772	352	"dpd",
f899fc64 CW	353	};
	354	struct drm_i915_private *dev_priv = dev->dev_private;
	355	int ret, i;
	356
	357	dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
	358	GFP_KERNEL);
	359	if (dev_priv->gmbus == NULL)
	360	return -ENOMEM;
	361
	362	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
	363	struct intel_gmbus *bus = &dev_priv->gmbus[i];
	364
	365	bus->adapter.owner = THIS_MODULE;
	366	bus->adapter.class = I2C_CLASS_DDC;
	367	snprintf(bus->adapter.name,
	368	I2C_NAME_SIZE,
	369	"gmbus %s",
	370	names[i]);
	371
	372	bus->adapter.dev.parent = &dev->pdev->dev;
	373	bus->adapter.algo_data = dev_priv;
	374
	375	bus->adapter.algo = &gmbus_algorithm;
	376	ret = i2c_add_adapter(&bus->adapter);
	377	if (ret)
	378	goto err;
	379
e957d772 CW	380	/* By default use a conservative clock rate */
e957d772 CW	381	bus->reg0 = i \| GMBUS_RATE_100KHZ;
cb8ea752 CW	382
	383	/* XXX force bit banging until GMBUS is fully debugged */
	384	bus->force_bit = intel_gpio_create(dev_priv, i);
f899fc64 CW	385	}
	386
	387	intel_i2c_reset(dev_priv->dev);
	388
	389	return 0;
	390
	391	err:
	392	while (--i) {
	393	struct intel_gmbus *bus = &dev_priv->gmbus[i];
	394	i2c_del_adapter(&bus->adapter);
	395	}
	396	kfree(dev_priv->gmbus);
	397	dev_priv->gmbus = NULL;
	398	return ret;
	399	}
	400
e957d772 CW	401	void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
	402	{
	403	struct intel_gmbus *bus = to_intel_gmbus(adapter);
	404
	405	/* speed:
	406	* 0x0 = 100 KHz
	407	* 0x1 = 50 KHz
	408	* 0x2 = 400 KHz
	409	* 0x3 = 1000 Khz
	410	*/
	411	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) \| (speed << 8);
	412	}
	413
	414	void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
	415	{
	416	struct intel_gmbus *bus = to_intel_gmbus(adapter);
	417
	418	if (force_bit) {
	419	if (bus->force_bit == NULL) {
	420	struct drm_i915_private *dev_priv = adapter->algo_data;
	421	bus->force_bit = intel_gpio_create(dev_priv,
	422	bus->reg0 & 0xff);
	423	}
	424	} else {
	425	if (bus->force_bit) {
	426	i2c_del_adapter(bus->force_bit);
	427	kfree(bus->force_bit);
	428	bus->force_bit = NULL;
	429	}
	430	}
	431	}
	432
f899fc64	433	void intel_teardown_gmbus(struct drm_device *dev)
79e53945	434	{
f899fc64 CW	435	struct drm_i915_private *dev_priv = dev->dev_private;
f899fc64 CW	436	int i;
f9c10a9b	437
f899fc64	438	if (dev_priv->gmbus == NULL)
79e53945 JB	439	return;
79e53945 JB	440
f899fc64 CW	441	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
f899fc64 CW	442	struct intel_gmbus *bus = &dev_priv->gmbus[i];
e957d772 CW	443	if (bus->force_bit) {
	444	i2c_del_adapter(bus->force_bit);
	445	kfree(bus->force_bit);
f899fc64 CW	446	}
	447	i2c_del_adapter(&bus->adapter);
	448	}
	449
	450	kfree(dev_priv->gmbus);
	451	dev_priv->gmbus = NULL;
79e53945	452	}