]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/i915/intel_dp.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/ringbuffer: Set ring->gem_buffer = NULL on init unwind
[net-next-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
a4fc5ed6
KP		 30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
ab2c0672 37#include "drm_dp_helper.h"
a4fc5ed6 38
ae266c98 39
a4fc5ed6
KP		 40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43#define DP_LINK_CONFIGURATION_SIZE 9
44
ea5b213a
CW		 45#define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46#define IS_PCH_eDP(i) ((i)->is_pch_edp)
32f9d658 47
ea5b213a
CW		 48struct intel_dp {
49 struct intel_encoder base;
a4fc5ed6
KP		 50 uint32_t output_reg;
51 uint32_t DP;
52 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 53 bool has_audio;
c8110e52 54 int dpms_mode;
a4fc5ed6
KP		 55 uint8_t link_bw;
56 uint8_t lane_count;
57 uint8_t dpcd[4];
a4fc5ed6
KP		 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
f0917379 60 bool is_pch_edp;
a4fc5ed6
KP		 61};
62
ea5b213a
CW		 63static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
64{
65 return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base);
66}
a4fc5ed6 67
ea5b213a
CW		 68static void intel_dp_link_train(struct intel_dp *intel_dp);
69static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 70
32f9d658 71void
21d40d37 72intel_edp_link_config (struct intel_encoder *intel_encoder,
ea5b213a 73 int *lane_num, int *link_bw)
32f9d658 74{
ea5b213a 75 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 76
ea5b213a
CW		 77 *lane_num = intel_dp->lane_count;
78 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 79 *link_bw = 162000;
ea5b213a 80 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 81 *link_bw = 270000;
82}
83
a4fc5ed6 84static int
ea5b213a 85intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 86{
a4fc5ed6
KP		 87 int max_lane_count = 4;
88
ea5b213a
CW		 89 if (intel_dp->dpcd[0] >= 0x11) {
90 max_lane_count = intel_dp->dpcd[2] & 0x1f;
a4fc5ed6
KP		 91 switch (max_lane_count) {
92 case 1: case 2: case 4:
93 break;
94 default:
95 max_lane_count = 4;
96 }
97 }
98 return max_lane_count;
99}
100
101static int
ea5b213a 102intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 103{
ea5b213a 104 int max_link_bw = intel_dp->dpcd[1];
a4fc5ed6
KP		 105
106 switch (max_link_bw) {
107 case DP_LINK_BW_1_62:
108 case DP_LINK_BW_2_7:
109 break;
110 default:
111 max_link_bw = DP_LINK_BW_1_62;
112 break;
113 }
114 return max_link_bw;
115}
116
117static int
118intel_dp_link_clock(uint8_t link_bw)
119{
120 if (link_bw == DP_LINK_BW_2_7)
121 return 270000;
122 else
123 return 162000;
124}
125
126/* I think this is a fiction */
127static int
ea5b213a 128intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
a4fc5ed6 129{
885a5fb5
ZW		 130 struct drm_i915_private *dev_priv = dev->dev_private;
131
ea5b213a 132 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
885a5fb5
ZW		 133 return (pixel_clock * dev_priv->edp_bpp) / 8;
134 else
135 return pixel_clock * 3;
a4fc5ed6
KP		 136}
137
fe27d53e
DA		 138static int
139intel_dp_max_data_rate(int max_link_clock, int max_lanes)
140{
141 return (max_link_clock * max_lanes * 8) / 10;
142}
143
a4fc5ed6
KP		 144static int
145intel_dp_mode_valid(struct drm_connector *connector,
146 struct drm_display_mode *mode)
147{
55f78c43 148 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 149 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
7de56f43
ZY		 150 struct drm_device *dev = connector->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a
CW		 152 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
153 int max_lanes = intel_dp_max_lane_count(intel_dp);
a4fc5ed6 154
ea5b213a 155 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
7de56f43
ZY		 156 dev_priv->panel_fixed_mode) {
157 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
158 return MODE_PANEL;
159
160 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
161 return MODE_PANEL;
162 }
163
fe27d53e
DA		 164 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
165 which are outside spec tolerances but somehow work by magic */
ea5b213a
CW		 166 if (!IS_eDP(intel_dp) &&
167 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
fe27d53e 168 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
a4fc5ed6
KP		 169 return MODE_CLOCK_HIGH;
170
171 if (mode->clock < 10000)
172 return MODE_CLOCK_LOW;
173
174 return MODE_OK;
175}
176
177static uint32_t
178pack_aux(uint8_t *src, int src_bytes)
179{
180 int i;
181 uint32_t v = 0;
182
183 if (src_bytes > 4)
184 src_bytes = 4;
185 for (i = 0; i < src_bytes; i++)
186 v |= ((uint32_t) src[i]) << ((3-i) * 8);
187 return v;
188}
189
190static void
191unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
192{
193 int i;
194 if (dst_bytes > 4)
195 dst_bytes = 4;
196 for (i = 0; i < dst_bytes; i++)
197 dst[i] = src >> ((3-i) * 8);
198}
199
fb0f8fbf
KP		 200/* hrawclock is 1/4 the FSB frequency */
201static int
202intel_hrawclk(struct drm_device *dev)
203{
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 uint32_t clkcfg;
206
207 clkcfg = I915_READ(CLKCFG);
208 switch (clkcfg & CLKCFG_FSB_MASK) {
209 case CLKCFG_FSB_400:
210 return 100;
211 case CLKCFG_FSB_533:
212 return 133;
213 case CLKCFG_FSB_667:
214 return 166;
215 case CLKCFG_FSB_800:
216 return 200;
217 case CLKCFG_FSB_1067:
218 return 266;
219 case CLKCFG_FSB_1333:
220 return 333;
221 /* these two are just a guess; one of them might be right */
222 case CLKCFG_FSB_1600:
223 case CLKCFG_FSB_1600_ALT:
224 return 400;
225 default:
226 return 133;
227 }
228}
229
a4fc5ed6 230static int
ea5b213a 231intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 232 uint8_t *send, int send_bytes,
233 uint8_t *recv, int recv_size)
234{
ea5b213a
CW		 235 uint32_t output_reg = intel_dp->output_reg;
236 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6
KP		 237 struct drm_i915_private *dev_priv = dev->dev_private;
238 uint32_t ch_ctl = output_reg + 0x10;
239 uint32_t ch_data = ch_ctl + 4;
240 int i;
241 int recv_bytes;
242 uint32_t ctl;
243 uint32_t status;
fb0f8fbf 244 uint32_t aux_clock_divider;
e3421a18 245 int try, precharge;
a4fc5ed6
KP		 246
247 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 248 * and would like to run at 2MHz. So, take the
249 * hrawclk value and divide by 2 and use that
a4fc5ed6 250 */
ea5b213a 251 if (IS_eDP(intel_dp)) {
e3421a18
ZW		 252 if (IS_GEN6(dev))
253 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
254 else
255 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
256 } else if (HAS_PCH_SPLIT(dev))
f2b115e6 257 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 258 else
259 aux_clock_divider = intel_hrawclk(dev) / 2;
260
e3421a18
ZW		 261 if (IS_GEN6(dev))
262 precharge = 3;
263 else
264 precharge = 5;
265
fb0f8fbf
KP		 266 /* Must try at least 3 times according to DP spec */
267 for (try = 0; try < 5; try++) {
268 /* Load the send data into the aux channel data registers */
269 for (i = 0; i < send_bytes; i += 4) {
a419aef8 270 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 271
272 I915_WRITE(ch_data + i, d);
273 }
274
275 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
276 DP_AUX_CH_CTL_TIME_OUT_400us |
277 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
e3421a18 278 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
fb0f8fbf
KP		 279 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
280 DP_AUX_CH_CTL_DONE |
281 DP_AUX_CH_CTL_TIME_OUT_ERROR |
282 DP_AUX_CH_CTL_RECEIVE_ERROR);
283
284 /* Send the command and wait for it to complete */
285 I915_WRITE(ch_ctl, ctl);
286 (void) I915_READ(ch_ctl);
287 for (;;) {
288 udelay(100);
289 status = I915_READ(ch_ctl);
290 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
291 break;
292 }
293
294 /* Clear done status and any errors */
eebc863e 295 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 296 DP_AUX_CH_CTL_DONE |
297 DP_AUX_CH_CTL_TIME_OUT_ERROR |
298 DP_AUX_CH_CTL_RECEIVE_ERROR));
299 (void) I915_READ(ch_ctl);
300 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 301 break;
302 }
303
a4fc5ed6 304 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 305 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 306 return -EBUSY;
a4fc5ed6
KP		 307 }
308
309 /* Check for timeout or receive error.
310 * Timeouts occur when the sink is not connected
311 */
a5b3da54 312 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 313 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 314 return -EIO;
315 }
1ae8c0a5
KP		 316
317 /* Timeouts occur when the device isn't connected, so they're
318 * "normal" -- don't fill the kernel log with these */
a5b3da54 319 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 320 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 321 return -ETIMEDOUT;
a4fc5ed6
KP		 322 }
323
324 /* Unload any bytes sent back from the other side */
325 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
326 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
327
328 if (recv_bytes > recv_size)
329 recv_bytes = recv_size;
330
331 for (i = 0; i < recv_bytes; i += 4) {
332 uint32_t d = I915_READ(ch_data + i);
333
334 unpack_aux(d, recv + i, recv_bytes - i);
335 }
336
337 return recv_bytes;
338}
339
340/* Write data to the aux channel in native mode */
341static int
ea5b213a 342intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 343 uint16_t address, uint8_t *send, int send_bytes)
344{
345 int ret;
346 uint8_t msg[20];
347 int msg_bytes;
348 uint8_t ack;
349
350 if (send_bytes > 16)
351 return -1;
352 msg[0] = AUX_NATIVE_WRITE << 4;
353 msg[1] = address >> 8;
eebc863e 354 msg[2] = address & 0xff;
a4fc5ed6
KP		 355 msg[3] = send_bytes - 1;
356 memcpy(&msg[4], send, send_bytes);
357 msg_bytes = send_bytes + 4;
358 for (;;) {
ea5b213a 359 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 360 if (ret < 0)
361 return ret;
362 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
363 break;
364 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
365 udelay(100);
366 else
a5b3da54 367 return -EIO;
a4fc5ed6
KP		 368 }
369 return send_bytes;
370}
371
372/* Write a single byte to the aux channel in native mode */
373static int
ea5b213a 374intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 375 uint16_t address, uint8_t byte)
376{
ea5b213a 377 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 378}
379
380/* read bytes from a native aux channel */
381static int
ea5b213a 382intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 383 uint16_t address, uint8_t *recv, int recv_bytes)
384{
385 uint8_t msg[4];
386 int msg_bytes;
387 uint8_t reply[20];
388 int reply_bytes;
389 uint8_t ack;
390 int ret;
391
392 msg[0] = AUX_NATIVE_READ << 4;
393 msg[1] = address >> 8;
394 msg[2] = address & 0xff;
395 msg[3] = recv_bytes - 1;
396
397 msg_bytes = 4;
398 reply_bytes = recv_bytes + 1;
399
400 for (;;) {
ea5b213a 401 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 402 reply, reply_bytes);
a5b3da54
KP		 403 if (ret == 0)
404 return -EPROTO;
405 if (ret < 0)
a4fc5ed6
KP		 406 return ret;
407 ack = reply[0];
408 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
409 memcpy(recv, reply + 1, ret - 1);
410 return ret - 1;
411 }
412 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
413 udelay(100);
414 else
a5b3da54 415 return -EIO;
a4fc5ed6
KP		 416 }
417}
418
419static int
ab2c0672
DA		 420intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
421 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 422{
ab2c0672 423 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 424 struct intel_dp *intel_dp = container_of(adapter,
425 struct intel_dp,
426 adapter);
ab2c0672
DA		 427 uint16_t address = algo_data->address;
428 uint8_t msg[5];
429 uint8_t reply[2];
430 int msg_bytes;
431 int reply_bytes;
432 int ret;
433
434 /* Set up the command byte */
435 if (mode & MODE_I2C_READ)
436 msg[0] = AUX_I2C_READ << 4;
437 else
438 msg[0] = AUX_I2C_WRITE << 4;
439
440 if (!(mode & MODE_I2C_STOP))
441 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 442
ab2c0672
DA		 443 msg[1] = address >> 8;
444 msg[2] = address;
445
446 switch (mode) {
447 case MODE_I2C_WRITE:
448 msg[3] = 0;
449 msg[4] = write_byte;
450 msg_bytes = 5;
451 reply_bytes = 1;
452 break;
453 case MODE_I2C_READ:
454 msg[3] = 0;
455 msg_bytes = 4;
456 reply_bytes = 2;
457 break;
458 default:
459 msg_bytes = 3;
460 reply_bytes = 1;
461 break;
462 }
463
464 for (;;) {
ea5b213a 465 ret = intel_dp_aux_ch(intel_dp,
ab2c0672
DA		 466 msg, msg_bytes,
467 reply, reply_bytes);
468 if (ret < 0) {
3ff99164 469 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 470 return ret;
471 }
472 switch (reply[0] & AUX_I2C_REPLY_MASK) {
473 case AUX_I2C_REPLY_ACK:
474 if (mode == MODE_I2C_READ) {
475 *read_byte = reply[1];
476 }
477 return reply_bytes - 1;
478 case AUX_I2C_REPLY_NACK:
3ff99164 479 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 480 return -EREMOTEIO;
481 case AUX_I2C_REPLY_DEFER:
3ff99164 482 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 483 udelay(100);
484 break;
485 default:
486 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
487 return -EREMOTEIO;
488 }
489 }
a4fc5ed6
KP		 490}
491
492static int
ea5b213a 493intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 494 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 495{
d54e9d28 496 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 497 intel_dp->algo.running = false;
498 intel_dp->algo.address = 0;
499 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
500
501 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
502 intel_dp->adapter.owner = THIS_MODULE;
503 intel_dp->adapter.class = I2C_CLASS_DDC;
504 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
505 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
506 intel_dp->adapter.algo_data = &intel_dp->algo;
507 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
508
509 return i2c_dp_aux_add_bus(&intel_dp->adapter);
a4fc5ed6
KP		 510}
511
512static bool
513intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
514 struct drm_display_mode *adjusted_mode)
515{
0d3a1bee
ZY		 516 struct drm_device *dev = encoder->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 518 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 519 int lane_count, clock;
ea5b213a
CW		 520 int max_lane_count = intel_dp_max_lane_count(intel_dp);
521 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
a4fc5ed6
KP		 522 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
523
ea5b213a 524 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
0d3a1bee 525 dev_priv->panel_fixed_mode) {
1d8e1c75
CW		 526 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
527 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
528 mode, adjusted_mode);
0d3a1bee
ZY		 529 /*
530 * the mode->clock is used to calculate the Data&Link M/N
531 * of the pipe. For the eDP the fixed clock should be used.
532 */
533 mode->clock = dev_priv->panel_fixed_mode->clock;
534 }
535
a4fc5ed6
KP		 536 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
537 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 538 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 539
ea5b213a 540 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
885a5fb5 541 <= link_avail) {
ea5b213a
CW		 542 intel_dp->link_bw = bws[clock];
543 intel_dp->lane_count = lane_count;
544 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
28c97730
ZY		 545 DRM_DEBUG_KMS("Display port link bw %02x lane "
546 "count %d clock %d\n",
ea5b213a 547 intel_dp->link_bw, intel_dp->lane_count,
a4fc5ed6
KP		 548 adjusted_mode->clock);
549 return true;
550 }
551 }
552 }
fe27d53e 553
ea5b213a 554 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
fe27d53e 555 /* okay we failed just pick the highest */
ea5b213a
CW		 556 intel_dp->lane_count = max_lane_count;
557 intel_dp->link_bw = bws[max_clock];
558 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
fe27d53e
DA		 559 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
560 "count %d clock %d\n",
ea5b213a 561 intel_dp->link_bw, intel_dp->lane_count,
fe27d53e 562 adjusted_mode->clock);
1d8e1c75 563
fe27d53e
DA		 564 return true;
565 }
1d8e1c75 566
a4fc5ed6
KP		 567 return false;
568}
569
570struct intel_dp_m_n {
571 uint32_t tu;
572 uint32_t gmch_m;
573 uint32_t gmch_n;
574 uint32_t link_m;
575 uint32_t link_n;
576};
577
578static void
579intel_reduce_ratio(uint32_t *num, uint32_t *den)
580{
581 while (*num > 0xffffff || *den > 0xffffff) {
582 *num >>= 1;
583 *den >>= 1;
584 }
585}
586
587static void
36e83a18 588intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 589 int nlanes,
590 int pixel_clock,
591 int link_clock,
592 struct intel_dp_m_n *m_n)
593{
594 m_n->tu = 64;
36e83a18 595 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 596 m_n->gmch_n = link_clock * nlanes;
597 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
598 m_n->link_m = pixel_clock;
599 m_n->link_n = link_clock;
600 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
601}
602
36e83a18
ZY		 603bool intel_pch_has_edp(struct drm_crtc *crtc)
604{
605 struct drm_device *dev = crtc->dev;
606 struct drm_mode_config *mode_config = &dev->mode_config;
607 struct drm_encoder *encoder;
608
609 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 610 struct intel_dp *intel_dp;
36e83a18 611
ea5b213a 612 if (encoder->crtc != crtc)
36e83a18
ZY		 613 continue;
614
ea5b213a
CW		 615 intel_dp = enc_to_intel_dp(encoder);
616 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
617 return intel_dp->is_pch_edp;
36e83a18
ZY		 618 }
619 return false;
620}
621
a4fc5ed6
KP		 622void
623intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
624 struct drm_display_mode *adjusted_mode)
625{
626 struct drm_device *dev = crtc->dev;
627 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 628 struct drm_encoder *encoder;
a4fc5ed6
KP		 629 struct drm_i915_private *dev_priv = dev->dev_private;
630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
36e83a18 631 int lane_count = 4, bpp = 24;
a4fc5ed6
KP		 632 struct intel_dp_m_n m_n;
633
634 /*
21d40d37 635 * Find the lane count in the intel_encoder private
a4fc5ed6 636 */
55f78c43 637 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 638 struct intel_dp *intel_dp;
a4fc5ed6 639
d8201ab6 640 if (encoder->crtc != crtc)
a4fc5ed6
KP		 641 continue;
642
ea5b213a
CW		 643 intel_dp = enc_to_intel_dp(encoder);
644 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
645 lane_count = intel_dp->lane_count;
646 if (IS_PCH_eDP(intel_dp))
36e83a18 647 bpp = dev_priv->edp_bpp;
a4fc5ed6
KP		 648 break;
649 }
650 }
651
652 /*
653 * Compute the GMCH and Link ratios. The '3' here is
654 * the number of bytes_per_pixel post-LUT, which we always
655 * set up for 8-bits of R/G/B, or 3 bytes total.
656 */
36e83a18 657 intel_dp_compute_m_n(bpp, lane_count,
a4fc5ed6
KP		 658 mode->clock, adjusted_mode->clock, &m_n);
659
c619eed4 660 if (HAS_PCH_SPLIT(dev)) {
5eb08b69
ZW		 661 if (intel_crtc->pipe == 0) {
662 I915_WRITE(TRANSA_DATA_M1,
663 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
664 m_n.gmch_m);
665 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
666 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
667 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
668 } else {
669 I915_WRITE(TRANSB_DATA_M1,
670 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
671 m_n.gmch_m);
672 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
673 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
674 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
675 }
a4fc5ed6 676 } else {
5eb08b69
ZW		 677 if (intel_crtc->pipe == 0) {
678 I915_WRITE(PIPEA_GMCH_DATA_M,
679 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
680 m_n.gmch_m);
681 I915_WRITE(PIPEA_GMCH_DATA_N,
682 m_n.gmch_n);
683 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
684 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
685 } else {
686 I915_WRITE(PIPEB_GMCH_DATA_M,
687 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
688 m_n.gmch_m);
689 I915_WRITE(PIPEB_GMCH_DATA_N,
690 m_n.gmch_n);
691 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
692 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
693 }
a4fc5ed6
KP		 694 }
695}
696
697static void
698intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
699 struct drm_display_mode *adjusted_mode)
700{
e3421a18 701 struct drm_device *dev = encoder->dev;
ea5b213a
CW		 702 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
703 struct drm_crtc *crtc = intel_dp->base.enc.crtc;
a4fc5ed6
KP		 704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
705
ea5b213a 706 intel_dp->DP = (DP_VOLTAGE_0_4 |
9c9e7927
AJ		 707 DP_PRE_EMPHASIS_0);
708
709 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
ea5b213a 710 intel_dp->DP |= DP_SYNC_HS_HIGH;
9c9e7927 711 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
ea5b213a 712 intel_dp->DP |= DP_SYNC_VS_HIGH;
a4fc5ed6 713
ea5b213a
CW		 714 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
715 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3421a18 716 else
ea5b213a 717 intel_dp->DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6 718
ea5b213a 719 switch (intel_dp->lane_count) {
a4fc5ed6 720 case 1:
ea5b213a 721 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 722 break;
723 case 2:
ea5b213a 724 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 725 break;
726 case 4:
ea5b213a 727 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 728 break;
729 }
ea5b213a
CW		 730 if (intel_dp->has_audio)
731 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
a4fc5ed6 732
ea5b213a
CW		 733 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
734 intel_dp->link_configuration[0] = intel_dp->link_bw;
735 intel_dp->link_configuration[1] = intel_dp->lane_count;
a4fc5ed6
KP		 736
737 /*
9962c925 738 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 739 */
ea5b213a
CW		 740 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
741 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
742 intel_dp->DP |= DP_ENHANCED_FRAMING;
a4fc5ed6
KP		 743 }
744
e3421a18
ZW		 745 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
746 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
ea5b213a 747 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 748
ea5b213a 749 if (IS_eDP(intel_dp)) {
32f9d658 750 /* don't miss out required setting for eDP */
ea5b213a 751 intel_dp->DP |= DP_PLL_ENABLE;
32f9d658 752 if (adjusted_mode->clock < 200000)
ea5b213a 753 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
32f9d658 754 else
ea5b213a 755 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
32f9d658 756 }
a4fc5ed6
KP		 757}
758
9934c132
JB		 759static void ironlake_edp_panel_on (struct drm_device *dev)
760{
761 struct drm_i915_private *dev_priv = dev->dev_private;
762 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
763 u32 pp, pp_status;
764
765 pp_status = I915_READ(PCH_PP_STATUS);
766 if (pp_status & PP_ON)
767 return;
768
769 pp = I915_READ(PCH_PP_CONTROL);
770 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
771 I915_WRITE(PCH_PP_CONTROL, pp);
772 do {
773 pp_status = I915_READ(PCH_PP_STATUS);
774 } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
775
776 if (time_after(jiffies, timeout))
777 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
778
779 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
780 I915_WRITE(PCH_PP_CONTROL, pp);
781}
782
783static void ironlake_edp_panel_off (struct drm_device *dev)
784{
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
787 u32 pp, pp_status;
788
789 pp = I915_READ(PCH_PP_CONTROL);
790 pp &= ~POWER_TARGET_ON;
791 I915_WRITE(PCH_PP_CONTROL, pp);
792 do {
793 pp_status = I915_READ(PCH_PP_STATUS);
794 } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
795
796 if (time_after(jiffies, timeout))
797 DRM_DEBUG_KMS("panel off wait timed out\n");
798
799 /* Make sure VDD is enabled so DP AUX will work */
800 pp |= EDP_FORCE_VDD;
801 I915_WRITE(PCH_PP_CONTROL, pp);
802}
803
f2b115e6 804static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 805{
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 u32 pp;
808
28c97730 809 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 810 pp = I915_READ(PCH_PP_CONTROL);
811 pp |= EDP_BLC_ENABLE;
812 I915_WRITE(PCH_PP_CONTROL, pp);
813}
814
f2b115e6 815static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 816{
817 struct drm_i915_private *dev_priv = dev->dev_private;
818 u32 pp;
819
28c97730 820 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 821 pp = I915_READ(PCH_PP_CONTROL);
822 pp &= ~EDP_BLC_ENABLE;
823 I915_WRITE(PCH_PP_CONTROL, pp);
824}
a4fc5ed6
KP		 825
826static void
827intel_dp_dpms(struct drm_encoder *encoder, int mode)
828{
ea5b213a 829 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
55f78c43 830 struct drm_device *dev = encoder->dev;
a4fc5ed6 831 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 832 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
a4fc5ed6
KP		 833
834 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 835 if (dp_reg & DP_PORT_EN) {
ea5b213a
CW		 836 intel_dp_link_down(intel_dp);
837 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
f2b115e6 838 ironlake_edp_backlight_off(dev);
5620ae29 839 ironlake_edp_panel_off(dev);
9934c132 840 }
32f9d658 841 }
a4fc5ed6 842 } else {
32f9d658 843 if (!(dp_reg & DP_PORT_EN)) {
ea5b213a
CW		 844 intel_dp_link_train(intel_dp);
845 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
9934c132 846 ironlake_edp_panel_on(dev);
f2b115e6 847 ironlake_edp_backlight_on(dev);
9934c132 848 }
32f9d658 849 }
a4fc5ed6 850 }
ea5b213a 851 intel_dp->dpms_mode = mode;
a4fc5ed6
KP		 852}
853
854/*
855 * Fetch AUX CH registers 0x202 - 0x207 which contain
856 * link status information
857 */
858static bool
ea5b213a 859intel_dp_get_link_status(struct intel_dp *intel_dp,
a4fc5ed6
KP		 860 uint8_t link_status[DP_LINK_STATUS_SIZE])
861{
862 int ret;
863
ea5b213a 864 ret = intel_dp_aux_native_read(intel_dp,
a4fc5ed6
KP		 865 DP_LANE0_1_STATUS,
866 link_status, DP_LINK_STATUS_SIZE);
867 if (ret != DP_LINK_STATUS_SIZE)
868 return false;
869 return true;
870}
871
872static uint8_t
873intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
874 int r)
875{
876 return link_status[r - DP_LANE0_1_STATUS];
877}
878
a4fc5ed6
KP		 879static uint8_t
880intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
881 int lane)
882{
883 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
884 int s = ((lane & 1) ?
885 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
886 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
887 uint8_t l = intel_dp_link_status(link_status, i);
888
889 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
890}
891
892static uint8_t
893intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
894 int lane)
895{
896 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
897 int s = ((lane & 1) ?
898 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
899 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
900 uint8_t l = intel_dp_link_status(link_status, i);
901
902 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
903}
904
905
906#if 0
907static char *voltage_names[] = {
908 "0.4V", "0.6V", "0.8V", "1.2V"
909};
910static char *pre_emph_names[] = {
911 "0dB", "3.5dB", "6dB", "9.5dB"
912};
913static char *link_train_names[] = {
914 "pattern 1", "pattern 2", "idle", "off"
915};
916#endif
917
918/*
919 * These are source-specific values; current Intel hardware supports
920 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
921 */
922#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
923
924static uint8_t
925intel_dp_pre_emphasis_max(uint8_t voltage_swing)
926{
927 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
928 case DP_TRAIN_VOLTAGE_SWING_400:
929 return DP_TRAIN_PRE_EMPHASIS_6;
930 case DP_TRAIN_VOLTAGE_SWING_600:
931 return DP_TRAIN_PRE_EMPHASIS_6;
932 case DP_TRAIN_VOLTAGE_SWING_800:
933 return DP_TRAIN_PRE_EMPHASIS_3_5;
934 case DP_TRAIN_VOLTAGE_SWING_1200:
935 default:
936 return DP_TRAIN_PRE_EMPHASIS_0;
937 }
938}
939
940static void
ea5b213a 941intel_get_adjust_train(struct intel_dp *intel_dp,
a4fc5ed6
KP		 942 uint8_t link_status[DP_LINK_STATUS_SIZE],
943 int lane_count,
944 uint8_t train_set[4])
945{
946 uint8_t v = 0;
947 uint8_t p = 0;
948 int lane;
949
950 for (lane = 0; lane < lane_count; lane++) {
951 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
952 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
953
954 if (this_v > v)
955 v = this_v;
956 if (this_p > p)
957 p = this_p;
958 }
959
960 if (v >= I830_DP_VOLTAGE_MAX)
961 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
962
963 if (p >= intel_dp_pre_emphasis_max(v))
964 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
965
966 for (lane = 0; lane < 4; lane++)
967 train_set[lane] = v | p;
968}
969
970static uint32_t
971intel_dp_signal_levels(uint8_t train_set, int lane_count)
972{
973 uint32_t signal_levels = 0;
974
975 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
976 case DP_TRAIN_VOLTAGE_SWING_400:
977 default:
978 signal_levels |= DP_VOLTAGE_0_4;
979 break;
980 case DP_TRAIN_VOLTAGE_SWING_600:
981 signal_levels |= DP_VOLTAGE_0_6;
982 break;
983 case DP_TRAIN_VOLTAGE_SWING_800:
984 signal_levels |= DP_VOLTAGE_0_8;
985 break;
986 case DP_TRAIN_VOLTAGE_SWING_1200:
987 signal_levels |= DP_VOLTAGE_1_2;
988 break;
989 }
990 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
991 case DP_TRAIN_PRE_EMPHASIS_0:
992 default:
993 signal_levels |= DP_PRE_EMPHASIS_0;
994 break;
995 case DP_TRAIN_PRE_EMPHASIS_3_5:
996 signal_levels |= DP_PRE_EMPHASIS_3_5;
997 break;
998 case DP_TRAIN_PRE_EMPHASIS_6:
999 signal_levels |= DP_PRE_EMPHASIS_6;
1000 break;
1001 case DP_TRAIN_PRE_EMPHASIS_9_5:
1002 signal_levels |= DP_PRE_EMPHASIS_9_5;
1003 break;
1004 }
1005 return signal_levels;
1006}
1007
e3421a18
ZW		 1008/* Gen6's DP voltage swing and pre-emphasis control */
1009static uint32_t
1010intel_gen6_edp_signal_levels(uint8_t train_set)
1011{
1012 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1013 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1014 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1015 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1016 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1017 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1018 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1019 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1020 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1021 default:
1022 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1023 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1024 }
1025}
1026
a4fc5ed6
KP		 1027static uint8_t
1028intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1029 int lane)
1030{
1031 int i = DP_LANE0_1_STATUS + (lane >> 1);
1032 int s = (lane & 1) * 4;
1033 uint8_t l = intel_dp_link_status(link_status, i);
1034
1035 return (l >> s) & 0xf;
1036}
1037
1038/* Check for clock recovery is done on all channels */
1039static bool
1040intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1041{
1042 int lane;
1043 uint8_t lane_status;
1044
1045 for (lane = 0; lane < lane_count; lane++) {
1046 lane_status = intel_get_lane_status(link_status, lane);
1047 if ((lane_status & DP_LANE_CR_DONE) == 0)
1048 return false;
1049 }
1050 return true;
1051}
1052
1053/* Check to see if channel eq is done on all channels */
1054#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1055 DP_LANE_CHANNEL_EQ_DONE|\
1056 DP_LANE_SYMBOL_LOCKED)
1057static bool
1058intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1059{
1060 uint8_t lane_align;
1061 uint8_t lane_status;
1062 int lane;
1063
1064 lane_align = intel_dp_link_status(link_status,
1065 DP_LANE_ALIGN_STATUS_UPDATED);
1066 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1067 return false;
1068 for (lane = 0; lane < lane_count; lane++) {
1069 lane_status = intel_get_lane_status(link_status, lane);
1070 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1071 return false;
1072 }
1073 return true;
1074}
1075
1076static bool
ea5b213a 1077intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6
KP		 1078 uint32_t dp_reg_value,
1079 uint8_t dp_train_pat,
1080 uint8_t train_set[4],
1081 bool first)
1082{
ea5b213a 1083 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1084 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1085 int ret;
1086
ea5b213a
CW		 1087 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1088 POSTING_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1089 if (first)
1090 intel_wait_for_vblank(dev);
1091
ea5b213a 1092 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1093 DP_TRAINING_PATTERN_SET,
1094 dp_train_pat);
1095
ea5b213a 1096 ret = intel_dp_aux_native_write(intel_dp,
a4fc5ed6
KP		 1097 DP_TRAINING_LANE0_SET, train_set, 4);
1098 if (ret != 4)
1099 return false;
1100
1101 return true;
1102}
1103
1104static void
ea5b213a 1105intel_dp_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1106{
ea5b213a 1107 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1108 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1109 uint8_t train_set[4];
1110 uint8_t link_status[DP_LINK_STATUS_SIZE];
1111 int i;
1112 uint8_t voltage;
1113 bool clock_recovery = false;
1114 bool channel_eq = false;
1115 bool first = true;
1116 int tries;
e3421a18 1117 u32 reg;
ea5b213a 1118 uint32_t DP = intel_dp->DP;
a4fc5ed6
KP		 1119
1120 /* Write the link configuration data */
ea5b213a
CW		 1121 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1122 intel_dp->link_configuration,
1123 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1124
1125 DP |= DP_PORT_EN;
ea5b213a 1126 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1127 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1128 else
1129 DP &= ~DP_LINK_TRAIN_MASK;
a4fc5ed6
KP		 1130 memset(train_set, 0, 4);
1131 voltage = 0xff;
1132 tries = 0;
1133 clock_recovery = false;
1134 for (;;) {
1135 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18 1136 uint32_t signal_levels;
ea5b213a 1137 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
e3421a18
ZW		 1138 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1139 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1140 } else {
ea5b213a 1141 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
e3421a18
ZW		 1142 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1143 }
a4fc5ed6 1144
ea5b213a 1145 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1146 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1147 else
1148 reg = DP | DP_LINK_TRAIN_PAT_1;
1149
ea5b213a 1150 if (!intel_dp_set_link_train(intel_dp, reg,
a4fc5ed6
KP		 1151 DP_TRAINING_PATTERN_1, train_set, first))
1152 break;
1153 first = false;
1154 /* Set training pattern 1 */
1155
1156 udelay(100);
ea5b213a 1157 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6
KP		 1158 break;
1159
ea5b213a 1160 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
a4fc5ed6
KP		 1161 clock_recovery = true;
1162 break;
1163 }
1164
1165 /* Check to see if we've tried the max voltage */
ea5b213a 1166 for (i = 0; i < intel_dp->lane_count; i++)
a4fc5ed6
KP		 1167 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1168 break;
ea5b213a 1169 if (i == intel_dp->lane_count)
a4fc5ed6
KP		 1170 break;
1171
1172 /* Check to see if we've tried the same voltage 5 times */
1173 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1174 ++tries;
1175 if (tries == 5)
1176 break;
1177 } else
1178 tries = 0;
1179 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1180
1181 /* Compute new train_set as requested by target */
ea5b213a 1182 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
a4fc5ed6
KP		 1183 }
1184
1185 /* channel equalization */
1186 tries = 0;
1187 channel_eq = false;
1188 for (;;) {
1189 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1190 uint32_t signal_levels;
1191
ea5b213a 1192 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
e3421a18
ZW		 1193 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1194 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1195 } else {
ea5b213a 1196 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
e3421a18
ZW		 1197 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1198 }
1199
ea5b213a 1200 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1201 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1202 else
1203 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1204
1205 /* channel eq pattern */
ea5b213a 1206 if (!intel_dp_set_link_train(intel_dp, reg,
a4fc5ed6
KP		 1207 DP_TRAINING_PATTERN_2, train_set,
1208 false))
1209 break;
1210
1211 udelay(400);
ea5b213a 1212 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6
KP		 1213 break;
1214
ea5b213a 1215 if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) {
a4fc5ed6
KP		 1216 channel_eq = true;
1217 break;
1218 }
1219
1220 /* Try 5 times */
1221 if (tries > 5)
1222 break;
1223
1224 /* Compute new train_set as requested by target */
ea5b213a 1225 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
a4fc5ed6
KP		 1226 ++tries;
1227 }
1228
ea5b213a 1229 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
e3421a18
ZW		 1230 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1231 else
1232 reg = DP | DP_LINK_TRAIN_OFF;
1233
ea5b213a
CW		 1234 I915_WRITE(intel_dp->output_reg, reg);
1235 POSTING_READ(intel_dp->output_reg);
1236 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1237 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1238}
1239
1240static void
ea5b213a 1241intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1242{
ea5b213a 1243 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1244 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1245 uint32_t DP = intel_dp->DP;
a4fc5ed6 1246
28c97730 1247 DRM_DEBUG_KMS("\n");
32f9d658 1248
ea5b213a 1249 if (IS_eDP(intel_dp)) {
32f9d658 1250 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1251 I915_WRITE(intel_dp->output_reg, DP);
1252 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1253 udelay(100);
1254 }
1255
ea5b213a 1256 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) {
e3421a18 1257 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a
CW		 1258 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1259 POSTING_READ(intel_dp->output_reg);
e3421a18
ZW		 1260 } else {
1261 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a
CW		 1262 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1263 POSTING_READ(intel_dp->output_reg);
e3421a18 1264 }
5eb08b69
ZW		 1265
1266 udelay(17000);
1267
ea5b213a 1268 if (IS_eDP(intel_dp))
32f9d658 1269 DP |= DP_LINK_TRAIN_OFF;
ea5b213a
CW		 1270 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1271 POSTING_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1272}
1273
a4fc5ed6
KP		 1274/*
1275 * According to DP spec
1276 * 5.1.2:
1277 * 1. Read DPCD
1278 * 2. Configure link according to Receiver Capabilities
1279 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1280 * 4. Check link status on receipt of hot-plug interrupt
1281 */
1282
1283static void
ea5b213a 1284intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 1285{
a4fc5ed6
KP		 1286 uint8_t link_status[DP_LINK_STATUS_SIZE];
1287
ea5b213a 1288 if (!intel_dp->base.enc.crtc)
a4fc5ed6
KP		 1289 return;
1290
ea5b213a
CW		 1291 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1292 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 1293 return;
1294 }
1295
ea5b213a
CW		 1296 if (!intel_channel_eq_ok(link_status, intel_dp->lane_count))
1297 intel_dp_link_train(intel_dp);
a4fc5ed6 1298}
a4fc5ed6 1299
5eb08b69 1300static enum drm_connector_status
f2b115e6 1301ironlake_dp_detect(struct drm_connector *connector)
5eb08b69 1302{
55f78c43 1303 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a 1304 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5eb08b69
ZW		 1305 enum drm_connector_status status;
1306
1307 status = connector_status_disconnected;
ea5b213a
CW		 1308 if (intel_dp_aux_native_read(intel_dp,
1309 0x000, intel_dp->dpcd,
1310 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
5eb08b69 1311 {
ea5b213a 1312 if (intel_dp->dpcd[0] != 0)
5eb08b69
ZW		 1313 status = connector_status_connected;
1314 }
ea5b213a
CW		 1315 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1316 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
5eb08b69
ZW		 1317 return status;
1318}
1319
a4fc5ed6
KP		 1320/**
1321 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1322 *
1323 * \return true if DP port is connected.
1324 * \return false if DP port is disconnected.
1325 */
1326static enum drm_connector_status
1327intel_dp_detect(struct drm_connector *connector)
1328{
55f78c43 1329 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a
CW		 1330 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1331 struct drm_device *dev = intel_dp->base.enc.dev;
a4fc5ed6 1332 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1333 uint32_t temp, bit;
1334 enum drm_connector_status status;
1335
ea5b213a 1336 intel_dp->has_audio = false;
a4fc5ed6 1337
c619eed4 1338 if (HAS_PCH_SPLIT(dev))
f2b115e6 1339 return ironlake_dp_detect(connector);
5eb08b69 1340
ea5b213a 1341 switch (intel_dp->output_reg) {
a4fc5ed6
KP		 1342 case DP_B:
1343 bit = DPB_HOTPLUG_INT_STATUS;
1344 break;
1345 case DP_C:
1346 bit = DPC_HOTPLUG_INT_STATUS;
1347 break;
1348 case DP_D:
1349 bit = DPD_HOTPLUG_INT_STATUS;
1350 break;
1351 default:
1352 return connector_status_unknown;
1353 }
1354
1355 temp = I915_READ(PORT_HOTPLUG_STAT);
1356
1357 if ((temp & bit) == 0)
1358 return connector_status_disconnected;
1359
1360 status = connector_status_disconnected;
ea5b213a
CW		 1361 if (intel_dp_aux_native_read(intel_dp,
1362 0x000, intel_dp->dpcd,
1363 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
a4fc5ed6 1364 {
ea5b213a 1365 if (intel_dp->dpcd[0] != 0)
a4fc5ed6
KP		 1366 status = connector_status_connected;
1367 }
1368 return status;
1369}
1370
1371static int intel_dp_get_modes(struct drm_connector *connector)
1372{
55f78c43 1373 struct drm_encoder *encoder = intel_attached_encoder(connector);
ea5b213a
CW		 1374 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1375 struct drm_device *dev = intel_dp->base.enc.dev;
32f9d658
ZW		 1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 int ret;
a4fc5ed6
KP		 1378
1379 /* We should parse the EDID data and find out if it has an audio sink
1380 */
1381
ea5b213a 1382 ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus);
b9efc480 1383 if (ret) {
ea5b213a 1384 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
b9efc480
ZY		 1385 !dev_priv->panel_fixed_mode) {
1386 struct drm_display_mode *newmode;
1387 list_for_each_entry(newmode, &connector->probed_modes,
1388 head) {
1389 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1390 dev_priv->panel_fixed_mode =
1391 drm_mode_duplicate(dev, newmode);
1392 break;
1393 }
1394 }
1395 }
1396
32f9d658 1397 return ret;
b9efc480 1398 }
32f9d658
ZW		 1399
1400 /* if eDP has no EDID, try to use fixed panel mode from VBT */
ea5b213a 1401 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
32f9d658
ZW		 1402 if (dev_priv->panel_fixed_mode != NULL) {
1403 struct drm_display_mode *mode;
1404 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1405 drm_mode_probed_add(connector, mode);
1406 return 1;
1407 }
1408 }
1409 return 0;
a4fc5ed6
KP		 1410}
1411
1412static void
1413intel_dp_destroy (struct drm_connector *connector)
1414{
a4fc5ed6
KP		 1415 drm_sysfs_connector_remove(connector);
1416 drm_connector_cleanup(connector);
55f78c43 1417 kfree(connector);
a4fc5ed6
KP		 1418}
1419
1420static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1421 .dpms = intel_dp_dpms,
1422 .mode_fixup = intel_dp_mode_fixup,
1423 .prepare = intel_encoder_prepare,
1424 .mode_set = intel_dp_mode_set,
1425 .commit = intel_encoder_commit,
1426};
1427
1428static const struct drm_connector_funcs intel_dp_connector_funcs = {
1429 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 1430 .detect = intel_dp_detect,
1431 .fill_modes = drm_helper_probe_single_connector_modes,
1432 .destroy = intel_dp_destroy,
1433};
1434
1435static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1436 .get_modes = intel_dp_get_modes,
1437 .mode_valid = intel_dp_mode_valid,
55f78c43 1438 .best_encoder = intel_attached_encoder,
a4fc5ed6
KP		 1439};
1440
a4fc5ed6 1441static const struct drm_encoder_funcs intel_dp_enc_funcs = {
ea5b213a 1442 .destroy = intel_encoder_destroy,
a4fc5ed6
KP		 1443};
1444
c8110e52 1445void
21d40d37 1446intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 1447{
ea5b213a 1448 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 1449
ea5b213a
CW		 1450 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1451 intel_dp_check_link_status(intel_dp);
c8110e52 1452}
6207937d 1453
e3421a18
ZW		 1454/* Return which DP Port should be selected for Transcoder DP control */
1455int
1456intel_trans_dp_port_sel (struct drm_crtc *crtc)
1457{
1458 struct drm_device *dev = crtc->dev;
1459 struct drm_mode_config *mode_config = &dev->mode_config;
1460 struct drm_encoder *encoder;
e3421a18
ZW		 1461
1462 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a
CW		 1463 struct intel_dp *intel_dp;
1464
d8201ab6 1465 if (encoder->crtc != crtc)
e3421a18
ZW		 1466 continue;
1467
ea5b213a
CW		 1468 intel_dp = enc_to_intel_dp(encoder);
1469 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1470 return intel_dp->output_reg;
e3421a18 1471 }
ea5b213a 1472
e3421a18
ZW		 1473 return -1;
1474}
1475
36e83a18 1476/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 1477bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 1478{
1479 struct drm_i915_private *dev_priv = dev->dev_private;
1480 struct child_device_config *p_child;
1481 int i;
1482
1483 if (!dev_priv->child_dev_num)
1484 return false;
1485
1486 for (i = 0; i < dev_priv->child_dev_num; i++) {
1487 p_child = dev_priv->child_dev + i;
1488
1489 if (p_child->dvo_port == PORT_IDPD &&
1490 p_child->device_type == DEVICE_TYPE_eDP)
1491 return true;
1492 }
1493 return false;
1494}
1495
a4fc5ed6
KP		 1496void
1497intel_dp_init(struct drm_device *dev, int output_reg)
1498{
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 struct drm_connector *connector;
ea5b213a 1501 struct intel_dp *intel_dp;
21d40d37 1502 struct intel_encoder *intel_encoder;
55f78c43 1503 struct intel_connector *intel_connector;
5eb08b69 1504 const char *name = NULL;
b329530c 1505 int type;
a4fc5ed6 1506
ea5b213a
CW		 1507 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1508 if (!intel_dp)
a4fc5ed6
KP		 1509 return;
1510
55f78c43
ZW		 1511 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1512 if (!intel_connector) {
ea5b213a 1513 kfree(intel_dp);
55f78c43
ZW		 1514 return;
1515 }
ea5b213a 1516 intel_encoder = &intel_dp->base;
55f78c43 1517
ea5b213a 1518 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 1519 if (intel_dpd_is_edp(dev))
ea5b213a 1520 intel_dp->is_pch_edp = true;
b329530c 1521
ea5b213a 1522 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
b329530c
AJ		 1523 type = DRM_MODE_CONNECTOR_eDP;
1524 intel_encoder->type = INTEL_OUTPUT_EDP;
1525 } else {
1526 type = DRM_MODE_CONNECTOR_DisplayPort;
1527 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1528 }
1529
55f78c43 1530 connector = &intel_connector->base;
b329530c 1531 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 1532 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1533
eb1f8e4f
DA		 1534 connector->polled = DRM_CONNECTOR_POLL_HPD;
1535
652af9d7 1536 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 1537 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1538 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 1539 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1540 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 1541 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 1542
ea5b213a 1543 if (IS_eDP(intel_dp))
21d40d37 1544 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a 1545
21d40d37 1546 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1547 connector->interlace_allowed = true;
1548 connector->doublescan_allowed = 0;
1549
ea5b213a
CW		 1550 intel_dp->output_reg = output_reg;
1551 intel_dp->has_audio = false;
1552 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
a4fc5ed6 1553
21d40d37 1554 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
a4fc5ed6 1555 DRM_MODE_ENCODER_TMDS);
21d40d37 1556 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
a4fc5ed6 1557
55f78c43 1558 drm_mode_connector_attach_encoder(&intel_connector->base,
21d40d37 1559 &intel_encoder->enc);
a4fc5ed6
KP		 1560 drm_sysfs_connector_add(connector);
1561
1562 /* Set up the DDC bus. */
5eb08b69 1563 switch (output_reg) {
32f9d658
ZW		 1564 case DP_A:
1565 name = "DPDDC-A";
1566 break;
5eb08b69
ZW		 1567 case DP_B:
1568 case PCH_DP_B:
b01f2c3a
JB		 1569 dev_priv->hotplug_supported_mask |=
1570 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1571 name = "DPDDC-B";
1572 break;
1573 case DP_C:
1574 case PCH_DP_C:
b01f2c3a
JB		 1575 dev_priv->hotplug_supported_mask |=
1576 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1577 name = "DPDDC-C";
1578 break;
1579 case DP_D:
1580 case PCH_DP_D:
b01f2c3a
JB		 1581 dev_priv->hotplug_supported_mask |=
1582 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1583 name = "DPDDC-D";
1584 break;
1585 }
1586
ea5b213a 1587 intel_dp_i2c_init(intel_dp, intel_connector, name);
32f9d658 1588
ea5b213a 1589 intel_encoder->ddc_bus = &intel_dp->adapter;
21d40d37 1590 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1591
ea5b213a 1592 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
32f9d658
ZW		 1593 /* initialize panel mode from VBT if available for eDP */
1594 if (dev_priv->lfp_lvds_vbt_mode) {
1595 dev_priv->panel_fixed_mode =
1596 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1597 if (dev_priv->panel_fixed_mode) {
1598 dev_priv->panel_fixed_mode->type |=
1599 DRM_MODE_TYPE_PREFERRED;
1600 }
1601 }
1602 }
1603
a4fc5ed6
KP		 1604 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1605 * 0xd. Failure to do so will result in spurious interrupts being
1606 * generated on the port when a cable is not attached.
1607 */
1608 if (IS_G4X(dev) && !IS_GM45(dev)) {
1609 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1610 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1611 }
1612}
Clone of davem's net-next-2.6 tree