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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
1da177e4 LT |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "i915_drm.h" | |
33 | #include "i915_drv.h" | |
1c5d22f7 | 34 | #include "i915_trace.h" |
79e53945 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
1da177e4 | 37 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 38 | |
7c463586 KP |
39 | /** |
40 | * Interrupts that are always left unmasked. | |
41 | * | |
42 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
43 | * we leave them always unmasked in IMR and then control enabling them through | |
44 | * PIPESTAT alone. | |
45 | */ | |
6b95a207 KH |
46 | #define I915_INTERRUPT_ENABLE_FIX \ |
47 | (I915_ASLE_INTERRUPT | \ | |
48 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
53 | |
54 | /** Interrupts that we mask and unmask at runtime. */ | |
55 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) | |
56 | ||
79e53945 JB |
57 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
58 | PIPE_VBLANK_INTERRUPT_STATUS) | |
59 | ||
60 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
61 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
62 | ||
63 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
64 | DRM_I915_VBLANK_PIPE_B) | |
65 | ||
036a4a7d | 66 | void |
f2b115e6 | 67 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
68 | { |
69 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
70 | dev_priv->gt_irq_mask_reg &= ~mask; | |
71 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
72 | (void) I915_READ(GTIMR); | |
73 | } | |
74 | } | |
75 | ||
76 | static inline void | |
f2b115e6 | 77 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
78 | { |
79 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
80 | dev_priv->gt_irq_mask_reg |= mask; | |
81 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
82 | (void) I915_READ(GTIMR); | |
83 | } | |
84 | } | |
85 | ||
86 | /* For display hotplug interrupt */ | |
87 | void | |
f2b115e6 | 88 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
89 | { |
90 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
91 | dev_priv->irq_mask_reg &= ~mask; | |
92 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
93 | (void) I915_READ(DEIMR); | |
94 | } | |
95 | } | |
96 | ||
97 | static inline void | |
f2b115e6 | 98 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
99 | { |
100 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
101 | dev_priv->irq_mask_reg |= mask; | |
102 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
103 | (void) I915_READ(DEIMR); | |
104 | } | |
105 | } | |
106 | ||
8ee1c3db | 107 | void |
ed4cb414 EA |
108 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
109 | { | |
110 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
111 | dev_priv->irq_mask_reg &= ~mask; | |
112 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
113 | (void) I915_READ(IMR); | |
114 | } | |
115 | } | |
116 | ||
117 | static inline void | |
118 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) | |
119 | { | |
120 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
121 | dev_priv->irq_mask_reg |= mask; | |
122 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
123 | (void) I915_READ(IMR); | |
124 | } | |
125 | } | |
126 | ||
7c463586 KP |
127 | static inline u32 |
128 | i915_pipestat(int pipe) | |
129 | { | |
130 | if (pipe == 0) | |
131 | return PIPEASTAT; | |
132 | if (pipe == 1) | |
133 | return PIPEBSTAT; | |
9c84ba4e | 134 | BUG(); |
7c463586 KP |
135 | } |
136 | ||
137 | void | |
138 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
139 | { | |
140 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
141 | u32 reg = i915_pipestat(pipe); | |
142 | ||
143 | dev_priv->pipestat[pipe] |= mask; | |
144 | /* Enable the interrupt, clear any pending status */ | |
145 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
146 | (void) I915_READ(reg); | |
147 | } | |
148 | } | |
149 | ||
150 | void | |
151 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
152 | { | |
153 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
154 | u32 reg = i915_pipestat(pipe); | |
155 | ||
156 | dev_priv->pipestat[pipe] &= ~mask; | |
157 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
158 | (void) I915_READ(reg); | |
159 | } | |
160 | } | |
161 | ||
01c66889 ZY |
162 | /** |
163 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
164 | */ | |
165 | void intel_enable_asle (struct drm_device *dev) | |
166 | { | |
167 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
168 | ||
f2b115e6 AJ |
169 | if (IS_IRONLAKE(dev)) |
170 | ironlake_enable_display_irq(dev_priv, DE_GSE); | |
01c66889 ZY |
171 | else |
172 | i915_enable_pipestat(dev_priv, 1, | |
173 | I915_LEGACY_BLC_EVENT_ENABLE); | |
174 | } | |
175 | ||
0a3e67a4 JB |
176 | /** |
177 | * i915_pipe_enabled - check if a pipe is enabled | |
178 | * @dev: DRM device | |
179 | * @pipe: pipe to check | |
180 | * | |
181 | * Reading certain registers when the pipe is disabled can hang the chip. | |
182 | * Use this routine to make sure the PLL is running and the pipe is active | |
183 | * before reading such registers if unsure. | |
184 | */ | |
185 | static int | |
186 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
187 | { | |
188 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
189 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
190 | ||
191 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
192 | return 1; | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
42f52ef8 KP |
197 | /* Called from drm generic code, passed a 'crtc', which |
198 | * we use as a pipe index | |
199 | */ | |
200 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
201 | { |
202 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
203 | unsigned long high_frame; | |
204 | unsigned long low_frame; | |
205 | u32 high1, high2, low, count; | |
0a3e67a4 | 206 | |
0a3e67a4 JB |
207 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
208 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
209 | ||
210 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
211 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
212 | "pipe %d\n", pipe); | |
0a3e67a4 JB |
213 | return 0; |
214 | } | |
215 | ||
216 | /* | |
217 | * High & low register fields aren't synchronized, so make sure | |
218 | * we get a low value that's stable across two reads of the high | |
219 | * register. | |
220 | */ | |
221 | do { | |
222 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
223 | PIPE_FRAME_HIGH_SHIFT); | |
224 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
225 | PIPE_FRAME_LOW_SHIFT); | |
226 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
227 | PIPE_FRAME_HIGH_SHIFT); | |
228 | } while (high1 != high2); | |
229 | ||
230 | count = (high1 << 8) | low; | |
231 | ||
232 | return count; | |
233 | } | |
234 | ||
9880b7a5 JB |
235 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
236 | { | |
237 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
238 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
239 | ||
240 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
241 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
242 | "pipe %d\n", pipe); | |
9880b7a5 JB |
243 | return 0; |
244 | } | |
245 | ||
246 | return I915_READ(reg); | |
247 | } | |
248 | ||
5ca58282 JB |
249 | /* |
250 | * Handle hotplug events outside the interrupt handler proper. | |
251 | */ | |
252 | static void i915_hotplug_work_func(struct work_struct *work) | |
253 | { | |
254 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
255 | hotplug_work); | |
256 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 KP |
257 | struct drm_mode_config *mode_config = &dev->mode_config; |
258 | struct drm_connector *connector; | |
259 | ||
260 | if (mode_config->num_connector) { | |
261 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
262 | struct intel_output *intel_output = to_intel_output(connector); | |
263 | ||
264 | if (intel_output->hot_plug) | |
265 | (*intel_output->hot_plug) (intel_output); | |
266 | } | |
267 | } | |
5ca58282 JB |
268 | /* Just fire off a uevent and let userspace tell us what to do */ |
269 | drm_sysfs_hotplug_event(dev); | |
270 | } | |
271 | ||
f2b115e6 | 272 | irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
036a4a7d ZW |
273 | { |
274 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
275 | int ret = IRQ_NONE; | |
3ff99164 | 276 | u32 de_iir, gt_iir, de_ier, pch_iir; |
036a4a7d ZW |
277 | struct drm_i915_master_private *master_priv; |
278 | ||
2d109a84 ZN |
279 | /* disable master interrupt before clearing iir */ |
280 | de_ier = I915_READ(DEIER); | |
281 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
282 | (void)I915_READ(DEIER); | |
283 | ||
036a4a7d ZW |
284 | de_iir = I915_READ(DEIIR); |
285 | gt_iir = I915_READ(GTIIR); | |
c650156a | 286 | pch_iir = I915_READ(SDEIIR); |
036a4a7d | 287 | |
c7c85101 ZN |
288 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
289 | goto done; | |
036a4a7d | 290 | |
c7c85101 | 291 | ret = IRQ_HANDLED; |
036a4a7d | 292 | |
c7c85101 ZN |
293 | if (dev->primary->master) { |
294 | master_priv = dev->primary->master->driver_priv; | |
295 | if (master_priv->sarea_priv) | |
296 | master_priv->sarea_priv->last_dispatch = | |
297 | READ_BREADCRUMB(dev_priv); | |
298 | } | |
036a4a7d | 299 | |
c7c85101 ZN |
300 | if (gt_iir & GT_USER_INTERRUPT) { |
301 | u32 seqno = i915_get_gem_seqno(dev); | |
302 | dev_priv->mm.irq_gem_seqno = seqno; | |
303 | trace_i915_gem_request_complete(dev, seqno); | |
304 | DRM_WAKEUP(&dev_priv->irq_queue); | |
305 | dev_priv->hangcheck_count = 0; | |
306 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
307 | } | |
01c66889 | 308 | |
c7c85101 ZN |
309 | if (de_iir & DE_GSE) |
310 | ironlake_opregion_gse_intr(dev); | |
c650156a | 311 | |
c062df61 LP |
312 | if (de_iir & DE_PIPEA_VBLANK) |
313 | drm_handle_vblank(dev, 0); | |
314 | ||
315 | if (de_iir & DE_PIPEB_VBLANK) | |
316 | drm_handle_vblank(dev, 1); | |
317 | ||
c7c85101 ZN |
318 | /* check event from PCH */ |
319 | if ((de_iir & DE_PCH_EVENT) && | |
320 | (pch_iir & SDE_HOTPLUG_MASK)) { | |
321 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
036a4a7d ZW |
322 | } |
323 | ||
c7c85101 ZN |
324 | /* should clear PCH hotplug event before clear CPU irq */ |
325 | I915_WRITE(SDEIIR, pch_iir); | |
326 | I915_WRITE(GTIIR, gt_iir); | |
327 | I915_WRITE(DEIIR, de_iir); | |
328 | ||
329 | done: | |
2d109a84 ZN |
330 | I915_WRITE(DEIER, de_ier); |
331 | (void)I915_READ(DEIER); | |
332 | ||
036a4a7d ZW |
333 | return ret; |
334 | } | |
335 | ||
8a905236 JB |
336 | /** |
337 | * i915_error_work_func - do process context error handling work | |
338 | * @work: work struct | |
339 | * | |
340 | * Fire an error uevent so userspace can see that a hang or error | |
341 | * was detected. | |
342 | */ | |
343 | static void i915_error_work_func(struct work_struct *work) | |
344 | { | |
345 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
346 | error_work); | |
347 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
348 | char *error_event[] = { "ERROR=1", NULL }; |
349 | char *reset_event[] = { "RESET=1", NULL }; | |
350 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 351 | |
44d98a61 | 352 | DRM_DEBUG_DRIVER("generating error event\n"); |
f316a42c BG |
353 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
354 | ||
ba1234d1 | 355 | if (atomic_read(&dev_priv->mm.wedged)) { |
f316a42c | 356 | if (IS_I965G(dev)) { |
44d98a61 | 357 | DRM_DEBUG_DRIVER("resetting chip\n"); |
f316a42c BG |
358 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
359 | if (!i965_reset(dev, GDRST_RENDER)) { | |
ba1234d1 | 360 | atomic_set(&dev_priv->mm.wedged, 0); |
f316a42c BG |
361 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
362 | } | |
363 | } else { | |
44d98a61 | 364 | DRM_DEBUG_DRIVER("reboot required\n"); |
f316a42c BG |
365 | } |
366 | } | |
8a905236 JB |
367 | } |
368 | ||
369 | /** | |
370 | * i915_capture_error_state - capture an error record for later analysis | |
371 | * @dev: drm device | |
372 | * | |
373 | * Should be called when an error is detected (either a hang or an error | |
374 | * interrupt) to capture error state from the time of the error. Fills | |
375 | * out a structure which becomes available in debugfs for user level tools | |
376 | * to pick up. | |
377 | */ | |
63eeaf38 JB |
378 | static void i915_capture_error_state(struct drm_device *dev) |
379 | { | |
380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
381 | struct drm_i915_error_state *error; | |
382 | unsigned long flags; | |
383 | ||
384 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
385 | if (dev_priv->first_error) | |
386 | goto out; | |
387 | ||
388 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
389 | if (!error) { | |
44d98a61 | 390 | DRM_DEBUG_DRIVER("out ot memory, not capturing error state\n"); |
63eeaf38 JB |
391 | goto out; |
392 | } | |
393 | ||
394 | error->eir = I915_READ(EIR); | |
395 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
396 | error->pipeastat = I915_READ(PIPEASTAT); | |
397 | error->pipebstat = I915_READ(PIPEBSTAT); | |
398 | error->instpm = I915_READ(INSTPM); | |
399 | if (!IS_I965G(dev)) { | |
400 | error->ipeir = I915_READ(IPEIR); | |
401 | error->ipehr = I915_READ(IPEHR); | |
402 | error->instdone = I915_READ(INSTDONE); | |
403 | error->acthd = I915_READ(ACTHD); | |
404 | } else { | |
405 | error->ipeir = I915_READ(IPEIR_I965); | |
406 | error->ipehr = I915_READ(IPEHR_I965); | |
407 | error->instdone = I915_READ(INSTDONE_I965); | |
408 | error->instps = I915_READ(INSTPS); | |
409 | error->instdone1 = I915_READ(INSTDONE1); | |
410 | error->acthd = I915_READ(ACTHD_I965); | |
411 | } | |
412 | ||
8a905236 JB |
413 | do_gettimeofday(&error->time); |
414 | ||
63eeaf38 JB |
415 | dev_priv->first_error = error; |
416 | ||
417 | out: | |
418 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
419 | } | |
420 | ||
8a905236 JB |
421 | /** |
422 | * i915_handle_error - handle an error interrupt | |
423 | * @dev: drm device | |
424 | * | |
425 | * Do some basic checking of regsiter state at error interrupt time and | |
426 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
427 | * sure we get a record and make it available in debugfs. Fire a uevent | |
428 | * so userspace knows something bad happened (should trigger collection | |
429 | * of a ring dump etc.). | |
430 | */ | |
ba1234d1 | 431 | static void i915_handle_error(struct drm_device *dev, bool wedged) |
8a905236 JB |
432 | { |
433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
434 | u32 eir = I915_READ(EIR); | |
435 | u32 pipea_stats = I915_READ(PIPEASTAT); | |
436 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
437 | ||
438 | i915_capture_error_state(dev); | |
439 | ||
440 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
441 | eir); | |
442 | ||
443 | if (IS_G4X(dev)) { | |
444 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
445 | u32 ipeir = I915_READ(IPEIR_I965); | |
446 | ||
447 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
448 | I915_READ(IPEIR_I965)); | |
449 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
450 | I915_READ(IPEHR_I965)); | |
451 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
452 | I915_READ(INSTDONE_I965)); | |
453 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
454 | I915_READ(INSTPS)); | |
455 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
456 | I915_READ(INSTDONE1)); | |
457 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
458 | I915_READ(ACTHD_I965)); | |
459 | I915_WRITE(IPEIR_I965, ipeir); | |
460 | (void)I915_READ(IPEIR_I965); | |
461 | } | |
462 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
463 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
464 | printk(KERN_ERR "page table error\n"); | |
465 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
466 | pgtbl_err); | |
467 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
468 | (void)I915_READ(PGTBL_ER); | |
469 | } | |
470 | } | |
471 | ||
472 | if (IS_I9XX(dev)) { | |
473 | if (eir & I915_ERROR_PAGE_TABLE) { | |
474 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
475 | printk(KERN_ERR "page table error\n"); | |
476 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
477 | pgtbl_err); | |
478 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
479 | (void)I915_READ(PGTBL_ER); | |
480 | } | |
481 | } | |
482 | ||
483 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
484 | printk(KERN_ERR "memory refresh error\n"); | |
485 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
486 | pipea_stats); | |
487 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
488 | pipeb_stats); | |
489 | /* pipestat has already been acked */ | |
490 | } | |
491 | if (eir & I915_ERROR_INSTRUCTION) { | |
492 | printk(KERN_ERR "instruction error\n"); | |
493 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
494 | I915_READ(INSTPM)); | |
495 | if (!IS_I965G(dev)) { | |
496 | u32 ipeir = I915_READ(IPEIR); | |
497 | ||
498 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
499 | I915_READ(IPEIR)); | |
500 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
501 | I915_READ(IPEHR)); | |
502 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
503 | I915_READ(INSTDONE)); | |
504 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
505 | I915_READ(ACTHD)); | |
506 | I915_WRITE(IPEIR, ipeir); | |
507 | (void)I915_READ(IPEIR); | |
508 | } else { | |
509 | u32 ipeir = I915_READ(IPEIR_I965); | |
510 | ||
511 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
512 | I915_READ(IPEIR_I965)); | |
513 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
514 | I915_READ(IPEHR_I965)); | |
515 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
516 | I915_READ(INSTDONE_I965)); | |
517 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
518 | I915_READ(INSTPS)); | |
519 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
520 | I915_READ(INSTDONE1)); | |
521 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
522 | I915_READ(ACTHD_I965)); | |
523 | I915_WRITE(IPEIR_I965, ipeir); | |
524 | (void)I915_READ(IPEIR_I965); | |
525 | } | |
526 | } | |
527 | ||
528 | I915_WRITE(EIR, eir); | |
529 | (void)I915_READ(EIR); | |
530 | eir = I915_READ(EIR); | |
531 | if (eir) { | |
532 | /* | |
533 | * some errors might have become stuck, | |
534 | * mask them. | |
535 | */ | |
536 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
537 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
538 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
539 | } | |
540 | ||
ba1234d1 BG |
541 | if (wedged) { |
542 | atomic_set(&dev_priv->mm.wedged, 1); | |
543 | ||
11ed50ec BG |
544 | /* |
545 | * Wakeup waiting processes so they don't hang | |
546 | */ | |
11ed50ec BG |
547 | DRM_WAKEUP(&dev_priv->irq_queue); |
548 | } | |
549 | ||
9c9fe1f8 | 550 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
551 | } |
552 | ||
1da177e4 LT |
553 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
554 | { | |
84b1fd10 | 555 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 556 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 557 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
558 | u32 iir, new_iir; |
559 | u32 pipea_stats, pipeb_stats; | |
05eff845 KP |
560 | u32 vblank_status; |
561 | u32 vblank_enable; | |
0a3e67a4 | 562 | int vblank = 0; |
7c463586 | 563 | unsigned long irqflags; |
05eff845 KP |
564 | int irq_received; |
565 | int ret = IRQ_NONE; | |
6e5fca53 | 566 | |
630681d9 EA |
567 | atomic_inc(&dev_priv->irq_received); |
568 | ||
f2b115e6 AJ |
569 | if (IS_IRONLAKE(dev)) |
570 | return ironlake_irq_handler(dev); | |
036a4a7d | 571 | |
ed4cb414 | 572 | iir = I915_READ(IIR); |
a6b54f3f | 573 | |
05eff845 KP |
574 | if (IS_I965G(dev)) { |
575 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; | |
576 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; | |
577 | } else { | |
578 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; | |
579 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; | |
580 | } | |
af6061af | 581 | |
05eff845 KP |
582 | for (;;) { |
583 | irq_received = iir != 0; | |
584 | ||
585 | /* Can't rely on pipestat interrupt bit in iir as it might | |
586 | * have been cleared after the pipestat interrupt was received. | |
587 | * It doesn't set the bit in iir again, but it still produces | |
588 | * interrupts (for non-MSI). | |
589 | */ | |
590 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
591 | pipea_stats = I915_READ(PIPEASTAT); | |
592 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 593 | |
8a905236 | 594 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 595 | i915_handle_error(dev, false); |
8a905236 | 596 | |
cdfbc41f EA |
597 | /* |
598 | * Clear the PIPE(A|B)STAT regs before the IIR | |
599 | */ | |
05eff845 | 600 | if (pipea_stats & 0x8000ffff) { |
7662c8bd | 601 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 602 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
cdfbc41f | 603 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 604 | irq_received = 1; |
cdfbc41f | 605 | } |
1da177e4 | 606 | |
05eff845 | 607 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd | 608 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 609 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
cdfbc41f | 610 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 611 | irq_received = 1; |
cdfbc41f | 612 | } |
05eff845 KP |
613 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
614 | ||
615 | if (!irq_received) | |
616 | break; | |
617 | ||
618 | ret = IRQ_HANDLED; | |
8ee1c3db | 619 | |
5ca58282 JB |
620 | /* Consume port. Then clear IIR or we'll miss events */ |
621 | if ((I915_HAS_HOTPLUG(dev)) && | |
622 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
623 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
624 | ||
44d98a61 | 625 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
626 | hotplug_status); |
627 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
628 | queue_work(dev_priv->wq, |
629 | &dev_priv->hotplug_work); | |
5ca58282 JB |
630 | |
631 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
632 | I915_READ(PORT_HOTPLUG_STAT); | |
633 | } | |
634 | ||
cdfbc41f EA |
635 | I915_WRITE(IIR, iir); |
636 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 637 | |
7c1c2871 DA |
638 | if (dev->primary->master) { |
639 | master_priv = dev->primary->master->driver_priv; | |
640 | if (master_priv->sarea_priv) | |
641 | master_priv->sarea_priv->last_dispatch = | |
642 | READ_BREADCRUMB(dev_priv); | |
643 | } | |
0a3e67a4 | 644 | |
cdfbc41f | 645 | if (iir & I915_USER_INTERRUPT) { |
1c5d22f7 CW |
646 | u32 seqno = i915_get_gem_seqno(dev); |
647 | dev_priv->mm.irq_gem_seqno = seqno; | |
648 | trace_i915_gem_request_complete(dev, seqno); | |
cdfbc41f | 649 | DRM_WAKEUP(&dev_priv->irq_queue); |
f65d9421 BG |
650 | dev_priv->hangcheck_count = 0; |
651 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
cdfbc41f | 652 | } |
673a394b | 653 | |
6b95a207 KH |
654 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) |
655 | intel_prepare_page_flip(dev, 0); | |
656 | ||
657 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) | |
658 | intel_prepare_page_flip(dev, 1); | |
659 | ||
05eff845 | 660 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
661 | vblank++; |
662 | drm_handle_vblank(dev, 0); | |
6b95a207 | 663 | intel_finish_page_flip(dev, 0); |
cdfbc41f | 664 | } |
7c463586 | 665 | |
05eff845 | 666 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
667 | vblank++; |
668 | drm_handle_vblank(dev, 1); | |
6b95a207 | 669 | intel_finish_page_flip(dev, 1); |
cdfbc41f | 670 | } |
7c463586 | 671 | |
cdfbc41f EA |
672 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
673 | (iir & I915_ASLE_INTERRUPT)) | |
674 | opregion_asle_intr(dev); | |
675 | ||
676 | /* With MSI, interrupts are only generated when iir | |
677 | * transitions from zero to nonzero. If another bit got | |
678 | * set while we were handling the existing iir bits, then | |
679 | * we would never get another interrupt. | |
680 | * | |
681 | * This is fine on non-MSI as well, as if we hit this path | |
682 | * we avoid exiting the interrupt handler only to generate | |
683 | * another one. | |
684 | * | |
685 | * Note that for MSI this could cause a stray interrupt report | |
686 | * if an interrupt landed in the time between writing IIR and | |
687 | * the posting read. This should be rare enough to never | |
688 | * trigger the 99% of 100,000 interrupts test for disabling | |
689 | * stray interrupts. | |
690 | */ | |
691 | iir = new_iir; | |
05eff845 | 692 | } |
0a3e67a4 | 693 | |
05eff845 | 694 | return ret; |
1da177e4 LT |
695 | } |
696 | ||
af6061af | 697 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
698 | { |
699 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 700 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
701 | RING_LOCALS; |
702 | ||
703 | i915_kernel_lost_context(dev); | |
704 | ||
44d98a61 | 705 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 706 | |
c99b058f | 707 | dev_priv->counter++; |
c29b669c | 708 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 709 | dev_priv->counter = 1; |
7c1c2871 DA |
710 | if (master_priv->sarea_priv) |
711 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 712 | |
0baf823a | 713 | BEGIN_LP_RING(4); |
585fb111 | 714 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 715 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 716 | OUT_RING(dev_priv->counter); |
585fb111 | 717 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 718 | ADVANCE_LP_RING(); |
bc5f4523 | 719 | |
c29b669c | 720 | return dev_priv->counter; |
1da177e4 LT |
721 | } |
722 | ||
673a394b | 723 | void i915_user_irq_get(struct drm_device *dev) |
ed4cb414 EA |
724 | { |
725 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 726 | unsigned long irqflags; |
ed4cb414 | 727 | |
e9d21d7f | 728 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
036a4a7d | 729 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
f2b115e6 AJ |
730 | if (IS_IRONLAKE(dev)) |
731 | ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
036a4a7d ZW |
732 | else |
733 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
734 | } | |
e9d21d7f | 735 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
736 | } |
737 | ||
0a3e67a4 | 738 | void i915_user_irq_put(struct drm_device *dev) |
ed4cb414 EA |
739 | { |
740 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 741 | unsigned long irqflags; |
ed4cb414 | 742 | |
e9d21d7f | 743 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 | 744 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
036a4a7d | 745 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
f2b115e6 AJ |
746 | if (IS_IRONLAKE(dev)) |
747 | ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); | |
036a4a7d ZW |
748 | else |
749 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
750 | } | |
e9d21d7f | 751 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
ed4cb414 EA |
752 | } |
753 | ||
9d34e5db CW |
754 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
755 | { | |
756 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
757 | ||
758 | if (dev_priv->trace_irq_seqno == 0) | |
759 | i915_user_irq_get(dev); | |
760 | ||
761 | dev_priv->trace_irq_seqno = seqno; | |
762 | } | |
763 | ||
84b1fd10 | 764 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
765 | { |
766 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 767 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
768 | int ret = 0; |
769 | ||
44d98a61 | 770 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
771 | READ_BREADCRUMB(dev_priv)); |
772 | ||
ed4cb414 | 773 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
774 | if (master_priv->sarea_priv) |
775 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 776 | return 0; |
ed4cb414 | 777 | } |
1da177e4 | 778 | |
7c1c2871 DA |
779 | if (master_priv->sarea_priv) |
780 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 781 | |
ed4cb414 | 782 | i915_user_irq_get(dev); |
1da177e4 LT |
783 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
784 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
ed4cb414 | 785 | i915_user_irq_put(dev); |
1da177e4 | 786 | |
20caafa6 | 787 | if (ret == -EBUSY) { |
3e684eae | 788 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
789 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
790 | } | |
791 | ||
af6061af DA |
792 | return ret; |
793 | } | |
794 | ||
1da177e4 LT |
795 | /* Needs the lock as it touches the ring. |
796 | */ | |
c153f45f EA |
797 | int i915_irq_emit(struct drm_device *dev, void *data, |
798 | struct drm_file *file_priv) | |
1da177e4 | 799 | { |
1da177e4 | 800 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 801 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
802 | int result; |
803 | ||
07f4f8bf | 804 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
3e684eae | 805 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 806 | return -EINVAL; |
1da177e4 | 807 | } |
299eb93c EA |
808 | |
809 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
810 | ||
546b0974 | 811 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 812 | result = i915_emit_irq(dev); |
546b0974 | 813 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 814 | |
c153f45f | 815 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 816 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 817 | return -EFAULT; |
1da177e4 LT |
818 | } |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
823 | /* Doesn't need the hardware lock. | |
824 | */ | |
c153f45f EA |
825 | int i915_irq_wait(struct drm_device *dev, void *data, |
826 | struct drm_file *file_priv) | |
1da177e4 | 827 | { |
1da177e4 | 828 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 829 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
830 | |
831 | if (!dev_priv) { | |
3e684eae | 832 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 833 | return -EINVAL; |
1da177e4 LT |
834 | } |
835 | ||
c153f45f | 836 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
837 | } |
838 | ||
42f52ef8 KP |
839 | /* Called from drm generic code, passed 'crtc' which |
840 | * we use as a pipe index | |
841 | */ | |
842 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
843 | { |
844 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 845 | unsigned long irqflags; |
71e0ffa5 JB |
846 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
847 | u32 pipeconf; | |
848 | ||
849 | pipeconf = I915_READ(pipeconf_reg); | |
850 | if (!(pipeconf & PIPEACONF_ENABLE)) | |
851 | return -EINVAL; | |
0a3e67a4 | 852 | |
e9d21d7f | 853 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
c062df61 LP |
854 | if (IS_IRONLAKE(dev)) |
855 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
856 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
857 | else if (IS_I965G(dev)) | |
7c463586 KP |
858 | i915_enable_pipestat(dev_priv, pipe, |
859 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 860 | else |
7c463586 KP |
861 | i915_enable_pipestat(dev_priv, pipe, |
862 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 863 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
864 | return 0; |
865 | } | |
866 | ||
42f52ef8 KP |
867 | /* Called from drm generic code, passed 'crtc' which |
868 | * we use as a pipe index | |
869 | */ | |
870 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
871 | { |
872 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 873 | unsigned long irqflags; |
0a3e67a4 | 874 | |
e9d21d7f | 875 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
c062df61 LP |
876 | if (IS_IRONLAKE(dev)) |
877 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
878 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
879 | else | |
880 | i915_disable_pipestat(dev_priv, pipe, | |
881 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
882 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 883 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
884 | } |
885 | ||
79e53945 JB |
886 | void i915_enable_interrupt (struct drm_device *dev) |
887 | { | |
888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 | 889 | |
f2b115e6 | 890 | if (!IS_IRONLAKE(dev)) |
e170b030 | 891 | opregion_enable_asle(dev); |
79e53945 JB |
892 | dev_priv->irq_enabled = 1; |
893 | } | |
894 | ||
895 | ||
702880f2 DA |
896 | /* Set the vblank monitor pipe |
897 | */ | |
c153f45f EA |
898 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
899 | struct drm_file *file_priv) | |
702880f2 | 900 | { |
702880f2 | 901 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
902 | |
903 | if (!dev_priv) { | |
3e684eae | 904 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 905 | return -EINVAL; |
702880f2 DA |
906 | } |
907 | ||
5b51694a | 908 | return 0; |
702880f2 DA |
909 | } |
910 | ||
c153f45f EA |
911 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
912 | struct drm_file *file_priv) | |
702880f2 | 913 | { |
702880f2 | 914 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 915 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
916 | |
917 | if (!dev_priv) { | |
3e684eae | 918 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 919 | return -EINVAL; |
702880f2 DA |
920 | } |
921 | ||
0a3e67a4 | 922 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 923 | |
702880f2 DA |
924 | return 0; |
925 | } | |
926 | ||
a6b54f3f MD |
927 | /** |
928 | * Schedule buffer swap at given vertical blank. | |
929 | */ | |
c153f45f EA |
930 | int i915_vblank_swap(struct drm_device *dev, void *data, |
931 | struct drm_file *file_priv) | |
a6b54f3f | 932 | { |
bd95e0a4 EA |
933 | /* The delayed swap mechanism was fundamentally racy, and has been |
934 | * removed. The model was that the client requested a delayed flip/swap | |
935 | * from the kernel, then waited for vblank before continuing to perform | |
936 | * rendering. The problem was that the kernel might wake the client | |
937 | * up before it dispatched the vblank swap (since the lock has to be | |
938 | * held while touching the ringbuffer), in which case the client would | |
939 | * clear and start the next frame before the swap occurred, and | |
940 | * flicker would occur in addition to likely missing the vblank. | |
941 | * | |
942 | * In the absence of this ioctl, userland falls back to a correct path | |
943 | * of waiting for a vblank, then dispatching the swap on its own. | |
944 | * Context switching to userland and back is plenty fast enough for | |
945 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 946 | */ |
bd95e0a4 | 947 | return -EINVAL; |
a6b54f3f MD |
948 | } |
949 | ||
f65d9421 BG |
950 | struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) { |
951 | drm_i915_private_t *dev_priv = dev->dev_private; | |
952 | return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list); | |
953 | } | |
954 | ||
955 | /** | |
956 | * This is called when the chip hasn't reported back with completed | |
957 | * batchbuffers in a long time. The first time this is called we simply record | |
958 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
959 | * again, we assume the chip is wedged and try to fix it. | |
960 | */ | |
961 | void i915_hangcheck_elapsed(unsigned long data) | |
962 | { | |
963 | struct drm_device *dev = (struct drm_device *)data; | |
964 | drm_i915_private_t *dev_priv = dev->dev_private; | |
965 | uint32_t acthd; | |
966 | ||
967 | if (!IS_I965G(dev)) | |
968 | acthd = I915_READ(ACTHD); | |
969 | else | |
970 | acthd = I915_READ(ACTHD_I965); | |
971 | ||
972 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
973 | if (list_empty(&dev_priv->mm.request_list) || | |
974 | i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) { | |
975 | dev_priv->hangcheck_count = 0; | |
976 | return; | |
977 | } | |
978 | ||
979 | if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) { | |
980 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
ba1234d1 | 981 | i915_handle_error(dev, true); |
f65d9421 BG |
982 | return; |
983 | } | |
984 | ||
985 | /* Reset timer case chip hangs without another request being added */ | |
986 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
987 | ||
988 | if (acthd != dev_priv->last_acthd) | |
989 | dev_priv->hangcheck_count = 0; | |
990 | else | |
991 | dev_priv->hangcheck_count++; | |
992 | ||
993 | dev_priv->last_acthd = acthd; | |
994 | } | |
995 | ||
1da177e4 LT |
996 | /* drm_dma.h hooks |
997 | */ | |
f2b115e6 | 998 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
999 | { |
1000 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1001 | ||
1002 | I915_WRITE(HWSTAM, 0xeffe); | |
1003 | ||
1004 | /* XXX hotplug from PCH */ | |
1005 | ||
1006 | I915_WRITE(DEIMR, 0xffffffff); | |
1007 | I915_WRITE(DEIER, 0x0); | |
1008 | (void) I915_READ(DEIER); | |
1009 | ||
1010 | /* and GT */ | |
1011 | I915_WRITE(GTIMR, 0xffffffff); | |
1012 | I915_WRITE(GTIER, 0x0); | |
1013 | (void) I915_READ(GTIER); | |
c650156a ZW |
1014 | |
1015 | /* south display irq */ | |
1016 | I915_WRITE(SDEIMR, 0xffffffff); | |
1017 | I915_WRITE(SDEIER, 0x0); | |
1018 | (void) I915_READ(SDEIER); | |
036a4a7d ZW |
1019 | } |
1020 | ||
f2b115e6 | 1021 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1022 | { |
1023 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1024 | /* enable kind of interrupts always enabled */ | |
c062df61 LP |
1025 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1026 | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; | |
036a4a7d | 1027 | u32 render_mask = GT_USER_INTERRUPT; |
c650156a ZW |
1028 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
1029 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
036a4a7d ZW |
1030 | |
1031 | dev_priv->irq_mask_reg = ~display_mask; | |
1032 | dev_priv->de_irq_enable_reg = display_mask; | |
1033 | ||
1034 | /* should always can generate irq */ | |
1035 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1036 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
1037 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
1038 | (void) I915_READ(DEIER); | |
1039 | ||
1040 | /* user interrupt should be enabled, but masked initial */ | |
1041 | dev_priv->gt_irq_mask_reg = 0xffffffff; | |
1042 | dev_priv->gt_irq_enable_reg = render_mask; | |
1043 | ||
1044 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1045 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
1046 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); | |
1047 | (void) I915_READ(GTIER); | |
1048 | ||
c650156a ZW |
1049 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
1050 | dev_priv->pch_irq_enable_reg = hotplug_mask; | |
1051 | ||
1052 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1053 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); | |
1054 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); | |
1055 | (void) I915_READ(SDEIER); | |
1056 | ||
036a4a7d ZW |
1057 | return 0; |
1058 | } | |
1059 | ||
84b1fd10 | 1060 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1061 | { |
1062 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1063 | ||
79e53945 JB |
1064 | atomic_set(&dev_priv->irq_received, 0); |
1065 | ||
036a4a7d | 1066 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1067 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 1068 | |
f2b115e6 AJ |
1069 | if (IS_IRONLAKE(dev)) { |
1070 | ironlake_irq_preinstall(dev); | |
036a4a7d ZW |
1071 | return; |
1072 | } | |
1073 | ||
5ca58282 JB |
1074 | if (I915_HAS_HOTPLUG(dev)) { |
1075 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1076 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1077 | } | |
1078 | ||
0a3e67a4 | 1079 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1080 | I915_WRITE(PIPEASTAT, 0); |
1081 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1082 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1083 | I915_WRITE(IER, 0x0); |
7c463586 | 1084 | (void) I915_READ(IER); |
1da177e4 LT |
1085 | } |
1086 | ||
b01f2c3a JB |
1087 | /* |
1088 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1089 | * enabled correctly. | |
1090 | */ | |
0a3e67a4 | 1091 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1092 | { |
1093 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1094 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1095 | u32 error_mask; |
0a3e67a4 | 1096 | |
036a4a7d ZW |
1097 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
1098 | ||
0a3e67a4 | 1099 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1100 | |
f2b115e6 AJ |
1101 | if (IS_IRONLAKE(dev)) |
1102 | return ironlake_irq_postinstall(dev); | |
036a4a7d | 1103 | |
7c463586 KP |
1104 | /* Unmask the interrupts that we always want on. */ |
1105 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
1106 | ||
1107 | dev_priv->pipestat[0] = 0; | |
1108 | dev_priv->pipestat[1] = 0; | |
1109 | ||
5ca58282 JB |
1110 | if (I915_HAS_HOTPLUG(dev)) { |
1111 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1112 | ||
b01f2c3a JB |
1113 | /* Note HDMI and DP share bits */ |
1114 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1115 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1116 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1117 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1118 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1119 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1120 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1121 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1122 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1123 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
1124 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) | |
1125 | hotplug_en |= CRT_HOTPLUG_INT_EN; | |
1126 | /* Ignore TV since it's buggy */ | |
1127 | ||
5ca58282 JB |
1128 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
1129 | ||
5ca58282 JB |
1130 | /* Enable in IER... */ |
1131 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1132 | /* and unmask in IMR */ | |
1133 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); | |
1134 | } | |
1135 | ||
63eeaf38 JB |
1136 | /* |
1137 | * Enable some error detection, note the instruction error mask | |
1138 | * bit is reserved, so we leave it masked. | |
1139 | */ | |
1140 | if (IS_G4X(dev)) { | |
1141 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1142 | GM45_ERROR_MEM_PRIV | | |
1143 | GM45_ERROR_CP_PRIV | | |
1144 | I915_ERROR_MEMORY_REFRESH); | |
1145 | } else { | |
1146 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1147 | I915_ERROR_MEMORY_REFRESH); | |
1148 | } | |
1149 | I915_WRITE(EMR, error_mask); | |
1150 | ||
7c463586 KP |
1151 | /* Disable pipe interrupt enables, clear pending pipe status */ |
1152 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); | |
1153 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1154 | /* Clear pending interrupt status */ | |
1155 | I915_WRITE(IIR, I915_READ(IIR)); | |
8ee1c3db | 1156 | |
5ca58282 | 1157 | I915_WRITE(IER, enable_mask); |
7c463586 | 1158 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
ed4cb414 EA |
1159 | (void) I915_READ(IER); |
1160 | ||
8ee1c3db | 1161 | opregion_enable_asle(dev); |
0a3e67a4 JB |
1162 | |
1163 | return 0; | |
1da177e4 LT |
1164 | } |
1165 | ||
f2b115e6 | 1166 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
1167 | { |
1168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1169 | I915_WRITE(HWSTAM, 0xffffffff); | |
1170 | ||
1171 | I915_WRITE(DEIMR, 0xffffffff); | |
1172 | I915_WRITE(DEIER, 0x0); | |
1173 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1174 | ||
1175 | I915_WRITE(GTIMR, 0xffffffff); | |
1176 | I915_WRITE(GTIER, 0x0); | |
1177 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1178 | } | |
1179 | ||
84b1fd10 | 1180 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1181 | { |
1182 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1183 | |
1da177e4 LT |
1184 | if (!dev_priv) |
1185 | return; | |
1186 | ||
0a3e67a4 JB |
1187 | dev_priv->vblank_pipe = 0; |
1188 | ||
f2b115e6 AJ |
1189 | if (IS_IRONLAKE(dev)) { |
1190 | ironlake_irq_uninstall(dev); | |
036a4a7d ZW |
1191 | return; |
1192 | } | |
1193 | ||
5ca58282 JB |
1194 | if (I915_HAS_HOTPLUG(dev)) { |
1195 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1196 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1197 | } | |
1198 | ||
0a3e67a4 | 1199 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1200 | I915_WRITE(PIPEASTAT, 0); |
1201 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1202 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1203 | I915_WRITE(IER, 0x0); |
af6061af | 1204 | |
7c463586 KP |
1205 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1206 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1207 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1208 | } |