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drm/i915: Implement GPU reset on i965
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
63eeaf38 29#include <linux/sysrq.h>
1da177e4
LT		 30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
79e53945 34#include "intel_drv.h"
1da177e4 35
1da177e4 36#define MAX_NOPID ((u32)~0)
1da177e4 37
7c463586
KP		 38/**
39 * Interrupts that are always left unmasked.
40 *
41 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
42 * we leave them always unmasked in IMR and then control enabling them through
43 * PIPESTAT alone.
44 */
63eeaf38
JB		 45#define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
46 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
47 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
48 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
7c463586
KP		 49
50/** Interrupts that we mask and unmask at runtime. */
51#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
52
79e53945
JB		 53#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
54 PIPE_VBLANK_INTERRUPT_STATUS)
55
56#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
57 PIPE_VBLANK_INTERRUPT_ENABLE)
58
59#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
60 DRM_I915_VBLANK_PIPE_B)
61
036a4a7d
ZW		 62void
63igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
64{
65 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
66 dev_priv->gt_irq_mask_reg &= ~mask;
67 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
68 (void) I915_READ(GTIMR);
69 }
70}
71
72static inline void
73igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
74{
75 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
76 dev_priv->gt_irq_mask_reg |= mask;
77 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
78 (void) I915_READ(GTIMR);
79 }
80}
81
82/* For display hotplug interrupt */
83void
84igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
85{
86 if ((dev_priv->irq_mask_reg & mask) != 0) {
87 dev_priv->irq_mask_reg &= ~mask;
88 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
89 (void) I915_READ(DEIMR);
90 }
91}
92
93static inline void
94igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
95{
96 if ((dev_priv->irq_mask_reg & mask) != mask) {
97 dev_priv->irq_mask_reg |= mask;
98 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
99 (void) I915_READ(DEIMR);
100 }
101}
102
8ee1c3db 103void
ed4cb414
EA		 104i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
105{
106 if ((dev_priv->irq_mask_reg & mask) != 0) {
107 dev_priv->irq_mask_reg &= ~mask;
108 I915_WRITE(IMR, dev_priv->irq_mask_reg);
109 (void) I915_READ(IMR);
110 }
111}
112
113static inline void
114i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
115{
116 if ((dev_priv->irq_mask_reg & mask) != mask) {
117 dev_priv->irq_mask_reg |= mask;
118 I915_WRITE(IMR, dev_priv->irq_mask_reg);
119 (void) I915_READ(IMR);
120 }
121}
122
7c463586
KP		 123static inline u32
124i915_pipestat(int pipe)
125{
126 if (pipe == 0)
127 return PIPEASTAT;
128 if (pipe == 1)
129 return PIPEBSTAT;
9c84ba4e 130 BUG();
7c463586
KP		 131}
132
133void
134i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
135{
136 if ((dev_priv->pipestat[pipe] & mask) != mask) {
137 u32 reg = i915_pipestat(pipe);
138
139 dev_priv->pipestat[pipe] |= mask;
140 /* Enable the interrupt, clear any pending status */
141 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
142 (void) I915_READ(reg);
143 }
144}
145
146void
147i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
148{
149 if ((dev_priv->pipestat[pipe] & mask) != 0) {
150 u32 reg = i915_pipestat(pipe);
151
152 dev_priv->pipestat[pipe] &= ~mask;
153 I915_WRITE(reg, dev_priv->pipestat[pipe]);
154 (void) I915_READ(reg);
155 }
156}
157
0a3e67a4
JB		 158/**
159 * i915_pipe_enabled - check if a pipe is enabled
160 * @dev: DRM device
161 * @pipe: pipe to check
162 *
163 * Reading certain registers when the pipe is disabled can hang the chip.
164 * Use this routine to make sure the PLL is running and the pipe is active
165 * before reading such registers if unsure.
166 */
167static int
168i915_pipe_enabled(struct drm_device *dev, int pipe)
169{
170 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
171 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
172
173 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
174 return 1;
175
176 return 0;
177}
178
42f52ef8
KP		 179/* Called from drm generic code, passed a 'crtc', which
180 * we use as a pipe index
181 */
182u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 183{
184 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
185 unsigned long high_frame;
186 unsigned long low_frame;
187 u32 high1, high2, low, count;
0a3e67a4 188
0a3e67a4
JB		 189 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
190 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
191
192 if (!i915_pipe_enabled(dev, pipe)) {
6cb504c2 193 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
0a3e67a4
JB		 194 return 0;
195 }
196
197 /*
198 * High & low register fields aren't synchronized, so make sure
199 * we get a low value that's stable across two reads of the high
200 * register.
201 */
202 do {
203 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
204 PIPE_FRAME_HIGH_SHIFT);
205 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
206 PIPE_FRAME_LOW_SHIFT);
207 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
208 PIPE_FRAME_HIGH_SHIFT);
209 } while (high1 != high2);
210
211 count = (high1 << 8) | low;
212
213 return count;
214}
215
9880b7a5
JB		 216u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
217{
218 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
219 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
220
221 if (!i915_pipe_enabled(dev, pipe)) {
6cb504c2 222 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
9880b7a5
JB		 223 return 0;
224 }
225
226 return I915_READ(reg);
227}
228
5ca58282
JB		 229/*
230 * Handle hotplug events outside the interrupt handler proper.
231 */
232static void i915_hotplug_work_func(struct work_struct *work)
233{
234 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
235 hotplug_work);
236 struct drm_device *dev = dev_priv->dev;
c31c4ba3
KP		 237 struct drm_mode_config *mode_config = &dev->mode_config;
238 struct drm_connector *connector;
239
240 if (mode_config->num_connector) {
241 list_for_each_entry(connector, &mode_config->connector_list, head) {
242 struct intel_output *intel_output = to_intel_output(connector);
243
244 if (intel_output->hot_plug)
245 (*intel_output->hot_plug) (intel_output);
246 }
247 }
5ca58282
JB		 248 /* Just fire off a uevent and let userspace tell us what to do */
249 drm_sysfs_hotplug_event(dev);
250}
251
036a4a7d
ZW		 252irqreturn_t igdng_irq_handler(struct drm_device *dev)
253{
254 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
255 int ret = IRQ_NONE;
256 u32 de_iir, gt_iir;
257 u32 new_de_iir, new_gt_iir;
258 struct drm_i915_master_private *master_priv;
259
260 de_iir = I915_READ(DEIIR);
261 gt_iir = I915_READ(GTIIR);
262
263 for (;;) {
264 if (de_iir == 0 && gt_iir == 0)
265 break;
266
267 ret = IRQ_HANDLED;
268
269 I915_WRITE(DEIIR, de_iir);
270 new_de_iir = I915_READ(DEIIR);
271 I915_WRITE(GTIIR, gt_iir);
272 new_gt_iir = I915_READ(GTIIR);
273
274 if (dev->primary->master) {
275 master_priv = dev->primary->master->driver_priv;
276 if (master_priv->sarea_priv)
277 master_priv->sarea_priv->last_dispatch =
278 READ_BREADCRUMB(dev_priv);
279 }
280
281 if (gt_iir & GT_USER_INTERRUPT) {
282 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
283 DRM_WAKEUP(&dev_priv->irq_queue);
284 }
285
286 de_iir = new_de_iir;
287 gt_iir = new_gt_iir;
288 }
289
290 return ret;
291}
292
8a905236
JB		 293/**
294 * i915_error_work_func - do process context error handling work
295 * @work: work struct
296 *
297 * Fire an error uevent so userspace can see that a hang or error
298 * was detected.
299 */
300static void i915_error_work_func(struct work_struct *work)
301{
302 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
303 error_work);
304 struct drm_device *dev = dev_priv->dev;
305 char *event_string = "ERROR=1";
306 char *envp[] = { event_string, NULL };
307
308 DRM_DEBUG("generating error event\n");
309
310 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, envp);
311}
312
313/**
314 * i915_capture_error_state - capture an error record for later analysis
315 * @dev: drm device
316 *
317 * Should be called when an error is detected (either a hang or an error
318 * interrupt) to capture error state from the time of the error. Fills
319 * out a structure which becomes available in debugfs for user level tools
320 * to pick up.
321 */
63eeaf38
JB		 322static void i915_capture_error_state(struct drm_device *dev)
323{
324 struct drm_i915_private *dev_priv = dev->dev_private;
325 struct drm_i915_error_state *error;
326 unsigned long flags;
327
328 spin_lock_irqsave(&dev_priv->error_lock, flags);
329 if (dev_priv->first_error)
330 goto out;
331
332 error = kmalloc(sizeof(*error), GFP_ATOMIC);
333 if (!error) {
334 DRM_DEBUG("out ot memory, not capturing error state\n");
335 goto out;
336 }
337
338 error->eir = I915_READ(EIR);
339 error->pgtbl_er = I915_READ(PGTBL_ER);
340 error->pipeastat = I915_READ(PIPEASTAT);
341 error->pipebstat = I915_READ(PIPEBSTAT);
342 error->instpm = I915_READ(INSTPM);
343 if (!IS_I965G(dev)) {
344 error->ipeir = I915_READ(IPEIR);
345 error->ipehr = I915_READ(IPEHR);
346 error->instdone = I915_READ(INSTDONE);
347 error->acthd = I915_READ(ACTHD);
348 } else {
349 error->ipeir = I915_READ(IPEIR_I965);
350 error->ipehr = I915_READ(IPEHR_I965);
351 error->instdone = I915_READ(INSTDONE_I965);
352 error->instps = I915_READ(INSTPS);
353 error->instdone1 = I915_READ(INSTDONE1);
354 error->acthd = I915_READ(ACTHD_I965);
355 }
356
8a905236
JB		 357 do_gettimeofday(&error->time);
358
63eeaf38
JB		 359 dev_priv->first_error = error;
360
361out:
362 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
363}
364
8a905236
JB		 365/**
366 * i915_handle_error - handle an error interrupt
367 * @dev: drm device
368 *
369 * Do some basic checking of regsiter state at error interrupt time and
370 * dump it to the syslog. Also call i915_capture_error_state() to make
371 * sure we get a record and make it available in debugfs. Fire a uevent
372 * so userspace knows something bad happened (should trigger collection
373 * of a ring dump etc.).
374 */
375static void i915_handle_error(struct drm_device *dev)
376{
377 struct drm_i915_private *dev_priv = dev->dev_private;
378 u32 eir = I915_READ(EIR);
379 u32 pipea_stats = I915_READ(PIPEASTAT);
380 u32 pipeb_stats = I915_READ(PIPEBSTAT);
381
382 i915_capture_error_state(dev);
383
384 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
385 eir);
386
387 if (IS_G4X(dev)) {
388 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
389 u32 ipeir = I915_READ(IPEIR_I965);
390
391 printk(KERN_ERR " IPEIR: 0x%08x\n",
392 I915_READ(IPEIR_I965));
393 printk(KERN_ERR " IPEHR: 0x%08x\n",
394 I915_READ(IPEHR_I965));
395 printk(KERN_ERR " INSTDONE: 0x%08x\n",
396 I915_READ(INSTDONE_I965));
397 printk(KERN_ERR " INSTPS: 0x%08x\n",
398 I915_READ(INSTPS));
399 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
400 I915_READ(INSTDONE1));
401 printk(KERN_ERR " ACTHD: 0x%08x\n",
402 I915_READ(ACTHD_I965));
403 I915_WRITE(IPEIR_I965, ipeir);
404 (void)I915_READ(IPEIR_I965);
405 }
406 if (eir & GM45_ERROR_PAGE_TABLE) {
407 u32 pgtbl_err = I915_READ(PGTBL_ER);
408 printk(KERN_ERR "page table error\n");
409 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
410 pgtbl_err);
411 I915_WRITE(PGTBL_ER, pgtbl_err);
412 (void)I915_READ(PGTBL_ER);
413 }
414 }
415
416 if (IS_I9XX(dev)) {
417 if (eir & I915_ERROR_PAGE_TABLE) {
418 u32 pgtbl_err = I915_READ(PGTBL_ER);
419 printk(KERN_ERR "page table error\n");
420 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
421 pgtbl_err);
422 I915_WRITE(PGTBL_ER, pgtbl_err);
423 (void)I915_READ(PGTBL_ER);
424 }
425 }
426
427 if (eir & I915_ERROR_MEMORY_REFRESH) {
428 printk(KERN_ERR "memory refresh error\n");
429 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
430 pipea_stats);
431 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
432 pipeb_stats);
433 /* pipestat has already been acked */
434 }
435 if (eir & I915_ERROR_INSTRUCTION) {
436 printk(KERN_ERR "instruction error\n");
437 printk(KERN_ERR " INSTPM: 0x%08x\n",
438 I915_READ(INSTPM));
439 if (!IS_I965G(dev)) {
440 u32 ipeir = I915_READ(IPEIR);
441
442 printk(KERN_ERR " IPEIR: 0x%08x\n",
443 I915_READ(IPEIR));
444 printk(KERN_ERR " IPEHR: 0x%08x\n",
445 I915_READ(IPEHR));
446 printk(KERN_ERR " INSTDONE: 0x%08x\n",
447 I915_READ(INSTDONE));
448 printk(KERN_ERR " ACTHD: 0x%08x\n",
449 I915_READ(ACTHD));
450 I915_WRITE(IPEIR, ipeir);
451 (void)I915_READ(IPEIR);
452 } else {
453 u32 ipeir = I915_READ(IPEIR_I965);
454
455 printk(KERN_ERR " IPEIR: 0x%08x\n",
456 I915_READ(IPEIR_I965));
457 printk(KERN_ERR " IPEHR: 0x%08x\n",
458 I915_READ(IPEHR_I965));
459 printk(KERN_ERR " INSTDONE: 0x%08x\n",
460 I915_READ(INSTDONE_I965));
461 printk(KERN_ERR " INSTPS: 0x%08x\n",
462 I915_READ(INSTPS));
463 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
464 I915_READ(INSTDONE1));
465 printk(KERN_ERR " ACTHD: 0x%08x\n",
466 I915_READ(ACTHD_I965));
467 I915_WRITE(IPEIR_I965, ipeir);
468 (void)I915_READ(IPEIR_I965);
469 }
470 }
471
472 I915_WRITE(EIR, eir);
473 (void)I915_READ(EIR);
474 eir = I915_READ(EIR);
475 if (eir) {
476 /*
477 * some errors might have become stuck,
478 * mask them.
479 */
480 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
481 I915_WRITE(EMR, I915_READ(EMR) | eir);
482 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
483 }
484
11ed50ec
BG		 485 if (dev_priv->mm.wedged) {
486 /*
487 * Wakeup waiting processes so they don't hang
488 */
489 printk("i915: Waking up sleeping processes\n");
490 DRM_WAKEUP(&dev_priv->irq_queue);
491 }
492
9c9fe1f8 493 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 494}
495
1da177e4
LT		 496irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
497{
84b1fd10 498 struct drm_device *dev = (struct drm_device *) arg;
1da177e4 499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 500 struct drm_i915_master_private *master_priv;
cdfbc41f
EA		 501 u32 iir, new_iir;
502 u32 pipea_stats, pipeb_stats;
05eff845
KP		 503 u32 vblank_status;
504 u32 vblank_enable;
0a3e67a4 505 int vblank = 0;
7c463586 506 unsigned long irqflags;
05eff845
KP		 507 int irq_received;
508 int ret = IRQ_NONE;
6e5fca53 509
630681d9
EA		 510 atomic_inc(&dev_priv->irq_received);
511
036a4a7d
ZW		 512 if (IS_IGDNG(dev))
513 return igdng_irq_handler(dev);
514
ed4cb414 515 iir = I915_READ(IIR);
a6b54f3f 516
05eff845
KP		 517 if (IS_I965G(dev)) {
518 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
519 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
520 } else {
521 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
522 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
523 }
af6061af 524
05eff845
KP		 525 for (;;) {
526 irq_received = iir != 0;
527
528 /* Can't rely on pipestat interrupt bit in iir as it might
529 * have been cleared after the pipestat interrupt was received.
530 * It doesn't set the bit in iir again, but it still produces
531 * interrupts (for non-MSI).
532 */
533 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
534 pipea_stats = I915_READ(PIPEASTAT);
535 pipeb_stats = I915_READ(PIPEBSTAT);
79e53945 536
8a905236
JB		 537 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
538 i915_handle_error(dev);
539
cdfbc41f
EA		 540 /*
541 * Clear the PIPE(A|B)STAT regs before the IIR
542 */
05eff845 543 if (pipea_stats & 0x8000ffff) {
7662c8bd
SL		 544 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
545 DRM_DEBUG("pipe a underrun\n");
cdfbc41f 546 I915_WRITE(PIPEASTAT, pipea_stats);
05eff845 547 irq_received = 1;
cdfbc41f 548 }
1da177e4 549
05eff845 550 if (pipeb_stats & 0x8000ffff) {
7662c8bd
SL		 551 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
552 DRM_DEBUG("pipe b underrun\n");
cdfbc41f 553 I915_WRITE(PIPEBSTAT, pipeb_stats);
05eff845 554 irq_received = 1;
cdfbc41f 555 }
05eff845
KP		 556 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
557
558 if (!irq_received)
559 break;
560
561 ret = IRQ_HANDLED;
8ee1c3db 562
5ca58282
JB		 563 /* Consume port. Then clear IIR or we'll miss events */
564 if ((I915_HAS_HOTPLUG(dev)) &&
565 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
566 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
567
568 DRM_DEBUG("hotplug event received, stat 0x%08x\n",
569 hotplug_status);
570 if (hotplug_status & dev_priv->hotplug_supported_mask)
9c9fe1f8
EA		 571 queue_work(dev_priv->wq,
572 &dev_priv->hotplug_work);
5ca58282
JB		 573
574 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
575 I915_READ(PORT_HOTPLUG_STAT);
04302965
SL		 576
577 /* EOS interrupts occurs */
578 if (IS_IGD(dev) &&
579 (hotplug_status & CRT_EOS_INT_STATUS)) {
580 u32 temp;
581
582 DRM_DEBUG("EOS interrupt occurs\n");
583 /* status is already cleared */
584 temp = I915_READ(ADPA);
585 temp &= ~ADPA_DAC_ENABLE;
586 I915_WRITE(ADPA, temp);
587
588 temp = I915_READ(PORT_HOTPLUG_EN);
589 temp &= ~CRT_EOS_INT_EN;
590 I915_WRITE(PORT_HOTPLUG_EN, temp);
591
592 temp = I915_READ(PORT_HOTPLUG_STAT);
593 if (temp & CRT_EOS_INT_STATUS)
594 I915_WRITE(PORT_HOTPLUG_STAT,
595 CRT_EOS_INT_STATUS);
596 }
5ca58282
JB		 597 }
598
cdfbc41f
EA		 599 I915_WRITE(IIR, iir);
600 new_iir = I915_READ(IIR); /* Flush posted writes */
7c463586 601
7c1c2871
DA		 602 if (dev->primary->master) {
603 master_priv = dev->primary->master->driver_priv;
604 if (master_priv->sarea_priv)
605 master_priv->sarea_priv->last_dispatch =
606 READ_BREADCRUMB(dev_priv);
607 }
0a3e67a4 608
cdfbc41f
EA		 609 if (iir & I915_USER_INTERRUPT) {
610 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
611 DRM_WAKEUP(&dev_priv->irq_queue);
f65d9421
BG		 612 dev_priv->hangcheck_count = 0;
613 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
cdfbc41f 614 }
673a394b 615
05eff845 616 if (pipea_stats & vblank_status) {
cdfbc41f
EA		 617 vblank++;
618 drm_handle_vblank(dev, 0);
619 }
7c463586 620
05eff845 621 if (pipeb_stats & vblank_status) {
cdfbc41f
EA		 622 vblank++;
623 drm_handle_vblank(dev, 1);
624 }
7c463586 625
cdfbc41f
EA		 626 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
627 (iir & I915_ASLE_INTERRUPT))
628 opregion_asle_intr(dev);
629
630 /* With MSI, interrupts are only generated when iir
631 * transitions from zero to nonzero. If another bit got
632 * set while we were handling the existing iir bits, then
633 * we would never get another interrupt.
634 *
635 * This is fine on non-MSI as well, as if we hit this path
636 * we avoid exiting the interrupt handler only to generate
637 * another one.
638 *
639 * Note that for MSI this could cause a stray interrupt report
640 * if an interrupt landed in the time between writing IIR and
641 * the posting read. This should be rare enough to never
642 * trigger the 99% of 100,000 interrupts test for disabling
643 * stray interrupts.
644 */
645 iir = new_iir;
05eff845 646 }
0a3e67a4 647
05eff845 648 return ret;
1da177e4
LT		 649}
650
af6061af 651static int i915_emit_irq(struct drm_device * dev)
1da177e4
LT		 652{
653 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 654 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4
LT		 655 RING_LOCALS;
656
657 i915_kernel_lost_context(dev);
658
3e684eae 659 DRM_DEBUG("\n");
1da177e4 660
c99b058f 661 dev_priv->counter++;
c29b669c 662 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 663 dev_priv->counter = 1;
7c1c2871
DA		 664 if (master_priv->sarea_priv)
665 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
c29b669c 666
0baf823a 667 BEGIN_LP_RING(4);
585fb111 668 OUT_RING(MI_STORE_DWORD_INDEX);
0baf823a 669 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
c29b669c 670 OUT_RING(dev_priv->counter);
585fb111 671 OUT_RING(MI_USER_INTERRUPT);
1da177e4 672 ADVANCE_LP_RING();
bc5f4523 673
c29b669c 674 return dev_priv->counter;
1da177e4
LT		 675}
676
673a394b 677void i915_user_irq_get(struct drm_device *dev)
ed4cb414
EA		 678{
679 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 680 unsigned long irqflags;
ed4cb414 681
e9d21d7f 682 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
036a4a7d
ZW		 683 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
684 if (IS_IGDNG(dev))
685 igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
686 else
687 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
688 }
e9d21d7f 689 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
ed4cb414
EA		 690}
691
0a3e67a4 692void i915_user_irq_put(struct drm_device *dev)
ed4cb414
EA		 693{
694 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 695 unsigned long irqflags;
ed4cb414 696
e9d21d7f 697 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
ed4cb414 698 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
036a4a7d
ZW		 699 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
700 if (IS_IGDNG(dev))
701 igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
702 else
703 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
704 }
e9d21d7f 705 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
ed4cb414
EA		 706}
707
84b1fd10 708static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1da177e4
LT		 709{
710 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 711 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4
LT		 712 int ret = 0;
713
3e684eae 714 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
1da177e4
LT		 715 READ_BREADCRUMB(dev_priv));
716
ed4cb414 717 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
7c1c2871
DA		 718 if (master_priv->sarea_priv)
719 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1da177e4 720 return 0;
ed4cb414 721 }
1da177e4 722
7c1c2871
DA		 723 if (master_priv->sarea_priv)
724 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1da177e4 725
ed4cb414 726 i915_user_irq_get(dev);
1da177e4
LT		 727 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
728 READ_BREADCRUMB(dev_priv) >= irq_nr);
ed4cb414 729 i915_user_irq_put(dev);
1da177e4 730
20caafa6 731 if (ret == -EBUSY) {
3e684eae 732 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1da177e4
LT		 733 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
734 }
735
af6061af
DA		 736 return ret;
737}
738
1da177e4
LT		 739/* Needs the lock as it touches the ring.
740 */
c153f45f
EA		 741int i915_irq_emit(struct drm_device *dev, void *data,
742 struct drm_file *file_priv)
1da177e4 743{
1da177e4 744 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 745 drm_i915_irq_emit_t *emit = data;
1da177e4
LT		 746 int result;
747
07f4f8bf 748 if (!dev_priv || !dev_priv->ring.virtual_start) {
3e684eae 749 DRM_ERROR("called with no initialization\n");
20caafa6 750 return -EINVAL;
1da177e4 751 }
299eb93c
EA		 752
753 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
754
546b0974 755 mutex_lock(&dev->struct_mutex);
1da177e4 756 result = i915_emit_irq(dev);
546b0974 757 mutex_unlock(&dev->struct_mutex);
1da177e4 758
c153f45f 759 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1da177e4 760 DRM_ERROR("copy_to_user\n");
20caafa6 761 return -EFAULT;
1da177e4
LT		 762 }
763
764 return 0;
765}
766
767/* Doesn't need the hardware lock.
768 */
c153f45f
EA		 769int i915_irq_wait(struct drm_device *dev, void *data,
770 struct drm_file *file_priv)
1da177e4 771{
1da177e4 772 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 773 drm_i915_irq_wait_t *irqwait = data;
1da177e4
LT		 774
775 if (!dev_priv) {
3e684eae 776 DRM_ERROR("called with no initialization\n");
20caafa6 777 return -EINVAL;
1da177e4
LT		 778 }
779
c153f45f 780 return i915_wait_irq(dev, irqwait->irq_seq);
1da177e4
LT		 781}
782
42f52ef8
KP		 783/* Called from drm generic code, passed 'crtc' which
784 * we use as a pipe index
785 */
786int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 787{
788 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 789 unsigned long irqflags;
71e0ffa5
JB		 790 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
791 u32 pipeconf;
792
793 pipeconf = I915_READ(pipeconf_reg);
794 if (!(pipeconf & PIPEACONF_ENABLE))
795 return -EINVAL;
0a3e67a4 796
036a4a7d
ZW		 797 if (IS_IGDNG(dev))
798 return 0;
799
e9d21d7f 800 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
e9d21d7f 801 if (IS_I965G(dev))
7c463586
KP		 802 i915_enable_pipestat(dev_priv, pipe,
803 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 804 else
7c463586
KP		 805 i915_enable_pipestat(dev_priv, pipe,
806 PIPE_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 807 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
0a3e67a4
JB		 808 return 0;
809}
810
42f52ef8
KP		 811/* Called from drm generic code, passed 'crtc' which
812 * we use as a pipe index
813 */
814void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 815{
816 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 817 unsigned long irqflags;
0a3e67a4 818
036a4a7d
ZW		 819 if (IS_IGDNG(dev))
820 return;
821
e9d21d7f 822 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
7c463586
KP		 823 i915_disable_pipestat(dev_priv, pipe,
824 PIPE_VBLANK_INTERRUPT_ENABLE |
825 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 826 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
0a3e67a4
JB		 827}
828
79e53945
JB		 829void i915_enable_interrupt (struct drm_device *dev)
830{
831 struct drm_i915_private *dev_priv = dev->dev_private;
e170b030
ZW		 832
833 if (!IS_IGDNG(dev))
834 opregion_enable_asle(dev);
79e53945
JB		 835 dev_priv->irq_enabled = 1;
836}
837
838
702880f2
DA		 839/* Set the vblank monitor pipe
840 */
c153f45f
EA		 841int i915_vblank_pipe_set(struct drm_device *dev, void *data,
842 struct drm_file *file_priv)
702880f2 843{
702880f2 844 drm_i915_private_t *dev_priv = dev->dev_private;
702880f2
DA		 845
846 if (!dev_priv) {
3e684eae 847 DRM_ERROR("called with no initialization\n");
20caafa6 848 return -EINVAL;
702880f2
DA		 849 }
850
5b51694a 851 return 0;
702880f2
DA		 852}
853
c153f45f
EA		 854int i915_vblank_pipe_get(struct drm_device *dev, void *data,
855 struct drm_file *file_priv)
702880f2 856{
702880f2 857 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 858 drm_i915_vblank_pipe_t *pipe = data;
702880f2
DA		 859
860 if (!dev_priv) {
3e684eae 861 DRM_ERROR("called with no initialization\n");
20caafa6 862 return -EINVAL;
702880f2
DA		 863 }
864
0a3e67a4 865 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
c153f45f 866
702880f2
DA		 867 return 0;
868}
869
a6b54f3f
MD		 870/**
871 * Schedule buffer swap at given vertical blank.
872 */
c153f45f
EA		 873int i915_vblank_swap(struct drm_device *dev, void *data,
874 struct drm_file *file_priv)
a6b54f3f 875{
bd95e0a4
EA		 876 /* The delayed swap mechanism was fundamentally racy, and has been
877 * removed. The model was that the client requested a delayed flip/swap
878 * from the kernel, then waited for vblank before continuing to perform
879 * rendering. The problem was that the kernel might wake the client
880 * up before it dispatched the vblank swap (since the lock has to be
881 * held while touching the ringbuffer), in which case the client would
882 * clear and start the next frame before the swap occurred, and
883 * flicker would occur in addition to likely missing the vblank.
884 *
885 * In the absence of this ioctl, userland falls back to a correct path
886 * of waiting for a vblank, then dispatching the swap on its own.
887 * Context switching to userland and back is plenty fast enough for
888 * meeting the requirements of vblank swapping.
0a3e67a4 889 */
bd95e0a4 890 return -EINVAL;
a6b54f3f
MD		 891}
892
f65d9421
BG		 893struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
894 drm_i915_private_t *dev_priv = dev->dev_private;
895 return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
896}
897
898/**
899 * This is called when the chip hasn't reported back with completed
900 * batchbuffers in a long time. The first time this is called we simply record
901 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
902 * again, we assume the chip is wedged and try to fix it.
903 */
904void i915_hangcheck_elapsed(unsigned long data)
905{
906 struct drm_device *dev = (struct drm_device *)data;
907 drm_i915_private_t *dev_priv = dev->dev_private;
908 uint32_t acthd;
909
910 if (!IS_I965G(dev))
911 acthd = I915_READ(ACTHD);
912 else
913 acthd = I915_READ(ACTHD_I965);
914
915 /* If all work is done then ACTHD clearly hasn't advanced. */
916 if (list_empty(&dev_priv->mm.request_list) ||
917 i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
918 dev_priv->hangcheck_count = 0;
919 return;
920 }
921
922 if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
923 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
924 dev_priv->mm.wedged = true; /* Hopefully this is atomic */
925 i915_handle_error(dev);
926 return;
927 }
928
929 /* Reset timer case chip hangs without another request being added */
930 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
931
932 if (acthd != dev_priv->last_acthd)
933 dev_priv->hangcheck_count = 0;
934 else
935 dev_priv->hangcheck_count++;
936
937 dev_priv->last_acthd = acthd;
938}
939
1da177e4
LT		 940/* drm_dma.h hooks
941*/
036a4a7d
ZW		 942static void igdng_irq_preinstall(struct drm_device *dev)
943{
944 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
945
946 I915_WRITE(HWSTAM, 0xeffe);
947
948 /* XXX hotplug from PCH */
949
950 I915_WRITE(DEIMR, 0xffffffff);
951 I915_WRITE(DEIER, 0x0);
952 (void) I915_READ(DEIER);
953
954 /* and GT */
955 I915_WRITE(GTIMR, 0xffffffff);
956 I915_WRITE(GTIER, 0x0);
957 (void) I915_READ(GTIER);
958}
959
960static int igdng_irq_postinstall(struct drm_device *dev)
961{
962 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
963 /* enable kind of interrupts always enabled */
964 u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
965 u32 render_mask = GT_USER_INTERRUPT;
966
967 dev_priv->irq_mask_reg = ~display_mask;
968 dev_priv->de_irq_enable_reg = display_mask;
969
970 /* should always can generate irq */
971 I915_WRITE(DEIIR, I915_READ(DEIIR));
972 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
973 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
974 (void) I915_READ(DEIER);
975
976 /* user interrupt should be enabled, but masked initial */
977 dev_priv->gt_irq_mask_reg = 0xffffffff;
978 dev_priv->gt_irq_enable_reg = render_mask;
979
980 I915_WRITE(GTIIR, I915_READ(GTIIR));
981 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
982 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
983 (void) I915_READ(GTIER);
984
985 return 0;
986}
987
84b1fd10 988void i915_driver_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 989{
990 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
991
79e53945
JB		 992 atomic_set(&dev_priv->irq_received, 0);
993
036a4a7d 994 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
8a905236 995 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
036a4a7d
ZW		 996
997 if (IS_IGDNG(dev)) {
998 igdng_irq_preinstall(dev);
999 return;
1000 }
1001
5ca58282
JB		 1002 if (I915_HAS_HOTPLUG(dev)) {
1003 I915_WRITE(PORT_HOTPLUG_EN, 0);
1004 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1005 }
1006
0a3e67a4 1007 I915_WRITE(HWSTAM, 0xeffe);
7c463586
KP		 1008 I915_WRITE(PIPEASTAT, 0);
1009 I915_WRITE(PIPEBSTAT, 0);
0a3e67a4 1010 I915_WRITE(IMR, 0xffffffff);
ed4cb414 1011 I915_WRITE(IER, 0x0);
7c463586 1012 (void) I915_READ(IER);
1da177e4
LT		 1013}
1014
0a3e67a4 1015int i915_driver_irq_postinstall(struct drm_device *dev)
1da177e4
LT		 1016{
1017 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5ca58282 1018 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
63eeaf38 1019 u32 error_mask;
0a3e67a4 1020
036a4a7d
ZW		 1021 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1022
0a3e67a4 1023 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
0a3e67a4 1024
036a4a7d
ZW		 1025 if (IS_IGDNG(dev))
1026 return igdng_irq_postinstall(dev);
1027
7c463586
KP		 1028 /* Unmask the interrupts that we always want on. */
1029 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1030
1031 dev_priv->pipestat[0] = 0;
1032 dev_priv->pipestat[1] = 0;
1033
5ca58282
JB		 1034 if (I915_HAS_HOTPLUG(dev)) {
1035 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1036
1037 /* Leave other bits alone */
1038 hotplug_en |= HOTPLUG_EN_MASK;
1039 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1040
1041 dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
1042 TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
1043 SDVOB_HOTPLUG_INT_STATUS;
1044 if (IS_G4X(dev)) {
1045 dev_priv->hotplug_supported_mask |=
1046 HDMIB_HOTPLUG_INT_STATUS |
1047 HDMIC_HOTPLUG_INT_STATUS |
1048 HDMID_HOTPLUG_INT_STATUS;
1049 }
1050 /* Enable in IER... */
1051 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1052 /* and unmask in IMR */
1053 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1054 }
1055
63eeaf38
JB		 1056 /*
1057 * Enable some error detection, note the instruction error mask
1058 * bit is reserved, so we leave it masked.
1059 */
1060 if (IS_G4X(dev)) {
1061 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1062 GM45_ERROR_MEM_PRIV |
1063 GM45_ERROR_CP_PRIV |
1064 I915_ERROR_MEMORY_REFRESH);
1065 } else {
1066 error_mask = ~(I915_ERROR_PAGE_TABLE |
1067 I915_ERROR_MEMORY_REFRESH);
1068 }
1069 I915_WRITE(EMR, error_mask);
1070
7c463586
KP		 1071 /* Disable pipe interrupt enables, clear pending pipe status */
1072 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1073 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1074 /* Clear pending interrupt status */
1075 I915_WRITE(IIR, I915_READ(IIR));
8ee1c3db 1076
5ca58282 1077 I915_WRITE(IER, enable_mask);
7c463586 1078 I915_WRITE(IMR, dev_priv->irq_mask_reg);
ed4cb414
EA		 1079 (void) I915_READ(IER);
1080
8ee1c3db 1081 opregion_enable_asle(dev);
0a3e67a4
JB		 1082
1083 return 0;
1da177e4
LT		 1084}
1085
036a4a7d
ZW		 1086static void igdng_irq_uninstall(struct drm_device *dev)
1087{
1088 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1089 I915_WRITE(HWSTAM, 0xffffffff);
1090
1091 I915_WRITE(DEIMR, 0xffffffff);
1092 I915_WRITE(DEIER, 0x0);
1093 I915_WRITE(DEIIR, I915_READ(DEIIR));
1094
1095 I915_WRITE(GTIMR, 0xffffffff);
1096 I915_WRITE(GTIER, 0x0);
1097 I915_WRITE(GTIIR, I915_READ(GTIIR));
1098}
1099
84b1fd10 1100void i915_driver_irq_uninstall(struct drm_device * dev)
1da177e4
LT		 1101{
1102 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
91e3738e 1103
1da177e4
LT		 1104 if (!dev_priv)
1105 return;
1106
0a3e67a4
JB		 1107 dev_priv->vblank_pipe = 0;
1108
036a4a7d
ZW		 1109 if (IS_IGDNG(dev)) {
1110 igdng_irq_uninstall(dev);
1111 return;
1112 }
1113
5ca58282
JB		 1114 if (I915_HAS_HOTPLUG(dev)) {
1115 I915_WRITE(PORT_HOTPLUG_EN, 0);
1116 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1117 }
1118
0a3e67a4 1119 I915_WRITE(HWSTAM, 0xffffffff);
7c463586
KP		 1120 I915_WRITE(PIPEASTAT, 0);
1121 I915_WRITE(PIPEBSTAT, 0);
0a3e67a4 1122 I915_WRITE(IMR, 0xffffffff);
ed4cb414 1123 I915_WRITE(IER, 0x0);
af6061af 1124
7c463586
KP		 1125 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1126 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1127 I915_WRITE(IIR, I915_READ(IIR));
1da177e4 1128}
Clone of davem's net-next-2.6 tree