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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 JB |
53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
54 | unsigned alignment); | |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
31169714 CW |
61 | static LIST_HEAD(shrink_list); |
62 | static DEFINE_SPINLOCK(shrink_list_lock); | |
63 | ||
7d1c4804 CW |
64 | static inline bool |
65 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
66 | { | |
67 | return obj_priv->gtt_space && | |
68 | !obj_priv->active && | |
69 | obj_priv->pin_count == 0; | |
70 | } | |
71 | ||
79e53945 JB |
72 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
73 | unsigned long end) | |
673a394b EA |
74 | { |
75 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 76 | |
79e53945 JB |
77 | if (start >= end || |
78 | (start & (PAGE_SIZE - 1)) != 0 || | |
79 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
80 | return -EINVAL; |
81 | } | |
82 | ||
79e53945 JB |
83 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
84 | end - start); | |
673a394b | 85 | |
79e53945 JB |
86 | dev->gtt_total = (uint32_t) (end - start); |
87 | ||
88 | return 0; | |
89 | } | |
673a394b | 90 | |
79e53945 JB |
91 | int |
92 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
93 | struct drm_file *file_priv) | |
94 | { | |
95 | struct drm_i915_gem_init *args = data; | |
96 | int ret; | |
97 | ||
98 | mutex_lock(&dev->struct_mutex); | |
99 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
100 | mutex_unlock(&dev->struct_mutex); |
101 | ||
79e53945 | 102 | return ret; |
673a394b EA |
103 | } |
104 | ||
5a125c3c EA |
105 | int |
106 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
107 | struct drm_file *file_priv) | |
108 | { | |
5a125c3c | 109 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
110 | |
111 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
112 | return -ENODEV; | |
113 | ||
114 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
115 | args->aper_available_size = (args->aper_size - |
116 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
117 | |
118 | return 0; | |
119 | } | |
120 | ||
673a394b EA |
121 | |
122 | /** | |
123 | * Creates a new mm object and returns a handle to it. | |
124 | */ | |
125 | int | |
126 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
127 | struct drm_file *file_priv) | |
128 | { | |
129 | struct drm_i915_gem_create *args = data; | |
130 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
131 | int ret; |
132 | u32 handle; | |
673a394b EA |
133 | |
134 | args->size = roundup(args->size, PAGE_SIZE); | |
135 | ||
136 | /* Allocate the new object */ | |
ac52bc56 | 137 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
138 | if (obj == NULL) |
139 | return -ENOMEM; | |
140 | ||
141 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 CW |
142 | if (ret) { |
143 | drm_gem_object_unreference_unlocked(obj); | |
673a394b | 144 | return ret; |
1dfd9754 | 145 | } |
673a394b | 146 | |
1dfd9754 CW |
147 | /* Sink the floating reference from kref_init(handlecount) */ |
148 | drm_gem_object_handle_unreference_unlocked(obj); | |
673a394b | 149 | |
1dfd9754 | 150 | args->handle = handle; |
673a394b EA |
151 | return 0; |
152 | } | |
153 | ||
eb01459f EA |
154 | static inline int |
155 | fast_shmem_read(struct page **pages, | |
156 | loff_t page_base, int page_offset, | |
157 | char __user *data, | |
158 | int length) | |
159 | { | |
160 | char __iomem *vaddr; | |
2bc43b5c | 161 | int unwritten; |
eb01459f EA |
162 | |
163 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
164 | if (vaddr == NULL) | |
165 | return -ENOMEM; | |
2bc43b5c | 166 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
167 | kunmap_atomic(vaddr, KM_USER0); |
168 | ||
2bc43b5c FM |
169 | if (unwritten) |
170 | return -EFAULT; | |
171 | ||
172 | return 0; | |
eb01459f EA |
173 | } |
174 | ||
280b713b EA |
175 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
176 | { | |
177 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 178 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
179 | |
180 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
181 | obj_priv->tiling_mode != I915_TILING_NONE; | |
182 | } | |
183 | ||
99a03df5 | 184 | static inline void |
40123c1f EA |
185 | slow_shmem_copy(struct page *dst_page, |
186 | int dst_offset, | |
187 | struct page *src_page, | |
188 | int src_offset, | |
189 | int length) | |
190 | { | |
191 | char *dst_vaddr, *src_vaddr; | |
192 | ||
99a03df5 CW |
193 | dst_vaddr = kmap(dst_page); |
194 | src_vaddr = kmap(src_page); | |
40123c1f EA |
195 | |
196 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
197 | ||
99a03df5 CW |
198 | kunmap(src_page); |
199 | kunmap(dst_page); | |
40123c1f EA |
200 | } |
201 | ||
99a03df5 | 202 | static inline void |
280b713b EA |
203 | slow_shmem_bit17_copy(struct page *gpu_page, |
204 | int gpu_offset, | |
205 | struct page *cpu_page, | |
206 | int cpu_offset, | |
207 | int length, | |
208 | int is_read) | |
209 | { | |
210 | char *gpu_vaddr, *cpu_vaddr; | |
211 | ||
212 | /* Use the unswizzled path if this page isn't affected. */ | |
213 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
214 | if (is_read) | |
215 | return slow_shmem_copy(cpu_page, cpu_offset, | |
216 | gpu_page, gpu_offset, length); | |
217 | else | |
218 | return slow_shmem_copy(gpu_page, gpu_offset, | |
219 | cpu_page, cpu_offset, length); | |
220 | } | |
221 | ||
99a03df5 CW |
222 | gpu_vaddr = kmap(gpu_page); |
223 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
224 | |
225 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
226 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
227 | */ | |
228 | while (length > 0) { | |
229 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
230 | int this_length = min(cacheline_end - gpu_offset, length); | |
231 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
232 | ||
233 | if (is_read) { | |
234 | memcpy(cpu_vaddr + cpu_offset, | |
235 | gpu_vaddr + swizzled_gpu_offset, | |
236 | this_length); | |
237 | } else { | |
238 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
239 | cpu_vaddr + cpu_offset, | |
240 | this_length); | |
241 | } | |
242 | cpu_offset += this_length; | |
243 | gpu_offset += this_length; | |
244 | length -= this_length; | |
245 | } | |
246 | ||
99a03df5 CW |
247 | kunmap(cpu_page); |
248 | kunmap(gpu_page); | |
280b713b EA |
249 | } |
250 | ||
eb01459f EA |
251 | /** |
252 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
253 | * from the backing pages of the object to the user's address space. On a | |
254 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
255 | */ | |
256 | static int | |
257 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
258 | struct drm_i915_gem_pread *args, | |
259 | struct drm_file *file_priv) | |
260 | { | |
23010e43 | 261 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
262 | ssize_t remain; |
263 | loff_t offset, page_base; | |
264 | char __user *user_data; | |
265 | int page_offset, page_length; | |
266 | int ret; | |
267 | ||
268 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
269 | remain = args->size; | |
270 | ||
271 | mutex_lock(&dev->struct_mutex); | |
272 | ||
4bdadb97 | 273 | ret = i915_gem_object_get_pages(obj, 0); |
eb01459f EA |
274 | if (ret != 0) |
275 | goto fail_unlock; | |
276 | ||
277 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
278 | args->size); | |
279 | if (ret != 0) | |
280 | goto fail_put_pages; | |
281 | ||
23010e43 | 282 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
283 | offset = args->offset; |
284 | ||
285 | while (remain > 0) { | |
286 | /* Operation in this page | |
287 | * | |
288 | * page_base = page offset within aperture | |
289 | * page_offset = offset within page | |
290 | * page_length = bytes to copy for this page | |
291 | */ | |
292 | page_base = (offset & ~(PAGE_SIZE-1)); | |
293 | page_offset = offset & (PAGE_SIZE-1); | |
294 | page_length = remain; | |
295 | if ((page_offset + remain) > PAGE_SIZE) | |
296 | page_length = PAGE_SIZE - page_offset; | |
297 | ||
298 | ret = fast_shmem_read(obj_priv->pages, | |
299 | page_base, page_offset, | |
300 | user_data, page_length); | |
301 | if (ret) | |
302 | goto fail_put_pages; | |
303 | ||
304 | remain -= page_length; | |
305 | user_data += page_length; | |
306 | offset += page_length; | |
307 | } | |
308 | ||
309 | fail_put_pages: | |
310 | i915_gem_object_put_pages(obj); | |
311 | fail_unlock: | |
312 | mutex_unlock(&dev->struct_mutex); | |
313 | ||
314 | return ret; | |
315 | } | |
316 | ||
07f73f69 CW |
317 | static int |
318 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
319 | { | |
320 | int ret; | |
321 | ||
4bdadb97 | 322 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
323 | |
324 | /* If we've insufficient memory to map in the pages, attempt | |
325 | * to make some space by throwing out some old buffers. | |
326 | */ | |
327 | if (ret == -ENOMEM) { | |
328 | struct drm_device *dev = obj->dev; | |
07f73f69 | 329 | |
0108a3ed DV |
330 | ret = i915_gem_evict_something(dev, obj->size, |
331 | i915_gem_get_gtt_alignment(obj)); | |
07f73f69 CW |
332 | if (ret) |
333 | return ret; | |
334 | ||
4bdadb97 | 335 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
336 | } |
337 | ||
338 | return ret; | |
339 | } | |
340 | ||
eb01459f EA |
341 | /** |
342 | * This is the fallback shmem pread path, which allocates temporary storage | |
343 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
344 | * can copy out of the object's backing pages while holding the struct mutex | |
345 | * and not take page faults. | |
346 | */ | |
347 | static int | |
348 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
349 | struct drm_i915_gem_pread *args, | |
350 | struct drm_file *file_priv) | |
351 | { | |
23010e43 | 352 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
353 | struct mm_struct *mm = current->mm; |
354 | struct page **user_pages; | |
355 | ssize_t remain; | |
356 | loff_t offset, pinned_pages, i; | |
357 | loff_t first_data_page, last_data_page, num_pages; | |
358 | int shmem_page_index, shmem_page_offset; | |
359 | int data_page_index, data_page_offset; | |
360 | int page_length; | |
361 | int ret; | |
362 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 363 | int do_bit17_swizzling; |
eb01459f EA |
364 | |
365 | remain = args->size; | |
366 | ||
367 | /* Pin the user pages containing the data. We can't fault while | |
368 | * holding the struct mutex, yet we want to hold it while | |
369 | * dereferencing the user data. | |
370 | */ | |
371 | first_data_page = data_ptr / PAGE_SIZE; | |
372 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
373 | num_pages = last_data_page - first_data_page + 1; | |
374 | ||
8e7d2b2c | 375 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
376 | if (user_pages == NULL) |
377 | return -ENOMEM; | |
378 | ||
379 | down_read(&mm->mmap_sem); | |
380 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 381 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
382 | up_read(&mm->mmap_sem); |
383 | if (pinned_pages < num_pages) { | |
384 | ret = -EFAULT; | |
385 | goto fail_put_user_pages; | |
386 | } | |
387 | ||
280b713b EA |
388 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
389 | ||
eb01459f EA |
390 | mutex_lock(&dev->struct_mutex); |
391 | ||
07f73f69 CW |
392 | ret = i915_gem_object_get_pages_or_evict(obj); |
393 | if (ret) | |
eb01459f EA |
394 | goto fail_unlock; |
395 | ||
396 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
397 | args->size); | |
398 | if (ret != 0) | |
399 | goto fail_put_pages; | |
400 | ||
23010e43 | 401 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
402 | offset = args->offset; |
403 | ||
404 | while (remain > 0) { | |
405 | /* Operation in this page | |
406 | * | |
407 | * shmem_page_index = page number within shmem file | |
408 | * shmem_page_offset = offset within page in shmem file | |
409 | * data_page_index = page number in get_user_pages return | |
410 | * data_page_offset = offset with data_page_index page. | |
411 | * page_length = bytes to copy for this page | |
412 | */ | |
413 | shmem_page_index = offset / PAGE_SIZE; | |
414 | shmem_page_offset = offset & ~PAGE_MASK; | |
415 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
416 | data_page_offset = data_ptr & ~PAGE_MASK; | |
417 | ||
418 | page_length = remain; | |
419 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
420 | page_length = PAGE_SIZE - shmem_page_offset; | |
421 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
422 | page_length = PAGE_SIZE - data_page_offset; | |
423 | ||
280b713b | 424 | if (do_bit17_swizzling) { |
99a03df5 | 425 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 426 | shmem_page_offset, |
99a03df5 CW |
427 | user_pages[data_page_index], |
428 | data_page_offset, | |
429 | page_length, | |
430 | 1); | |
431 | } else { | |
432 | slow_shmem_copy(user_pages[data_page_index], | |
433 | data_page_offset, | |
434 | obj_priv->pages[shmem_page_index], | |
435 | shmem_page_offset, | |
436 | page_length); | |
280b713b | 437 | } |
eb01459f EA |
438 | |
439 | remain -= page_length; | |
440 | data_ptr += page_length; | |
441 | offset += page_length; | |
442 | } | |
443 | ||
444 | fail_put_pages: | |
445 | i915_gem_object_put_pages(obj); | |
446 | fail_unlock: | |
447 | mutex_unlock(&dev->struct_mutex); | |
448 | fail_put_user_pages: | |
449 | for (i = 0; i < pinned_pages; i++) { | |
450 | SetPageDirty(user_pages[i]); | |
451 | page_cache_release(user_pages[i]); | |
452 | } | |
8e7d2b2c | 453 | drm_free_large(user_pages); |
eb01459f EA |
454 | |
455 | return ret; | |
456 | } | |
457 | ||
673a394b EA |
458 | /** |
459 | * Reads data from the object referenced by handle. | |
460 | * | |
461 | * On error, the contents of *data are undefined. | |
462 | */ | |
463 | int | |
464 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
465 | struct drm_file *file_priv) | |
466 | { | |
467 | struct drm_i915_gem_pread *args = data; | |
468 | struct drm_gem_object *obj; | |
469 | struct drm_i915_gem_object *obj_priv; | |
673a394b EA |
470 | int ret; |
471 | ||
472 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
473 | if (obj == NULL) | |
bf79cb91 | 474 | return -ENOENT; |
23010e43 | 475 | obj_priv = to_intel_bo(obj); |
673a394b EA |
476 | |
477 | /* Bounds check source. | |
478 | * | |
479 | * XXX: This could use review for overflow issues... | |
480 | */ | |
481 | if (args->offset > obj->size || args->size > obj->size || | |
482 | args->offset + args->size > obj->size) { | |
bc9025bd | 483 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
484 | return -EINVAL; |
485 | } | |
486 | ||
280b713b | 487 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 488 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
489 | } else { |
490 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
491 | if (ret != 0) | |
492 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
493 | file_priv); | |
494 | } | |
673a394b | 495 | |
bc9025bd | 496 | drm_gem_object_unreference_unlocked(obj); |
673a394b | 497 | |
eb01459f | 498 | return ret; |
673a394b EA |
499 | } |
500 | ||
0839ccb8 KP |
501 | /* This is the fast write path which cannot handle |
502 | * page faults in the source data | |
9b7530cc | 503 | */ |
0839ccb8 KP |
504 | |
505 | static inline int | |
506 | fast_user_write(struct io_mapping *mapping, | |
507 | loff_t page_base, int page_offset, | |
508 | char __user *user_data, | |
509 | int length) | |
9b7530cc | 510 | { |
9b7530cc | 511 | char *vaddr_atomic; |
0839ccb8 | 512 | unsigned long unwritten; |
9b7530cc | 513 | |
fca3ec01 | 514 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
0839ccb8 KP |
515 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
516 | user_data, length); | |
fca3ec01 | 517 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
0839ccb8 KP |
518 | if (unwritten) |
519 | return -EFAULT; | |
520 | return 0; | |
521 | } | |
522 | ||
523 | /* Here's the write path which can sleep for | |
524 | * page faults | |
525 | */ | |
526 | ||
ab34c226 | 527 | static inline void |
3de09aa3 EA |
528 | slow_kernel_write(struct io_mapping *mapping, |
529 | loff_t gtt_base, int gtt_offset, | |
530 | struct page *user_page, int user_offset, | |
531 | int length) | |
0839ccb8 | 532 | { |
ab34c226 CW |
533 | char __iomem *dst_vaddr; |
534 | char *src_vaddr; | |
0839ccb8 | 535 | |
ab34c226 CW |
536 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
537 | src_vaddr = kmap(user_page); | |
538 | ||
539 | memcpy_toio(dst_vaddr + gtt_offset, | |
540 | src_vaddr + user_offset, | |
541 | length); | |
542 | ||
543 | kunmap(user_page); | |
544 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
545 | } |
546 | ||
40123c1f EA |
547 | static inline int |
548 | fast_shmem_write(struct page **pages, | |
549 | loff_t page_base, int page_offset, | |
550 | char __user *data, | |
551 | int length) | |
552 | { | |
553 | char __iomem *vaddr; | |
d0088775 | 554 | unsigned long unwritten; |
40123c1f EA |
555 | |
556 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
557 | if (vaddr == NULL) | |
558 | return -ENOMEM; | |
d0088775 | 559 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
560 | kunmap_atomic(vaddr, KM_USER0); |
561 | ||
d0088775 DA |
562 | if (unwritten) |
563 | return -EFAULT; | |
40123c1f EA |
564 | return 0; |
565 | } | |
566 | ||
3de09aa3 EA |
567 | /** |
568 | * This is the fast pwrite path, where we copy the data directly from the | |
569 | * user into the GTT, uncached. | |
570 | */ | |
673a394b | 571 | static int |
3de09aa3 EA |
572 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
573 | struct drm_i915_gem_pwrite *args, | |
574 | struct drm_file *file_priv) | |
673a394b | 575 | { |
23010e43 | 576 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 577 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 578 | ssize_t remain; |
0839ccb8 | 579 | loff_t offset, page_base; |
673a394b | 580 | char __user *user_data; |
0839ccb8 KP |
581 | int page_offset, page_length; |
582 | int ret; | |
673a394b EA |
583 | |
584 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
585 | remain = args->size; | |
586 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
587 | return -EFAULT; | |
588 | ||
589 | ||
590 | mutex_lock(&dev->struct_mutex); | |
591 | ret = i915_gem_object_pin(obj, 0); | |
592 | if (ret) { | |
593 | mutex_unlock(&dev->struct_mutex); | |
594 | return ret; | |
595 | } | |
2ef7eeaa | 596 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
597 | if (ret) |
598 | goto fail; | |
599 | ||
23010e43 | 600 | obj_priv = to_intel_bo(obj); |
673a394b | 601 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
602 | |
603 | while (remain > 0) { | |
604 | /* Operation in this page | |
605 | * | |
0839ccb8 KP |
606 | * page_base = page offset within aperture |
607 | * page_offset = offset within page | |
608 | * page_length = bytes to copy for this page | |
673a394b | 609 | */ |
0839ccb8 KP |
610 | page_base = (offset & ~(PAGE_SIZE-1)); |
611 | page_offset = offset & (PAGE_SIZE-1); | |
612 | page_length = remain; | |
613 | if ((page_offset + remain) > PAGE_SIZE) | |
614 | page_length = PAGE_SIZE - page_offset; | |
615 | ||
616 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
617 | page_offset, user_data, page_length); | |
618 | ||
619 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
620 | * source page isn't available. Return the error and we'll |
621 | * retry in the slow path. | |
0839ccb8 | 622 | */ |
3de09aa3 EA |
623 | if (ret) |
624 | goto fail; | |
673a394b | 625 | |
0839ccb8 KP |
626 | remain -= page_length; |
627 | user_data += page_length; | |
628 | offset += page_length; | |
673a394b | 629 | } |
673a394b EA |
630 | |
631 | fail: | |
632 | i915_gem_object_unpin(obj); | |
633 | mutex_unlock(&dev->struct_mutex); | |
634 | ||
635 | return ret; | |
636 | } | |
637 | ||
3de09aa3 EA |
638 | /** |
639 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
640 | * the memory and maps it using kmap_atomic for copying. | |
641 | * | |
642 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
643 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
644 | */ | |
3043c60c | 645 | static int |
3de09aa3 EA |
646 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
647 | struct drm_i915_gem_pwrite *args, | |
648 | struct drm_file *file_priv) | |
673a394b | 649 | { |
23010e43 | 650 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
651 | drm_i915_private_t *dev_priv = dev->dev_private; |
652 | ssize_t remain; | |
653 | loff_t gtt_page_base, offset; | |
654 | loff_t first_data_page, last_data_page, num_pages; | |
655 | loff_t pinned_pages, i; | |
656 | struct page **user_pages; | |
657 | struct mm_struct *mm = current->mm; | |
658 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 659 | int ret; |
3de09aa3 EA |
660 | uint64_t data_ptr = args->data_ptr; |
661 | ||
662 | remain = args->size; | |
663 | ||
664 | /* Pin the user pages containing the data. We can't fault while | |
665 | * holding the struct mutex, and all of the pwrite implementations | |
666 | * want to hold it while dereferencing the user data. | |
667 | */ | |
668 | first_data_page = data_ptr / PAGE_SIZE; | |
669 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
670 | num_pages = last_data_page - first_data_page + 1; | |
671 | ||
8e7d2b2c | 672 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
673 | if (user_pages == NULL) |
674 | return -ENOMEM; | |
675 | ||
676 | down_read(&mm->mmap_sem); | |
677 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
678 | num_pages, 0, 0, user_pages, NULL); | |
679 | up_read(&mm->mmap_sem); | |
680 | if (pinned_pages < num_pages) { | |
681 | ret = -EFAULT; | |
682 | goto out_unpin_pages; | |
683 | } | |
673a394b EA |
684 | |
685 | mutex_lock(&dev->struct_mutex); | |
3de09aa3 EA |
686 | ret = i915_gem_object_pin(obj, 0); |
687 | if (ret) | |
688 | goto out_unlock; | |
689 | ||
690 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
691 | if (ret) | |
692 | goto out_unpin_object; | |
693 | ||
23010e43 | 694 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
695 | offset = obj_priv->gtt_offset + args->offset; |
696 | ||
697 | while (remain > 0) { | |
698 | /* Operation in this page | |
699 | * | |
700 | * gtt_page_base = page offset within aperture | |
701 | * gtt_page_offset = offset within page in aperture | |
702 | * data_page_index = page number in get_user_pages return | |
703 | * data_page_offset = offset with data_page_index page. | |
704 | * page_length = bytes to copy for this page | |
705 | */ | |
706 | gtt_page_base = offset & PAGE_MASK; | |
707 | gtt_page_offset = offset & ~PAGE_MASK; | |
708 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
709 | data_page_offset = data_ptr & ~PAGE_MASK; | |
710 | ||
711 | page_length = remain; | |
712 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
713 | page_length = PAGE_SIZE - gtt_page_offset; | |
714 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
715 | page_length = PAGE_SIZE - data_page_offset; | |
716 | ||
ab34c226 CW |
717 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
718 | gtt_page_base, gtt_page_offset, | |
719 | user_pages[data_page_index], | |
720 | data_page_offset, | |
721 | page_length); | |
3de09aa3 EA |
722 | |
723 | remain -= page_length; | |
724 | offset += page_length; | |
725 | data_ptr += page_length; | |
726 | } | |
727 | ||
728 | out_unpin_object: | |
729 | i915_gem_object_unpin(obj); | |
730 | out_unlock: | |
731 | mutex_unlock(&dev->struct_mutex); | |
732 | out_unpin_pages: | |
733 | for (i = 0; i < pinned_pages; i++) | |
734 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 735 | drm_free_large(user_pages); |
3de09aa3 EA |
736 | |
737 | return ret; | |
738 | } | |
739 | ||
40123c1f EA |
740 | /** |
741 | * This is the fast shmem pwrite path, which attempts to directly | |
742 | * copy_from_user into the kmapped pages backing the object. | |
743 | */ | |
3043c60c | 744 | static int |
40123c1f EA |
745 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
746 | struct drm_i915_gem_pwrite *args, | |
747 | struct drm_file *file_priv) | |
673a394b | 748 | { |
23010e43 | 749 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
750 | ssize_t remain; |
751 | loff_t offset, page_base; | |
752 | char __user *user_data; | |
753 | int page_offset, page_length; | |
673a394b | 754 | int ret; |
40123c1f EA |
755 | |
756 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
757 | remain = args->size; | |
673a394b EA |
758 | |
759 | mutex_lock(&dev->struct_mutex); | |
760 | ||
4bdadb97 | 761 | ret = i915_gem_object_get_pages(obj, 0); |
40123c1f EA |
762 | if (ret != 0) |
763 | goto fail_unlock; | |
673a394b | 764 | |
e47c68e9 | 765 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
766 | if (ret != 0) |
767 | goto fail_put_pages; | |
768 | ||
23010e43 | 769 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
770 | offset = args->offset; |
771 | obj_priv->dirty = 1; | |
772 | ||
773 | while (remain > 0) { | |
774 | /* Operation in this page | |
775 | * | |
776 | * page_base = page offset within aperture | |
777 | * page_offset = offset within page | |
778 | * page_length = bytes to copy for this page | |
779 | */ | |
780 | page_base = (offset & ~(PAGE_SIZE-1)); | |
781 | page_offset = offset & (PAGE_SIZE-1); | |
782 | page_length = remain; | |
783 | if ((page_offset + remain) > PAGE_SIZE) | |
784 | page_length = PAGE_SIZE - page_offset; | |
785 | ||
786 | ret = fast_shmem_write(obj_priv->pages, | |
787 | page_base, page_offset, | |
788 | user_data, page_length); | |
789 | if (ret) | |
790 | goto fail_put_pages; | |
791 | ||
792 | remain -= page_length; | |
793 | user_data += page_length; | |
794 | offset += page_length; | |
795 | } | |
796 | ||
797 | fail_put_pages: | |
798 | i915_gem_object_put_pages(obj); | |
799 | fail_unlock: | |
800 | mutex_unlock(&dev->struct_mutex); | |
801 | ||
802 | return ret; | |
803 | } | |
804 | ||
805 | /** | |
806 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
807 | * the memory and maps it using kmap_atomic for copying. | |
808 | * | |
809 | * This avoids taking mmap_sem for faulting on the user's address while the | |
810 | * struct_mutex is held. | |
811 | */ | |
812 | static int | |
813 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
814 | struct drm_i915_gem_pwrite *args, | |
815 | struct drm_file *file_priv) | |
816 | { | |
23010e43 | 817 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
818 | struct mm_struct *mm = current->mm; |
819 | struct page **user_pages; | |
820 | ssize_t remain; | |
821 | loff_t offset, pinned_pages, i; | |
822 | loff_t first_data_page, last_data_page, num_pages; | |
823 | int shmem_page_index, shmem_page_offset; | |
824 | int data_page_index, data_page_offset; | |
825 | int page_length; | |
826 | int ret; | |
827 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 828 | int do_bit17_swizzling; |
40123c1f EA |
829 | |
830 | remain = args->size; | |
831 | ||
832 | /* Pin the user pages containing the data. We can't fault while | |
833 | * holding the struct mutex, and all of the pwrite implementations | |
834 | * want to hold it while dereferencing the user data. | |
835 | */ | |
836 | first_data_page = data_ptr / PAGE_SIZE; | |
837 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
838 | num_pages = last_data_page - first_data_page + 1; | |
839 | ||
8e7d2b2c | 840 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
841 | if (user_pages == NULL) |
842 | return -ENOMEM; | |
843 | ||
844 | down_read(&mm->mmap_sem); | |
845 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
846 | num_pages, 0, 0, user_pages, NULL); | |
847 | up_read(&mm->mmap_sem); | |
848 | if (pinned_pages < num_pages) { | |
849 | ret = -EFAULT; | |
850 | goto fail_put_user_pages; | |
673a394b EA |
851 | } |
852 | ||
280b713b EA |
853 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
854 | ||
40123c1f EA |
855 | mutex_lock(&dev->struct_mutex); |
856 | ||
07f73f69 CW |
857 | ret = i915_gem_object_get_pages_or_evict(obj); |
858 | if (ret) | |
40123c1f EA |
859 | goto fail_unlock; |
860 | ||
861 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
862 | if (ret != 0) | |
863 | goto fail_put_pages; | |
864 | ||
23010e43 | 865 | obj_priv = to_intel_bo(obj); |
673a394b | 866 | offset = args->offset; |
40123c1f | 867 | obj_priv->dirty = 1; |
673a394b | 868 | |
40123c1f EA |
869 | while (remain > 0) { |
870 | /* Operation in this page | |
871 | * | |
872 | * shmem_page_index = page number within shmem file | |
873 | * shmem_page_offset = offset within page in shmem file | |
874 | * data_page_index = page number in get_user_pages return | |
875 | * data_page_offset = offset with data_page_index page. | |
876 | * page_length = bytes to copy for this page | |
877 | */ | |
878 | shmem_page_index = offset / PAGE_SIZE; | |
879 | shmem_page_offset = offset & ~PAGE_MASK; | |
880 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
881 | data_page_offset = data_ptr & ~PAGE_MASK; | |
882 | ||
883 | page_length = remain; | |
884 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
885 | page_length = PAGE_SIZE - shmem_page_offset; | |
886 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
887 | page_length = PAGE_SIZE - data_page_offset; | |
888 | ||
280b713b | 889 | if (do_bit17_swizzling) { |
99a03df5 | 890 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
891 | shmem_page_offset, |
892 | user_pages[data_page_index], | |
893 | data_page_offset, | |
99a03df5 CW |
894 | page_length, |
895 | 0); | |
896 | } else { | |
897 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
898 | shmem_page_offset, | |
899 | user_pages[data_page_index], | |
900 | data_page_offset, | |
901 | page_length); | |
280b713b | 902 | } |
40123c1f EA |
903 | |
904 | remain -= page_length; | |
905 | data_ptr += page_length; | |
906 | offset += page_length; | |
673a394b EA |
907 | } |
908 | ||
40123c1f EA |
909 | fail_put_pages: |
910 | i915_gem_object_put_pages(obj); | |
911 | fail_unlock: | |
673a394b | 912 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
913 | fail_put_user_pages: |
914 | for (i = 0; i < pinned_pages; i++) | |
915 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 916 | drm_free_large(user_pages); |
673a394b | 917 | |
40123c1f | 918 | return ret; |
673a394b EA |
919 | } |
920 | ||
921 | /** | |
922 | * Writes data to the object referenced by handle. | |
923 | * | |
924 | * On error, the contents of the buffer that were to be modified are undefined. | |
925 | */ | |
926 | int | |
927 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
928 | struct drm_file *file_priv) | |
929 | { | |
930 | struct drm_i915_gem_pwrite *args = data; | |
931 | struct drm_gem_object *obj; | |
932 | struct drm_i915_gem_object *obj_priv; | |
933 | int ret = 0; | |
934 | ||
935 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
936 | if (obj == NULL) | |
bf79cb91 | 937 | return -ENOENT; |
23010e43 | 938 | obj_priv = to_intel_bo(obj); |
673a394b EA |
939 | |
940 | /* Bounds check destination. | |
941 | * | |
942 | * XXX: This could use review for overflow issues... | |
943 | */ | |
944 | if (args->offset > obj->size || args->size > obj->size || | |
945 | args->offset + args->size > obj->size) { | |
bc9025bd | 946 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
947 | return -EINVAL; |
948 | } | |
949 | ||
950 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
951 | * it would end up going through the fenced access, and we'll get | |
952 | * different detiling behavior between reading and writing. | |
953 | * pread/pwrite currently are reading and writing from the CPU | |
954 | * perspective, requiring manual detiling by the client. | |
955 | */ | |
71acb5eb DA |
956 | if (obj_priv->phys_obj) |
957 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
958 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
9b8c4a0b CW |
959 | dev->gtt_total != 0 && |
960 | obj->write_domain != I915_GEM_DOMAIN_CPU) { | |
3de09aa3 EA |
961 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
962 | if (ret == -EFAULT) { | |
963 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
964 | file_priv); | |
965 | } | |
280b713b EA |
966 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
967 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
968 | } else { |
969 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
970 | if (ret == -EFAULT) { | |
971 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
972 | file_priv); | |
973 | } | |
974 | } | |
673a394b EA |
975 | |
976 | #if WATCH_PWRITE | |
977 | if (ret) | |
978 | DRM_INFO("pwrite failed %d\n", ret); | |
979 | #endif | |
980 | ||
bc9025bd | 981 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
982 | |
983 | return ret; | |
984 | } | |
985 | ||
986 | /** | |
2ef7eeaa EA |
987 | * Called when user space prepares to use an object with the CPU, either |
988 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
989 | */ |
990 | int | |
991 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
992 | struct drm_file *file_priv) | |
993 | { | |
a09ba7fa | 994 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
995 | struct drm_i915_gem_set_domain *args = data; |
996 | struct drm_gem_object *obj; | |
652c393a | 997 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
998 | uint32_t read_domains = args->read_domains; |
999 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1000 | int ret; |
1001 | ||
1002 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1003 | return -ENODEV; | |
1004 | ||
2ef7eeaa | 1005 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1006 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1007 | return -EINVAL; |
1008 | ||
21d509e3 | 1009 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1010 | return -EINVAL; |
1011 | ||
1012 | /* Having something in the write domain implies it's in the read | |
1013 | * domain, and only that read domain. Enforce that in the request. | |
1014 | */ | |
1015 | if (write_domain != 0 && read_domains != write_domain) | |
1016 | return -EINVAL; | |
1017 | ||
673a394b EA |
1018 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1019 | if (obj == NULL) | |
bf79cb91 | 1020 | return -ENOENT; |
23010e43 | 1021 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1022 | |
1023 | mutex_lock(&dev->struct_mutex); | |
652c393a JB |
1024 | |
1025 | intel_mark_busy(dev, obj); | |
1026 | ||
673a394b | 1027 | #if WATCH_BUF |
cfd43c02 | 1028 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
2ef7eeaa | 1029 | obj, obj->size, read_domains, write_domain); |
673a394b | 1030 | #endif |
2ef7eeaa EA |
1031 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1032 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1033 | |
a09ba7fa EA |
1034 | /* Update the LRU on the fence for the CPU access that's |
1035 | * about to occur. | |
1036 | */ | |
1037 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1038 | struct drm_i915_fence_reg *reg = |
1039 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1040 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1041 | &dev_priv->mm.fence_list); |
1042 | } | |
1043 | ||
02354392 EA |
1044 | /* Silently promote "you're not bound, there was nothing to do" |
1045 | * to success, since the client was just asking us to | |
1046 | * make sure everything was done. | |
1047 | */ | |
1048 | if (ret == -EINVAL) | |
1049 | ret = 0; | |
2ef7eeaa | 1050 | } else { |
e47c68e9 | 1051 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1052 | } |
1053 | ||
7d1c4804 CW |
1054 | /* Maintain LRU order of "inactive" objects */ |
1055 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
1056 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1057 | ||
673a394b EA |
1058 | drm_gem_object_unreference(obj); |
1059 | mutex_unlock(&dev->struct_mutex); | |
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | /** | |
1064 | * Called when user space has done writes to this buffer | |
1065 | */ | |
1066 | int | |
1067 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1068 | struct drm_file *file_priv) | |
1069 | { | |
1070 | struct drm_i915_gem_sw_finish *args = data; | |
1071 | struct drm_gem_object *obj; | |
1072 | struct drm_i915_gem_object *obj_priv; | |
1073 | int ret = 0; | |
1074 | ||
1075 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1076 | return -ENODEV; | |
1077 | ||
1078 | mutex_lock(&dev->struct_mutex); | |
1079 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1080 | if (obj == NULL) { | |
1081 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 1082 | return -ENOENT; |
673a394b EA |
1083 | } |
1084 | ||
1085 | #if WATCH_BUF | |
cfd43c02 | 1086 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
673a394b EA |
1087 | __func__, args->handle, obj, obj->size); |
1088 | #endif | |
23010e43 | 1089 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1090 | |
1091 | /* Pinned buffers may be scanout, so flush the cache */ | |
e47c68e9 EA |
1092 | if (obj_priv->pin_count) |
1093 | i915_gem_object_flush_cpu_write_domain(obj); | |
1094 | ||
673a394b EA |
1095 | drm_gem_object_unreference(obj); |
1096 | mutex_unlock(&dev->struct_mutex); | |
1097 | return ret; | |
1098 | } | |
1099 | ||
1100 | /** | |
1101 | * Maps the contents of an object, returning the address it is mapped | |
1102 | * into. | |
1103 | * | |
1104 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1105 | * imply a ref on the object itself. | |
1106 | */ | |
1107 | int | |
1108 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1109 | struct drm_file *file_priv) | |
1110 | { | |
1111 | struct drm_i915_gem_mmap *args = data; | |
1112 | struct drm_gem_object *obj; | |
1113 | loff_t offset; | |
1114 | unsigned long addr; | |
1115 | ||
1116 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1117 | return -ENODEV; | |
1118 | ||
1119 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1120 | if (obj == NULL) | |
bf79cb91 | 1121 | return -ENOENT; |
673a394b EA |
1122 | |
1123 | offset = args->offset; | |
1124 | ||
1125 | down_write(¤t->mm->mmap_sem); | |
1126 | addr = do_mmap(obj->filp, 0, args->size, | |
1127 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1128 | args->offset); | |
1129 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1130 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1131 | if (IS_ERR((void *)addr)) |
1132 | return addr; | |
1133 | ||
1134 | args->addr_ptr = (uint64_t) addr; | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
de151cf6 JB |
1139 | /** |
1140 | * i915_gem_fault - fault a page into the GTT | |
1141 | * vma: VMA in question | |
1142 | * vmf: fault info | |
1143 | * | |
1144 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1145 | * from userspace. The fault handler takes care of binding the object to | |
1146 | * the GTT (if needed), allocating and programming a fence register (again, | |
1147 | * only if needed based on whether the old reg is still valid or the object | |
1148 | * is tiled) and inserting a new PTE into the faulting process. | |
1149 | * | |
1150 | * Note that the faulting process may involve evicting existing objects | |
1151 | * from the GTT and/or fence registers to make room. So performance may | |
1152 | * suffer if the GTT working set is large or there are few fence registers | |
1153 | * left. | |
1154 | */ | |
1155 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1156 | { | |
1157 | struct drm_gem_object *obj = vma->vm_private_data; | |
1158 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1159 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1160 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1161 | pgoff_t page_offset; |
1162 | unsigned long pfn; | |
1163 | int ret = 0; | |
0f973f27 | 1164 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1165 | |
1166 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1167 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1168 | PAGE_SHIFT; | |
1169 | ||
1170 | /* Now bind it into the GTT if needed */ | |
1171 | mutex_lock(&dev->struct_mutex); | |
1172 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1173 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1174 | if (ret) |
1175 | goto unlock; | |
07f4f3e8 | 1176 | |
07f4f3e8 | 1177 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1178 | if (ret) |
1179 | goto unlock; | |
de151cf6 JB |
1180 | } |
1181 | ||
1182 | /* Need a new fence register? */ | |
a09ba7fa | 1183 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1184 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1185 | if (ret) |
1186 | goto unlock; | |
d9ddcb96 | 1187 | } |
de151cf6 | 1188 | |
7d1c4804 CW |
1189 | if (i915_gem_object_is_inactive(obj_priv)) |
1190 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1191 | ||
de151cf6 JB |
1192 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1193 | page_offset; | |
1194 | ||
1195 | /* Finally, remap it using the new GTT offset */ | |
1196 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1197 | unlock: |
de151cf6 JB |
1198 | mutex_unlock(&dev->struct_mutex); |
1199 | ||
1200 | switch (ret) { | |
c715089f CW |
1201 | case 0: |
1202 | case -ERESTARTSYS: | |
1203 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1204 | case -ENOMEM: |
1205 | case -EAGAIN: | |
1206 | return VM_FAULT_OOM; | |
de151cf6 | 1207 | default: |
c715089f | 1208 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1209 | } |
1210 | } | |
1211 | ||
1212 | /** | |
1213 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1214 | * @obj: obj in question | |
1215 | * | |
1216 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1217 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1218 | * up the object based on the offset and sets up the various memory mapping | |
1219 | * structures. | |
1220 | * | |
1221 | * This routine allocates and attaches a fake offset for @obj. | |
1222 | */ | |
1223 | static int | |
1224 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1225 | { | |
1226 | struct drm_device *dev = obj->dev; | |
1227 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1228 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1229 | struct drm_map_list *list; |
f77d390c | 1230 | struct drm_local_map *map; |
de151cf6 JB |
1231 | int ret = 0; |
1232 | ||
1233 | /* Set the object up for mmap'ing */ | |
1234 | list = &obj->map_list; | |
9a298b2a | 1235 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1236 | if (!list->map) |
1237 | return -ENOMEM; | |
1238 | ||
1239 | map = list->map; | |
1240 | map->type = _DRM_GEM; | |
1241 | map->size = obj->size; | |
1242 | map->handle = obj; | |
1243 | ||
1244 | /* Get a DRM GEM mmap offset allocated... */ | |
1245 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1246 | obj->size / PAGE_SIZE, 0, 0); | |
1247 | if (!list->file_offset_node) { | |
1248 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1249 | ret = -ENOSPC; |
de151cf6 JB |
1250 | goto out_free_list; |
1251 | } | |
1252 | ||
1253 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1254 | obj->size / PAGE_SIZE, 0); | |
1255 | if (!list->file_offset_node) { | |
1256 | ret = -ENOMEM; | |
1257 | goto out_free_list; | |
1258 | } | |
1259 | ||
1260 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1261 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1262 | if (ret) { | |
de151cf6 JB |
1263 | DRM_ERROR("failed to add to map hash\n"); |
1264 | goto out_free_mm; | |
1265 | } | |
1266 | ||
1267 | /* By now we should be all set, any drm_mmap request on the offset | |
1268 | * below will get to our mmap & fault handler */ | |
1269 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1270 | ||
1271 | return 0; | |
1272 | ||
1273 | out_free_mm: | |
1274 | drm_mm_put_block(list->file_offset_node); | |
1275 | out_free_list: | |
9a298b2a | 1276 | kfree(list->map); |
de151cf6 JB |
1277 | |
1278 | return ret; | |
1279 | } | |
1280 | ||
901782b2 CW |
1281 | /** |
1282 | * i915_gem_release_mmap - remove physical page mappings | |
1283 | * @obj: obj in question | |
1284 | * | |
af901ca1 | 1285 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1286 | * relinquish ownership of the pages back to the system. |
1287 | * | |
1288 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1289 | * object through the GTT and then lose the fence register due to | |
1290 | * resource pressure. Similarly if the object has been moved out of the | |
1291 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1292 | * mapping will then trigger a page fault on the next user access, allowing | |
1293 | * fixup by i915_gem_fault(). | |
1294 | */ | |
d05ca301 | 1295 | void |
901782b2 CW |
1296 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1297 | { | |
1298 | struct drm_device *dev = obj->dev; | |
23010e43 | 1299 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1300 | |
1301 | if (dev->dev_mapping) | |
1302 | unmap_mapping_range(dev->dev_mapping, | |
1303 | obj_priv->mmap_offset, obj->size, 1); | |
1304 | } | |
1305 | ||
ab00b3e5 JB |
1306 | static void |
1307 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1308 | { | |
1309 | struct drm_device *dev = obj->dev; | |
23010e43 | 1310 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1311 | struct drm_gem_mm *mm = dev->mm_private; |
1312 | struct drm_map_list *list; | |
1313 | ||
1314 | list = &obj->map_list; | |
1315 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1316 | ||
1317 | if (list->file_offset_node) { | |
1318 | drm_mm_put_block(list->file_offset_node); | |
1319 | list->file_offset_node = NULL; | |
1320 | } | |
1321 | ||
1322 | if (list->map) { | |
9a298b2a | 1323 | kfree(list->map); |
ab00b3e5 JB |
1324 | list->map = NULL; |
1325 | } | |
1326 | ||
1327 | obj_priv->mmap_offset = 0; | |
1328 | } | |
1329 | ||
de151cf6 JB |
1330 | /** |
1331 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1332 | * @obj: object to check | |
1333 | * | |
1334 | * Return the required GTT alignment for an object, taking into account | |
1335 | * potential fence register mapping if needed. | |
1336 | */ | |
1337 | static uint32_t | |
1338 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1339 | { | |
1340 | struct drm_device *dev = obj->dev; | |
23010e43 | 1341 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1342 | int start, i; |
1343 | ||
1344 | /* | |
1345 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1346 | * if a fence register is needed for the object. | |
1347 | */ | |
a6c45cf0 | 1348 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1349 | return 4096; |
1350 | ||
1351 | /* | |
1352 | * Previous chips need to be aligned to the size of the smallest | |
1353 | * fence register that can contain the object. | |
1354 | */ | |
a6c45cf0 | 1355 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1356 | start = 1024*1024; |
1357 | else | |
1358 | start = 512*1024; | |
1359 | ||
1360 | for (i = start; i < obj->size; i <<= 1) | |
1361 | ; | |
1362 | ||
1363 | return i; | |
1364 | } | |
1365 | ||
1366 | /** | |
1367 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1368 | * @dev: DRM device | |
1369 | * @data: GTT mapping ioctl data | |
1370 | * @file_priv: GEM object info | |
1371 | * | |
1372 | * Simply returns the fake offset to userspace so it can mmap it. | |
1373 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1374 | * up so we can get faults in the handler above. | |
1375 | * | |
1376 | * The fault handler will take care of binding the object into the GTT | |
1377 | * (since it may have been evicted to make room for something), allocating | |
1378 | * a fence register, and mapping the appropriate aperture address into | |
1379 | * userspace. | |
1380 | */ | |
1381 | int | |
1382 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1383 | struct drm_file *file_priv) | |
1384 | { | |
1385 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1386 | struct drm_gem_object *obj; |
1387 | struct drm_i915_gem_object *obj_priv; | |
1388 | int ret; | |
1389 | ||
1390 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1391 | return -ENODEV; | |
1392 | ||
1393 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1394 | if (obj == NULL) | |
bf79cb91 | 1395 | return -ENOENT; |
de151cf6 JB |
1396 | |
1397 | mutex_lock(&dev->struct_mutex); | |
1398 | ||
23010e43 | 1399 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1400 | |
ab18282d CW |
1401 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1402 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1403 | drm_gem_object_unreference(obj); | |
1404 | mutex_unlock(&dev->struct_mutex); | |
1405 | return -EINVAL; | |
1406 | } | |
1407 | ||
1408 | ||
de151cf6 JB |
1409 | if (!obj_priv->mmap_offset) { |
1410 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1411 | if (ret) { |
1412 | drm_gem_object_unreference(obj); | |
1413 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1414 | return ret; |
13af1062 | 1415 | } |
de151cf6 JB |
1416 | } |
1417 | ||
1418 | args->offset = obj_priv->mmap_offset; | |
1419 | ||
de151cf6 JB |
1420 | /* |
1421 | * Pull it into the GTT so that we have a page list (makes the | |
1422 | * initial fault faster and any subsequent flushing possible). | |
1423 | */ | |
1424 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1425 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1426 | if (ret) { |
1427 | drm_gem_object_unreference(obj); | |
1428 | mutex_unlock(&dev->struct_mutex); | |
1429 | return ret; | |
1430 | } | |
de151cf6 JB |
1431 | } |
1432 | ||
1433 | drm_gem_object_unreference(obj); | |
1434 | mutex_unlock(&dev->struct_mutex); | |
1435 | ||
1436 | return 0; | |
1437 | } | |
1438 | ||
6911a9b8 | 1439 | void |
856fa198 | 1440 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1441 | { |
23010e43 | 1442 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1443 | int page_count = obj->size / PAGE_SIZE; |
1444 | int i; | |
1445 | ||
856fa198 | 1446 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1447 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1448 | |
856fa198 EA |
1449 | if (--obj_priv->pages_refcount != 0) |
1450 | return; | |
673a394b | 1451 | |
280b713b EA |
1452 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1453 | i915_gem_object_save_bit_17_swizzle(obj); | |
1454 | ||
3ef94daa | 1455 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1456 | obj_priv->dirty = 0; |
3ef94daa CW |
1457 | |
1458 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1459 | if (obj_priv->dirty) |
1460 | set_page_dirty(obj_priv->pages[i]); | |
1461 | ||
1462 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1463 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1464 | |
1465 | page_cache_release(obj_priv->pages[i]); | |
1466 | } | |
673a394b EA |
1467 | obj_priv->dirty = 0; |
1468 | ||
8e7d2b2c | 1469 | drm_free_large(obj_priv->pages); |
856fa198 | 1470 | obj_priv->pages = NULL; |
673a394b EA |
1471 | } |
1472 | ||
e35a41de | 1473 | static uint32_t |
a6910434 DV |
1474 | i915_gem_next_request_seqno(struct drm_device *dev, |
1475 | struct intel_ring_buffer *ring) | |
e35a41de DV |
1476 | { |
1477 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1478 | ||
a6910434 DV |
1479 | ring->outstanding_lazy_request = true; |
1480 | ||
e35a41de DV |
1481 | return dev_priv->next_seqno; |
1482 | } | |
1483 | ||
673a394b | 1484 | static void |
617dbe27 | 1485 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1486 | struct intel_ring_buffer *ring) |
673a394b EA |
1487 | { |
1488 | struct drm_device *dev = obj->dev; | |
23010e43 | 1489 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
617dbe27 DV |
1490 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
1491 | ||
852835f3 ZN |
1492 | BUG_ON(ring == NULL); |
1493 | obj_priv->ring = ring; | |
673a394b EA |
1494 | |
1495 | /* Add a reference if we're newly entering the active list. */ | |
1496 | if (!obj_priv->active) { | |
1497 | drm_gem_object_reference(obj); | |
1498 | obj_priv->active = 1; | |
1499 | } | |
e35a41de | 1500 | |
673a394b | 1501 | /* Move from whatever list we were on to the tail of execution. */ |
852835f3 | 1502 | list_move_tail(&obj_priv->list, &ring->active_list); |
ce44b0ea | 1503 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1504 | } |
1505 | ||
ce44b0ea EA |
1506 | static void |
1507 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1508 | { | |
1509 | struct drm_device *dev = obj->dev; | |
1510 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1511 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1512 | |
1513 | BUG_ON(!obj_priv->active); | |
1514 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1515 | obj_priv->last_rendering_seqno = 0; | |
1516 | } | |
673a394b | 1517 | |
963b4836 CW |
1518 | /* Immediately discard the backing storage */ |
1519 | static void | |
1520 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1521 | { | |
23010e43 | 1522 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1523 | struct inode *inode; |
963b4836 | 1524 | |
ae9fed6b CW |
1525 | /* Our goal here is to return as much of the memory as |
1526 | * is possible back to the system as we are called from OOM. | |
1527 | * To do this we must instruct the shmfs to drop all of its | |
1528 | * backing pages, *now*. Here we mirror the actions taken | |
1529 | * when by shmem_delete_inode() to release the backing store. | |
1530 | */ | |
bb6baf76 | 1531 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1532 | truncate_inode_pages(inode->i_mapping, 0); |
1533 | if (inode->i_op->truncate_range) | |
1534 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1535 | |
1536 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1537 | } |
1538 | ||
1539 | static inline int | |
1540 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1541 | { | |
1542 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1543 | } | |
1544 | ||
673a394b EA |
1545 | static void |
1546 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1547 | { | |
1548 | struct drm_device *dev = obj->dev; | |
1549 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1550 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1551 | |
1552 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1553 | if (obj_priv->pin_count != 0) | |
f13d3f73 | 1554 | list_move_tail(&obj_priv->list, &dev_priv->mm.pinned_list); |
673a394b EA |
1555 | else |
1556 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1557 | ||
99fcb766 DV |
1558 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1559 | ||
ce44b0ea | 1560 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1561 | obj_priv->ring = NULL; |
673a394b EA |
1562 | if (obj_priv->active) { |
1563 | obj_priv->active = 0; | |
1564 | drm_gem_object_unreference(obj); | |
1565 | } | |
1566 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1567 | } | |
1568 | ||
9220434a | 1569 | static void |
63560396 | 1570 | i915_gem_process_flushing_list(struct drm_device *dev, |
8a1a49f9 | 1571 | uint32_t flush_domains, |
852835f3 | 1572 | struct intel_ring_buffer *ring) |
63560396 DV |
1573 | { |
1574 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1575 | struct drm_i915_gem_object *obj_priv, *next; | |
1576 | ||
1577 | list_for_each_entry_safe(obj_priv, next, | |
1578 | &dev_priv->mm.gpu_write_list, | |
1579 | gpu_write_list) { | |
a8089e84 | 1580 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1581 | |
2b6efaa4 CW |
1582 | if (obj->write_domain & flush_domains && |
1583 | obj_priv->ring == ring) { | |
63560396 DV |
1584 | uint32_t old_write_domain = obj->write_domain; |
1585 | ||
1586 | obj->write_domain = 0; | |
1587 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1588 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1589 | |
1590 | /* update the fence lru list */ | |
007cc8ac DV |
1591 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1592 | struct drm_i915_fence_reg *reg = | |
1593 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1594 | list_move_tail(®->lru_list, | |
63560396 | 1595 | &dev_priv->mm.fence_list); |
007cc8ac | 1596 | } |
63560396 DV |
1597 | |
1598 | trace_i915_gem_object_change_domain(obj, | |
1599 | obj->read_domains, | |
1600 | old_write_domain); | |
1601 | } | |
1602 | } | |
1603 | } | |
8187a2b7 | 1604 | |
5a5a0c64 | 1605 | uint32_t |
8a1a49f9 DV |
1606 | i915_add_request(struct drm_device *dev, |
1607 | struct drm_file *file_priv, | |
8dc5d147 | 1608 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1609 | struct intel_ring_buffer *ring) |
673a394b EA |
1610 | { |
1611 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b962442e | 1612 | struct drm_i915_file_private *i915_file_priv = NULL; |
673a394b EA |
1613 | uint32_t seqno; |
1614 | int was_empty; | |
673a394b | 1615 | |
b962442e EA |
1616 | if (file_priv != NULL) |
1617 | i915_file_priv = file_priv->driver_priv; | |
1618 | ||
8dc5d147 CW |
1619 | if (request == NULL) { |
1620 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1621 | if (request == NULL) | |
1622 | return 0; | |
1623 | } | |
673a394b | 1624 | |
8a1a49f9 | 1625 | seqno = ring->add_request(dev, ring, file_priv, 0); |
673a394b EA |
1626 | |
1627 | request->seqno = seqno; | |
852835f3 | 1628 | request->ring = ring; |
673a394b | 1629 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1630 | was_empty = list_empty(&ring->request_list); |
1631 | list_add_tail(&request->list, &ring->request_list); | |
1632 | ||
b962442e EA |
1633 | if (i915_file_priv) { |
1634 | list_add_tail(&request->client_list, | |
1635 | &i915_file_priv->mm.request_list); | |
1636 | } else { | |
1637 | INIT_LIST_HEAD(&request->client_list); | |
1638 | } | |
673a394b | 1639 | |
f65d9421 | 1640 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1641 | mod_timer(&dev_priv->hangcheck_timer, |
1642 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1643 | if (was_empty) |
b3b079db CW |
1644 | queue_delayed_work(dev_priv->wq, |
1645 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1646 | } |
673a394b EA |
1647 | return seqno; |
1648 | } | |
1649 | ||
1650 | /** | |
1651 | * Command execution barrier | |
1652 | * | |
1653 | * Ensures that all commands in the ring are finished | |
1654 | * before signalling the CPU | |
1655 | */ | |
8a1a49f9 | 1656 | static void |
852835f3 | 1657 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1658 | { |
673a394b | 1659 | uint32_t flush_domains = 0; |
673a394b EA |
1660 | |
1661 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1662 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1663 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 ZN |
1664 | |
1665 | ring->flush(dev, ring, | |
1666 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1667 | } |
1668 | ||
673a394b EA |
1669 | /** |
1670 | * Returns true if seq1 is later than seq2. | |
1671 | */ | |
22be1724 | 1672 | bool |
673a394b EA |
1673 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1674 | { | |
1675 | return (int32_t)(seq1 - seq2) >= 0; | |
1676 | } | |
1677 | ||
1678 | uint32_t | |
852835f3 | 1679 | i915_get_gem_seqno(struct drm_device *dev, |
d1b851fc | 1680 | struct intel_ring_buffer *ring) |
673a394b | 1681 | { |
852835f3 | 1682 | return ring->get_gem_seqno(dev, ring); |
673a394b EA |
1683 | } |
1684 | ||
9375e446 CW |
1685 | void i915_gem_reset_flushing_list(struct drm_device *dev) |
1686 | { | |
1687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1688 | ||
1689 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1690 | struct drm_i915_gem_object *obj_priv; | |
1691 | ||
1692 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1693 | struct drm_i915_gem_object, | |
1694 | list); | |
1695 | ||
1696 | obj_priv->base.write_domain = 0; | |
1697 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1698 | } | |
1699 | } | |
1700 | ||
77f01230 CW |
1701 | void i915_gem_reset_inactive_gpu_domains(struct drm_device *dev) |
1702 | { | |
1703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1704 | struct drm_i915_gem_object *obj_priv; | |
1705 | ||
1706 | list_for_each_entry(obj_priv, | |
1707 | &dev_priv->mm.inactive_list, | |
1708 | list) | |
1709 | { | |
1710 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1711 | } | |
1712 | } | |
1713 | ||
673a394b EA |
1714 | /** |
1715 | * This function clears the request list as sequence numbers are passed. | |
1716 | */ | |
b09a1fec CW |
1717 | static void |
1718 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1719 | struct intel_ring_buffer *ring) | |
673a394b EA |
1720 | { |
1721 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1722 | uint32_t seqno; | |
b84d5f0c | 1723 | bool wedged; |
673a394b | 1724 | |
b84d5f0c CW |
1725 | if (!ring->status_page.page_addr || |
1726 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1727 | return; |
1728 | ||
852835f3 | 1729 | seqno = i915_get_gem_seqno(dev, ring); |
b84d5f0c | 1730 | wedged = atomic_read(&dev_priv->mm.wedged); |
673a394b | 1731 | |
852835f3 | 1732 | while (!list_empty(&ring->request_list)) { |
673a394b | 1733 | struct drm_i915_gem_request *request; |
673a394b | 1734 | |
852835f3 | 1735 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1736 | struct drm_i915_gem_request, |
1737 | list); | |
673a394b | 1738 | |
b84d5f0c CW |
1739 | if (!wedged && !i915_seqno_passed(seqno, request->seqno)) |
1740 | break; | |
1741 | ||
1742 | trace_i915_gem_request_retire(dev, request->seqno); | |
1743 | ||
1744 | list_del(&request->list); | |
1745 | list_del(&request->client_list); | |
1746 | kfree(request); | |
1747 | } | |
1748 | ||
1749 | /* Move any buffers on the active list that are no longer referenced | |
1750 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1751 | */ | |
1752 | while (!list_empty(&ring->active_list)) { | |
1753 | struct drm_gem_object *obj; | |
1754 | struct drm_i915_gem_object *obj_priv; | |
1755 | ||
1756 | obj_priv = list_first_entry(&ring->active_list, | |
1757 | struct drm_i915_gem_object, | |
1758 | list); | |
673a394b | 1759 | |
b84d5f0c CW |
1760 | if (!wedged && |
1761 | !i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) | |
673a394b | 1762 | break; |
b84d5f0c CW |
1763 | |
1764 | obj = &obj_priv->base; | |
1765 | ||
1766 | #if WATCH_LRU | |
1767 | DRM_INFO("%s: retire %d moves to inactive list %p\n", | |
1768 | __func__, request->seqno, obj); | |
1769 | #endif | |
1770 | ||
1771 | if (obj->write_domain != 0) | |
1772 | i915_gem_object_move_to_flushing(obj); | |
1773 | else | |
1774 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1775 | } |
9d34e5db CW |
1776 | |
1777 | if (unlikely (dev_priv->trace_irq_seqno && | |
1778 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 | 1779 | ring->user_irq_put(dev, ring); |
9d34e5db CW |
1780 | dev_priv->trace_irq_seqno = 0; |
1781 | } | |
673a394b EA |
1782 | } |
1783 | ||
b09a1fec CW |
1784 | void |
1785 | i915_gem_retire_requests(struct drm_device *dev) | |
1786 | { | |
1787 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1788 | ||
be72615b CW |
1789 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1790 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1791 | ||
1792 | /* We must be careful that during unbind() we do not | |
1793 | * accidentally infinitely recurse into retire requests. | |
1794 | * Currently: | |
1795 | * retire -> free -> unbind -> wait -> retire_ring | |
1796 | */ | |
1797 | list_for_each_entry_safe(obj_priv, tmp, | |
1798 | &dev_priv->mm.deferred_free_list, | |
1799 | list) | |
1800 | i915_gem_free_object_tail(&obj_priv->base); | |
1801 | } | |
1802 | ||
b09a1fec CW |
1803 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
1804 | if (HAS_BSD(dev)) | |
1805 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); | |
1806 | } | |
1807 | ||
75ef9da2 | 1808 | static void |
673a394b EA |
1809 | i915_gem_retire_work_handler(struct work_struct *work) |
1810 | { | |
1811 | drm_i915_private_t *dev_priv; | |
1812 | struct drm_device *dev; | |
1813 | ||
1814 | dev_priv = container_of(work, drm_i915_private_t, | |
1815 | mm.retire_work.work); | |
1816 | dev = dev_priv->dev; | |
1817 | ||
1818 | mutex_lock(&dev->struct_mutex); | |
b09a1fec | 1819 | i915_gem_retire_requests(dev); |
d1b851fc | 1820 | |
6dbe2772 | 1821 | if (!dev_priv->mm.suspended && |
d1b851fc ZN |
1822 | (!list_empty(&dev_priv->render_ring.request_list) || |
1823 | (HAS_BSD(dev) && | |
1824 | !list_empty(&dev_priv->bsd_ring.request_list)))) | |
9c9fe1f8 | 1825 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1826 | mutex_unlock(&dev->struct_mutex); |
1827 | } | |
1828 | ||
5a5a0c64 | 1829 | int |
852835f3 | 1830 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1831 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1832 | { |
1833 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1834 | u32 ier; |
673a394b EA |
1835 | int ret = 0; |
1836 | ||
1837 | BUG_ON(seqno == 0); | |
1838 | ||
e35a41de | 1839 | if (seqno == dev_priv->next_seqno) { |
8dc5d147 | 1840 | seqno = i915_add_request(dev, NULL, NULL, ring); |
e35a41de DV |
1841 | if (seqno == 0) |
1842 | return -ENOMEM; | |
1843 | } | |
1844 | ||
ba1234d1 | 1845 | if (atomic_read(&dev_priv->mm.wedged)) |
ffed1d09 BG |
1846 | return -EIO; |
1847 | ||
852835f3 | 1848 | if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) { |
bad720ff | 1849 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1850 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1851 | else | |
1852 | ier = I915_READ(IER); | |
802c7eb6 JB |
1853 | if (!ier) { |
1854 | DRM_ERROR("something (likely vbetool) disabled " | |
1855 | "interrupts, re-enabling\n"); | |
1856 | i915_driver_irq_preinstall(dev); | |
1857 | i915_driver_irq_postinstall(dev); | |
1858 | } | |
1859 | ||
1c5d22f7 CW |
1860 | trace_i915_gem_request_wait_begin(dev, seqno); |
1861 | ||
852835f3 | 1862 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 1863 | ring->user_irq_get(dev, ring); |
48764bf4 | 1864 | if (interruptible) |
852835f3 ZN |
1865 | ret = wait_event_interruptible(ring->irq_queue, |
1866 | i915_seqno_passed( | |
1867 | ring->get_gem_seqno(dev, ring), seqno) | |
1868 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1869 | else |
852835f3 ZN |
1870 | wait_event(ring->irq_queue, |
1871 | i915_seqno_passed( | |
1872 | ring->get_gem_seqno(dev, ring), seqno) | |
1873 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1874 | |
8187a2b7 | 1875 | ring->user_irq_put(dev, ring); |
852835f3 | 1876 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
1877 | |
1878 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 1879 | } |
ba1234d1 | 1880 | if (atomic_read(&dev_priv->mm.wedged)) |
673a394b EA |
1881 | ret = -EIO; |
1882 | ||
1883 | if (ret && ret != -ERESTARTSYS) | |
8bff917c DV |
1884 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
1885 | __func__, ret, seqno, ring->get_gem_seqno(dev, ring), | |
1886 | dev_priv->next_seqno); | |
673a394b EA |
1887 | |
1888 | /* Directly dispatch request retiring. While we have the work queue | |
1889 | * to handle this, the waiter on a request often wants an associated | |
1890 | * buffer to have made it to the inactive list, and we would need | |
1891 | * a separate wait queue to handle that. | |
1892 | */ | |
1893 | if (ret == 0) | |
b09a1fec | 1894 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
1895 | |
1896 | return ret; | |
1897 | } | |
1898 | ||
48764bf4 DV |
1899 | /** |
1900 | * Waits for a sequence number to be signaled, and cleans up the | |
1901 | * request and object lists appropriately for that event. | |
1902 | */ | |
1903 | static int | |
852835f3 ZN |
1904 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
1905 | struct intel_ring_buffer *ring) | |
48764bf4 | 1906 | { |
852835f3 | 1907 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
1908 | } |
1909 | ||
c7f9f9a8 | 1910 | void |
9220434a | 1911 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 1912 | struct drm_file *file_priv, |
9220434a CW |
1913 | struct intel_ring_buffer *ring, |
1914 | uint32_t invalidate_domains, | |
1915 | uint32_t flush_domains) | |
1916 | { | |
1917 | ring->flush(dev, ring, invalidate_domains, flush_domains); | |
1918 | i915_gem_process_flushing_list(dev, flush_domains, ring); | |
c78ec30b CW |
1919 | |
1920 | if (ring->outstanding_lazy_request) { | |
1921 | (void)i915_add_request(dev, file_priv, NULL, ring); | |
1922 | ring->outstanding_lazy_request = false; | |
1923 | } | |
9220434a CW |
1924 | } |
1925 | ||
8187a2b7 ZN |
1926 | static void |
1927 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 1928 | struct drm_file *file_priv, |
8187a2b7 | 1929 | uint32_t invalidate_domains, |
9220434a CW |
1930 | uint32_t flush_domains, |
1931 | uint32_t flush_rings) | |
8187a2b7 ZN |
1932 | { |
1933 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 1934 | |
8187a2b7 ZN |
1935 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
1936 | drm_agp_chipset_flush(dev); | |
8bff917c | 1937 | |
9220434a CW |
1938 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
1939 | if (flush_rings & RING_RENDER) | |
c78ec30b | 1940 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
1941 | &dev_priv->render_ring, |
1942 | invalidate_domains, flush_domains); | |
1943 | if (flush_rings & RING_BSD) | |
c78ec30b | 1944 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
1945 | &dev_priv->bsd_ring, |
1946 | invalidate_domains, flush_domains); | |
1947 | } | |
8187a2b7 ZN |
1948 | } |
1949 | ||
673a394b EA |
1950 | /** |
1951 | * Ensures that all rendering to the object has completed and the object is | |
1952 | * safe to unbind from the GTT or access from the CPU. | |
1953 | */ | |
1954 | static int | |
2cf34d7b CW |
1955 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
1956 | bool interruptible) | |
673a394b EA |
1957 | { |
1958 | struct drm_device *dev = obj->dev; | |
23010e43 | 1959 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1960 | int ret; |
1961 | ||
e47c68e9 EA |
1962 | /* This function only exists to support waiting for existing rendering, |
1963 | * not for emitting required flushes. | |
673a394b | 1964 | */ |
e47c68e9 | 1965 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1966 | |
1967 | /* If there is rendering queued on the buffer being evicted, wait for | |
1968 | * it. | |
1969 | */ | |
1970 | if (obj_priv->active) { | |
1971 | #if WATCH_BUF | |
1972 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
1973 | __func__, obj, obj_priv->last_rendering_seqno); | |
1974 | #endif | |
2cf34d7b CW |
1975 | ret = i915_do_wait_request(dev, |
1976 | obj_priv->last_rendering_seqno, | |
1977 | interruptible, | |
1978 | obj_priv->ring); | |
1979 | if (ret) | |
673a394b EA |
1980 | return ret; |
1981 | } | |
1982 | ||
1983 | return 0; | |
1984 | } | |
1985 | ||
1986 | /** | |
1987 | * Unbinds an object from the GTT aperture. | |
1988 | */ | |
0f973f27 | 1989 | int |
673a394b EA |
1990 | i915_gem_object_unbind(struct drm_gem_object *obj) |
1991 | { | |
1992 | struct drm_device *dev = obj->dev; | |
23010e43 | 1993 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1994 | int ret = 0; |
1995 | ||
1996 | #if WATCH_BUF | |
1997 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); | |
1998 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); | |
1999 | #endif | |
2000 | if (obj_priv->gtt_space == NULL) | |
2001 | return 0; | |
2002 | ||
2003 | if (obj_priv->pin_count != 0) { | |
2004 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2005 | return -EINVAL; | |
2006 | } | |
2007 | ||
5323fd04 EA |
2008 | /* blow away mappings if mapped through GTT */ |
2009 | i915_gem_release_mmap(obj); | |
2010 | ||
673a394b EA |
2011 | /* Move the object to the CPU domain to ensure that |
2012 | * any possible CPU writes while it's not in the GTT | |
2013 | * are flushed when we go to remap it. This will | |
2014 | * also ensure that all pending GPU writes are finished | |
2015 | * before we unbind. | |
2016 | */ | |
e47c68e9 | 2017 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2018 | if (ret == -ERESTARTSYS) |
673a394b | 2019 | return ret; |
8dc1775d CW |
2020 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2021 | * should be safe and we need to cleanup or else we might | |
2022 | * cause memory corruption through use-after-free. | |
2023 | */ | |
673a394b | 2024 | |
96b47b65 DV |
2025 | /* release the fence reg _after_ flushing */ |
2026 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2027 | i915_gem_clear_fence_reg(obj); | |
2028 | ||
673a394b EA |
2029 | if (obj_priv->agp_mem != NULL) { |
2030 | drm_unbind_agp(obj_priv->agp_mem); | |
2031 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
2032 | obj_priv->agp_mem = NULL; | |
2033 | } | |
2034 | ||
856fa198 | 2035 | i915_gem_object_put_pages(obj); |
a32808c0 | 2036 | BUG_ON(obj_priv->pages_refcount); |
673a394b EA |
2037 | |
2038 | if (obj_priv->gtt_space) { | |
2039 | atomic_dec(&dev->gtt_count); | |
2040 | atomic_sub(obj->size, &dev->gtt_memory); | |
2041 | ||
2042 | drm_mm_put_block(obj_priv->gtt_space); | |
2043 | obj_priv->gtt_space = NULL; | |
2044 | } | |
2045 | ||
f13d3f73 | 2046 | list_del_init(&obj_priv->list); |
673a394b | 2047 | |
963b4836 CW |
2048 | if (i915_gem_object_is_purgeable(obj_priv)) |
2049 | i915_gem_object_truncate(obj); | |
2050 | ||
1c5d22f7 CW |
2051 | trace_i915_gem_object_unbind(obj); |
2052 | ||
8dc1775d | 2053 | return ret; |
673a394b EA |
2054 | } |
2055 | ||
b47eb4a2 | 2056 | int |
4df2faf4 DV |
2057 | i915_gpu_idle(struct drm_device *dev) |
2058 | { | |
2059 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2060 | bool lists_empty; | |
c78ec30b | 2061 | u32 seqno; |
852835f3 | 2062 | int ret; |
4df2faf4 | 2063 | |
d1b851fc ZN |
2064 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2065 | list_empty(&dev_priv->render_ring.active_list) && | |
2066 | (!HAS_BSD(dev) || | |
2067 | list_empty(&dev_priv->bsd_ring.active_list))); | |
4df2faf4 DV |
2068 | if (lists_empty) |
2069 | return 0; | |
2070 | ||
2071 | /* Flush everything onto the inactive list. */ | |
c78ec30b CW |
2072 | seqno = i915_gem_next_request_seqno(dev, &dev_priv->render_ring); |
2073 | i915_gem_flush_ring(dev, NULL, &dev_priv->render_ring, | |
9220434a | 2074 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
c78ec30b | 2075 | ret = i915_wait_request(dev, seqno, &dev_priv->render_ring); |
8a1a49f9 DV |
2076 | if (ret) |
2077 | return ret; | |
d1b851fc ZN |
2078 | |
2079 | if (HAS_BSD(dev)) { | |
c78ec30b CW |
2080 | seqno = i915_gem_next_request_seqno(dev, &dev_priv->render_ring); |
2081 | i915_gem_flush_ring(dev, NULL, &dev_priv->bsd_ring, | |
9220434a | 2082 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
c78ec30b | 2083 | ret = i915_wait_request(dev, seqno, &dev_priv->bsd_ring); |
d1b851fc ZN |
2084 | if (ret) |
2085 | return ret; | |
2086 | } | |
2087 | ||
8a1a49f9 | 2088 | return 0; |
4df2faf4 DV |
2089 | } |
2090 | ||
6911a9b8 | 2091 | int |
4bdadb97 CW |
2092 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2093 | gfp_t gfpmask) | |
673a394b | 2094 | { |
23010e43 | 2095 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2096 | int page_count, i; |
2097 | struct address_space *mapping; | |
2098 | struct inode *inode; | |
2099 | struct page *page; | |
673a394b | 2100 | |
778c3544 DV |
2101 | BUG_ON(obj_priv->pages_refcount |
2102 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2103 | ||
856fa198 | 2104 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2105 | return 0; |
2106 | ||
2107 | /* Get the list of pages out of our struct file. They'll be pinned | |
2108 | * at this point until we release them. | |
2109 | */ | |
2110 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2111 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2112 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2113 | if (obj_priv->pages == NULL) { |
856fa198 | 2114 | obj_priv->pages_refcount--; |
673a394b EA |
2115 | return -ENOMEM; |
2116 | } | |
2117 | ||
2118 | inode = obj->filp->f_path.dentry->d_inode; | |
2119 | mapping = inode->i_mapping; | |
2120 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2121 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2122 | GFP_HIGHUSER | |
4bdadb97 | 2123 | __GFP_COLD | |
cd9f040d | 2124 | __GFP_RECLAIMABLE | |
4bdadb97 | 2125 | gfpmask); |
1f2b1013 CW |
2126 | if (IS_ERR(page)) |
2127 | goto err_pages; | |
2128 | ||
856fa198 | 2129 | obj_priv->pages[i] = page; |
673a394b | 2130 | } |
280b713b EA |
2131 | |
2132 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2133 | i915_gem_object_do_bit_17_swizzle(obj); | |
2134 | ||
673a394b | 2135 | return 0; |
1f2b1013 CW |
2136 | |
2137 | err_pages: | |
2138 | while (i--) | |
2139 | page_cache_release(obj_priv->pages[i]); | |
2140 | ||
2141 | drm_free_large(obj_priv->pages); | |
2142 | obj_priv->pages = NULL; | |
2143 | obj_priv->pages_refcount--; | |
2144 | return PTR_ERR(page); | |
673a394b EA |
2145 | } |
2146 | ||
4e901fdc EA |
2147 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2148 | { | |
2149 | struct drm_gem_object *obj = reg->obj; | |
2150 | struct drm_device *dev = obj->dev; | |
2151 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2152 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2153 | int regnum = obj_priv->fence_reg; |
2154 | uint64_t val; | |
2155 | ||
2156 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2157 | 0xfffff000) << 32; | |
2158 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2159 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2160 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2161 | ||
2162 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2163 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2164 | val |= I965_FENCE_REG_VALID; | |
2165 | ||
2166 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2167 | } | |
2168 | ||
de151cf6 JB |
2169 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2170 | { | |
2171 | struct drm_gem_object *obj = reg->obj; | |
2172 | struct drm_device *dev = obj->dev; | |
2173 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2174 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2175 | int regnum = obj_priv->fence_reg; |
2176 | uint64_t val; | |
2177 | ||
2178 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2179 | 0xfffff000) << 32; | |
2180 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2181 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2182 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2183 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2184 | val |= I965_FENCE_REG_VALID; | |
2185 | ||
2186 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2187 | } | |
2188 | ||
2189 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2190 | { | |
2191 | struct drm_gem_object *obj = reg->obj; | |
2192 | struct drm_device *dev = obj->dev; | |
2193 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2194 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2195 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2196 | int tile_width; |
dc529a4f | 2197 | uint32_t fence_reg, val; |
de151cf6 JB |
2198 | uint32_t pitch_val; |
2199 | ||
2200 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2201 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2202 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2203 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2204 | return; |
2205 | } | |
2206 | ||
0f973f27 JB |
2207 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2208 | HAS_128_BYTE_Y_TILING(dev)) | |
2209 | tile_width = 128; | |
de151cf6 | 2210 | else |
0f973f27 JB |
2211 | tile_width = 512; |
2212 | ||
2213 | /* Note: pitch better be a power of two tile widths */ | |
2214 | pitch_val = obj_priv->stride / tile_width; | |
2215 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2216 | |
c36a2a6d DV |
2217 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2218 | HAS_128_BYTE_Y_TILING(dev)) | |
2219 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2220 | else | |
2221 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2222 | ||
de151cf6 JB |
2223 | val = obj_priv->gtt_offset; |
2224 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2225 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2226 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2227 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2228 | val |= I830_FENCE_REG_VALID; | |
2229 | ||
dc529a4f EA |
2230 | if (regnum < 8) |
2231 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2232 | else | |
2233 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2234 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2235 | } |
2236 | ||
2237 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2238 | { | |
2239 | struct drm_gem_object *obj = reg->obj; | |
2240 | struct drm_device *dev = obj->dev; | |
2241 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2242 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2243 | int regnum = obj_priv->fence_reg; |
2244 | uint32_t val; | |
2245 | uint32_t pitch_val; | |
8d7773a3 | 2246 | uint32_t fence_size_bits; |
de151cf6 | 2247 | |
8d7773a3 | 2248 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2249 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2250 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2251 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2252 | return; |
2253 | } | |
2254 | ||
e76a16de EA |
2255 | pitch_val = obj_priv->stride / 128; |
2256 | pitch_val = ffs(pitch_val) - 1; | |
2257 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2258 | ||
de151cf6 JB |
2259 | val = obj_priv->gtt_offset; |
2260 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2261 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2262 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2263 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2264 | val |= fence_size_bits; | |
de151cf6 JB |
2265 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2266 | val |= I830_FENCE_REG_VALID; | |
2267 | ||
2268 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2269 | } |
2270 | ||
2cf34d7b CW |
2271 | static int i915_find_fence_reg(struct drm_device *dev, |
2272 | bool interruptible) | |
ae3db24a DV |
2273 | { |
2274 | struct drm_i915_fence_reg *reg = NULL; | |
2275 | struct drm_i915_gem_object *obj_priv = NULL; | |
2276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2277 | struct drm_gem_object *obj = NULL; | |
2278 | int i, avail, ret; | |
2279 | ||
2280 | /* First try to find a free reg */ | |
2281 | avail = 0; | |
2282 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2283 | reg = &dev_priv->fence_regs[i]; | |
2284 | if (!reg->obj) | |
2285 | return i; | |
2286 | ||
23010e43 | 2287 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2288 | if (!obj_priv->pin_count) |
2289 | avail++; | |
2290 | } | |
2291 | ||
2292 | if (avail == 0) | |
2293 | return -ENOSPC; | |
2294 | ||
2295 | /* None available, try to steal one or wait for a user to finish */ | |
2296 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2297 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2298 | lru_list) { | |
2299 | obj = reg->obj; | |
2300 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2301 | |
2302 | if (obj_priv->pin_count) | |
2303 | continue; | |
2304 | ||
2305 | /* found one! */ | |
2306 | i = obj_priv->fence_reg; | |
2307 | break; | |
2308 | } | |
2309 | ||
2310 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2311 | ||
2312 | /* We only have a reference on obj from the active list. put_fence_reg | |
2313 | * might drop that one, causing a use-after-free in it. So hold a | |
2314 | * private reference to obj like the other callers of put_fence_reg | |
2315 | * (set_tiling ioctl) do. */ | |
2316 | drm_gem_object_reference(obj); | |
2cf34d7b | 2317 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2318 | drm_gem_object_unreference(obj); |
2319 | if (ret != 0) | |
2320 | return ret; | |
2321 | ||
2322 | return i; | |
2323 | } | |
2324 | ||
de151cf6 JB |
2325 | /** |
2326 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2327 | * @obj: object to map through a fence reg | |
2328 | * | |
2329 | * When mapping objects through the GTT, userspace wants to be able to write | |
2330 | * to them without having to worry about swizzling if the object is tiled. | |
2331 | * | |
2332 | * This function walks the fence regs looking for a free one for @obj, | |
2333 | * stealing one if it can't find any. | |
2334 | * | |
2335 | * It then sets up the reg based on the object's properties: address, pitch | |
2336 | * and tiling format. | |
2337 | */ | |
8c4b8c3f | 2338 | int |
2cf34d7b CW |
2339 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2340 | bool interruptible) | |
de151cf6 JB |
2341 | { |
2342 | struct drm_device *dev = obj->dev; | |
79e53945 | 2343 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2344 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2345 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2346 | int ret; |
de151cf6 | 2347 | |
a09ba7fa EA |
2348 | /* Just update our place in the LRU if our fence is getting used. */ |
2349 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2350 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2351 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2352 | return 0; |
2353 | } | |
2354 | ||
de151cf6 JB |
2355 | switch (obj_priv->tiling_mode) { |
2356 | case I915_TILING_NONE: | |
2357 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2358 | break; | |
2359 | case I915_TILING_X: | |
0f973f27 JB |
2360 | if (!obj_priv->stride) |
2361 | return -EINVAL; | |
2362 | WARN((obj_priv->stride & (512 - 1)), | |
2363 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2364 | obj_priv->gtt_offset); | |
de151cf6 JB |
2365 | break; |
2366 | case I915_TILING_Y: | |
0f973f27 JB |
2367 | if (!obj_priv->stride) |
2368 | return -EINVAL; | |
2369 | WARN((obj_priv->stride & (128 - 1)), | |
2370 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2371 | obj_priv->gtt_offset); | |
de151cf6 JB |
2372 | break; |
2373 | } | |
2374 | ||
2cf34d7b | 2375 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2376 | if (ret < 0) |
2377 | return ret; | |
de151cf6 | 2378 | |
ae3db24a DV |
2379 | obj_priv->fence_reg = ret; |
2380 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2381 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2382 | |
de151cf6 JB |
2383 | reg->obj = obj; |
2384 | ||
e259befd CW |
2385 | switch (INTEL_INFO(dev)->gen) { |
2386 | case 6: | |
4e901fdc | 2387 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2388 | break; |
2389 | case 5: | |
2390 | case 4: | |
de151cf6 | 2391 | i965_write_fence_reg(reg); |
e259befd CW |
2392 | break; |
2393 | case 3: | |
de151cf6 | 2394 | i915_write_fence_reg(reg); |
e259befd CW |
2395 | break; |
2396 | case 2: | |
de151cf6 | 2397 | i830_write_fence_reg(reg); |
e259befd CW |
2398 | break; |
2399 | } | |
d9ddcb96 | 2400 | |
ae3db24a DV |
2401 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2402 | obj_priv->tiling_mode); | |
1c5d22f7 | 2403 | |
d9ddcb96 | 2404 | return 0; |
de151cf6 JB |
2405 | } |
2406 | ||
2407 | /** | |
2408 | * i915_gem_clear_fence_reg - clear out fence register info | |
2409 | * @obj: object to clear | |
2410 | * | |
2411 | * Zeroes out the fence register itself and clears out the associated | |
2412 | * data structures in dev_priv and obj_priv. | |
2413 | */ | |
2414 | static void | |
2415 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2416 | { | |
2417 | struct drm_device *dev = obj->dev; | |
79e53945 | 2418 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2419 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2420 | struct drm_i915_fence_reg *reg = |
2421 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2422 | uint32_t fence_reg; |
de151cf6 | 2423 | |
e259befd CW |
2424 | switch (INTEL_INFO(dev)->gen) { |
2425 | case 6: | |
4e901fdc EA |
2426 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2427 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2428 | break; |
2429 | case 5: | |
2430 | case 4: | |
de151cf6 | 2431 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2432 | break; |
2433 | case 3: | |
2434 | if (obj_priv->fence_reg > 8) | |
2435 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; | |
dc529a4f | 2436 | else |
e259befd CW |
2437 | case 2: |
2438 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2439 | |
2440 | I915_WRITE(fence_reg, 0); | |
e259befd | 2441 | break; |
dc529a4f | 2442 | } |
de151cf6 | 2443 | |
007cc8ac | 2444 | reg->obj = NULL; |
de151cf6 | 2445 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2446 | list_del_init(®->lru_list); |
de151cf6 JB |
2447 | } |
2448 | ||
52dc7d32 CW |
2449 | /** |
2450 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2451 | * to the buffer to finish, and then resets the fence register. | |
2452 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2453 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2454 | * |
2455 | * Zeroes out the fence register itself and clears out the associated | |
2456 | * data structures in dev_priv and obj_priv. | |
2457 | */ | |
2458 | int | |
2cf34d7b CW |
2459 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2460 | bool interruptible) | |
52dc7d32 CW |
2461 | { |
2462 | struct drm_device *dev = obj->dev; | |
53640e1d | 2463 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2464 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2465 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2466 | |
2467 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2468 | return 0; | |
2469 | ||
10ae9bd2 DV |
2470 | /* If we've changed tiling, GTT-mappings of the object |
2471 | * need to re-fault to ensure that the correct fence register | |
2472 | * setup is in place. | |
2473 | */ | |
2474 | i915_gem_release_mmap(obj); | |
2475 | ||
52dc7d32 CW |
2476 | /* On the i915, GPU access to tiled buffers is via a fence, |
2477 | * therefore we must wait for any outstanding access to complete | |
2478 | * before clearing the fence. | |
2479 | */ | |
53640e1d CW |
2480 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2481 | if (reg->gpu) { | |
52dc7d32 CW |
2482 | int ret; |
2483 | ||
2cf34d7b | 2484 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad CW |
2485 | if (ret) |
2486 | return ret; | |
2487 | ||
2cf34d7b | 2488 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2489 | if (ret) |
52dc7d32 | 2490 | return ret; |
53640e1d CW |
2491 | |
2492 | reg->gpu = false; | |
52dc7d32 CW |
2493 | } |
2494 | ||
4a726612 | 2495 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2496 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2497 | |
2498 | return 0; | |
2499 | } | |
2500 | ||
673a394b EA |
2501 | /** |
2502 | * Finds free space in the GTT aperture and binds the object there. | |
2503 | */ | |
2504 | static int | |
2505 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2506 | { | |
2507 | struct drm_device *dev = obj->dev; | |
2508 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2509 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2510 | struct drm_mm_node *free_space; |
4bdadb97 | 2511 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2512 | int ret; |
673a394b | 2513 | |
bb6baf76 | 2514 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2515 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2516 | return -EINVAL; | |
2517 | } | |
2518 | ||
673a394b | 2519 | if (alignment == 0) |
0f973f27 | 2520 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2521 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2522 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2523 | return -EINVAL; | |
2524 | } | |
2525 | ||
654fc607 CW |
2526 | /* If the object is bigger than the entire aperture, reject it early |
2527 | * before evicting everything in a vain attempt to find space. | |
2528 | */ | |
2529 | if (obj->size > dev->gtt_total) { | |
2530 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); | |
2531 | return -E2BIG; | |
2532 | } | |
2533 | ||
673a394b EA |
2534 | search_free: |
2535 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2536 | obj->size, alignment, 0); | |
2537 | if (free_space != NULL) { | |
2538 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2539 | alignment); | |
db3307a9 | 2540 | if (obj_priv->gtt_space != NULL) |
673a394b | 2541 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
673a394b EA |
2542 | } |
2543 | if (obj_priv->gtt_space == NULL) { | |
2544 | /* If the gtt is empty and we're still having trouble | |
2545 | * fitting our object in, we're out of memory. | |
2546 | */ | |
2547 | #if WATCH_LRU | |
2548 | DRM_INFO("%s: GTT full, evicting something\n", __func__); | |
2549 | #endif | |
0108a3ed | 2550 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2551 | if (ret) |
673a394b | 2552 | return ret; |
9731129c | 2553 | |
673a394b EA |
2554 | goto search_free; |
2555 | } | |
2556 | ||
2557 | #if WATCH_BUF | |
cfd43c02 | 2558 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
673a394b EA |
2559 | obj->size, obj_priv->gtt_offset); |
2560 | #endif | |
4bdadb97 | 2561 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2562 | if (ret) { |
2563 | drm_mm_put_block(obj_priv->gtt_space); | |
2564 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2565 | |
2566 | if (ret == -ENOMEM) { | |
2567 | /* first try to clear up some space from the GTT */ | |
0108a3ed DV |
2568 | ret = i915_gem_evict_something(dev, obj->size, |
2569 | alignment); | |
07f73f69 | 2570 | if (ret) { |
07f73f69 | 2571 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2572 | if (gfpmask) { |
2573 | gfpmask = 0; | |
2574 | goto search_free; | |
07f73f69 CW |
2575 | } |
2576 | ||
2577 | return ret; | |
2578 | } | |
2579 | ||
2580 | goto search_free; | |
2581 | } | |
2582 | ||
673a394b EA |
2583 | return ret; |
2584 | } | |
2585 | ||
673a394b EA |
2586 | /* Create an AGP memory structure pointing at our pages, and bind it |
2587 | * into the GTT. | |
2588 | */ | |
2589 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2590 | obj_priv->pages, |
07f73f69 | 2591 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2592 | obj_priv->gtt_offset, |
2593 | obj_priv->agp_type); | |
673a394b | 2594 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2595 | i915_gem_object_put_pages(obj); |
673a394b EA |
2596 | drm_mm_put_block(obj_priv->gtt_space); |
2597 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2598 | |
0108a3ed | 2599 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2600 | if (ret) |
07f73f69 | 2601 | return ret; |
07f73f69 CW |
2602 | |
2603 | goto search_free; | |
673a394b EA |
2604 | } |
2605 | atomic_inc(&dev->gtt_count); | |
2606 | atomic_add(obj->size, &dev->gtt_memory); | |
2607 | ||
bf1a1092 CW |
2608 | /* keep track of bounds object by adding it to the inactive list */ |
2609 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
2610 | ||
673a394b EA |
2611 | /* Assert that the object is not currently in any GPU domain. As it |
2612 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2613 | * a GPU cache | |
2614 | */ | |
21d509e3 CW |
2615 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2616 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2617 | |
1c5d22f7 CW |
2618 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2619 | ||
673a394b EA |
2620 | return 0; |
2621 | } | |
2622 | ||
2623 | void | |
2624 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2625 | { | |
23010e43 | 2626 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2627 | |
2628 | /* If we don't have a page list set up, then we're not pinned | |
2629 | * to GPU, and we can ignore the cache flush because it'll happen | |
2630 | * again at bind time. | |
2631 | */ | |
856fa198 | 2632 | if (obj_priv->pages == NULL) |
673a394b EA |
2633 | return; |
2634 | ||
1c5d22f7 | 2635 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2636 | |
856fa198 | 2637 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2638 | } |
2639 | ||
e47c68e9 | 2640 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2641 | static int |
ba3d8d74 DV |
2642 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2643 | bool pipelined) | |
e47c68e9 EA |
2644 | { |
2645 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2646 | uint32_t old_write_domain; |
e47c68e9 EA |
2647 | |
2648 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2649 | return 0; |
e47c68e9 EA |
2650 | |
2651 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2652 | old_write_domain = obj->write_domain; |
c78ec30b | 2653 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2654 | to_intel_bo(obj)->ring, |
2655 | 0, obj->write_domain); | |
48b956c5 | 2656 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2657 | |
2658 | trace_i915_gem_object_change_domain(obj, | |
2659 | obj->read_domains, | |
2660 | old_write_domain); | |
ba3d8d74 DV |
2661 | |
2662 | if (pipelined) | |
2663 | return 0; | |
2664 | ||
2cf34d7b | 2665 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2666 | } |
2667 | ||
2668 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2669 | static void | |
2670 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2671 | { | |
1c5d22f7 CW |
2672 | uint32_t old_write_domain; |
2673 | ||
e47c68e9 EA |
2674 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2675 | return; | |
2676 | ||
2677 | /* No actual flushing is required for the GTT write domain. Writes | |
2678 | * to it immediately go to main memory as far as we know, so there's | |
2679 | * no chipset flush. It also doesn't land in render cache. | |
2680 | */ | |
1c5d22f7 | 2681 | old_write_domain = obj->write_domain; |
e47c68e9 | 2682 | obj->write_domain = 0; |
1c5d22f7 CW |
2683 | |
2684 | trace_i915_gem_object_change_domain(obj, | |
2685 | obj->read_domains, | |
2686 | old_write_domain); | |
e47c68e9 EA |
2687 | } |
2688 | ||
2689 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2690 | static void | |
2691 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2692 | { | |
2693 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2694 | uint32_t old_write_domain; |
e47c68e9 EA |
2695 | |
2696 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2697 | return; | |
2698 | ||
2699 | i915_gem_clflush_object(obj); | |
2700 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2701 | old_write_domain = obj->write_domain; |
e47c68e9 | 2702 | obj->write_domain = 0; |
1c5d22f7 CW |
2703 | |
2704 | trace_i915_gem_object_change_domain(obj, | |
2705 | obj->read_domains, | |
2706 | old_write_domain); | |
e47c68e9 EA |
2707 | } |
2708 | ||
2ef7eeaa EA |
2709 | /** |
2710 | * Moves a single object to the GTT read, and possibly write domain. | |
2711 | * | |
2712 | * This function returns when the move is complete, including waiting on | |
2713 | * flushes to occur. | |
2714 | */ | |
79e53945 | 2715 | int |
2ef7eeaa EA |
2716 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2717 | { | |
23010e43 | 2718 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2719 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2720 | int ret; |
2ef7eeaa | 2721 | |
02354392 EA |
2722 | /* Not valid to be called on unbound objects. */ |
2723 | if (obj_priv->gtt_space == NULL) | |
2724 | return -EINVAL; | |
2725 | ||
ba3d8d74 | 2726 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2727 | if (ret != 0) |
2728 | return ret; | |
2729 | ||
7213342d | 2730 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2731 | |
ba3d8d74 | 2732 | if (write) { |
2cf34d7b | 2733 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2734 | if (ret) |
2735 | return ret; | |
ba3d8d74 | 2736 | } |
2ef7eeaa | 2737 | |
7213342d CW |
2738 | old_write_domain = obj->write_domain; |
2739 | old_read_domains = obj->read_domains; | |
2ef7eeaa | 2740 | |
e47c68e9 EA |
2741 | /* It should now be out of any other write domains, and we can update |
2742 | * the domain values for our changes. | |
2743 | */ | |
2744 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2745 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2746 | if (write) { | |
7213342d | 2747 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2748 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2749 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2750 | } |
2751 | ||
1c5d22f7 CW |
2752 | trace_i915_gem_object_change_domain(obj, |
2753 | old_read_domains, | |
2754 | old_write_domain); | |
2755 | ||
e47c68e9 EA |
2756 | return 0; |
2757 | } | |
2758 | ||
b9241ea3 ZW |
2759 | /* |
2760 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2761 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2762 | */ | |
2763 | int | |
48b956c5 CW |
2764 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2765 | bool pipelined) | |
b9241ea3 | 2766 | { |
23010e43 | 2767 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2768 | uint32_t old_read_domains; |
b9241ea3 ZW |
2769 | int ret; |
2770 | ||
2771 | /* Not valid to be called on unbound objects. */ | |
2772 | if (obj_priv->gtt_space == NULL) | |
2773 | return -EINVAL; | |
2774 | ||
48b956c5 CW |
2775 | ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined); |
2776 | if (ret) | |
e35a41de | 2777 | return ret; |
b9241ea3 | 2778 | |
b118c1e3 CW |
2779 | i915_gem_object_flush_cpu_write_domain(obj); |
2780 | ||
b9241ea3 | 2781 | old_read_domains = obj->read_domains; |
c78ec30b | 2782 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2783 | |
2784 | trace_i915_gem_object_change_domain(obj, | |
2785 | old_read_domains, | |
ba3d8d74 | 2786 | obj->write_domain); |
b9241ea3 ZW |
2787 | |
2788 | return 0; | |
2789 | } | |
2790 | ||
e47c68e9 EA |
2791 | /** |
2792 | * Moves a single object to the CPU read, and possibly write domain. | |
2793 | * | |
2794 | * This function returns when the move is complete, including waiting on | |
2795 | * flushes to occur. | |
2796 | */ | |
2797 | static int | |
2798 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2799 | { | |
1c5d22f7 | 2800 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2801 | int ret; |
2802 | ||
ba3d8d74 | 2803 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2804 | if (ret != 0) |
2805 | return ret; | |
2ef7eeaa | 2806 | |
e47c68e9 | 2807 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2808 | |
e47c68e9 EA |
2809 | /* If we have a partially-valid cache of the object in the CPU, |
2810 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2811 | */ |
e47c68e9 | 2812 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2813 | |
7213342d | 2814 | if (write) { |
2cf34d7b | 2815 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
2816 | if (ret) |
2817 | return ret; | |
2818 | } | |
2819 | ||
1c5d22f7 CW |
2820 | old_write_domain = obj->write_domain; |
2821 | old_read_domains = obj->read_domains; | |
2822 | ||
e47c68e9 EA |
2823 | /* Flush the CPU cache if it's still invalid. */ |
2824 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2825 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2826 | |
e47c68e9 | 2827 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2828 | } |
2829 | ||
2830 | /* It should now be out of any other write domains, and we can update | |
2831 | * the domain values for our changes. | |
2832 | */ | |
e47c68e9 EA |
2833 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2834 | ||
2835 | /* If we're writing through the CPU, then the GPU read domains will | |
2836 | * need to be invalidated at next use. | |
2837 | */ | |
2838 | if (write) { | |
c78ec30b | 2839 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
2840 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
2841 | } | |
2ef7eeaa | 2842 | |
1c5d22f7 CW |
2843 | trace_i915_gem_object_change_domain(obj, |
2844 | old_read_domains, | |
2845 | old_write_domain); | |
2846 | ||
2ef7eeaa EA |
2847 | return 0; |
2848 | } | |
2849 | ||
673a394b EA |
2850 | /* |
2851 | * Set the next domain for the specified object. This | |
2852 | * may not actually perform the necessary flushing/invaliding though, | |
2853 | * as that may want to be batched with other set_domain operations | |
2854 | * | |
2855 | * This is (we hope) the only really tricky part of gem. The goal | |
2856 | * is fairly simple -- track which caches hold bits of the object | |
2857 | * and make sure they remain coherent. A few concrete examples may | |
2858 | * help to explain how it works. For shorthand, we use the notation | |
2859 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2860 | * a pair of read and write domain masks. | |
2861 | * | |
2862 | * Case 1: the batch buffer | |
2863 | * | |
2864 | * 1. Allocated | |
2865 | * 2. Written by CPU | |
2866 | * 3. Mapped to GTT | |
2867 | * 4. Read by GPU | |
2868 | * 5. Unmapped from GTT | |
2869 | * 6. Freed | |
2870 | * | |
2871 | * Let's take these a step at a time | |
2872 | * | |
2873 | * 1. Allocated | |
2874 | * Pages allocated from the kernel may still have | |
2875 | * cache contents, so we set them to (CPU, CPU) always. | |
2876 | * 2. Written by CPU (using pwrite) | |
2877 | * The pwrite function calls set_domain (CPU, CPU) and | |
2878 | * this function does nothing (as nothing changes) | |
2879 | * 3. Mapped by GTT | |
2880 | * This function asserts that the object is not | |
2881 | * currently in any GPU-based read or write domains | |
2882 | * 4. Read by GPU | |
2883 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
2884 | * As write_domain is zero, this function adds in the | |
2885 | * current read domains (CPU+COMMAND, 0). | |
2886 | * flush_domains is set to CPU. | |
2887 | * invalidate_domains is set to COMMAND | |
2888 | * clflush is run to get data out of the CPU caches | |
2889 | * then i915_dev_set_domain calls i915_gem_flush to | |
2890 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
2891 | * 5. Unmapped from GTT | |
2892 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
2893 | * flush_domains and invalidate_domains end up both zero | |
2894 | * so no flushing/invalidating happens | |
2895 | * 6. Freed | |
2896 | * yay, done | |
2897 | * | |
2898 | * Case 2: The shared render buffer | |
2899 | * | |
2900 | * 1. Allocated | |
2901 | * 2. Mapped to GTT | |
2902 | * 3. Read/written by GPU | |
2903 | * 4. set_domain to (CPU,CPU) | |
2904 | * 5. Read/written by CPU | |
2905 | * 6. Read/written by GPU | |
2906 | * | |
2907 | * 1. Allocated | |
2908 | * Same as last example, (CPU, CPU) | |
2909 | * 2. Mapped to GTT | |
2910 | * Nothing changes (assertions find that it is not in the GPU) | |
2911 | * 3. Read/written by GPU | |
2912 | * execbuffer calls set_domain (RENDER, RENDER) | |
2913 | * flush_domains gets CPU | |
2914 | * invalidate_domains gets GPU | |
2915 | * clflush (obj) | |
2916 | * MI_FLUSH and drm_agp_chipset_flush | |
2917 | * 4. set_domain (CPU, CPU) | |
2918 | * flush_domains gets GPU | |
2919 | * invalidate_domains gets CPU | |
2920 | * wait_rendering (obj) to make sure all drawing is complete. | |
2921 | * This will include an MI_FLUSH to get the data from GPU | |
2922 | * to memory | |
2923 | * clflush (obj) to invalidate the CPU cache | |
2924 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
2925 | * 5. Read/written by CPU | |
2926 | * cache lines are loaded and dirtied | |
2927 | * 6. Read written by GPU | |
2928 | * Same as last GPU access | |
2929 | * | |
2930 | * Case 3: The constant buffer | |
2931 | * | |
2932 | * 1. Allocated | |
2933 | * 2. Written by CPU | |
2934 | * 3. Read by GPU | |
2935 | * 4. Updated (written) by CPU again | |
2936 | * 5. Read by GPU | |
2937 | * | |
2938 | * 1. Allocated | |
2939 | * (CPU, CPU) | |
2940 | * 2. Written by CPU | |
2941 | * (CPU, CPU) | |
2942 | * 3. Read by GPU | |
2943 | * (CPU+RENDER, 0) | |
2944 | * flush_domains = CPU | |
2945 | * invalidate_domains = RENDER | |
2946 | * clflush (obj) | |
2947 | * MI_FLUSH | |
2948 | * drm_agp_chipset_flush | |
2949 | * 4. Updated (written) by CPU again | |
2950 | * (CPU, CPU) | |
2951 | * flush_domains = 0 (no previous write domain) | |
2952 | * invalidate_domains = 0 (no new read domains) | |
2953 | * 5. Read by GPU | |
2954 | * (CPU+RENDER, 0) | |
2955 | * flush_domains = CPU | |
2956 | * invalidate_domains = RENDER | |
2957 | * clflush (obj) | |
2958 | * MI_FLUSH | |
2959 | * drm_agp_chipset_flush | |
2960 | */ | |
c0d90829 | 2961 | static void |
8b0e378a | 2962 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
2963 | { |
2964 | struct drm_device *dev = obj->dev; | |
9220434a | 2965 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2966 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2967 | uint32_t invalidate_domains = 0; |
2968 | uint32_t flush_domains = 0; | |
1c5d22f7 | 2969 | uint32_t old_read_domains; |
e47c68e9 | 2970 | |
8b0e378a EA |
2971 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
2972 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 2973 | |
652c393a JB |
2974 | intel_mark_busy(dev, obj); |
2975 | ||
673a394b EA |
2976 | #if WATCH_BUF |
2977 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", | |
2978 | __func__, obj, | |
8b0e378a EA |
2979 | obj->read_domains, obj->pending_read_domains, |
2980 | obj->write_domain, obj->pending_write_domain); | |
673a394b EA |
2981 | #endif |
2982 | /* | |
2983 | * If the object isn't moving to a new write domain, | |
2984 | * let the object stay in multiple read domains | |
2985 | */ | |
8b0e378a EA |
2986 | if (obj->pending_write_domain == 0) |
2987 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
2988 | else |
2989 | obj_priv->dirty = 1; | |
2990 | ||
2991 | /* | |
2992 | * Flush the current write domain if | |
2993 | * the new read domains don't match. Invalidate | |
2994 | * any read domains which differ from the old | |
2995 | * write domain | |
2996 | */ | |
8b0e378a EA |
2997 | if (obj->write_domain && |
2998 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 2999 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3000 | invalidate_domains |= |
3001 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3002 | } |
3003 | /* | |
3004 | * Invalidate any read caches which may have | |
3005 | * stale data. That is, any new read domains. | |
3006 | */ | |
8b0e378a | 3007 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
673a394b EA |
3008 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
3009 | #if WATCH_BUF | |
3010 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", | |
3011 | __func__, flush_domains, invalidate_domains); | |
3012 | #endif | |
673a394b EA |
3013 | i915_gem_clflush_object(obj); |
3014 | } | |
3015 | ||
1c5d22f7 CW |
3016 | old_read_domains = obj->read_domains; |
3017 | ||
efbeed96 EA |
3018 | /* The actual obj->write_domain will be updated with |
3019 | * pending_write_domain after we emit the accumulated flush for all | |
3020 | * of our domain changes in execbuffers (which clears objects' | |
3021 | * write_domains). So if we have a current write domain that we | |
3022 | * aren't changing, set pending_write_domain to that. | |
3023 | */ | |
3024 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3025 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3026 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
3027 | |
3028 | dev->invalidate_domains |= invalidate_domains; | |
3029 | dev->flush_domains |= flush_domains; | |
9220434a CW |
3030 | if (obj_priv->ring) |
3031 | dev_priv->mm.flush_rings |= obj_priv->ring->id; | |
673a394b EA |
3032 | #if WATCH_BUF |
3033 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", | |
3034 | __func__, | |
3035 | obj->read_domains, obj->write_domain, | |
3036 | dev->invalidate_domains, dev->flush_domains); | |
3037 | #endif | |
1c5d22f7 CW |
3038 | |
3039 | trace_i915_gem_object_change_domain(obj, | |
3040 | old_read_domains, | |
3041 | obj->write_domain); | |
673a394b EA |
3042 | } |
3043 | ||
3044 | /** | |
e47c68e9 | 3045 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3046 | * |
e47c68e9 EA |
3047 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3048 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3049 | */ |
e47c68e9 EA |
3050 | static void |
3051 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3052 | { |
23010e43 | 3053 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3054 | |
e47c68e9 EA |
3055 | if (!obj_priv->page_cpu_valid) |
3056 | return; | |
3057 | ||
3058 | /* If we're partially in the CPU read domain, finish moving it in. | |
3059 | */ | |
3060 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3061 | int i; | |
3062 | ||
3063 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3064 | if (obj_priv->page_cpu_valid[i]) | |
3065 | continue; | |
856fa198 | 3066 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3067 | } |
e47c68e9 EA |
3068 | } |
3069 | ||
3070 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3071 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3072 | */ | |
9a298b2a | 3073 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3074 | obj_priv->page_cpu_valid = NULL; |
3075 | } | |
3076 | ||
3077 | /** | |
3078 | * Set the CPU read domain on a range of the object. | |
3079 | * | |
3080 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3081 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3082 | * pages have been flushed, and will be respected by | |
3083 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3084 | * of the whole object. | |
3085 | * | |
3086 | * This function returns when the move is complete, including waiting on | |
3087 | * flushes to occur. | |
3088 | */ | |
3089 | static int | |
3090 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3091 | uint64_t offset, uint64_t size) | |
3092 | { | |
23010e43 | 3093 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3094 | uint32_t old_read_domains; |
e47c68e9 | 3095 | int i, ret; |
673a394b | 3096 | |
e47c68e9 EA |
3097 | if (offset == 0 && size == obj->size) |
3098 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3099 | |
ba3d8d74 | 3100 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3101 | if (ret != 0) |
6a47baa6 | 3102 | return ret; |
e47c68e9 EA |
3103 | i915_gem_object_flush_gtt_write_domain(obj); |
3104 | ||
3105 | /* If we're already fully in the CPU read domain, we're done. */ | |
3106 | if (obj_priv->page_cpu_valid == NULL && | |
3107 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3108 | return 0; | |
673a394b | 3109 | |
e47c68e9 EA |
3110 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3111 | * newly adding I915_GEM_DOMAIN_CPU | |
3112 | */ | |
673a394b | 3113 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3114 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3115 | GFP_KERNEL); | |
e47c68e9 EA |
3116 | if (obj_priv->page_cpu_valid == NULL) |
3117 | return -ENOMEM; | |
3118 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3119 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3120 | |
3121 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3122 | * perspective. | |
3123 | */ | |
e47c68e9 EA |
3124 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3125 | i++) { | |
673a394b EA |
3126 | if (obj_priv->page_cpu_valid[i]) |
3127 | continue; | |
3128 | ||
856fa198 | 3129 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3130 | |
3131 | obj_priv->page_cpu_valid[i] = 1; | |
3132 | } | |
3133 | ||
e47c68e9 EA |
3134 | /* It should now be out of any other write domains, and we can update |
3135 | * the domain values for our changes. | |
3136 | */ | |
3137 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3138 | ||
1c5d22f7 | 3139 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3140 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3141 | ||
1c5d22f7 CW |
3142 | trace_i915_gem_object_change_domain(obj, |
3143 | old_read_domains, | |
3144 | obj->write_domain); | |
3145 | ||
673a394b EA |
3146 | return 0; |
3147 | } | |
3148 | ||
673a394b EA |
3149 | /** |
3150 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3151 | */ | |
3152 | static int | |
3153 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3154 | struct drm_file *file_priv, | |
76446cac | 3155 | struct drm_i915_gem_exec_object2 *entry, |
40a5f0de | 3156 | struct drm_i915_gem_relocation_entry *relocs) |
673a394b EA |
3157 | { |
3158 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3159 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 3160 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3161 | int i, ret; |
0839ccb8 | 3162 | void __iomem *reloc_page; |
76446cac JB |
3163 | bool need_fence; |
3164 | ||
3165 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3166 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3167 | ||
3168 | /* Check fence reg constraints and rebind if necessary */ | |
808b24d6 CW |
3169 | if (need_fence && |
3170 | !i915_gem_object_fence_offset_ok(obj, | |
3171 | obj_priv->tiling_mode)) { | |
3172 | ret = i915_gem_object_unbind(obj); | |
3173 | if (ret) | |
3174 | return ret; | |
3175 | } | |
673a394b EA |
3176 | |
3177 | /* Choose the GTT offset for our buffer and put it there. */ | |
3178 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3179 | if (ret) | |
3180 | return ret; | |
3181 | ||
76446cac JB |
3182 | /* |
3183 | * Pre-965 chips need a fence register set up in order to | |
3184 | * properly handle blits to/from tiled surfaces. | |
3185 | */ | |
3186 | if (need_fence) { | |
53640e1d | 3187 | ret = i915_gem_object_get_fence_reg(obj, true); |
76446cac | 3188 | if (ret != 0) { |
76446cac JB |
3189 | i915_gem_object_unpin(obj); |
3190 | return ret; | |
3191 | } | |
53640e1d CW |
3192 | |
3193 | dev_priv->fence_regs[obj_priv->fence_reg].gpu = true; | |
76446cac JB |
3194 | } |
3195 | ||
673a394b EA |
3196 | entry->offset = obj_priv->gtt_offset; |
3197 | ||
673a394b EA |
3198 | /* Apply the relocations, using the GTT aperture to avoid cache |
3199 | * flushing requirements. | |
3200 | */ | |
3201 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 3202 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
3203 | struct drm_gem_object *target_obj; |
3204 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
3205 | uint32_t reloc_val, reloc_offset; |
3206 | uint32_t __iomem *reloc_entry; | |
673a394b | 3207 | |
673a394b | 3208 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 3209 | reloc->target_handle); |
673a394b EA |
3210 | if (target_obj == NULL) { |
3211 | i915_gem_object_unpin(obj); | |
bf79cb91 | 3212 | return -ENOENT; |
673a394b | 3213 | } |
23010e43 | 3214 | target_obj_priv = to_intel_bo(target_obj); |
673a394b | 3215 | |
8542a0bb CW |
3216 | #if WATCH_RELOC |
3217 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3218 | "read %08x write %08x gtt %08x " | |
3219 | "presumed %08x delta %08x\n", | |
3220 | __func__, | |
3221 | obj, | |
3222 | (int) reloc->offset, | |
3223 | (int) reloc->target_handle, | |
3224 | (int) reloc->read_domains, | |
3225 | (int) reloc->write_domain, | |
3226 | (int) target_obj_priv->gtt_offset, | |
3227 | (int) reloc->presumed_offset, | |
3228 | reloc->delta); | |
3229 | #endif | |
3230 | ||
673a394b EA |
3231 | /* The target buffer should have appeared before us in the |
3232 | * exec_object list, so it should have a GTT space bound by now. | |
3233 | */ | |
3234 | if (target_obj_priv->gtt_space == NULL) { | |
3235 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 3236 | reloc->target_handle); |
673a394b EA |
3237 | drm_gem_object_unreference(target_obj); |
3238 | i915_gem_object_unpin(obj); | |
3239 | return -EINVAL; | |
3240 | } | |
3241 | ||
8542a0bb | 3242 | /* Validate that the target is in a valid r/w GPU domain */ |
16edd550 DV |
3243 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
3244 | DRM_ERROR("reloc with multiple write domains: " | |
3245 | "obj %p target %d offset %d " | |
3246 | "read %08x write %08x", | |
3247 | obj, reloc->target_handle, | |
3248 | (int) reloc->offset, | |
3249 | reloc->read_domains, | |
3250 | reloc->write_domain); | |
3251 | return -EINVAL; | |
3252 | } | |
40a5f0de EA |
3253 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3254 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3255 | DRM_ERROR("reloc with read/write CPU domains: " |
3256 | "obj %p target %d offset %d " | |
3257 | "read %08x write %08x", | |
40a5f0de EA |
3258 | obj, reloc->target_handle, |
3259 | (int) reloc->offset, | |
3260 | reloc->read_domains, | |
3261 | reloc->write_domain); | |
491152b8 CW |
3262 | drm_gem_object_unreference(target_obj); |
3263 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3264 | return -EINVAL; |
3265 | } | |
40a5f0de EA |
3266 | if (reloc->write_domain && target_obj->pending_write_domain && |
3267 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3268 | DRM_ERROR("Write domain conflict: " |
3269 | "obj %p target %d offset %d " | |
3270 | "new %08x old %08x\n", | |
40a5f0de EA |
3271 | obj, reloc->target_handle, |
3272 | (int) reloc->offset, | |
3273 | reloc->write_domain, | |
673a394b EA |
3274 | target_obj->pending_write_domain); |
3275 | drm_gem_object_unreference(target_obj); | |
3276 | i915_gem_object_unpin(obj); | |
3277 | return -EINVAL; | |
3278 | } | |
3279 | ||
40a5f0de EA |
3280 | target_obj->pending_read_domains |= reloc->read_domains; |
3281 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3282 | |
3283 | /* If the relocation already has the right value in it, no | |
3284 | * more work needs to be done. | |
3285 | */ | |
40a5f0de | 3286 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3287 | drm_gem_object_unreference(target_obj); |
3288 | continue; | |
3289 | } | |
3290 | ||
8542a0bb CW |
3291 | /* Check that the relocation address is valid... */ |
3292 | if (reloc->offset > obj->size - 4) { | |
3293 | DRM_ERROR("Relocation beyond object bounds: " | |
3294 | "obj %p target %d offset %d size %d.\n", | |
3295 | obj, reloc->target_handle, | |
3296 | (int) reloc->offset, (int) obj->size); | |
3297 | drm_gem_object_unreference(target_obj); | |
3298 | i915_gem_object_unpin(obj); | |
3299 | return -EINVAL; | |
3300 | } | |
3301 | if (reloc->offset & 3) { | |
3302 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3303 | "obj %p target %d offset %d.\n", | |
3304 | obj, reloc->target_handle, | |
3305 | (int) reloc->offset); | |
3306 | drm_gem_object_unreference(target_obj); | |
3307 | i915_gem_object_unpin(obj); | |
3308 | return -EINVAL; | |
3309 | } | |
3310 | ||
3311 | /* and points to somewhere within the target object. */ | |
3312 | if (reloc->delta >= target_obj->size) { | |
3313 | DRM_ERROR("Relocation beyond target object bounds: " | |
3314 | "obj %p target %d delta %d size %d.\n", | |
3315 | obj, reloc->target_handle, | |
3316 | (int) reloc->delta, (int) target_obj->size); | |
3317 | drm_gem_object_unreference(target_obj); | |
3318 | i915_gem_object_unpin(obj); | |
3319 | return -EINVAL; | |
3320 | } | |
3321 | ||
2ef7eeaa EA |
3322 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3323 | if (ret != 0) { | |
3324 | drm_gem_object_unreference(target_obj); | |
3325 | i915_gem_object_unpin(obj); | |
3326 | return -EINVAL; | |
673a394b EA |
3327 | } |
3328 | ||
3329 | /* Map the page containing the relocation we're going to | |
3330 | * perform. | |
3331 | */ | |
40a5f0de | 3332 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3333 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3334 | (reloc_offset & | |
fca3ec01 CW |
3335 | ~(PAGE_SIZE - 1)), |
3336 | KM_USER0); | |
3043c60c | 3337 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3338 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3339 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b EA |
3340 | |
3341 | #if WATCH_BUF | |
3342 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", | |
40a5f0de | 3343 | obj, (unsigned int) reloc->offset, |
673a394b EA |
3344 | readl(reloc_entry), reloc_val); |
3345 | #endif | |
3346 | writel(reloc_val, reloc_entry); | |
fca3ec01 | 3347 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
673a394b | 3348 | |
40a5f0de EA |
3349 | /* The updated presumed offset for this entry will be |
3350 | * copied back out to the user. | |
673a394b | 3351 | */ |
40a5f0de | 3352 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3353 | |
3354 | drm_gem_object_unreference(target_obj); | |
3355 | } | |
3356 | ||
673a394b EA |
3357 | #if WATCH_BUF |
3358 | if (0) | |
3359 | i915_gem_dump_object(obj, 128, __func__, ~0); | |
3360 | #endif | |
3361 | return 0; | |
3362 | } | |
3363 | ||
673a394b EA |
3364 | /* Throttle our rendering by waiting until the ring has completed our requests |
3365 | * emitted over 20 msec ago. | |
3366 | * | |
b962442e EA |
3367 | * Note that if we were to use the current jiffies each time around the loop, |
3368 | * we wouldn't escape the function with any frames outstanding if the time to | |
3369 | * render a frame was over 20ms. | |
3370 | * | |
673a394b EA |
3371 | * This should get us reasonable parallelism between CPU and GPU but also |
3372 | * relatively low latency when blocking on a particular request to finish. | |
3373 | */ | |
3374 | static int | |
3375 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) | |
3376 | { | |
3377 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
3378 | int ret = 0; | |
b962442e | 3379 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
673a394b EA |
3380 | |
3381 | mutex_lock(&dev->struct_mutex); | |
b962442e EA |
3382 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
3383 | struct drm_i915_gem_request *request; | |
3384 | ||
3385 | request = list_first_entry(&i915_file_priv->mm.request_list, | |
3386 | struct drm_i915_gem_request, | |
3387 | client_list); | |
3388 | ||
3389 | if (time_after_eq(request->emitted_jiffies, recent_enough)) | |
3390 | break; | |
3391 | ||
852835f3 | 3392 | ret = i915_wait_request(dev, request->seqno, request->ring); |
b962442e EA |
3393 | if (ret != 0) |
3394 | break; | |
3395 | } | |
673a394b | 3396 | mutex_unlock(&dev->struct_mutex); |
b962442e | 3397 | |
673a394b EA |
3398 | return ret; |
3399 | } | |
3400 | ||
40a5f0de | 3401 | static int |
76446cac | 3402 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3403 | uint32_t buffer_count, |
3404 | struct drm_i915_gem_relocation_entry **relocs) | |
3405 | { | |
3406 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3407 | int ret; | |
3408 | ||
3409 | *relocs = NULL; | |
3410 | for (i = 0; i < buffer_count; i++) { | |
3411 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3412 | return -EINVAL; | |
3413 | reloc_count += exec_list[i].relocation_count; | |
3414 | } | |
3415 | ||
8e7d2b2c | 3416 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
76446cac JB |
3417 | if (*relocs == NULL) { |
3418 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); | |
40a5f0de | 3419 | return -ENOMEM; |
76446cac | 3420 | } |
40a5f0de EA |
3421 | |
3422 | for (i = 0; i < buffer_count; i++) { | |
3423 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3424 | ||
3425 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3426 | ||
3427 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3428 | user_relocs, | |
3429 | exec_list[i].relocation_count * | |
3430 | sizeof(**relocs)); | |
3431 | if (ret != 0) { | |
8e7d2b2c | 3432 | drm_free_large(*relocs); |
40a5f0de | 3433 | *relocs = NULL; |
2bc43b5c | 3434 | return -EFAULT; |
40a5f0de EA |
3435 | } |
3436 | ||
3437 | reloc_index += exec_list[i].relocation_count; | |
3438 | } | |
3439 | ||
2bc43b5c | 3440 | return 0; |
40a5f0de EA |
3441 | } |
3442 | ||
3443 | static int | |
76446cac | 3444 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3445 | uint32_t buffer_count, |
3446 | struct drm_i915_gem_relocation_entry *relocs) | |
3447 | { | |
3448 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3449 | int ret = 0; |
40a5f0de | 3450 | |
93533c29 CW |
3451 | if (relocs == NULL) |
3452 | return 0; | |
3453 | ||
40a5f0de EA |
3454 | for (i = 0; i < buffer_count; i++) { |
3455 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3456 | int unwritten; |
40a5f0de EA |
3457 | |
3458 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3459 | ||
2bc43b5c FM |
3460 | unwritten = copy_to_user(user_relocs, |
3461 | &relocs[reloc_count], | |
3462 | exec_list[i].relocation_count * | |
3463 | sizeof(*relocs)); | |
3464 | ||
3465 | if (unwritten) { | |
3466 | ret = -EFAULT; | |
3467 | goto err; | |
40a5f0de EA |
3468 | } |
3469 | ||
3470 | reloc_count += exec_list[i].relocation_count; | |
3471 | } | |
3472 | ||
2bc43b5c | 3473 | err: |
8e7d2b2c | 3474 | drm_free_large(relocs); |
40a5f0de EA |
3475 | |
3476 | return ret; | |
3477 | } | |
3478 | ||
83d60795 | 3479 | static int |
76446cac | 3480 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
83d60795 CW |
3481 | uint64_t exec_offset) |
3482 | { | |
3483 | uint32_t exec_start, exec_len; | |
3484 | ||
3485 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3486 | exec_len = (uint32_t) exec->batch_len; | |
3487 | ||
3488 | if ((exec_start | exec_len) & 0x7) | |
3489 | return -EINVAL; | |
3490 | ||
3491 | if (!exec_start) | |
3492 | return -EINVAL; | |
3493 | ||
3494 | return 0; | |
3495 | } | |
3496 | ||
265db958 | 3497 | int |
6b95a207 KH |
3498 | i915_gem_wait_for_pending_flip(struct drm_device *dev, |
3499 | struct drm_gem_object **object_list, | |
3500 | int count) | |
3501 | { | |
3502 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3503 | struct drm_i915_gem_object *obj_priv; | |
3504 | DEFINE_WAIT(wait); | |
3505 | int i, ret = 0; | |
3506 | ||
3507 | for (;;) { | |
3508 | prepare_to_wait(&dev_priv->pending_flip_queue, | |
3509 | &wait, TASK_INTERRUPTIBLE); | |
3510 | for (i = 0; i < count; i++) { | |
23010e43 | 3511 | obj_priv = to_intel_bo(object_list[i]); |
6b95a207 KH |
3512 | if (atomic_read(&obj_priv->pending_flip) > 0) |
3513 | break; | |
3514 | } | |
3515 | if (i == count) | |
3516 | break; | |
3517 | ||
3518 | if (!signal_pending(current)) { | |
3519 | mutex_unlock(&dev->struct_mutex); | |
3520 | schedule(); | |
3521 | mutex_lock(&dev->struct_mutex); | |
3522 | continue; | |
3523 | } | |
3524 | ret = -ERESTARTSYS; | |
3525 | break; | |
3526 | } | |
3527 | finish_wait(&dev_priv->pending_flip_queue, &wait); | |
3528 | ||
3529 | return ret; | |
3530 | } | |
3531 | ||
8dc5d147 | 3532 | static int |
76446cac JB |
3533 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
3534 | struct drm_file *file_priv, | |
3535 | struct drm_i915_gem_execbuffer2 *args, | |
3536 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3537 | { |
3538 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3539 | struct drm_gem_object **object_list = NULL; |
3540 | struct drm_gem_object *batch_obj; | |
b70d11da | 3541 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3542 | struct drm_clip_rect *cliprects = NULL; |
93533c29 | 3543 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
8dc5d147 | 3544 | struct drm_i915_gem_request *request = NULL; |
76446cac | 3545 | int ret = 0, ret2, i, pinned = 0; |
673a394b | 3546 | uint64_t exec_offset; |
8a1a49f9 | 3547 | uint32_t seqno, reloc_index; |
6b95a207 | 3548 | int pin_tries, flips; |
673a394b | 3549 | |
852835f3 ZN |
3550 | struct intel_ring_buffer *ring = NULL; |
3551 | ||
673a394b EA |
3552 | #if WATCH_EXEC |
3553 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3554 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3555 | #endif | |
d1b851fc ZN |
3556 | if (args->flags & I915_EXEC_BSD) { |
3557 | if (!HAS_BSD(dev)) { | |
3558 | DRM_ERROR("execbuf with wrong flag\n"); | |
3559 | return -EINVAL; | |
3560 | } | |
3561 | ring = &dev_priv->bsd_ring; | |
3562 | } else { | |
3563 | ring = &dev_priv->render_ring; | |
3564 | } | |
3565 | ||
4f481ed2 EA |
3566 | if (args->buffer_count < 1) { |
3567 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3568 | return -EINVAL; | |
3569 | } | |
c8e0f93a | 3570 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3571 | if (object_list == NULL) { |
3572 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3573 | args->buffer_count); |
3574 | ret = -ENOMEM; | |
3575 | goto pre_mutex_err; | |
3576 | } | |
673a394b | 3577 | |
201361a5 | 3578 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3579 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3580 | GFP_KERNEL); | |
a40e8d31 OA |
3581 | if (cliprects == NULL) { |
3582 | ret = -ENOMEM; | |
201361a5 | 3583 | goto pre_mutex_err; |
a40e8d31 | 3584 | } |
201361a5 EA |
3585 | |
3586 | ret = copy_from_user(cliprects, | |
3587 | (struct drm_clip_rect __user *) | |
3588 | (uintptr_t) args->cliprects_ptr, | |
3589 | sizeof(*cliprects) * args->num_cliprects); | |
3590 | if (ret != 0) { | |
3591 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3592 | args->num_cliprects, ret); | |
c877cdce | 3593 | ret = -EFAULT; |
201361a5 EA |
3594 | goto pre_mutex_err; |
3595 | } | |
3596 | } | |
3597 | ||
8dc5d147 CW |
3598 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3599 | if (request == NULL) { | |
3600 | ret = -ENOMEM; | |
3601 | goto pre_mutex_err; | |
3602 | } | |
3603 | ||
40a5f0de EA |
3604 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3605 | &relocs); | |
3606 | if (ret != 0) | |
3607 | goto pre_mutex_err; | |
3608 | ||
673a394b EA |
3609 | mutex_lock(&dev->struct_mutex); |
3610 | ||
3611 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3612 | ||
ba1234d1 | 3613 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3614 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3615 | ret = -EIO; |
3616 | goto pre_mutex_err; | |
673a394b EA |
3617 | } |
3618 | ||
3619 | if (dev_priv->mm.suspended) { | |
673a394b | 3620 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3621 | ret = -EBUSY; |
3622 | goto pre_mutex_err; | |
673a394b EA |
3623 | } |
3624 | ||
ac94a962 | 3625 | /* Look up object handles */ |
6b95a207 | 3626 | flips = 0; |
673a394b EA |
3627 | for (i = 0; i < args->buffer_count; i++) { |
3628 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3629 | exec_list[i].handle); | |
3630 | if (object_list[i] == NULL) { | |
3631 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3632 | exec_list[i].handle, i); | |
0ce907f8 CW |
3633 | /* prevent error path from reading uninitialized data */ |
3634 | args->buffer_count = i + 1; | |
bf79cb91 | 3635 | ret = -ENOENT; |
673a394b EA |
3636 | goto err; |
3637 | } | |
b70d11da | 3638 | |
23010e43 | 3639 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3640 | if (obj_priv->in_execbuffer) { |
3641 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3642 | object_list[i]); | |
0ce907f8 CW |
3643 | /* prevent error path from reading uninitialized data */ |
3644 | args->buffer_count = i + 1; | |
bf79cb91 | 3645 | ret = -EINVAL; |
b70d11da KH |
3646 | goto err; |
3647 | } | |
3648 | obj_priv->in_execbuffer = true; | |
6b95a207 KH |
3649 | flips += atomic_read(&obj_priv->pending_flip); |
3650 | } | |
3651 | ||
3652 | if (flips > 0) { | |
3653 | ret = i915_gem_wait_for_pending_flip(dev, object_list, | |
3654 | args->buffer_count); | |
3655 | if (ret) | |
3656 | goto err; | |
ac94a962 | 3657 | } |
673a394b | 3658 | |
ac94a962 KP |
3659 | /* Pin and relocate */ |
3660 | for (pin_tries = 0; ; pin_tries++) { | |
3661 | ret = 0; | |
40a5f0de EA |
3662 | reloc_index = 0; |
3663 | ||
ac94a962 KP |
3664 | for (i = 0; i < args->buffer_count; i++) { |
3665 | object_list[i]->pending_read_domains = 0; | |
3666 | object_list[i]->pending_write_domain = 0; | |
3667 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3668 | file_priv, | |
40a5f0de EA |
3669 | &exec_list[i], |
3670 | &relocs[reloc_index]); | |
ac94a962 KP |
3671 | if (ret) |
3672 | break; | |
3673 | pinned = i + 1; | |
40a5f0de | 3674 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3675 | } |
3676 | /* success */ | |
3677 | if (ret == 0) | |
3678 | break; | |
3679 | ||
3680 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3681 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3682 | if (ret != -ERESTARTSYS) { |
3683 | unsigned long long total_size = 0; | |
3d1cc470 CW |
3684 | int num_fences = 0; |
3685 | for (i = 0; i < args->buffer_count; i++) { | |
43b27f40 | 3686 | obj_priv = to_intel_bo(object_list[i]); |
3d1cc470 | 3687 | |
07f73f69 | 3688 | total_size += object_list[i]->size; |
3d1cc470 CW |
3689 | num_fences += |
3690 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && | |
3691 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3692 | } | |
3693 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", | |
07f73f69 | 3694 | pinned+1, args->buffer_count, |
3d1cc470 CW |
3695 | total_size, num_fences, |
3696 | ret); | |
07f73f69 CW |
3697 | DRM_ERROR("%d objects [%d pinned], " |
3698 | "%d object bytes [%d pinned], " | |
3699 | "%d/%d gtt bytes\n", | |
3700 | atomic_read(&dev->object_count), | |
3701 | atomic_read(&dev->pin_count), | |
3702 | atomic_read(&dev->object_memory), | |
3703 | atomic_read(&dev->pin_memory), | |
3704 | atomic_read(&dev->gtt_memory), | |
3705 | dev->gtt_total); | |
3706 | } | |
673a394b EA |
3707 | goto err; |
3708 | } | |
ac94a962 KP |
3709 | |
3710 | /* unpin all of our buffers */ | |
3711 | for (i = 0; i < pinned; i++) | |
3712 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3713 | pinned = 0; |
ac94a962 KP |
3714 | |
3715 | /* evict everyone we can from the aperture */ | |
3716 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3717 | if (ret && ret != -ENOSPC) |
ac94a962 | 3718 | goto err; |
673a394b EA |
3719 | } |
3720 | ||
3721 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3722 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3723 | if (batch_obj->pending_write_domain) { |
3724 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3725 | ret = -EINVAL; | |
3726 | goto err; | |
3727 | } | |
3728 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3729 | |
83d60795 CW |
3730 | /* Sanity check the batch buffer, prior to moving objects */ |
3731 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3732 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3733 | if (ret != 0) { | |
3734 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3735 | goto err; | |
3736 | } | |
3737 | ||
673a394b EA |
3738 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3739 | ||
646f0f6e KP |
3740 | /* Zero the global flush/invalidate flags. These |
3741 | * will be modified as new domains are computed | |
3742 | * for each object | |
3743 | */ | |
3744 | dev->invalidate_domains = 0; | |
3745 | dev->flush_domains = 0; | |
9220434a | 3746 | dev_priv->mm.flush_rings = 0; |
646f0f6e | 3747 | |
673a394b EA |
3748 | for (i = 0; i < args->buffer_count; i++) { |
3749 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3750 | |
646f0f6e | 3751 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3752 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3753 | } |
3754 | ||
3755 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3756 | ||
646f0f6e KP |
3757 | if (dev->invalidate_domains | dev->flush_domains) { |
3758 | #if WATCH_EXEC | |
3759 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3760 | __func__, | |
3761 | dev->invalidate_domains, | |
3762 | dev->flush_domains); | |
3763 | #endif | |
c78ec30b | 3764 | i915_gem_flush(dev, file_priv, |
646f0f6e | 3765 | dev->invalidate_domains, |
9220434a CW |
3766 | dev->flush_domains, |
3767 | dev_priv->mm.flush_rings); | |
a6910434 DV |
3768 | } |
3769 | ||
efbeed96 EA |
3770 | for (i = 0; i < args->buffer_count; i++) { |
3771 | struct drm_gem_object *obj = object_list[i]; | |
23010e43 | 3772 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3773 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3774 | |
3775 | obj->write_domain = obj->pending_write_domain; | |
99fcb766 DV |
3776 | if (obj->write_domain) |
3777 | list_move_tail(&obj_priv->gpu_write_list, | |
3778 | &dev_priv->mm.gpu_write_list); | |
3779 | else | |
3780 | list_del_init(&obj_priv->gpu_write_list); | |
3781 | ||
1c5d22f7 CW |
3782 | trace_i915_gem_object_change_domain(obj, |
3783 | obj->read_domains, | |
3784 | old_write_domain); | |
efbeed96 EA |
3785 | } |
3786 | ||
673a394b EA |
3787 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3788 | ||
3789 | #if WATCH_COHERENCY | |
3790 | for (i = 0; i < args->buffer_count; i++) { | |
3791 | i915_gem_object_check_coherency(object_list[i], | |
3792 | exec_list[i].handle); | |
3793 | } | |
3794 | #endif | |
3795 | ||
673a394b | 3796 | #if WATCH_EXEC |
6911a9b8 | 3797 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3798 | args->batch_len, |
3799 | __func__, | |
3800 | ~0); | |
3801 | #endif | |
3802 | ||
673a394b | 3803 | /* Exec the batchbuffer */ |
852835f3 ZN |
3804 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
3805 | cliprects, exec_offset); | |
673a394b EA |
3806 | if (ret) { |
3807 | DRM_ERROR("dispatch failed %d\n", ret); | |
3808 | goto err; | |
3809 | } | |
3810 | ||
3811 | /* | |
3812 | * Ensure that the commands in the batch buffer are | |
3813 | * finished before the interrupt fires | |
3814 | */ | |
8a1a49f9 | 3815 | i915_retire_commands(dev, ring); |
673a394b EA |
3816 | |
3817 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3818 | ||
617dbe27 DV |
3819 | for (i = 0; i < args->buffer_count; i++) { |
3820 | struct drm_gem_object *obj = object_list[i]; | |
3821 | obj_priv = to_intel_bo(obj); | |
3822 | ||
3823 | i915_gem_object_move_to_active(obj, ring); | |
3824 | #if WATCH_LRU | |
3825 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); | |
3826 | #endif | |
3827 | } | |
3828 | ||
673a394b EA |
3829 | /* |
3830 | * Get a seqno representing the execution of the current buffer, | |
3831 | * which we can wait on. We would like to mitigate these interrupts, | |
3832 | * likely by only creating seqnos occasionally (so that we have | |
3833 | * *some* interrupts representing completion of buffers that we can | |
3834 | * wait on when trying to clear up gtt space). | |
3835 | */ | |
8dc5d147 CW |
3836 | seqno = i915_add_request(dev, file_priv, request, ring); |
3837 | request = NULL; | |
673a394b | 3838 | |
673a394b EA |
3839 | #if WATCH_LRU |
3840 | i915_dump_lru(dev, __func__); | |
3841 | #endif | |
3842 | ||
3843 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3844 | ||
673a394b | 3845 | err: |
aad87dff JL |
3846 | for (i = 0; i < pinned; i++) |
3847 | i915_gem_object_unpin(object_list[i]); | |
3848 | ||
b70d11da KH |
3849 | for (i = 0; i < args->buffer_count; i++) { |
3850 | if (object_list[i]) { | |
23010e43 | 3851 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3852 | obj_priv->in_execbuffer = false; |
3853 | } | |
aad87dff | 3854 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3855 | } |
673a394b | 3856 | |
673a394b EA |
3857 | mutex_unlock(&dev->struct_mutex); |
3858 | ||
93533c29 | 3859 | pre_mutex_err: |
40a5f0de EA |
3860 | /* Copy the updated relocations out regardless of current error |
3861 | * state. Failure to update the relocs would mean that the next | |
3862 | * time userland calls execbuf, it would do so with presumed offset | |
3863 | * state that didn't match the actual object state. | |
3864 | */ | |
3865 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3866 | relocs); | |
3867 | if (ret2 != 0) { | |
3868 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3869 | ||
3870 | if (ret == 0) | |
3871 | ret = ret2; | |
3872 | } | |
3873 | ||
8e7d2b2c | 3874 | drm_free_large(object_list); |
9a298b2a | 3875 | kfree(cliprects); |
8dc5d147 | 3876 | kfree(request); |
673a394b EA |
3877 | |
3878 | return ret; | |
3879 | } | |
3880 | ||
76446cac JB |
3881 | /* |
3882 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3883 | * list array and passes it to the real function. | |
3884 | */ | |
3885 | int | |
3886 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3887 | struct drm_file *file_priv) | |
3888 | { | |
3889 | struct drm_i915_gem_execbuffer *args = data; | |
3890 | struct drm_i915_gem_execbuffer2 exec2; | |
3891 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3892 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3893 | int ret, i; | |
3894 | ||
3895 | #if WATCH_EXEC | |
3896 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3897 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3898 | #endif | |
3899 | ||
3900 | if (args->buffer_count < 1) { | |
3901 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3902 | return -EINVAL; | |
3903 | } | |
3904 | ||
3905 | /* Copy in the exec list from userland */ | |
3906 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3907 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3908 | if (exec_list == NULL || exec2_list == NULL) { | |
3909 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3910 | args->buffer_count); | |
3911 | drm_free_large(exec_list); | |
3912 | drm_free_large(exec2_list); | |
3913 | return -ENOMEM; | |
3914 | } | |
3915 | ret = copy_from_user(exec_list, | |
3916 | (struct drm_i915_relocation_entry __user *) | |
3917 | (uintptr_t) args->buffers_ptr, | |
3918 | sizeof(*exec_list) * args->buffer_count); | |
3919 | if (ret != 0) { | |
3920 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3921 | args->buffer_count, ret); | |
3922 | drm_free_large(exec_list); | |
3923 | drm_free_large(exec2_list); | |
3924 | return -EFAULT; | |
3925 | } | |
3926 | ||
3927 | for (i = 0; i < args->buffer_count; i++) { | |
3928 | exec2_list[i].handle = exec_list[i].handle; | |
3929 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3930 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3931 | exec2_list[i].alignment = exec_list[i].alignment; | |
3932 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 3933 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
3934 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
3935 | else | |
3936 | exec2_list[i].flags = 0; | |
3937 | } | |
3938 | ||
3939 | exec2.buffers_ptr = args->buffers_ptr; | |
3940 | exec2.buffer_count = args->buffer_count; | |
3941 | exec2.batch_start_offset = args->batch_start_offset; | |
3942 | exec2.batch_len = args->batch_len; | |
3943 | exec2.DR1 = args->DR1; | |
3944 | exec2.DR4 = args->DR4; | |
3945 | exec2.num_cliprects = args->num_cliprects; | |
3946 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 3947 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
3948 | |
3949 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
3950 | if (!ret) { | |
3951 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3952 | for (i = 0; i < args->buffer_count; i++) | |
3953 | exec_list[i].offset = exec2_list[i].offset; | |
3954 | /* ... and back out to userspace */ | |
3955 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3956 | (uintptr_t) args->buffers_ptr, | |
3957 | exec_list, | |
3958 | sizeof(*exec_list) * args->buffer_count); | |
3959 | if (ret) { | |
3960 | ret = -EFAULT; | |
3961 | DRM_ERROR("failed to copy %d exec entries " | |
3962 | "back to user (%d)\n", | |
3963 | args->buffer_count, ret); | |
3964 | } | |
76446cac JB |
3965 | } |
3966 | ||
3967 | drm_free_large(exec_list); | |
3968 | drm_free_large(exec2_list); | |
3969 | return ret; | |
3970 | } | |
3971 | ||
3972 | int | |
3973 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
3974 | struct drm_file *file_priv) | |
3975 | { | |
3976 | struct drm_i915_gem_execbuffer2 *args = data; | |
3977 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3978 | int ret; | |
3979 | ||
3980 | #if WATCH_EXEC | |
3981 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3982 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3983 | #endif | |
3984 | ||
3985 | if (args->buffer_count < 1) { | |
3986 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
3987 | return -EINVAL; | |
3988 | } | |
3989 | ||
3990 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3991 | if (exec2_list == NULL) { | |
3992 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3993 | args->buffer_count); | |
3994 | return -ENOMEM; | |
3995 | } | |
3996 | ret = copy_from_user(exec2_list, | |
3997 | (struct drm_i915_relocation_entry __user *) | |
3998 | (uintptr_t) args->buffers_ptr, | |
3999 | sizeof(*exec2_list) * args->buffer_count); | |
4000 | if (ret != 0) { | |
4001 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4002 | args->buffer_count, ret); | |
4003 | drm_free_large(exec2_list); | |
4004 | return -EFAULT; | |
4005 | } | |
4006 | ||
4007 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4008 | if (!ret) { | |
4009 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4010 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4011 | (uintptr_t) args->buffers_ptr, | |
4012 | exec2_list, | |
4013 | sizeof(*exec2_list) * args->buffer_count); | |
4014 | if (ret) { | |
4015 | ret = -EFAULT; | |
4016 | DRM_ERROR("failed to copy %d exec entries " | |
4017 | "back to user (%d)\n", | |
4018 | args->buffer_count, ret); | |
4019 | } | |
4020 | } | |
4021 | ||
4022 | drm_free_large(exec2_list); | |
4023 | return ret; | |
4024 | } | |
4025 | ||
673a394b EA |
4026 | int |
4027 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
4028 | { | |
4029 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4030 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4031 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4032 | int ret; |
4033 | ||
778c3544 DV |
4034 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
4035 | ||
673a394b | 4036 | i915_verify_inactive(dev, __FILE__, __LINE__); |
ac0c6b5a CW |
4037 | |
4038 | if (obj_priv->gtt_space != NULL) { | |
4039 | if (alignment == 0) | |
4040 | alignment = i915_gem_get_gtt_alignment(obj); | |
4041 | if (obj_priv->gtt_offset & (alignment - 1)) { | |
ae7d49d8 CW |
4042 | WARN(obj_priv->pin_count, |
4043 | "bo is already pinned with incorrect alignment:" | |
4044 | " offset=%x, req.alignment=%x\n", | |
4045 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4046 | ret = i915_gem_object_unbind(obj); |
4047 | if (ret) | |
4048 | return ret; | |
4049 | } | |
4050 | } | |
4051 | ||
673a394b EA |
4052 | if (obj_priv->gtt_space == NULL) { |
4053 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 4054 | if (ret) |
673a394b | 4055 | return ret; |
22c344e9 | 4056 | } |
76446cac | 4057 | |
673a394b EA |
4058 | obj_priv->pin_count++; |
4059 | ||
4060 | /* If the object is not active and not pending a flush, | |
4061 | * remove it from the inactive list | |
4062 | */ | |
4063 | if (obj_priv->pin_count == 1) { | |
4064 | atomic_inc(&dev->pin_count); | |
4065 | atomic_add(obj->size, &dev->pin_memory); | |
f13d3f73 CW |
4066 | if (!obj_priv->active) |
4067 | list_move_tail(&obj_priv->list, | |
4068 | &dev_priv->mm.pinned_list); | |
673a394b EA |
4069 | } |
4070 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4071 | ||
4072 | return 0; | |
4073 | } | |
4074 | ||
4075 | void | |
4076 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4077 | { | |
4078 | struct drm_device *dev = obj->dev; | |
4079 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4080 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4081 | |
4082 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4083 | obj_priv->pin_count--; | |
4084 | BUG_ON(obj_priv->pin_count < 0); | |
4085 | BUG_ON(obj_priv->gtt_space == NULL); | |
4086 | ||
4087 | /* If the object is no longer pinned, and is | |
4088 | * neither active nor being flushed, then stick it on | |
4089 | * the inactive list | |
4090 | */ | |
4091 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4092 | if (!obj_priv->active) |
673a394b EA |
4093 | list_move_tail(&obj_priv->list, |
4094 | &dev_priv->mm.inactive_list); | |
4095 | atomic_dec(&dev->pin_count); | |
4096 | atomic_sub(obj->size, &dev->pin_memory); | |
4097 | } | |
4098 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4099 | } | |
4100 | ||
4101 | int | |
4102 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4103 | struct drm_file *file_priv) | |
4104 | { | |
4105 | struct drm_i915_gem_pin *args = data; | |
4106 | struct drm_gem_object *obj; | |
4107 | struct drm_i915_gem_object *obj_priv; | |
4108 | int ret; | |
4109 | ||
4110 | mutex_lock(&dev->struct_mutex); | |
4111 | ||
4112 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4113 | if (obj == NULL) { | |
4114 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
4115 | args->handle); | |
4116 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 4117 | return -ENOENT; |
673a394b | 4118 | } |
23010e43 | 4119 | obj_priv = to_intel_bo(obj); |
673a394b | 4120 | |
bb6baf76 CW |
4121 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4122 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
4123 | drm_gem_object_unreference(obj); |
4124 | mutex_unlock(&dev->struct_mutex); | |
4125 | return -EINVAL; | |
4126 | } | |
4127 | ||
79e53945 JB |
4128 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4129 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4130 | args->handle); | |
96dec61d | 4131 | drm_gem_object_unreference(obj); |
673a394b | 4132 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
4133 | return -EINVAL; |
4134 | } | |
4135 | ||
4136 | obj_priv->user_pin_count++; | |
4137 | obj_priv->pin_filp = file_priv; | |
4138 | if (obj_priv->user_pin_count == 1) { | |
4139 | ret = i915_gem_object_pin(obj, args->alignment); | |
4140 | if (ret != 0) { | |
4141 | drm_gem_object_unreference(obj); | |
4142 | mutex_unlock(&dev->struct_mutex); | |
4143 | return ret; | |
4144 | } | |
673a394b EA |
4145 | } |
4146 | ||
4147 | /* XXX - flush the CPU caches for pinned objects | |
4148 | * as the X server doesn't manage domains yet | |
4149 | */ | |
e47c68e9 | 4150 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
4151 | args->offset = obj_priv->gtt_offset; |
4152 | drm_gem_object_unreference(obj); | |
4153 | mutex_unlock(&dev->struct_mutex); | |
4154 | ||
4155 | return 0; | |
4156 | } | |
4157 | ||
4158 | int | |
4159 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4160 | struct drm_file *file_priv) | |
4161 | { | |
4162 | struct drm_i915_gem_pin *args = data; | |
4163 | struct drm_gem_object *obj; | |
79e53945 | 4164 | struct drm_i915_gem_object *obj_priv; |
673a394b EA |
4165 | |
4166 | mutex_lock(&dev->struct_mutex); | |
4167 | ||
4168 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4169 | if (obj == NULL) { | |
4170 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
4171 | args->handle); | |
4172 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 4173 | return -ENOENT; |
673a394b EA |
4174 | } |
4175 | ||
23010e43 | 4176 | obj_priv = to_intel_bo(obj); |
79e53945 JB |
4177 | if (obj_priv->pin_filp != file_priv) { |
4178 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4179 | args->handle); | |
4180 | drm_gem_object_unreference(obj); | |
4181 | mutex_unlock(&dev->struct_mutex); | |
4182 | return -EINVAL; | |
4183 | } | |
4184 | obj_priv->user_pin_count--; | |
4185 | if (obj_priv->user_pin_count == 0) { | |
4186 | obj_priv->pin_filp = NULL; | |
4187 | i915_gem_object_unpin(obj); | |
4188 | } | |
673a394b EA |
4189 | |
4190 | drm_gem_object_unreference(obj); | |
4191 | mutex_unlock(&dev->struct_mutex); | |
4192 | return 0; | |
4193 | } | |
4194 | ||
4195 | int | |
4196 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4197 | struct drm_file *file_priv) | |
4198 | { | |
4199 | struct drm_i915_gem_busy *args = data; | |
4200 | struct drm_gem_object *obj; | |
4201 | struct drm_i915_gem_object *obj_priv; | |
4202 | ||
673a394b EA |
4203 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4204 | if (obj == NULL) { | |
4205 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4206 | args->handle); | |
bf79cb91 | 4207 | return -ENOENT; |
673a394b EA |
4208 | } |
4209 | ||
b1ce786c | 4210 | mutex_lock(&dev->struct_mutex); |
d1b851fc | 4211 | |
0be555b6 CW |
4212 | /* Count all active objects as busy, even if they are currently not used |
4213 | * by the gpu. Users of this interface expect objects to eventually | |
4214 | * become non-busy without any further actions, therefore emit any | |
4215 | * necessary flushes here. | |
c4de0a5d | 4216 | */ |
0be555b6 CW |
4217 | obj_priv = to_intel_bo(obj); |
4218 | args->busy = obj_priv->active; | |
4219 | if (args->busy) { | |
4220 | /* Unconditionally flush objects, even when the gpu still uses this | |
4221 | * object. Userspace calling this function indicates that it wants to | |
4222 | * use this buffer rather sooner than later, so issuing the required | |
4223 | * flush earlier is beneficial. | |
4224 | */ | |
c78ec30b CW |
4225 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4226 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4227 | obj_priv->ring, |
4228 | 0, obj->write_domain); | |
0be555b6 CW |
4229 | |
4230 | /* Update the active list for the hardware's current position. | |
4231 | * Otherwise this only updates on a delayed timer or when irqs | |
4232 | * are actually unmasked, and our working set ends up being | |
4233 | * larger than required. | |
4234 | */ | |
4235 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4236 | ||
4237 | args->busy = obj_priv->active; | |
4238 | } | |
673a394b EA |
4239 | |
4240 | drm_gem_object_unreference(obj); | |
4241 | mutex_unlock(&dev->struct_mutex); | |
4242 | return 0; | |
4243 | } | |
4244 | ||
4245 | int | |
4246 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4247 | struct drm_file *file_priv) | |
4248 | { | |
4249 | return i915_gem_ring_throttle(dev, file_priv); | |
4250 | } | |
4251 | ||
3ef94daa CW |
4252 | int |
4253 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4254 | struct drm_file *file_priv) | |
4255 | { | |
4256 | struct drm_i915_gem_madvise *args = data; | |
4257 | struct drm_gem_object *obj; | |
4258 | struct drm_i915_gem_object *obj_priv; | |
4259 | ||
4260 | switch (args->madv) { | |
4261 | case I915_MADV_DONTNEED: | |
4262 | case I915_MADV_WILLNEED: | |
4263 | break; | |
4264 | default: | |
4265 | return -EINVAL; | |
4266 | } | |
4267 | ||
4268 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4269 | if (obj == NULL) { | |
4270 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4271 | args->handle); | |
bf79cb91 | 4272 | return -ENOENT; |
3ef94daa CW |
4273 | } |
4274 | ||
4275 | mutex_lock(&dev->struct_mutex); | |
23010e43 | 4276 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4277 | |
4278 | if (obj_priv->pin_count) { | |
4279 | drm_gem_object_unreference(obj); | |
4280 | mutex_unlock(&dev->struct_mutex); | |
4281 | ||
4282 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4283 | return -EINVAL; | |
4284 | } | |
4285 | ||
bb6baf76 CW |
4286 | if (obj_priv->madv != __I915_MADV_PURGED) |
4287 | obj_priv->madv = args->madv; | |
3ef94daa | 4288 | |
2d7ef395 CW |
4289 | /* if the object is no longer bound, discard its backing storage */ |
4290 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4291 | obj_priv->gtt_space == NULL) | |
4292 | i915_gem_object_truncate(obj); | |
4293 | ||
bb6baf76 CW |
4294 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4295 | ||
3ef94daa CW |
4296 | drm_gem_object_unreference(obj); |
4297 | mutex_unlock(&dev->struct_mutex); | |
4298 | ||
4299 | return 0; | |
4300 | } | |
4301 | ||
ac52bc56 DV |
4302 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4303 | size_t size) | |
4304 | { | |
c397b908 | 4305 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4306 | |
c397b908 DV |
4307 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4308 | if (obj == NULL) | |
4309 | return NULL; | |
673a394b | 4310 | |
c397b908 DV |
4311 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4312 | kfree(obj); | |
4313 | return NULL; | |
4314 | } | |
673a394b | 4315 | |
c397b908 DV |
4316 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4317 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4318 | |
c397b908 | 4319 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4320 | obj->base.driver_private = NULL; |
c397b908 DV |
4321 | obj->fence_reg = I915_FENCE_REG_NONE; |
4322 | INIT_LIST_HEAD(&obj->list); | |
4323 | INIT_LIST_HEAD(&obj->gpu_write_list); | |
c397b908 | 4324 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4325 | |
c397b908 DV |
4326 | trace_i915_gem_object_create(&obj->base); |
4327 | ||
4328 | return &obj->base; | |
4329 | } | |
4330 | ||
4331 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4332 | { | |
4333 | BUG(); | |
de151cf6 | 4334 | |
673a394b EA |
4335 | return 0; |
4336 | } | |
4337 | ||
be72615b | 4338 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4339 | { |
de151cf6 | 4340 | struct drm_device *dev = obj->dev; |
be72615b | 4341 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4342 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4343 | int ret; |
673a394b | 4344 | |
be72615b CW |
4345 | ret = i915_gem_object_unbind(obj); |
4346 | if (ret == -ERESTARTSYS) { | |
4347 | list_move(&obj_priv->list, | |
4348 | &dev_priv->mm.deferred_free_list); | |
4349 | return; | |
4350 | } | |
673a394b | 4351 | |
7e616158 CW |
4352 | if (obj_priv->mmap_offset) |
4353 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4354 | |
c397b908 DV |
4355 | drm_gem_object_release(obj); |
4356 | ||
9a298b2a | 4357 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4358 | kfree(obj_priv->bit_17); |
c397b908 | 4359 | kfree(obj_priv); |
673a394b EA |
4360 | } |
4361 | ||
be72615b CW |
4362 | void i915_gem_free_object(struct drm_gem_object *obj) |
4363 | { | |
4364 | struct drm_device *dev = obj->dev; | |
4365 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4366 | ||
4367 | trace_i915_gem_object_destroy(obj); | |
4368 | ||
4369 | while (obj_priv->pin_count > 0) | |
4370 | i915_gem_object_unpin(obj); | |
4371 | ||
4372 | if (obj_priv->phys_obj) | |
4373 | i915_gem_detach_phys_object(dev, obj); | |
4374 | ||
4375 | i915_gem_free_object_tail(obj); | |
4376 | } | |
4377 | ||
29105ccc CW |
4378 | int |
4379 | i915_gem_idle(struct drm_device *dev) | |
4380 | { | |
4381 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4382 | int ret; | |
28dfe52a | 4383 | |
29105ccc | 4384 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4385 | |
8187a2b7 | 4386 | if (dev_priv->mm.suspended || |
d1b851fc ZN |
4387 | (dev_priv->render_ring.gem_object == NULL) || |
4388 | (HAS_BSD(dev) && | |
4389 | dev_priv->bsd_ring.gem_object == NULL)) { | |
29105ccc CW |
4390 | mutex_unlock(&dev->struct_mutex); |
4391 | return 0; | |
28dfe52a EA |
4392 | } |
4393 | ||
29105ccc | 4394 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4395 | if (ret) { |
4396 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4397 | return ret; |
6dbe2772 | 4398 | } |
673a394b | 4399 | |
29105ccc CW |
4400 | /* Under UMS, be paranoid and evict. */ |
4401 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4402 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4403 | if (ret) { |
4404 | mutex_unlock(&dev->struct_mutex); | |
4405 | return ret; | |
4406 | } | |
4407 | } | |
4408 | ||
4409 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4410 | * We need to replace this with a semaphore, or something. | |
4411 | * And not confound mm.suspended! | |
4412 | */ | |
4413 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4414 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4415 | |
4416 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4417 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4418 | |
6dbe2772 KP |
4419 | mutex_unlock(&dev->struct_mutex); |
4420 | ||
29105ccc CW |
4421 | /* Cancel the retire work handler, which should be idle now. */ |
4422 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4423 | ||
673a394b EA |
4424 | return 0; |
4425 | } | |
4426 | ||
e552eb70 JB |
4427 | /* |
4428 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4429 | * over cache flushing. | |
4430 | */ | |
8187a2b7 | 4431 | static int |
e552eb70 JB |
4432 | i915_gem_init_pipe_control(struct drm_device *dev) |
4433 | { | |
4434 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4435 | struct drm_gem_object *obj; | |
4436 | struct drm_i915_gem_object *obj_priv; | |
4437 | int ret; | |
4438 | ||
34dc4d44 | 4439 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4440 | if (obj == NULL) { |
4441 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4442 | ret = -ENOMEM; | |
4443 | goto err; | |
4444 | } | |
4445 | obj_priv = to_intel_bo(obj); | |
4446 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4447 | ||
4448 | ret = i915_gem_object_pin(obj, 4096); | |
4449 | if (ret) | |
4450 | goto err_unref; | |
4451 | ||
4452 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4453 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4454 | if (dev_priv->seqno_page == NULL) | |
4455 | goto err_unpin; | |
4456 | ||
4457 | dev_priv->seqno_obj = obj; | |
4458 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4459 | ||
4460 | return 0; | |
4461 | ||
4462 | err_unpin: | |
4463 | i915_gem_object_unpin(obj); | |
4464 | err_unref: | |
4465 | drm_gem_object_unreference(obj); | |
4466 | err: | |
4467 | return ret; | |
4468 | } | |
4469 | ||
8187a2b7 ZN |
4470 | |
4471 | static void | |
e552eb70 JB |
4472 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4473 | { | |
4474 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4475 | struct drm_gem_object *obj; | |
4476 | struct drm_i915_gem_object *obj_priv; | |
4477 | ||
4478 | obj = dev_priv->seqno_obj; | |
4479 | obj_priv = to_intel_bo(obj); | |
4480 | kunmap(obj_priv->pages[0]); | |
4481 | i915_gem_object_unpin(obj); | |
4482 | drm_gem_object_unreference(obj); | |
4483 | dev_priv->seqno_obj = NULL; | |
4484 | ||
4485 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4486 | } |
4487 | ||
8187a2b7 ZN |
4488 | int |
4489 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4490 | { | |
4491 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4492 | int ret; | |
68f95ba9 | 4493 | |
8187a2b7 ZN |
4494 | if (HAS_PIPE_CONTROL(dev)) { |
4495 | ret = i915_gem_init_pipe_control(dev); | |
4496 | if (ret) | |
4497 | return ret; | |
4498 | } | |
68f95ba9 | 4499 | |
5c1143bb | 4500 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4501 | if (ret) |
4502 | goto cleanup_pipe_control; | |
4503 | ||
4504 | if (HAS_BSD(dev)) { | |
5c1143bb | 4505 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4506 | if (ret) |
4507 | goto cleanup_render_ring; | |
d1b851fc | 4508 | } |
68f95ba9 | 4509 | |
6f392d54 CW |
4510 | dev_priv->next_seqno = 1; |
4511 | ||
68f95ba9 CW |
4512 | return 0; |
4513 | ||
4514 | cleanup_render_ring: | |
4515 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
4516 | cleanup_pipe_control: | |
4517 | if (HAS_PIPE_CONTROL(dev)) | |
4518 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4519 | return ret; |
4520 | } | |
4521 | ||
4522 | void | |
4523 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4524 | { | |
4525 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4526 | ||
4527 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4528 | if (HAS_BSD(dev)) |
4529 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
8187a2b7 ZN |
4530 | if (HAS_PIPE_CONTROL(dev)) |
4531 | i915_gem_cleanup_pipe_control(dev); | |
4532 | } | |
4533 | ||
673a394b EA |
4534 | int |
4535 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4536 | struct drm_file *file_priv) | |
4537 | { | |
4538 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4539 | int ret; | |
4540 | ||
79e53945 JB |
4541 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4542 | return 0; | |
4543 | ||
ba1234d1 | 4544 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4545 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4546 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4547 | } |
4548 | ||
673a394b | 4549 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4550 | dev_priv->mm.suspended = 0; |
4551 | ||
4552 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4553 | if (ret != 0) { |
4554 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4555 | return ret; |
d816f6ac | 4556 | } |
9bb2d6f9 | 4557 | |
852835f3 | 4558 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
d1b851fc | 4559 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
673a394b EA |
4560 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4561 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4562 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
d1b851fc | 4563 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
673a394b | 4564 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4565 | |
5f35308b CW |
4566 | ret = drm_irq_install(dev); |
4567 | if (ret) | |
4568 | goto cleanup_ringbuffer; | |
dbb19d30 | 4569 | |
673a394b | 4570 | return 0; |
5f35308b CW |
4571 | |
4572 | cleanup_ringbuffer: | |
4573 | mutex_lock(&dev->struct_mutex); | |
4574 | i915_gem_cleanup_ringbuffer(dev); | |
4575 | dev_priv->mm.suspended = 1; | |
4576 | mutex_unlock(&dev->struct_mutex); | |
4577 | ||
4578 | return ret; | |
673a394b EA |
4579 | } |
4580 | ||
4581 | int | |
4582 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4583 | struct drm_file *file_priv) | |
4584 | { | |
79e53945 JB |
4585 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4586 | return 0; | |
4587 | ||
dbb19d30 | 4588 | drm_irq_uninstall(dev); |
e6890f6f | 4589 | return i915_gem_idle(dev); |
673a394b EA |
4590 | } |
4591 | ||
4592 | void | |
4593 | i915_gem_lastclose(struct drm_device *dev) | |
4594 | { | |
4595 | int ret; | |
673a394b | 4596 | |
e806b495 EA |
4597 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4598 | return; | |
4599 | ||
6dbe2772 KP |
4600 | ret = i915_gem_idle(dev); |
4601 | if (ret) | |
4602 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4603 | } |
4604 | ||
4605 | void | |
4606 | i915_gem_load(struct drm_device *dev) | |
4607 | { | |
b5aa8a0f | 4608 | int i; |
673a394b EA |
4609 | drm_i915_private_t *dev_priv = dev->dev_private; |
4610 | ||
673a394b | 4611 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
99fcb766 | 4612 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
673a394b | 4613 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
f13d3f73 | 4614 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4615 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4616 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
852835f3 ZN |
4617 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
4618 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); | |
d1b851fc ZN |
4619 | if (HAS_BSD(dev)) { |
4620 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); | |
4621 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); | |
4622 | } | |
007cc8ac DV |
4623 | for (i = 0; i < 16; i++) |
4624 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4625 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4626 | i915_gem_retire_work_handler); | |
31169714 CW |
4627 | spin_lock(&shrink_list_lock); |
4628 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4629 | spin_unlock(&shrink_list_lock); | |
4630 | ||
94400120 DA |
4631 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4632 | if (IS_GEN3(dev)) { | |
4633 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4634 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4635 | /* arb state is a masked write, so set bit + bit in mask */ | |
4636 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4637 | I915_WRITE(MI_ARB_STATE, tmp); | |
4638 | } | |
4639 | } | |
4640 | ||
de151cf6 | 4641 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4642 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4643 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4644 | |
a6c45cf0 | 4645 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4646 | dev_priv->num_fence_regs = 16; |
4647 | else | |
4648 | dev_priv->num_fence_regs = 8; | |
4649 | ||
b5aa8a0f | 4650 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4651 | switch (INTEL_INFO(dev)->gen) { |
4652 | case 6: | |
4653 | for (i = 0; i < 16; i++) | |
4654 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4655 | break; | |
4656 | case 5: | |
4657 | case 4: | |
b5aa8a0f GH |
4658 | for (i = 0; i < 16; i++) |
4659 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4660 | break; |
4661 | case 3: | |
b5aa8a0f GH |
4662 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4663 | for (i = 0; i < 8; i++) | |
4664 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4665 | case 2: |
4666 | for (i = 0; i < 8; i++) | |
4667 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4668 | break; | |
b5aa8a0f | 4669 | } |
673a394b | 4670 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4671 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4672 | } |
71acb5eb DA |
4673 | |
4674 | /* | |
4675 | * Create a physically contiguous memory object for this object | |
4676 | * e.g. for cursor + overlay regs | |
4677 | */ | |
995b6762 CW |
4678 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4679 | int id, int size, int align) | |
71acb5eb DA |
4680 | { |
4681 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4682 | struct drm_i915_gem_phys_object *phys_obj; | |
4683 | int ret; | |
4684 | ||
4685 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4686 | return 0; | |
4687 | ||
9a298b2a | 4688 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4689 | if (!phys_obj) |
4690 | return -ENOMEM; | |
4691 | ||
4692 | phys_obj->id = id; | |
4693 | ||
6eeefaf3 | 4694 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4695 | if (!phys_obj->handle) { |
4696 | ret = -ENOMEM; | |
4697 | goto kfree_obj; | |
4698 | } | |
4699 | #ifdef CONFIG_X86 | |
4700 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4701 | #endif | |
4702 | ||
4703 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4704 | ||
4705 | return 0; | |
4706 | kfree_obj: | |
9a298b2a | 4707 | kfree(phys_obj); |
71acb5eb DA |
4708 | return ret; |
4709 | } | |
4710 | ||
995b6762 | 4711 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4712 | { |
4713 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4714 | struct drm_i915_gem_phys_object *phys_obj; | |
4715 | ||
4716 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4717 | return; | |
4718 | ||
4719 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4720 | if (phys_obj->cur_obj) { | |
4721 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4722 | } | |
4723 | ||
4724 | #ifdef CONFIG_X86 | |
4725 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4726 | #endif | |
4727 | drm_pci_free(dev, phys_obj->handle); | |
4728 | kfree(phys_obj); | |
4729 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4730 | } | |
4731 | ||
4732 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4733 | { | |
4734 | int i; | |
4735 | ||
260883c8 | 4736 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4737 | i915_gem_free_phys_object(dev, i); |
4738 | } | |
4739 | ||
4740 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4741 | struct drm_gem_object *obj) | |
4742 | { | |
4743 | struct drm_i915_gem_object *obj_priv; | |
4744 | int i; | |
4745 | int ret; | |
4746 | int page_count; | |
4747 | ||
23010e43 | 4748 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4749 | if (!obj_priv->phys_obj) |
4750 | return; | |
4751 | ||
4bdadb97 | 4752 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4753 | if (ret) |
4754 | goto out; | |
4755 | ||
4756 | page_count = obj->size / PAGE_SIZE; | |
4757 | ||
4758 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4759 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4760 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4761 | ||
4762 | memcpy(dst, src, PAGE_SIZE); | |
4763 | kunmap_atomic(dst, KM_USER0); | |
4764 | } | |
856fa198 | 4765 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4766 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4767 | |
4768 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4769 | out: |
4770 | obj_priv->phys_obj->cur_obj = NULL; | |
4771 | obj_priv->phys_obj = NULL; | |
4772 | } | |
4773 | ||
4774 | int | |
4775 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4776 | struct drm_gem_object *obj, |
4777 | int id, | |
4778 | int align) | |
71acb5eb DA |
4779 | { |
4780 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4781 | struct drm_i915_gem_object *obj_priv; | |
4782 | int ret = 0; | |
4783 | int page_count; | |
4784 | int i; | |
4785 | ||
4786 | if (id > I915_MAX_PHYS_OBJECT) | |
4787 | return -EINVAL; | |
4788 | ||
23010e43 | 4789 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4790 | |
4791 | if (obj_priv->phys_obj) { | |
4792 | if (obj_priv->phys_obj->id == id) | |
4793 | return 0; | |
4794 | i915_gem_detach_phys_object(dev, obj); | |
4795 | } | |
4796 | ||
71acb5eb DA |
4797 | /* create a new object */ |
4798 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4799 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4800 | obj->size, align); |
71acb5eb | 4801 | if (ret) { |
aeb565df | 4802 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4803 | goto out; |
4804 | } | |
4805 | } | |
4806 | ||
4807 | /* bind to the object */ | |
4808 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4809 | obj_priv->phys_obj->cur_obj = obj; | |
4810 | ||
4bdadb97 | 4811 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4812 | if (ret) { |
4813 | DRM_ERROR("failed to get page list\n"); | |
4814 | goto out; | |
4815 | } | |
4816 | ||
4817 | page_count = obj->size / PAGE_SIZE; | |
4818 | ||
4819 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4820 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4821 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4822 | ||
4823 | memcpy(dst, src, PAGE_SIZE); | |
4824 | kunmap_atomic(src, KM_USER0); | |
4825 | } | |
4826 | ||
d78b47b9 CW |
4827 | i915_gem_object_put_pages(obj); |
4828 | ||
71acb5eb DA |
4829 | return 0; |
4830 | out: | |
4831 | return ret; | |
4832 | } | |
4833 | ||
4834 | static int | |
4835 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4836 | struct drm_i915_gem_pwrite *args, | |
4837 | struct drm_file *file_priv) | |
4838 | { | |
23010e43 | 4839 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4840 | void *obj_addr; |
4841 | int ret; | |
4842 | char __user *user_data; | |
4843 | ||
4844 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4845 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4846 | ||
44d98a61 | 4847 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4848 | ret = copy_from_user(obj_addr, user_data, args->size); |
4849 | if (ret) | |
4850 | return -EFAULT; | |
4851 | ||
4852 | drm_agp_chipset_flush(dev); | |
4853 | return 0; | |
4854 | } | |
b962442e EA |
4855 | |
4856 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) | |
4857 | { | |
4858 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
4859 | ||
4860 | /* Clean up our request list when the client is going away, so that | |
4861 | * later retire_requests won't dereference our soon-to-be-gone | |
4862 | * file_priv. | |
4863 | */ | |
4864 | mutex_lock(&dev->struct_mutex); | |
4865 | while (!list_empty(&i915_file_priv->mm.request_list)) | |
4866 | list_del_init(i915_file_priv->mm.request_list.next); | |
4867 | mutex_unlock(&dev->struct_mutex); | |
4868 | } | |
31169714 | 4869 | |
1637ef41 CW |
4870 | static int |
4871 | i915_gpu_is_active(struct drm_device *dev) | |
4872 | { | |
4873 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4874 | int lists_empty; | |
4875 | ||
1637ef41 | 4876 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
852835f3 | 4877 | list_empty(&dev_priv->render_ring.active_list); |
d1b851fc ZN |
4878 | if (HAS_BSD(dev)) |
4879 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); | |
1637ef41 CW |
4880 | |
4881 | return !lists_empty; | |
4882 | } | |
4883 | ||
31169714 | 4884 | static int |
7f8275d0 | 4885 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
4886 | { |
4887 | drm_i915_private_t *dev_priv, *next_dev; | |
4888 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4889 | int cnt = 0; | |
4890 | int would_deadlock = 1; | |
4891 | ||
4892 | /* "fast-path" to count number of available objects */ | |
4893 | if (nr_to_scan == 0) { | |
4894 | spin_lock(&shrink_list_lock); | |
4895 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4896 | struct drm_device *dev = dev_priv->dev; | |
4897 | ||
4898 | if (mutex_trylock(&dev->struct_mutex)) { | |
4899 | list_for_each_entry(obj_priv, | |
4900 | &dev_priv->mm.inactive_list, | |
4901 | list) | |
4902 | cnt++; | |
4903 | mutex_unlock(&dev->struct_mutex); | |
4904 | } | |
4905 | } | |
4906 | spin_unlock(&shrink_list_lock); | |
4907 | ||
4908 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4909 | } | |
4910 | ||
4911 | spin_lock(&shrink_list_lock); | |
4912 | ||
1637ef41 | 4913 | rescan: |
31169714 CW |
4914 | /* first scan for clean buffers */ |
4915 | list_for_each_entry_safe(dev_priv, next_dev, | |
4916 | &shrink_list, mm.shrink_list) { | |
4917 | struct drm_device *dev = dev_priv->dev; | |
4918 | ||
4919 | if (! mutex_trylock(&dev->struct_mutex)) | |
4920 | continue; | |
4921 | ||
4922 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 4923 | i915_gem_retire_requests(dev); |
31169714 CW |
4924 | |
4925 | list_for_each_entry_safe(obj_priv, next_obj, | |
4926 | &dev_priv->mm.inactive_list, | |
4927 | list) { | |
4928 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
a8089e84 | 4929 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4930 | if (--nr_to_scan <= 0) |
4931 | break; | |
4932 | } | |
4933 | } | |
4934 | ||
4935 | spin_lock(&shrink_list_lock); | |
4936 | mutex_unlock(&dev->struct_mutex); | |
4937 | ||
963b4836 CW |
4938 | would_deadlock = 0; |
4939 | ||
31169714 CW |
4940 | if (nr_to_scan <= 0) |
4941 | break; | |
4942 | } | |
4943 | ||
4944 | /* second pass, evict/count anything still on the inactive list */ | |
4945 | list_for_each_entry_safe(dev_priv, next_dev, | |
4946 | &shrink_list, mm.shrink_list) { | |
4947 | struct drm_device *dev = dev_priv->dev; | |
4948 | ||
4949 | if (! mutex_trylock(&dev->struct_mutex)) | |
4950 | continue; | |
4951 | ||
4952 | spin_unlock(&shrink_list_lock); | |
4953 | ||
4954 | list_for_each_entry_safe(obj_priv, next_obj, | |
4955 | &dev_priv->mm.inactive_list, | |
4956 | list) { | |
4957 | if (nr_to_scan > 0) { | |
a8089e84 | 4958 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4959 | nr_to_scan--; |
4960 | } else | |
4961 | cnt++; | |
4962 | } | |
4963 | ||
4964 | spin_lock(&shrink_list_lock); | |
4965 | mutex_unlock(&dev->struct_mutex); | |
4966 | ||
4967 | would_deadlock = 0; | |
4968 | } | |
4969 | ||
1637ef41 CW |
4970 | if (nr_to_scan) { |
4971 | int active = 0; | |
4972 | ||
4973 | /* | |
4974 | * We are desperate for pages, so as a last resort, wait | |
4975 | * for the GPU to finish and discard whatever we can. | |
4976 | * This has a dramatic impact to reduce the number of | |
4977 | * OOM-killer events whilst running the GPU aggressively. | |
4978 | */ | |
4979 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4980 | struct drm_device *dev = dev_priv->dev; | |
4981 | ||
4982 | if (!mutex_trylock(&dev->struct_mutex)) | |
4983 | continue; | |
4984 | ||
4985 | spin_unlock(&shrink_list_lock); | |
4986 | ||
4987 | if (i915_gpu_is_active(dev)) { | |
4988 | i915_gpu_idle(dev); | |
4989 | active++; | |
4990 | } | |
4991 | ||
4992 | spin_lock(&shrink_list_lock); | |
4993 | mutex_unlock(&dev->struct_mutex); | |
4994 | } | |
4995 | ||
4996 | if (active) | |
4997 | goto rescan; | |
4998 | } | |
4999 | ||
31169714 CW |
5000 | spin_unlock(&shrink_list_lock); |
5001 | ||
5002 | if (would_deadlock) | |
5003 | return -1; | |
5004 | else if (cnt > 0) | |
5005 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5006 | else | |
5007 | return 0; | |
5008 | } | |
5009 | ||
5010 | static struct shrinker shrinker = { | |
5011 | .shrink = i915_gem_shrink, | |
5012 | .seeks = DEFAULT_SEEKS, | |
5013 | }; | |
5014 | ||
5015 | __init void | |
5016 | i915_gem_shrinker_init(void) | |
5017 | { | |
5018 | register_shrinker(&shrinker); | |
5019 | } | |
5020 | ||
5021 | __exit void | |
5022 | i915_gem_shrinker_exit(void) | |
5023 | { | |
5024 | unregister_shrinker(&shrinker); | |
5025 | } |