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drm/i915: kill a no longer necessary BUG_ON
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
f8f235e5 37#include <linux/intel-gtt.h>
673a394b 38
0108a3ed 39static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
2dafb1e0 40static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 41static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 43static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 int write);
45static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 uint64_t offset,
47 uint64_t size);
48static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
e35a41de
DV		 49static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
50 bool interruptible);
de151cf6
JB		 51static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
52 unsigned alignment);
de151cf6 53static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
71acb5eb
DA		 54static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
be72615b 57static void i915_gem_free_object_tail(struct drm_gem_object *obj);
673a394b 58
31169714
CW		 59static LIST_HEAD(shrink_list);
60static DEFINE_SPINLOCK(shrink_list_lock);
61
7d1c4804
CW		 62static inline bool
63i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
64{
65 return obj_priv->gtt_space &&
66 !obj_priv->active &&
67 obj_priv->pin_count == 0;
68}
69
79e53945
JB		 70int i915_gem_do_init(struct drm_device *dev, unsigned long start,
71 unsigned long end)
673a394b
EA		 72{
73 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 74
79e53945
JB		 75 if (start >= end ||
76 (start & (PAGE_SIZE - 1)) != 0 ||
77 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 78 return -EINVAL;
79 }
80
79e53945
JB		 81 drm_mm_init(&dev_priv->mm.gtt_space, start,
82 end - start);
673a394b 83
79e53945
JB		 84 dev->gtt_total = (uint32_t) (end - start);
85
86 return 0;
87}
673a394b 88
79e53945
JB		 89int
90i915_gem_init_ioctl(struct drm_device *dev, void *data,
91 struct drm_file *file_priv)
92{
93 struct drm_i915_gem_init *args = data;
94 int ret;
95
96 mutex_lock(&dev->struct_mutex);
97 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 98 mutex_unlock(&dev->struct_mutex);
99
79e53945 100 return ret;
673a394b
EA		 101}
102
5a125c3c
EA		 103int
104i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
105 struct drm_file *file_priv)
106{
5a125c3c 107 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 108
109 if (!(dev->driver->driver_features & DRIVER_GEM))
110 return -ENODEV;
111
112 args->aper_size = dev->gtt_total;
2678d9d6
KP		 113 args->aper_available_size = (args->aper_size -
114 atomic_read(&dev->pin_memory));
5a125c3c
EA		 115
116 return 0;
117}
118
673a394b
EA		 119
120/**
121 * Creates a new mm object and returns a handle to it.
122 */
123int
124i915_gem_create_ioctl(struct drm_device *dev, void *data,
125 struct drm_file *file_priv)
126{
127 struct drm_i915_gem_create *args = data;
128 struct drm_gem_object *obj;
a1a2d1d3
PP		 129 int ret;
130 u32 handle;
673a394b
EA		 131
132 args->size = roundup(args->size, PAGE_SIZE);
133
134 /* Allocate the new object */
ac52bc56 135 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 136 if (obj == NULL)
137 return -ENOMEM;
138
139 ret = drm_gem_handle_create(file_priv, obj, &handle);
1dfd9754
CW		 140 if (ret) {
141 drm_gem_object_unreference_unlocked(obj);
673a394b 142 return ret;
1dfd9754 143 }
673a394b 144
1dfd9754
CW		 145 /* Sink the floating reference from kref_init(handlecount) */
146 drm_gem_object_handle_unreference_unlocked(obj);
673a394b 147
1dfd9754 148 args->handle = handle;
673a394b
EA		 149 return 0;
150}
151
eb01459f
EA		 152static inline int
153fast_shmem_read(struct page **pages,
154 loff_t page_base, int page_offset,
155 char __user *data,
156 int length)
157{
158 char __iomem *vaddr;
2bc43b5c 159 int unwritten;
eb01459f
EA		 160
161 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
162 if (vaddr == NULL)
163 return -ENOMEM;
2bc43b5c 164 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 165 kunmap_atomic(vaddr, KM_USER0);
166
2bc43b5c
FM		 167 if (unwritten)
168 return -EFAULT;
169
170 return 0;
eb01459f
EA		 171}
172
280b713b
EA		 173static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
174{
175 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 176 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 177
178 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
179 obj_priv->tiling_mode != I915_TILING_NONE;
180}
181
99a03df5 182static inline void
40123c1f
EA		 183slow_shmem_copy(struct page *dst_page,
184 int dst_offset,
185 struct page *src_page,
186 int src_offset,
187 int length)
188{
189 char *dst_vaddr, *src_vaddr;
190
99a03df5
CW		 191 dst_vaddr = kmap(dst_page);
192 src_vaddr = kmap(src_page);
40123c1f
EA		 193
194 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
195
99a03df5
CW		 196 kunmap(src_page);
197 kunmap(dst_page);
40123c1f
EA		 198}
199
99a03df5 200static inline void
280b713b
EA		 201slow_shmem_bit17_copy(struct page *gpu_page,
202 int gpu_offset,
203 struct page *cpu_page,
204 int cpu_offset,
205 int length,
206 int is_read)
207{
208 char *gpu_vaddr, *cpu_vaddr;
209
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 if (is_read)
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
215 else
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
218 }
219
99a03df5
CW		 220 gpu_vaddr = kmap(gpu_page);
221 cpu_vaddr = kmap(cpu_page);
280b713b
EA		 222
223 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
224 * XORing with the other bits (A9 for Y, A9 and A10 for X)
225 */
226 while (length > 0) {
227 int cacheline_end = ALIGN(gpu_offset + 1, 64);
228 int this_length = min(cacheline_end - gpu_offset, length);
229 int swizzled_gpu_offset = gpu_offset ^ 64;
230
231 if (is_read) {
232 memcpy(cpu_vaddr + cpu_offset,
233 gpu_vaddr + swizzled_gpu_offset,
234 this_length);
235 } else {
236 memcpy(gpu_vaddr + swizzled_gpu_offset,
237 cpu_vaddr + cpu_offset,
238 this_length);
239 }
240 cpu_offset += this_length;
241 gpu_offset += this_length;
242 length -= this_length;
243 }
244
99a03df5
CW		 245 kunmap(cpu_page);
246 kunmap(gpu_page);
280b713b
EA		 247}
248
eb01459f
EA		 249/**
250 * This is the fast shmem pread path, which attempts to copy_from_user directly
251 * from the backing pages of the object to the user's address space. On a
252 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
253 */
254static int
255i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
256 struct drm_i915_gem_pread *args,
257 struct drm_file *file_priv)
258{
23010e43 259 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 260 ssize_t remain;
261 loff_t offset, page_base;
262 char __user *user_data;
263 int page_offset, page_length;
264 int ret;
265
266 user_data = (char __user *) (uintptr_t) args->data_ptr;
267 remain = args->size;
268
269 mutex_lock(&dev->struct_mutex);
270
4bdadb97 271 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 272 if (ret != 0)
273 goto fail_unlock;
274
275 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
276 args->size);
277 if (ret != 0)
278 goto fail_put_pages;
279
23010e43 280 obj_priv = to_intel_bo(obj);
eb01459f
EA		 281 offset = args->offset;
282
283 while (remain > 0) {
284 /* Operation in this page
285 *
286 * page_base = page offset within aperture
287 * page_offset = offset within page
288 * page_length = bytes to copy for this page
289 */
290 page_base = (offset & ~(PAGE_SIZE-1));
291 page_offset = offset & (PAGE_SIZE-1);
292 page_length = remain;
293 if ((page_offset + remain) > PAGE_SIZE)
294 page_length = PAGE_SIZE - page_offset;
295
296 ret = fast_shmem_read(obj_priv->pages,
297 page_base, page_offset,
298 user_data, page_length);
299 if (ret)
300 goto fail_put_pages;
301
302 remain -= page_length;
303 user_data += page_length;
304 offset += page_length;
305 }
306
307fail_put_pages:
308 i915_gem_object_put_pages(obj);
309fail_unlock:
310 mutex_unlock(&dev->struct_mutex);
311
312 return ret;
313}
314
07f73f69
CW		 315static int
316i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
317{
318 int ret;
319
4bdadb97 320 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 321
322 /* If we've insufficient memory to map in the pages, attempt
323 * to make some space by throwing out some old buffers.
324 */
325 if (ret == -ENOMEM) {
326 struct drm_device *dev = obj->dev;
07f73f69 327
0108a3ed
DV		 328 ret = i915_gem_evict_something(dev, obj->size,
329 i915_gem_get_gtt_alignment(obj));
07f73f69
CW		 330 if (ret)
331 return ret;
332
4bdadb97 333 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 334 }
335
336 return ret;
337}
338
eb01459f
EA		 339/**
340 * This is the fallback shmem pread path, which allocates temporary storage
341 * in kernel space to copy_to_user into outside of the struct_mutex, so we
342 * can copy out of the object's backing pages while holding the struct mutex
343 * and not take page faults.
344 */
345static int
346i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
347 struct drm_i915_gem_pread *args,
348 struct drm_file *file_priv)
349{
23010e43 350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 351 struct mm_struct *mm = current->mm;
352 struct page **user_pages;
353 ssize_t remain;
354 loff_t offset, pinned_pages, i;
355 loff_t first_data_page, last_data_page, num_pages;
356 int shmem_page_index, shmem_page_offset;
357 int data_page_index, data_page_offset;
358 int page_length;
359 int ret;
360 uint64_t data_ptr = args->data_ptr;
280b713b 361 int do_bit17_swizzling;
eb01459f
EA		 362
363 remain = args->size;
364
365 /* Pin the user pages containing the data. We can't fault while
366 * holding the struct mutex, yet we want to hold it while
367 * dereferencing the user data.
368 */
369 first_data_page = data_ptr / PAGE_SIZE;
370 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
371 num_pages = last_data_page - first_data_page + 1;
372
8e7d2b2c 373 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 374 if (user_pages == NULL)
375 return -ENOMEM;
376
377 down_read(&mm->mmap_sem);
378 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 379 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 380 up_read(&mm->mmap_sem);
381 if (pinned_pages < num_pages) {
382 ret = -EFAULT;
383 goto fail_put_user_pages;
384 }
385
280b713b
EA		 386 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
387
eb01459f
EA		 388 mutex_lock(&dev->struct_mutex);
389
07f73f69
CW		 390 ret = i915_gem_object_get_pages_or_evict(obj);
391 if (ret)
eb01459f
EA		 392 goto fail_unlock;
393
394 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
395 args->size);
396 if (ret != 0)
397 goto fail_put_pages;
398
23010e43 399 obj_priv = to_intel_bo(obj);
eb01459f
EA		 400 offset = args->offset;
401
402 while (remain > 0) {
403 /* Operation in this page
404 *
405 * shmem_page_index = page number within shmem file
406 * shmem_page_offset = offset within page in shmem file
407 * data_page_index = page number in get_user_pages return
408 * data_page_offset = offset with data_page_index page.
409 * page_length = bytes to copy for this page
410 */
411 shmem_page_index = offset / PAGE_SIZE;
412 shmem_page_offset = offset & ~PAGE_MASK;
413 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
414 data_page_offset = data_ptr & ~PAGE_MASK;
415
416 page_length = remain;
417 if ((shmem_page_offset + page_length) > PAGE_SIZE)
418 page_length = PAGE_SIZE - shmem_page_offset;
419 if ((data_page_offset + page_length) > PAGE_SIZE)
420 page_length = PAGE_SIZE - data_page_offset;
421
280b713b 422 if (do_bit17_swizzling) {
99a03df5 423 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b 424 shmem_page_offset,
99a03df5
CW		 425 user_pages[data_page_index],
426 data_page_offset,
427 page_length,
428 1);
429 } else {
430 slow_shmem_copy(user_pages[data_page_index],
431 data_page_offset,
432 obj_priv->pages[shmem_page_index],
433 shmem_page_offset,
434 page_length);
280b713b 435 }
eb01459f
EA		 436
437 remain -= page_length;
438 data_ptr += page_length;
439 offset += page_length;
440 }
441
442fail_put_pages:
443 i915_gem_object_put_pages(obj);
444fail_unlock:
445 mutex_unlock(&dev->struct_mutex);
446fail_put_user_pages:
447 for (i = 0; i < pinned_pages; i++) {
448 SetPageDirty(user_pages[i]);
449 page_cache_release(user_pages[i]);
450 }
8e7d2b2c 451 drm_free_large(user_pages);
eb01459f
EA		 452
453 return ret;
454}
455
673a394b
EA		 456/**
457 * Reads data from the object referenced by handle.
458 *
459 * On error, the contents of *data are undefined.
460 */
461int
462i915_gem_pread_ioctl(struct drm_device *dev, void *data,
463 struct drm_file *file_priv)
464{
465 struct drm_i915_gem_pread *args = data;
466 struct drm_gem_object *obj;
467 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 468 int ret;
469
470 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
471 if (obj == NULL)
bf79cb91 472 return -ENOENT;
23010e43 473 obj_priv = to_intel_bo(obj);
673a394b
EA		 474
475 /* Bounds check source.
476 *
477 * XXX: This could use review for overflow issues...
478 */
479 if (args->offset > obj->size || args->size > obj->size ||
480 args->offset + args->size > obj->size) {
bc9025bd 481 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 482 return -EINVAL;
483 }
484
280b713b 485 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 486 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 487 } else {
488 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
489 if (ret != 0)
490 ret = i915_gem_shmem_pread_slow(dev, obj, args,
491 file_priv);
492 }
673a394b 493
bc9025bd 494 drm_gem_object_unreference_unlocked(obj);
673a394b 495
eb01459f 496 return ret;
673a394b
EA		 497}
498
0839ccb8
KP		 499/* This is the fast write path which cannot handle
500 * page faults in the source data
9b7530cc 501 */
0839ccb8
KP		 502
503static inline int
504fast_user_write(struct io_mapping *mapping,
505 loff_t page_base, int page_offset,
506 char __user *user_data,
507 int length)
9b7530cc 508{
9b7530cc 509 char *vaddr_atomic;
0839ccb8 510 unsigned long unwritten;
9b7530cc 511
fca3ec01 512 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
0839ccb8
KP		 513 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
514 user_data, length);
fca3ec01 515 io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
0839ccb8
KP		 516 if (unwritten)
517 return -EFAULT;
518 return 0;
519}
520
521/* Here's the write path which can sleep for
522 * page faults
523 */
524
ab34c226 525static inline void
3de09aa3
EA		 526slow_kernel_write(struct io_mapping *mapping,
527 loff_t gtt_base, int gtt_offset,
528 struct page *user_page, int user_offset,
529 int length)
0839ccb8 530{
ab34c226
CW		 531 char __iomem *dst_vaddr;
532 char *src_vaddr;
0839ccb8 533
ab34c226
CW		 534 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
535 src_vaddr = kmap(user_page);
536
537 memcpy_toio(dst_vaddr + gtt_offset,
538 src_vaddr + user_offset,
539 length);
540
541 kunmap(user_page);
542 io_mapping_unmap(dst_vaddr);
9b7530cc
LT		 543}
544
40123c1f
EA		 545static inline int
546fast_shmem_write(struct page **pages,
547 loff_t page_base, int page_offset,
548 char __user *data,
549 int length)
550{
551 char __iomem *vaddr;
d0088775 552 unsigned long unwritten;
40123c1f
EA		 553
554 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
555 if (vaddr == NULL)
556 return -ENOMEM;
d0088775 557 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 558 kunmap_atomic(vaddr, KM_USER0);
559
d0088775
DA		 560 if (unwritten)
561 return -EFAULT;
40123c1f
EA		 562 return 0;
563}
564
3de09aa3
EA		 565/**
566 * This is the fast pwrite path, where we copy the data directly from the
567 * user into the GTT, uncached.
568 */
673a394b 569static int
3de09aa3
EA		 570i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
571 struct drm_i915_gem_pwrite *args,
572 struct drm_file *file_priv)
673a394b 573{
23010e43 574 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 575 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 576 ssize_t remain;
0839ccb8 577 loff_t offset, page_base;
673a394b 578 char __user *user_data;
0839ccb8
KP		 579 int page_offset, page_length;
580 int ret;
673a394b
EA		 581
582 user_data = (char __user *) (uintptr_t) args->data_ptr;
583 remain = args->size;
584 if (!access_ok(VERIFY_READ, user_data, remain))
585 return -EFAULT;
586
587
588 mutex_lock(&dev->struct_mutex);
589 ret = i915_gem_object_pin(obj, 0);
590 if (ret) {
591 mutex_unlock(&dev->struct_mutex);
592 return ret;
593 }
2ef7eeaa 594 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 595 if (ret)
596 goto fail;
597
23010e43 598 obj_priv = to_intel_bo(obj);
673a394b 599 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 600
601 while (remain > 0) {
602 /* Operation in this page
603 *
0839ccb8
KP		 604 * page_base = page offset within aperture
605 * page_offset = offset within page
606 * page_length = bytes to copy for this page
673a394b 607 */
0839ccb8
KP		 608 page_base = (offset & ~(PAGE_SIZE-1));
609 page_offset = offset & (PAGE_SIZE-1);
610 page_length = remain;
611 if ((page_offset + remain) > PAGE_SIZE)
612 page_length = PAGE_SIZE - page_offset;
613
614 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
615 page_offset, user_data, page_length);
616
617 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 618 * source page isn't available. Return the error and we'll
619 * retry in the slow path.
0839ccb8 620 */
3de09aa3
EA		 621 if (ret)
622 goto fail;
673a394b 623
0839ccb8
KP		 624 remain -= page_length;
625 user_data += page_length;
626 offset += page_length;
673a394b 627 }
673a394b
EA		 628
629fail:
630 i915_gem_object_unpin(obj);
631 mutex_unlock(&dev->struct_mutex);
632
633 return ret;
634}
635
3de09aa3
EA		 636/**
637 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
638 * the memory and maps it using kmap_atomic for copying.
639 *
640 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
641 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
642 */
3043c60c 643static int
3de09aa3
EA		 644i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
645 struct drm_i915_gem_pwrite *args,
646 struct drm_file *file_priv)
673a394b 647{
23010e43 648 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 649 drm_i915_private_t *dev_priv = dev->dev_private;
650 ssize_t remain;
651 loff_t gtt_page_base, offset;
652 loff_t first_data_page, last_data_page, num_pages;
653 loff_t pinned_pages, i;
654 struct page **user_pages;
655 struct mm_struct *mm = current->mm;
656 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 657 int ret;
3de09aa3
EA		 658 uint64_t data_ptr = args->data_ptr;
659
660 remain = args->size;
661
662 /* Pin the user pages containing the data. We can't fault while
663 * holding the struct mutex, and all of the pwrite implementations
664 * want to hold it while dereferencing the user data.
665 */
666 first_data_page = data_ptr / PAGE_SIZE;
667 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
668 num_pages = last_data_page - first_data_page + 1;
669
8e7d2b2c 670 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 671 if (user_pages == NULL)
672 return -ENOMEM;
673
674 down_read(&mm->mmap_sem);
675 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
676 num_pages, 0, 0, user_pages, NULL);
677 up_read(&mm->mmap_sem);
678 if (pinned_pages < num_pages) {
679 ret = -EFAULT;
680 goto out_unpin_pages;
681 }
673a394b
EA		 682
683 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 684 ret = i915_gem_object_pin(obj, 0);
685 if (ret)
686 goto out_unlock;
687
688 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
689 if (ret)
690 goto out_unpin_object;
691
23010e43 692 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 693 offset = obj_priv->gtt_offset + args->offset;
694
695 while (remain > 0) {
696 /* Operation in this page
697 *
698 * gtt_page_base = page offset within aperture
699 * gtt_page_offset = offset within page in aperture
700 * data_page_index = page number in get_user_pages return
701 * data_page_offset = offset with data_page_index page.
702 * page_length = bytes to copy for this page
703 */
704 gtt_page_base = offset & PAGE_MASK;
705 gtt_page_offset = offset & ~PAGE_MASK;
706 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
707 data_page_offset = data_ptr & ~PAGE_MASK;
708
709 page_length = remain;
710 if ((gtt_page_offset + page_length) > PAGE_SIZE)
711 page_length = PAGE_SIZE - gtt_page_offset;
712 if ((data_page_offset + page_length) > PAGE_SIZE)
713 page_length = PAGE_SIZE - data_page_offset;
714
ab34c226
CW		 715 slow_kernel_write(dev_priv->mm.gtt_mapping,
716 gtt_page_base, gtt_page_offset,
717 user_pages[data_page_index],
718 data_page_offset,
719 page_length);
3de09aa3
EA		 720
721 remain -= page_length;
722 offset += page_length;
723 data_ptr += page_length;
724 }
725
726out_unpin_object:
727 i915_gem_object_unpin(obj);
728out_unlock:
729 mutex_unlock(&dev->struct_mutex);
730out_unpin_pages:
731 for (i = 0; i < pinned_pages; i++)
732 page_cache_release(user_pages[i]);
8e7d2b2c 733 drm_free_large(user_pages);
3de09aa3
EA		 734
735 return ret;
736}
737
40123c1f
EA		 738/**
739 * This is the fast shmem pwrite path, which attempts to directly
740 * copy_from_user into the kmapped pages backing the object.
741 */
3043c60c 742static int
40123c1f
EA		 743i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
744 struct drm_i915_gem_pwrite *args,
745 struct drm_file *file_priv)
673a394b 746{
23010e43 747 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 748 ssize_t remain;
749 loff_t offset, page_base;
750 char __user *user_data;
751 int page_offset, page_length;
673a394b 752 int ret;
40123c1f
EA		 753
754 user_data = (char __user *) (uintptr_t) args->data_ptr;
755 remain = args->size;
673a394b
EA		 756
757 mutex_lock(&dev->struct_mutex);
758
4bdadb97 759 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 760 if (ret != 0)
761 goto fail_unlock;
673a394b 762
e47c68e9 763 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 764 if (ret != 0)
765 goto fail_put_pages;
766
23010e43 767 obj_priv = to_intel_bo(obj);
40123c1f
EA		 768 offset = args->offset;
769 obj_priv->dirty = 1;
770
771 while (remain > 0) {
772 /* Operation in this page
773 *
774 * page_base = page offset within aperture
775 * page_offset = offset within page
776 * page_length = bytes to copy for this page
777 */
778 page_base = (offset & ~(PAGE_SIZE-1));
779 page_offset = offset & (PAGE_SIZE-1);
780 page_length = remain;
781 if ((page_offset + remain) > PAGE_SIZE)
782 page_length = PAGE_SIZE - page_offset;
783
784 ret = fast_shmem_write(obj_priv->pages,
785 page_base, page_offset,
786 user_data, page_length);
787 if (ret)
788 goto fail_put_pages;
789
790 remain -= page_length;
791 user_data += page_length;
792 offset += page_length;
793 }
794
795fail_put_pages:
796 i915_gem_object_put_pages(obj);
797fail_unlock:
798 mutex_unlock(&dev->struct_mutex);
799
800 return ret;
801}
802
803/**
804 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
805 * the memory and maps it using kmap_atomic for copying.
806 *
807 * This avoids taking mmap_sem for faulting on the user's address while the
808 * struct_mutex is held.
809 */
810static int
811i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
812 struct drm_i915_gem_pwrite *args,
813 struct drm_file *file_priv)
814{
23010e43 815 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 816 struct mm_struct *mm = current->mm;
817 struct page **user_pages;
818 ssize_t remain;
819 loff_t offset, pinned_pages, i;
820 loff_t first_data_page, last_data_page, num_pages;
821 int shmem_page_index, shmem_page_offset;
822 int data_page_index, data_page_offset;
823 int page_length;
824 int ret;
825 uint64_t data_ptr = args->data_ptr;
280b713b 826 int do_bit17_swizzling;
40123c1f
EA		 827
828 remain = args->size;
829
830 /* Pin the user pages containing the data. We can't fault while
831 * holding the struct mutex, and all of the pwrite implementations
832 * want to hold it while dereferencing the user data.
833 */
834 first_data_page = data_ptr / PAGE_SIZE;
835 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
836 num_pages = last_data_page - first_data_page + 1;
837
8e7d2b2c 838 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 839 if (user_pages == NULL)
840 return -ENOMEM;
841
842 down_read(&mm->mmap_sem);
843 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
844 num_pages, 0, 0, user_pages, NULL);
845 up_read(&mm->mmap_sem);
846 if (pinned_pages < num_pages) {
847 ret = -EFAULT;
848 goto fail_put_user_pages;
673a394b
EA		 849 }
850
280b713b
EA		 851 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
852
40123c1f
EA		 853 mutex_lock(&dev->struct_mutex);
854
07f73f69
CW		 855 ret = i915_gem_object_get_pages_or_evict(obj);
856 if (ret)
40123c1f
EA		 857 goto fail_unlock;
858
859 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
860 if (ret != 0)
861 goto fail_put_pages;
862
23010e43 863 obj_priv = to_intel_bo(obj);
673a394b 864 offset = args->offset;
40123c1f 865 obj_priv->dirty = 1;
673a394b 866
40123c1f
EA		 867 while (remain > 0) {
868 /* Operation in this page
869 *
870 * shmem_page_index = page number within shmem file
871 * shmem_page_offset = offset within page in shmem file
872 * data_page_index = page number in get_user_pages return
873 * data_page_offset = offset with data_page_index page.
874 * page_length = bytes to copy for this page
875 */
876 shmem_page_index = offset / PAGE_SIZE;
877 shmem_page_offset = offset & ~PAGE_MASK;
878 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
879 data_page_offset = data_ptr & ~PAGE_MASK;
880
881 page_length = remain;
882 if ((shmem_page_offset + page_length) > PAGE_SIZE)
883 page_length = PAGE_SIZE - shmem_page_offset;
884 if ((data_page_offset + page_length) > PAGE_SIZE)
885 page_length = PAGE_SIZE - data_page_offset;
886
280b713b 887 if (do_bit17_swizzling) {
99a03df5 888 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b
EA		 889 shmem_page_offset,
890 user_pages[data_page_index],
891 data_page_offset,
99a03df5
CW		 892 page_length,
893 0);
894 } else {
895 slow_shmem_copy(obj_priv->pages[shmem_page_index],
896 shmem_page_offset,
897 user_pages[data_page_index],
898 data_page_offset,
899 page_length);
280b713b 900 }
40123c1f
EA		 901
902 remain -= page_length;
903 data_ptr += page_length;
904 offset += page_length;
673a394b
EA		 905 }
906
40123c1f
EA		 907fail_put_pages:
908 i915_gem_object_put_pages(obj);
909fail_unlock:
673a394b 910 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 911fail_put_user_pages:
912 for (i = 0; i < pinned_pages; i++)
913 page_cache_release(user_pages[i]);
8e7d2b2c 914 drm_free_large(user_pages);
673a394b 915
40123c1f 916 return ret;
673a394b
EA		 917}
918
919/**
920 * Writes data to the object referenced by handle.
921 *
922 * On error, the contents of the buffer that were to be modified are undefined.
923 */
924int
925i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
926 struct drm_file *file_priv)
927{
928 struct drm_i915_gem_pwrite *args = data;
929 struct drm_gem_object *obj;
930 struct drm_i915_gem_object *obj_priv;
931 int ret = 0;
932
933 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
934 if (obj == NULL)
bf79cb91 935 return -ENOENT;
23010e43 936 obj_priv = to_intel_bo(obj);
673a394b
EA		 937
938 /* Bounds check destination.
939 *
940 * XXX: This could use review for overflow issues...
941 */
942 if (args->offset > obj->size || args->size > obj->size ||
943 args->offset + args->size > obj->size) {
bc9025bd 944 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 945 return -EINVAL;
946 }
947
948 /* We can only do the GTT pwrite on untiled buffers, as otherwise
949 * it would end up going through the fenced access, and we'll get
950 * different detiling behavior between reading and writing.
951 * pread/pwrite currently are reading and writing from the CPU
952 * perspective, requiring manual detiling by the client.
953 */
71acb5eb
DA		 954 if (obj_priv->phys_obj)
955 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
956 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
9b8c4a0b
CW		 957 dev->gtt_total != 0 &&
958 obj->write_domain != I915_GEM_DOMAIN_CPU) {
3de09aa3
EA		 959 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
960 if (ret == -EFAULT) {
961 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
962 file_priv);
963 }
280b713b
EA		 964 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
965 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 966 } else {
967 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
968 if (ret == -EFAULT) {
969 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
970 file_priv);
971 }
972 }
673a394b
EA		 973
974#if WATCH_PWRITE
975 if (ret)
976 DRM_INFO("pwrite failed %d\n", ret);
977#endif
978
bc9025bd 979 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 980
981 return ret;
982}
983
984/**
2ef7eeaa
EA		 985 * Called when user space prepares to use an object with the CPU, either
986 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 987 */
988int
989i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
990 struct drm_file *file_priv)
991{
a09ba7fa 992 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 993 struct drm_i915_gem_set_domain *args = data;
994 struct drm_gem_object *obj;
652c393a 995 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 996 uint32_t read_domains = args->read_domains;
997 uint32_t write_domain = args->write_domain;
673a394b
EA		 998 int ret;
999
1000 if (!(dev->driver->driver_features & DRIVER_GEM))
1001 return -ENODEV;
1002
2ef7eeaa 1003 /* Only handle setting domains to types used by the CPU. */
21d509e3 1004 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1005 return -EINVAL;
1006
21d509e3 1007 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1008 return -EINVAL;
1009
1010 /* Having something in the write domain implies it's in the read
1011 * domain, and only that read domain. Enforce that in the request.
1012 */
1013 if (write_domain != 0 && read_domains != write_domain)
1014 return -EINVAL;
1015
673a394b
EA		 1016 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1017 if (obj == NULL)
bf79cb91 1018 return -ENOENT;
23010e43 1019 obj_priv = to_intel_bo(obj);
673a394b
EA		 1020
1021 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1022
1023 intel_mark_busy(dev, obj);
1024
673a394b 1025#if WATCH_BUF
cfd43c02 1026 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1027 obj, obj->size, read_domains, write_domain);
673a394b 1028#endif
2ef7eeaa
EA		 1029 if (read_domains & I915_GEM_DOMAIN_GTT) {
1030 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1031
a09ba7fa
EA		 1032 /* Update the LRU on the fence for the CPU access that's
1033 * about to occur.
1034 */
1035 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 1036 struct drm_i915_fence_reg *reg =
1037 &dev_priv->fence_regs[obj_priv->fence_reg];
1038 list_move_tail(&reg->lru_list,
a09ba7fa
EA		 1039 &dev_priv->mm.fence_list);
1040 }
1041
02354392
EA		 1042 /* Silently promote "you're not bound, there was nothing to do"
1043 * to success, since the client was just asking us to
1044 * make sure everything was done.
1045 */
1046 if (ret == -EINVAL)
1047 ret = 0;
2ef7eeaa 1048 } else {
e47c68e9 1049 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1050 }
1051
7d1c4804
CW		 1052
1053 /* Maintain LRU order of "inactive" objects */
1054 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1055 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1056
673a394b
EA		 1057 drm_gem_object_unreference(obj);
1058 mutex_unlock(&dev->struct_mutex);
1059 return ret;
1060}
1061
1062/**
1063 * Called when user space has done writes to this buffer
1064 */
1065int
1066i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1067 struct drm_file *file_priv)
1068{
1069 struct drm_i915_gem_sw_finish *args = data;
1070 struct drm_gem_object *obj;
1071 struct drm_i915_gem_object *obj_priv;
1072 int ret = 0;
1073
1074 if (!(dev->driver->driver_features & DRIVER_GEM))
1075 return -ENODEV;
1076
1077 mutex_lock(&dev->struct_mutex);
1078 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1079 if (obj == NULL) {
1080 mutex_unlock(&dev->struct_mutex);
bf79cb91 1081 return -ENOENT;
673a394b
EA		 1082 }
1083
1084#if WATCH_BUF
cfd43c02 1085 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1086 __func__, args->handle, obj, obj->size);
1087#endif
23010e43 1088 obj_priv = to_intel_bo(obj);
673a394b
EA		 1089
1090 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1091 if (obj_priv->pin_count)
1092 i915_gem_object_flush_cpu_write_domain(obj);
1093
673a394b
EA		 1094 drm_gem_object_unreference(obj);
1095 mutex_unlock(&dev->struct_mutex);
1096 return ret;
1097}
1098
1099/**
1100 * Maps the contents of an object, returning the address it is mapped
1101 * into.
1102 *
1103 * While the mapping holds a reference on the contents of the object, it doesn't
1104 * imply a ref on the object itself.
1105 */
1106int
1107i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1108 struct drm_file *file_priv)
1109{
1110 struct drm_i915_gem_mmap *args = data;
1111 struct drm_gem_object *obj;
1112 loff_t offset;
1113 unsigned long addr;
1114
1115 if (!(dev->driver->driver_features & DRIVER_GEM))
1116 return -ENODEV;
1117
1118 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1119 if (obj == NULL)
bf79cb91 1120 return -ENOENT;
673a394b
EA		 1121
1122 offset = args->offset;
1123
1124 down_write(&current->mm->mmap_sem);
1125 addr = do_mmap(obj->filp, 0, args->size,
1126 PROT_READ | PROT_WRITE, MAP_SHARED,
1127 args->offset);
1128 up_write(&current->mm->mmap_sem);
bc9025bd 1129 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1130 if (IS_ERR((void *)addr))
1131 return addr;
1132
1133 args->addr_ptr = (uint64_t) addr;
1134
1135 return 0;
1136}
1137
de151cf6
JB		 1138/**
1139 * i915_gem_fault - fault a page into the GTT
1140 * vma: VMA in question
1141 * vmf: fault info
1142 *
1143 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1144 * from userspace. The fault handler takes care of binding the object to
1145 * the GTT (if needed), allocating and programming a fence register (again,
1146 * only if needed based on whether the old reg is still valid or the object
1147 * is tiled) and inserting a new PTE into the faulting process.
1148 *
1149 * Note that the faulting process may involve evicting existing objects
1150 * from the GTT and/or fence registers to make room. So performance may
1151 * suffer if the GTT working set is large or there are few fence registers
1152 * left.
1153 */
1154int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1155{
1156 struct drm_gem_object *obj = vma->vm_private_data;
1157 struct drm_device *dev = obj->dev;
7d1c4804 1158 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1159 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1160 pgoff_t page_offset;
1161 unsigned long pfn;
1162 int ret = 0;
0f973f27 1163 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1164
1165 /* We don't use vmf->pgoff since that has the fake offset */
1166 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1167 PAGE_SHIFT;
1168
1169 /* Now bind it into the GTT if needed */
1170 mutex_lock(&dev->struct_mutex);
1171 if (!obj_priv->gtt_space) {
e67b8ce1 1172 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1173 if (ret)
1174 goto unlock;
07f4f3e8 1175
07f4f3e8 1176 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1177 if (ret)
1178 goto unlock;
de151cf6
JB		 1179 }
1180
1181 /* Need a new fence register? */
a09ba7fa 1182 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1183 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1184 if (ret)
1185 goto unlock;
d9ddcb96 1186 }
de151cf6 1187
7d1c4804
CW		 1188 if (i915_gem_object_is_inactive(obj_priv))
1189 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1190
de151cf6
JB		 1191 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1192 page_offset;
1193
1194 /* Finally, remap it using the new GTT offset */
1195 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1196unlock:
de151cf6
JB		 1197 mutex_unlock(&dev->struct_mutex);
1198
1199 switch (ret) {
c715089f
CW		 1200 case 0:
1201 case -ERESTARTSYS:
1202 return VM_FAULT_NOPAGE;
de151cf6
JB		 1203 case -ENOMEM:
1204 case -EAGAIN:
1205 return VM_FAULT_OOM;
de151cf6 1206 default:
c715089f 1207 return VM_FAULT_SIGBUS;
de151cf6
JB		 1208 }
1209}
1210
1211/**
1212 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1213 * @obj: obj in question
1214 *
1215 * GEM memory mapping works by handing back to userspace a fake mmap offset
1216 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1217 * up the object based on the offset and sets up the various memory mapping
1218 * structures.
1219 *
1220 * This routine allocates and attaches a fake offset for @obj.
1221 */
1222static int
1223i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1224{
1225 struct drm_device *dev = obj->dev;
1226 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1227 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1228 struct drm_map_list *list;
f77d390c 1229 struct drm_local_map *map;
de151cf6
JB		 1230 int ret = 0;
1231
1232 /* Set the object up for mmap'ing */
1233 list = &obj->map_list;
9a298b2a 1234 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1235 if (!list->map)
1236 return -ENOMEM;
1237
1238 map = list->map;
1239 map->type = _DRM_GEM;
1240 map->size = obj->size;
1241 map->handle = obj;
1242
1243 /* Get a DRM GEM mmap offset allocated... */
1244 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1245 obj->size / PAGE_SIZE, 0, 0);
1246 if (!list->file_offset_node) {
1247 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1248 ret = -ENOMEM;
1249 goto out_free_list;
1250 }
1251
1252 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1253 obj->size / PAGE_SIZE, 0);
1254 if (!list->file_offset_node) {
1255 ret = -ENOMEM;
1256 goto out_free_list;
1257 }
1258
1259 list->hash.key = list->file_offset_node->start;
1260 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1261 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1262 ret = -ENOMEM;
de151cf6
JB		 1263 goto out_free_mm;
1264 }
1265
1266 /* By now we should be all set, any drm_mmap request on the offset
1267 * below will get to our mmap & fault handler */
1268 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1269
1270 return 0;
1271
1272out_free_mm:
1273 drm_mm_put_block(list->file_offset_node);
1274out_free_list:
9a298b2a 1275 kfree(list->map);
de151cf6
JB		 1276
1277 return ret;
1278}
1279
901782b2
CW		 1280/**
1281 * i915_gem_release_mmap - remove physical page mappings
1282 * @obj: obj in question
1283 *
af901ca1 1284 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1285 * relinquish ownership of the pages back to the system.
1286 *
1287 * It is vital that we remove the page mapping if we have mapped a tiled
1288 * object through the GTT and then lose the fence register due to
1289 * resource pressure. Similarly if the object has been moved out of the
1290 * aperture, than pages mapped into userspace must be revoked. Removing the
1291 * mapping will then trigger a page fault on the next user access, allowing
1292 * fixup by i915_gem_fault().
1293 */
d05ca301 1294void
901782b2
CW		 1295i915_gem_release_mmap(struct drm_gem_object *obj)
1296{
1297 struct drm_device *dev = obj->dev;
23010e43 1298 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1299
1300 if (dev->dev_mapping)
1301 unmap_mapping_range(dev->dev_mapping,
1302 obj_priv->mmap_offset, obj->size, 1);
1303}
1304
ab00b3e5
JB		 1305static void
1306i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1307{
1308 struct drm_device *dev = obj->dev;
23010e43 1309 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1310 struct drm_gem_mm *mm = dev->mm_private;
1311 struct drm_map_list *list;
1312
1313 list = &obj->map_list;
1314 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1315
1316 if (list->file_offset_node) {
1317 drm_mm_put_block(list->file_offset_node);
1318 list->file_offset_node = NULL;
1319 }
1320
1321 if (list->map) {
9a298b2a 1322 kfree(list->map);
ab00b3e5
JB		 1323 list->map = NULL;
1324 }
1325
1326 obj_priv->mmap_offset = 0;
1327}
1328
de151cf6
JB		 1329/**
1330 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1331 * @obj: object to check
1332 *
1333 * Return the required GTT alignment for an object, taking into account
1334 * potential fence register mapping if needed.
1335 */
1336static uint32_t
1337i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1338{
1339 struct drm_device *dev = obj->dev;
23010e43 1340 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1341 int start, i;
1342
1343 /*
1344 * Minimum alignment is 4k (GTT page size), but might be greater
1345 * if a fence register is needed for the object.
1346 */
1347 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1348 return 4096;
1349
1350 /*
1351 * Previous chips need to be aligned to the size of the smallest
1352 * fence register that can contain the object.
1353 */
1354 if (IS_I9XX(dev))
1355 start = 1024*1024;
1356 else
1357 start = 512*1024;
1358
1359 for (i = start; i < obj->size; i <<= 1)
1360 ;
1361
1362 return i;
1363}
1364
1365/**
1366 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1367 * @dev: DRM device
1368 * @data: GTT mapping ioctl data
1369 * @file_priv: GEM object info
1370 *
1371 * Simply returns the fake offset to userspace so it can mmap it.
1372 * The mmap call will end up in drm_gem_mmap(), which will set things
1373 * up so we can get faults in the handler above.
1374 *
1375 * The fault handler will take care of binding the object into the GTT
1376 * (since it may have been evicted to make room for something), allocating
1377 * a fence register, and mapping the appropriate aperture address into
1378 * userspace.
1379 */
1380int
1381i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1382 struct drm_file *file_priv)
1383{
1384 struct drm_i915_gem_mmap_gtt *args = data;
de151cf6
JB		 1385 struct drm_gem_object *obj;
1386 struct drm_i915_gem_object *obj_priv;
1387 int ret;
1388
1389 if (!(dev->driver->driver_features & DRIVER_GEM))
1390 return -ENODEV;
1391
1392 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1393 if (obj == NULL)
bf79cb91 1394 return -ENOENT;
de151cf6
JB		 1395
1396 mutex_lock(&dev->struct_mutex);
1397
23010e43 1398 obj_priv = to_intel_bo(obj);
de151cf6 1399
ab18282d
CW		 1400 if (obj_priv->madv != I915_MADV_WILLNEED) {
1401 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1402 drm_gem_object_unreference(obj);
1403 mutex_unlock(&dev->struct_mutex);
1404 return -EINVAL;
1405 }
1406
1407
de151cf6
JB		 1408 if (!obj_priv->mmap_offset) {
1409 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1410 if (ret) {
1411 drm_gem_object_unreference(obj);
1412 mutex_unlock(&dev->struct_mutex);
de151cf6 1413 return ret;
13af1062 1414 }
de151cf6
JB		 1415 }
1416
1417 args->offset = obj_priv->mmap_offset;
1418
de151cf6
JB		 1419 /*
1420 * Pull it into the GTT so that we have a page list (makes the
1421 * initial fault faster and any subsequent flushing possible).
1422 */
1423 if (!obj_priv->agp_mem) {
e67b8ce1 1424 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1425 if (ret) {
1426 drm_gem_object_unreference(obj);
1427 mutex_unlock(&dev->struct_mutex);
1428 return ret;
1429 }
de151cf6
JB		 1430 }
1431
1432 drm_gem_object_unreference(obj);
1433 mutex_unlock(&dev->struct_mutex);
1434
1435 return 0;
1436}
1437
6911a9b8 1438void
856fa198 1439i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1440{
23010e43 1441 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1442 int page_count = obj->size / PAGE_SIZE;
1443 int i;
1444
856fa198 1445 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1446 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1447
856fa198
EA		 1448 if (--obj_priv->pages_refcount != 0)
1449 return;
673a394b 1450
280b713b
EA		 1451 if (obj_priv->tiling_mode != I915_TILING_NONE)
1452 i915_gem_object_save_bit_17_swizzle(obj);
1453
3ef94daa 1454 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1455 obj_priv->dirty = 0;
3ef94daa
CW		 1456
1457 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1458 if (obj_priv->dirty)
1459 set_page_dirty(obj_priv->pages[i]);
1460
1461 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1462 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1463
1464 page_cache_release(obj_priv->pages[i]);
1465 }
673a394b
EA		 1466 obj_priv->dirty = 0;
1467
8e7d2b2c 1468 drm_free_large(obj_priv->pages);
856fa198 1469 obj_priv->pages = NULL;
673a394b
EA		 1470}
1471
e35a41de 1472static uint32_t
a6910434
DV		 1473i915_gem_next_request_seqno(struct drm_device *dev,
1474 struct intel_ring_buffer *ring)
e35a41de
DV		 1475{
1476 drm_i915_private_t *dev_priv = dev->dev_private;
1477
a6910434
DV		 1478 ring->outstanding_lazy_request = true;
1479
e35a41de
DV		 1480 return dev_priv->next_seqno;
1481}
1482
673a394b 1483static void
852835f3
ZN		 1484i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1485 struct intel_ring_buffer *ring)
673a394b
EA		 1486{
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
852835f3
ZN		 1490 BUG_ON(ring == NULL);
1491 obj_priv->ring = ring;
673a394b
EA		 1492
1493 /* Add a reference if we're newly entering the active list. */
1494 if (!obj_priv->active) {
1495 drm_gem_object_reference(obj);
1496 obj_priv->active = 1;
1497 }
e35a41de
DV		 1498
1499 /* Take the seqno of the next request if none is given */
1500 if (seqno == 0)
a6910434 1501 seqno = i915_gem_next_request_seqno(dev, ring);
e35a41de 1502
673a394b 1503 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1504 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1505 list_move_tail(&obj_priv->list, &ring->active_list);
5e118f41 1506 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1507 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1508}
1509
ce44b0ea
EA		 1510static void
1511i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1512{
1513 struct drm_device *dev = obj->dev;
1514 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1515 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1516
1517 BUG_ON(!obj_priv->active);
1518 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1519 obj_priv->last_rendering_seqno = 0;
1520}
673a394b 1521
963b4836
CW		 1522/* Immediately discard the backing storage */
1523static void
1524i915_gem_object_truncate(struct drm_gem_object *obj)
1525{
23010e43 1526 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1527 struct inode *inode;
963b4836 1528
ae9fed6b
CW		 1529 /* Our goal here is to return as much of the memory as
1530 * is possible back to the system as we are called from OOM.
1531 * To do this we must instruct the shmfs to drop all of its
1532 * backing pages, *now*. Here we mirror the actions taken
1533 * when by shmem_delete_inode() to release the backing store.
1534 */
bb6baf76 1535 inode = obj->filp->f_path.dentry->d_inode;
ae9fed6b
CW		 1536 truncate_inode_pages(inode->i_mapping, 0);
1537 if (inode->i_op->truncate_range)
1538 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
bb6baf76
CW		 1539
1540 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1541}
1542
1543static inline int
1544i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1545{
1546 return obj_priv->madv == I915_MADV_DONTNEED;
1547}
1548
673a394b
EA		 1549static void
1550i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1551{
1552 struct drm_device *dev = obj->dev;
1553 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1554 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1555
1556 i915_verify_inactive(dev, __FILE__, __LINE__);
1557 if (obj_priv->pin_count != 0)
1558 list_del_init(&obj_priv->list);
1559 else
1560 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1561
99fcb766
DV		 1562 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1563
ce44b0ea 1564 obj_priv->last_rendering_seqno = 0;
852835f3 1565 obj_priv->ring = NULL;
673a394b
EA		 1566 if (obj_priv->active) {
1567 obj_priv->active = 0;
1568 drm_gem_object_unreference(obj);
1569 }
1570 i915_verify_inactive(dev, __FILE__, __LINE__);
1571}
1572
8a1a49f9 1573void
63560396 1574i915_gem_process_flushing_list(struct drm_device *dev,
8a1a49f9 1575 uint32_t flush_domains,
852835f3 1576 struct intel_ring_buffer *ring)
63560396
DV		 1577{
1578 drm_i915_private_t *dev_priv = dev->dev_private;
1579 struct drm_i915_gem_object *obj_priv, *next;
1580
1581 list_for_each_entry_safe(obj_priv, next,
1582 &dev_priv->mm.gpu_write_list,
1583 gpu_write_list) {
a8089e84 1584 struct drm_gem_object *obj = &obj_priv->base;
63560396
DV		 1585
1586 if ((obj->write_domain & flush_domains) ==
852835f3
ZN		 1587 obj->write_domain &&
1588 obj_priv->ring->ring_flag == ring->ring_flag) {
63560396
DV		 1589 uint32_t old_write_domain = obj->write_domain;
1590
1591 obj->write_domain = 0;
1592 list_del_init(&obj_priv->gpu_write_list);
8a1a49f9 1593 i915_gem_object_move_to_active(obj, 0, ring);
63560396
DV		 1594
1595 /* update the fence lru list */
007cc8ac
DV		 1596 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1597 struct drm_i915_fence_reg *reg =
1598 &dev_priv->fence_regs[obj_priv->fence_reg];
1599 list_move_tail(&reg->lru_list,
63560396 1600 &dev_priv->mm.fence_list);
007cc8ac 1601 }
63560396
DV		 1602
1603 trace_i915_gem_object_change_domain(obj,
1604 obj->read_domains,
1605 old_write_domain);
1606 }
1607 }
1608}
8187a2b7 1609
5a5a0c64 1610uint32_t
8a1a49f9
DV		 1611i915_add_request(struct drm_device *dev,
1612 struct drm_file *file_priv,
1613 struct intel_ring_buffer *ring)
673a394b
EA		 1614{
1615 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1616 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1617 struct drm_i915_gem_request *request;
1618 uint32_t seqno;
1619 int was_empty;
673a394b 1620
b962442e
EA		 1621 if (file_priv != NULL)
1622 i915_file_priv = file_priv->driver_priv;
1623
9a298b2a 1624 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1625 if (request == NULL)
1626 return 0;
1627
8a1a49f9 1628 seqno = ring->add_request(dev, ring, file_priv, 0);
673a394b
EA		 1629
1630 request->seqno = seqno;
852835f3 1631 request->ring = ring;
673a394b 1632 request->emitted_jiffies = jiffies;
852835f3
ZN		 1633 was_empty = list_empty(&ring->request_list);
1634 list_add_tail(&request->list, &ring->request_list);
1635
b962442e
EA		 1636 if (i915_file_priv) {
1637 list_add_tail(&request->client_list,
1638 &i915_file_priv->mm.request_list);
1639 } else {
1640 INIT_LIST_HEAD(&request->client_list);
1641 }
673a394b 1642
f65d9421
BG		 1643 if (!dev_priv->mm.suspended) {
1644 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1645 if (was_empty)
1646 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1647 }
673a394b
EA		 1648 return seqno;
1649}
1650
1651/**
1652 * Command execution barrier
1653 *
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1656 */
8a1a49f9 1657static void
852835f3 1658i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
673a394b 1659{
673a394b 1660 uint32_t flush_domains = 0;
673a394b
EA		 1661
1662 /* The sampler always gets flushed on i965 (sigh) */
1663 if (IS_I965G(dev))
1664 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
852835f3
ZN		 1665
1666 ring->flush(dev, ring,
1667 I915_GEM_DOMAIN_COMMAND, flush_domains);
673a394b
EA		 1668}
1669
1670/**
1671 * Moves buffers associated only with the given active seqno from the active
1672 * to inactive list, potentially freeing them.
1673 */
1674static void
1675i915_gem_retire_request(struct drm_device *dev,
1676 struct drm_i915_gem_request *request)
1677{
1678 drm_i915_private_t *dev_priv = dev->dev_private;
1679
1c5d22f7
CW		 1680 trace_i915_gem_request_retire(dev, request->seqno);
1681
673a394b
EA		 1682 /* Move any buffers on the active list that are no longer referenced
1683 * by the ringbuffer to the flushing/inactive lists as appropriate.
1684 */
5e118f41 1685 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1686 while (!list_empty(&request->ring->active_list)) {
673a394b
EA		 1687 struct drm_gem_object *obj;
1688 struct drm_i915_gem_object *obj_priv;
1689
852835f3 1690 obj_priv = list_first_entry(&request->ring->active_list,
673a394b
EA		 1691 struct drm_i915_gem_object,
1692 list);
a8089e84 1693 obj = &obj_priv->base;
673a394b
EA		 1694
1695 /* If the seqno being retired doesn't match the oldest in the
1696 * list, then the oldest in the list must still be newer than
1697 * this seqno.
1698 */
1699 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1700 goto out;
de151cf6 1701
673a394b
EA		 1702#if WATCH_LRU
1703 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1704 __func__, request->seqno, obj);
1705#endif
1706
ce44b0ea
EA		 1707 if (obj->write_domain != 0)
1708 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1709 else {
1710 /* Take a reference on the object so it won't be
1711 * freed while the spinlock is held. The list
1712 * protection for this spinlock is safe when breaking
1713 * the lock like this since the next thing we do
1714 * is just get the head of the list again.
1715 */
1716 drm_gem_object_reference(obj);
673a394b 1717 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1718 spin_unlock(&dev_priv->mm.active_list_lock);
1719 drm_gem_object_unreference(obj);
1720 spin_lock(&dev_priv->mm.active_list_lock);
1721 }
673a394b 1722 }
5e118f41
CW		 1723out:
1724 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1725}
1726
1727/**
1728 * Returns true if seq1 is later than seq2.
1729 */
22be1724 1730bool
673a394b
EA		 1731i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1732{
1733 return (int32_t)(seq1 - seq2) >= 0;
1734}
1735
1736uint32_t
852835f3 1737i915_get_gem_seqno(struct drm_device *dev,
d1b851fc 1738 struct intel_ring_buffer *ring)
673a394b 1739{
852835f3 1740 return ring->get_gem_seqno(dev, ring);
673a394b
EA		 1741}
1742
1743/**
1744 * This function clears the request list as sequence numbers are passed.
1745 */
b09a1fec
CW		 1746static void
1747i915_gem_retire_requests_ring(struct drm_device *dev,
1748 struct intel_ring_buffer *ring)
673a394b
EA		 1749{
1750 drm_i915_private_t *dev_priv = dev->dev_private;
1751 uint32_t seqno;
1752
8187a2b7 1753 if (!ring->status_page.page_addr
852835f3 1754 || list_empty(&ring->request_list))
6c0594a3
KW		 1755 return;
1756
852835f3 1757 seqno = i915_get_gem_seqno(dev, ring);
673a394b 1758
852835f3 1759 while (!list_empty(&ring->request_list)) {
673a394b
EA		 1760 struct drm_i915_gem_request *request;
1761 uint32_t retiring_seqno;
1762
852835f3 1763 request = list_first_entry(&ring->request_list,
673a394b
EA		 1764 struct drm_i915_gem_request,
1765 list);
1766 retiring_seqno = request->seqno;
1767
1768 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1769 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1770 i915_gem_retire_request(dev, request);
1771
1772 list_del(&request->list);
b962442e 1773 list_del(&request->client_list);
9a298b2a 1774 kfree(request);
673a394b
EA		 1775 } else
1776 break;
1777 }
9d34e5db
CW		 1778
1779 if (unlikely (dev_priv->trace_irq_seqno &&
1780 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
8187a2b7
ZN		 1781
1782 ring->user_irq_put(dev, ring);
9d34e5db
CW		 1783 dev_priv->trace_irq_seqno = 0;
1784 }
673a394b
EA		 1785}
1786
b09a1fec
CW		 1787void
1788i915_gem_retire_requests(struct drm_device *dev)
1789{
1790 drm_i915_private_t *dev_priv = dev->dev_private;
1791
be72615b
CW		 1792 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1793 struct drm_i915_gem_object *obj_priv, *tmp;
1794
1795 /* We must be careful that during unbind() we do not
1796 * accidentally infinitely recurse into retire requests.
1797 * Currently:
1798 * retire -> free -> unbind -> wait -> retire_ring
1799 */
1800 list_for_each_entry_safe(obj_priv, tmp,
1801 &dev_priv->mm.deferred_free_list,
1802 list)
1803 i915_gem_free_object_tail(&obj_priv->base);
1804 }
1805
b09a1fec
CW		 1806 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1807 if (HAS_BSD(dev))
1808 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1809}
1810
75ef9da2 1811static void
673a394b
EA		 1812i915_gem_retire_work_handler(struct work_struct *work)
1813{
1814 drm_i915_private_t *dev_priv;
1815 struct drm_device *dev;
1816
1817 dev_priv = container_of(work, drm_i915_private_t,
1818 mm.retire_work.work);
1819 dev = dev_priv->dev;
1820
1821 mutex_lock(&dev->struct_mutex);
b09a1fec 1822 i915_gem_retire_requests(dev);
d1b851fc 1823
6dbe2772 1824 if (!dev_priv->mm.suspended &&
d1b851fc
ZN		 1825 (!list_empty(&dev_priv->render_ring.request_list) ||
1826 (HAS_BSD(dev) &&
1827 !list_empty(&dev_priv->bsd_ring.request_list))))
9c9fe1f8 1828 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1829 mutex_unlock(&dev->struct_mutex);
1830}
1831
5a5a0c64 1832int
852835f3 1833i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
8a1a49f9 1834 bool interruptible, struct intel_ring_buffer *ring)
673a394b
EA		 1835{
1836 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1837 u32 ier;
673a394b
EA		 1838 int ret = 0;
1839
1840 BUG_ON(seqno == 0);
1841
e35a41de 1842 if (seqno == dev_priv->next_seqno) {
8a1a49f9 1843 seqno = i915_add_request(dev, NULL, ring);
e35a41de
DV		 1844 if (seqno == 0)
1845 return -ENOMEM;
1846 }
1847
ba1234d1 1848 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1849 return -EIO;
1850
852835f3 1851 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
bad720ff 1852 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1853 ier = I915_READ(DEIER) | I915_READ(GTIER);
1854 else
1855 ier = I915_READ(IER);
802c7eb6
JB		 1856 if (!ier) {
1857 DRM_ERROR("something (likely vbetool) disabled "
1858 "interrupts, re-enabling\n");
1859 i915_driver_irq_preinstall(dev);
1860 i915_driver_irq_postinstall(dev);
1861 }
1862
1c5d22f7
CW		 1863 trace_i915_gem_request_wait_begin(dev, seqno);
1864
852835f3 1865 ring->waiting_gem_seqno = seqno;
8187a2b7 1866 ring->user_irq_get(dev, ring);
48764bf4 1867 if (interruptible)
852835f3
ZN		 1868 ret = wait_event_interruptible(ring->irq_queue,
1869 i915_seqno_passed(
1870 ring->get_gem_seqno(dev, ring), seqno)
1871 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1872 else
852835f3
ZN		 1873 wait_event(ring->irq_queue,
1874 i915_seqno_passed(
1875 ring->get_gem_seqno(dev, ring), seqno)
1876 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1877
8187a2b7 1878 ring->user_irq_put(dev, ring);
852835f3 1879 ring->waiting_gem_seqno = 0;
1c5d22f7
CW		 1880
1881 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1882 }
ba1234d1 1883 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1884 ret = -EIO;
1885
1886 if (ret && ret != -ERESTARTSYS)
8bff917c
DV		 1887 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1888 __func__, ret, seqno, ring->get_gem_seqno(dev, ring),
1889 dev_priv->next_seqno);
673a394b
EA		 1890
1891 /* Directly dispatch request retiring. While we have the work queue
1892 * to handle this, the waiter on a request often wants an associated
1893 * buffer to have made it to the inactive list, and we would need
1894 * a separate wait queue to handle that.
1895 */
1896 if (ret == 0)
b09a1fec 1897 i915_gem_retire_requests_ring(dev, ring);
673a394b
EA		 1898
1899 return ret;
1900}
1901
48764bf4
DV		 1902/**
1903 * Waits for a sequence number to be signaled, and cleans up the
1904 * request and object lists appropriately for that event.
1905 */
1906static int
852835f3
ZN		 1907i915_wait_request(struct drm_device *dev, uint32_t seqno,
1908 struct intel_ring_buffer *ring)
48764bf4 1909{
852835f3 1910 return i915_do_wait_request(dev, seqno, 1, ring);
48764bf4
DV		 1911}
1912
8187a2b7
ZN		 1913static void
1914i915_gem_flush(struct drm_device *dev,
1915 uint32_t invalidate_domains,
1916 uint32_t flush_domains)
1917{
1918 drm_i915_private_t *dev_priv = dev->dev_private;
8bff917c 1919
8187a2b7
ZN		 1920 if (flush_domains & I915_GEM_DOMAIN_CPU)
1921 drm_agp_chipset_flush(dev);
8bff917c 1922
8187a2b7
ZN		 1923 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1924 invalidate_domains,
1925 flush_domains);
d1b851fc
ZN		 1926
1927 if (HAS_BSD(dev))
1928 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1929 invalidate_domains,
1930 flush_domains);
8187a2b7
ZN		 1931}
1932
673a394b
EA		 1933/**
1934 * Ensures that all rendering to the object has completed and the object is
1935 * safe to unbind from the GTT or access from the CPU.
1936 */
1937static int
e35a41de
DV		 1938i915_gem_object_wait_rendering(struct drm_gem_object *obj,
1939 bool interruptible)
673a394b
EA		 1940{
1941 struct drm_device *dev = obj->dev;
23010e43 1942 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1943 int ret;
1944
e47c68e9
EA		 1945 /* This function only exists to support waiting for existing rendering,
1946 * not for emitting required flushes.
673a394b 1947 */
e47c68e9 1948 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1949
1950 /* If there is rendering queued on the buffer being evicted, wait for
1951 * it.
1952 */
1953 if (obj_priv->active) {
1954#if WATCH_BUF
1955 DRM_INFO("%s: object %p wait for seqno %08x\n",
1956 __func__, obj, obj_priv->last_rendering_seqno);
1957#endif
e35a41de
DV		 1958 ret = i915_do_wait_request(dev,
1959 obj_priv->last_rendering_seqno,
1960 interruptible,
1961 obj_priv->ring);
673a394b
EA		 1962 if (ret != 0)
1963 return ret;
1964 }
1965
1966 return 0;
1967}
1968
1969/**
1970 * Unbinds an object from the GTT aperture.
1971 */
0f973f27 1972int
673a394b
EA		 1973i915_gem_object_unbind(struct drm_gem_object *obj)
1974{
1975 struct drm_device *dev = obj->dev;
4a87b8ca 1976 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1977 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1978 int ret = 0;
1979
1980#if WATCH_BUF
1981 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1982 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1983#endif
1984 if (obj_priv->gtt_space == NULL)
1985 return 0;
1986
1987 if (obj_priv->pin_count != 0) {
1988 DRM_ERROR("Attempting to unbind pinned buffer\n");
1989 return -EINVAL;
1990 }
1991
5323fd04
EA		 1992 /* blow away mappings if mapped through GTT */
1993 i915_gem_release_mmap(obj);
1994
673a394b
EA		 1995 /* Move the object to the CPU domain to ensure that
1996 * any possible CPU writes while it's not in the GTT
1997 * are flushed when we go to remap it. This will
1998 * also ensure that all pending GPU writes are finished
1999 * before we unbind.
2000 */
e47c68e9 2001 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
8dc1775d 2002 if (ret == -ERESTARTSYS)
673a394b 2003 return ret;
8dc1775d
CW		 2004 /* Continue on if we fail due to EIO, the GPU is hung so we
2005 * should be safe and we need to cleanup or else we might
2006 * cause memory corruption through use-after-free.
2007 */
673a394b 2008
96b47b65
DV		 2009 /* release the fence reg _after_ flushing */
2010 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2011 i915_gem_clear_fence_reg(obj);
2012
673a394b
EA		 2013 if (obj_priv->agp_mem != NULL) {
2014 drm_unbind_agp(obj_priv->agp_mem);
2015 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2016 obj_priv->agp_mem = NULL;
2017 }
2018
856fa198 2019 i915_gem_object_put_pages(obj);
a32808c0 2020 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 2021
2022 if (obj_priv->gtt_space) {
2023 atomic_dec(&dev->gtt_count);
2024 atomic_sub(obj->size, &dev->gtt_memory);
2025
2026 drm_mm_put_block(obj_priv->gtt_space);
2027 obj_priv->gtt_space = NULL;
2028 }
2029
2030 /* Remove ourselves from the LRU list if present. */
4a87b8ca 2031 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 2032 if (!list_empty(&obj_priv->list))
2033 list_del_init(&obj_priv->list);
4a87b8ca 2034 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 2035
963b4836
CW		 2036 if (i915_gem_object_is_purgeable(obj_priv))
2037 i915_gem_object_truncate(obj);
2038
1c5d22f7
CW		 2039 trace_i915_gem_object_unbind(obj);
2040
8dc1775d 2041 return ret;
673a394b
EA		 2042}
2043
b47eb4a2 2044int
4df2faf4
DV		 2045i915_gpu_idle(struct drm_device *dev)
2046{
2047 drm_i915_private_t *dev_priv = dev->dev_private;
2048 bool lists_empty;
d1b851fc 2049 uint32_t seqno1, seqno2;
852835f3 2050 int ret;
4df2faf4
DV		 2051
2052 spin_lock(&dev_priv->mm.active_list_lock);
d1b851fc
ZN		 2053 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2054 list_empty(&dev_priv->render_ring.active_list) &&
2055 (!HAS_BSD(dev) ||
2056 list_empty(&dev_priv->bsd_ring.active_list)));
4df2faf4
DV		 2057 spin_unlock(&dev_priv->mm.active_list_lock);
2058
2059 if (lists_empty)
2060 return 0;
2061
2062 /* Flush everything onto the inactive list. */
2063 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
8a1a49f9 2064 seqno1 = i915_add_request(dev, NULL, &dev_priv->render_ring);
d1b851fc 2065 if (seqno1 == 0)
4df2faf4 2066 return -ENOMEM;
d1b851fc 2067 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
8a1a49f9
DV		 2068 if (ret)
2069 return ret;
d1b851fc
ZN		 2070
2071 if (HAS_BSD(dev)) {
8a1a49f9 2072 seqno2 = i915_add_request(dev, NULL, &dev_priv->bsd_ring);
d1b851fc
ZN		 2073 if (seqno2 == 0)
2074 return -ENOMEM;
d1b851fc
ZN		 2075 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2076 if (ret)
2077 return ret;
2078 }
2079
8a1a49f9 2080 return 0;
4df2faf4
DV		 2081}
2082
6911a9b8 2083int
4bdadb97
CW		 2084i915_gem_object_get_pages(struct drm_gem_object *obj,
2085 gfp_t gfpmask)
673a394b 2086{
23010e43 2087 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2088 int page_count, i;
2089 struct address_space *mapping;
2090 struct inode *inode;
2091 struct page *page;
673a394b 2092
778c3544
DV		 2093 BUG_ON(obj_priv->pages_refcount
2094 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2095
856fa198 2096 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2097 return 0;
2098
2099 /* Get the list of pages out of our struct file. They'll be pinned
2100 * at this point until we release them.
2101 */
2102 page_count = obj->size / PAGE_SIZE;
856fa198 2103 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2104 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2105 if (obj_priv->pages == NULL) {
856fa198 2106 obj_priv->pages_refcount--;
673a394b
EA		 2107 return -ENOMEM;
2108 }
2109
2110 inode = obj->filp->f_path.dentry->d_inode;
2111 mapping = inode->i_mapping;
2112 for (i = 0; i < page_count; i++) {
4bdadb97 2113 page = read_cache_page_gfp(mapping, i,
985b823b 2114 GFP_HIGHUSER |
4bdadb97 2115 __GFP_COLD |
cd9f040d 2116 __GFP_RECLAIMABLE |
4bdadb97 2117 gfpmask);
1f2b1013
CW		 2118 if (IS_ERR(page))
2119 goto err_pages;
2120
856fa198 2121 obj_priv->pages[i] = page;
673a394b 2122 }
280b713b
EA		 2123
2124 if (obj_priv->tiling_mode != I915_TILING_NONE)
2125 i915_gem_object_do_bit_17_swizzle(obj);
2126
673a394b 2127 return 0;
1f2b1013
CW		 2128
2129err_pages:
2130 while (i--)
2131 page_cache_release(obj_priv->pages[i]);
2132
2133 drm_free_large(obj_priv->pages);
2134 obj_priv->pages = NULL;
2135 obj_priv->pages_refcount--;
2136 return PTR_ERR(page);
673a394b
EA		 2137}
2138
4e901fdc
EA		 2139static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2140{
2141 struct drm_gem_object *obj = reg->obj;
2142 struct drm_device *dev = obj->dev;
2143 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2144 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2145 int regnum = obj_priv->fence_reg;
2146 uint64_t val;
2147
2148 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2149 0xfffff000) << 32;
2150 val |= obj_priv->gtt_offset & 0xfffff000;
2151 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2152 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2153
2154 if (obj_priv->tiling_mode == I915_TILING_Y)
2155 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2156 val |= I965_FENCE_REG_VALID;
2157
2158 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2159}
2160
de151cf6
JB		 2161static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2162{
2163 struct drm_gem_object *obj = reg->obj;
2164 struct drm_device *dev = obj->dev;
2165 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2166 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2167 int regnum = obj_priv->fence_reg;
2168 uint64_t val;
2169
2170 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2171 0xfffff000) << 32;
2172 val |= obj_priv->gtt_offset & 0xfffff000;
2173 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2174 if (obj_priv->tiling_mode == I915_TILING_Y)
2175 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2176 val |= I965_FENCE_REG_VALID;
2177
2178 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2179}
2180
2181static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2182{
2183 struct drm_gem_object *obj = reg->obj;
2184 struct drm_device *dev = obj->dev;
2185 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2186 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2187 int regnum = obj_priv->fence_reg;
0f973f27 2188 int tile_width;
dc529a4f 2189 uint32_t fence_reg, val;
de151cf6
JB		 2190 uint32_t pitch_val;
2191
2192 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2193 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2194 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2195 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2196 return;
2197 }
2198
0f973f27
JB		 2199 if (obj_priv->tiling_mode == I915_TILING_Y &&
2200 HAS_128_BYTE_Y_TILING(dev))
2201 tile_width = 128;
de151cf6 2202 else
0f973f27
JB		 2203 tile_width = 512;
2204
2205 /* Note: pitch better be a power of two tile widths */
2206 pitch_val = obj_priv->stride / tile_width;
2207 pitch_val = ffs(pitch_val) - 1;
de151cf6 2208
c36a2a6d
DV		 2209 if (obj_priv->tiling_mode == I915_TILING_Y &&
2210 HAS_128_BYTE_Y_TILING(dev))
2211 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2212 else
2213 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2214
de151cf6
JB		 2215 val = obj_priv->gtt_offset;
2216 if (obj_priv->tiling_mode == I915_TILING_Y)
2217 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2218 val |= I915_FENCE_SIZE_BITS(obj->size);
2219 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2220 val |= I830_FENCE_REG_VALID;
2221
dc529a4f
EA		 2222 if (regnum < 8)
2223 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2224 else
2225 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2226 I915_WRITE(fence_reg, val);
de151cf6
JB		 2227}
2228
2229static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2230{
2231 struct drm_gem_object *obj = reg->obj;
2232 struct drm_device *dev = obj->dev;
2233 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2234 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2235 int regnum = obj_priv->fence_reg;
2236 uint32_t val;
2237 uint32_t pitch_val;
8d7773a3 2238 uint32_t fence_size_bits;
de151cf6 2239
8d7773a3 2240 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2241 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2242 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2243 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2244 return;
2245 }
2246
e76a16de
EA		 2247 pitch_val = obj_priv->stride / 128;
2248 pitch_val = ffs(pitch_val) - 1;
2249 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2250
de151cf6
JB		 2251 val = obj_priv->gtt_offset;
2252 if (obj_priv->tiling_mode == I915_TILING_Y)
2253 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2254 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2255 WARN_ON(fence_size_bits & ~0x00000f00);
2256 val |= fence_size_bits;
de151cf6
JB		 2257 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2258 val |= I830_FENCE_REG_VALID;
2259
2260 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2261}
2262
ae3db24a
DV		 2263static int i915_find_fence_reg(struct drm_device *dev)
2264{
2265 struct drm_i915_fence_reg *reg = NULL;
2266 struct drm_i915_gem_object *obj_priv = NULL;
2267 struct drm_i915_private *dev_priv = dev->dev_private;
2268 struct drm_gem_object *obj = NULL;
2269 int i, avail, ret;
2270
2271 /* First try to find a free reg */
2272 avail = 0;
2273 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2274 reg = &dev_priv->fence_regs[i];
2275 if (!reg->obj)
2276 return i;
2277
23010e43 2278 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2279 if (!obj_priv->pin_count)
2280 avail++;
2281 }
2282
2283 if (avail == 0)
2284 return -ENOSPC;
2285
2286 /* None available, try to steal one or wait for a user to finish */
2287 i = I915_FENCE_REG_NONE;
007cc8ac
DV		 2288 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2289 lru_list) {
2290 obj = reg->obj;
2291 obj_priv = to_intel_bo(obj);
ae3db24a
DV		 2292
2293 if (obj_priv->pin_count)
2294 continue;
2295
2296 /* found one! */
2297 i = obj_priv->fence_reg;
2298 break;
2299 }
2300
2301 BUG_ON(i == I915_FENCE_REG_NONE);
2302
2303 /* We only have a reference on obj from the active list. put_fence_reg
2304 * might drop that one, causing a use-after-free in it. So hold a
2305 * private reference to obj like the other callers of put_fence_reg
2306 * (set_tiling ioctl) do. */
2307 drm_gem_object_reference(obj);
2308 ret = i915_gem_object_put_fence_reg(obj);
2309 drm_gem_object_unreference(obj);
2310 if (ret != 0)
2311 return ret;
2312
2313 return i;
2314}
2315
de151cf6
JB		 2316/**
2317 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2318 * @obj: object to map through a fence reg
2319 *
2320 * When mapping objects through the GTT, userspace wants to be able to write
2321 * to them without having to worry about swizzling if the object is tiled.
2322 *
2323 * This function walks the fence regs looking for a free one for @obj,
2324 * stealing one if it can't find any.
2325 *
2326 * It then sets up the reg based on the object's properties: address, pitch
2327 * and tiling format.
2328 */
8c4b8c3f
CW		 2329int
2330i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2331{
2332 struct drm_device *dev = obj->dev;
79e53945 2333 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2334 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2335 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2336 int ret;
de151cf6 2337
a09ba7fa
EA		 2338 /* Just update our place in the LRU if our fence is getting used. */
2339 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 2340 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2341 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa
EA		 2342 return 0;
2343 }
2344
de151cf6
JB		 2345 switch (obj_priv->tiling_mode) {
2346 case I915_TILING_NONE:
2347 WARN(1, "allocating a fence for non-tiled object?\n");
2348 break;
2349 case I915_TILING_X:
0f973f27
JB		 2350 if (!obj_priv->stride)
2351 return -EINVAL;
2352 WARN((obj_priv->stride & (512 - 1)),
2353 "object 0x%08x is X tiled but has non-512B pitch\n",
2354 obj_priv->gtt_offset);
de151cf6
JB		 2355 break;
2356 case I915_TILING_Y:
0f973f27
JB		 2357 if (!obj_priv->stride)
2358 return -EINVAL;
2359 WARN((obj_priv->stride & (128 - 1)),
2360 "object 0x%08x is Y tiled but has non-128B pitch\n",
2361 obj_priv->gtt_offset);
de151cf6
JB		 2362 break;
2363 }
2364
ae3db24a
DV		 2365 ret = i915_find_fence_reg(dev);
2366 if (ret < 0)
2367 return ret;
de151cf6 2368
ae3db24a
DV		 2369 obj_priv->fence_reg = ret;
2370 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
007cc8ac 2371 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa 2372
de151cf6
JB		 2373 reg->obj = obj;
2374
4e901fdc
EA		 2375 if (IS_GEN6(dev))
2376 sandybridge_write_fence_reg(reg);
2377 else if (IS_I965G(dev))
de151cf6
JB		 2378 i965_write_fence_reg(reg);
2379 else if (IS_I9XX(dev))
2380 i915_write_fence_reg(reg);
2381 else
2382 i830_write_fence_reg(reg);
d9ddcb96 2383
ae3db24a
DV		 2384 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2385 obj_priv->tiling_mode);
1c5d22f7 2386
d9ddcb96 2387 return 0;
de151cf6
JB		 2388}
2389
2390/**
2391 * i915_gem_clear_fence_reg - clear out fence register info
2392 * @obj: object to clear
2393 *
2394 * Zeroes out the fence register itself and clears out the associated
2395 * data structures in dev_priv and obj_priv.
2396 */
2397static void
2398i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2399{
2400 struct drm_device *dev = obj->dev;
79e53945 2401 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2402 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
007cc8ac
DV		 2403 struct drm_i915_fence_reg *reg =
2404 &dev_priv->fence_regs[obj_priv->fence_reg];
de151cf6 2405
4e901fdc
EA		 2406 if (IS_GEN6(dev)) {
2407 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2408 (obj_priv->fence_reg * 8), 0);
2409 } else if (IS_I965G(dev)) {
de151cf6 2410 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
4e901fdc 2411 } else {
dc529a4f
EA		 2412 uint32_t fence_reg;
2413
2414 if (obj_priv->fence_reg < 8)
2415 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2416 else
2417 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2418 8) * 4;
2419
2420 I915_WRITE(fence_reg, 0);
2421 }
de151cf6 2422
007cc8ac 2423 reg->obj = NULL;
de151cf6 2424 obj_priv->fence_reg = I915_FENCE_REG_NONE;
007cc8ac 2425 list_del_init(&reg->lru_list);
de151cf6
JB		 2426}
2427
52dc7d32
CW		 2428/**
2429 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2430 * to the buffer to finish, and then resets the fence register.
2431 * @obj: tiled object holding a fence register.
2432 *
2433 * Zeroes out the fence register itself and clears out the associated
2434 * data structures in dev_priv and obj_priv.
2435 */
2436int
2437i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2438{
2439 struct drm_device *dev = obj->dev;
23010e43 2440 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2441
2442 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2443 return 0;
2444
10ae9bd2
DV		 2445 /* If we've changed tiling, GTT-mappings of the object
2446 * need to re-fault to ensure that the correct fence register
2447 * setup is in place.
2448 */
2449 i915_gem_release_mmap(obj);
2450
52dc7d32
CW		 2451 /* On the i915, GPU access to tiled buffers is via a fence,
2452 * therefore we must wait for any outstanding access to complete
2453 * before clearing the fence.
2454 */
2455 if (!IS_I965G(dev)) {
2456 int ret;
2457
2dafb1e0
CW		 2458 ret = i915_gem_object_flush_gpu_write_domain(obj);
2459 if (ret != 0)
2460 return ret;
2461
e35a41de 2462 ret = i915_gem_object_wait_rendering(obj, true);
52dc7d32
CW		 2463 if (ret != 0)
2464 return ret;
2465 }
2466
4a726612 2467 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2468 i915_gem_clear_fence_reg (obj);
2469
2470 return 0;
2471}
2472
673a394b
EA		 2473/**
2474 * Finds free space in the GTT aperture and binds the object there.
2475 */
2476static int
2477i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2478{
2479 struct drm_device *dev = obj->dev;
2480 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2481 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2482 struct drm_mm_node *free_space;
4bdadb97 2483 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2484 int ret;
673a394b 2485
bb6baf76 2486 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2487 DRM_ERROR("Attempting to bind a purgeable object\n");
2488 return -EINVAL;
2489 }
2490
673a394b 2491 if (alignment == 0)
0f973f27 2492 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2493 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2494 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2495 return -EINVAL;
2496 }
2497
654fc607
CW		 2498 /* If the object is bigger than the entire aperture, reject it early
2499 * before evicting everything in a vain attempt to find space.
2500 */
2501 if (obj->size > dev->gtt_total) {
2502 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2503 return -E2BIG;
2504 }
2505
673a394b
EA		 2506 search_free:
2507 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2508 obj->size, alignment, 0);
2509 if (free_space != NULL) {
2510 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2511 alignment);
db3307a9 2512 if (obj_priv->gtt_space != NULL)
673a394b 2513 obj_priv->gtt_offset = obj_priv->gtt_space->start;
673a394b
EA		 2514 }
2515 if (obj_priv->gtt_space == NULL) {
2516 /* If the gtt is empty and we're still having trouble
2517 * fitting our object in, we're out of memory.
2518 */
2519#if WATCH_LRU
2520 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2521#endif
0108a3ed 2522 ret = i915_gem_evict_something(dev, obj->size, alignment);
9731129c 2523 if (ret)
673a394b 2524 return ret;
9731129c 2525
673a394b
EA		 2526 goto search_free;
2527 }
2528
2529#if WATCH_BUF
cfd43c02 2530 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2531 obj->size, obj_priv->gtt_offset);
2532#endif
4bdadb97 2533 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2534 if (ret) {
2535 drm_mm_put_block(obj_priv->gtt_space);
2536 obj_priv->gtt_space = NULL;
07f73f69
CW		 2537
2538 if (ret == -ENOMEM) {
2539 /* first try to clear up some space from the GTT */
0108a3ed
DV		 2540 ret = i915_gem_evict_something(dev, obj->size,
2541 alignment);
07f73f69 2542 if (ret) {
07f73f69 2543 /* now try to shrink everyone else */
4bdadb97
CW		 2544 if (gfpmask) {
2545 gfpmask = 0;
2546 goto search_free;
07f73f69
CW		 2547 }
2548
2549 return ret;
2550 }
2551
2552 goto search_free;
2553 }
2554
673a394b
EA		 2555 return ret;
2556 }
2557
673a394b
EA		 2558 /* Create an AGP memory structure pointing at our pages, and bind it
2559 * into the GTT.
2560 */
2561 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2562 obj_priv->pages,
07f73f69 2563 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2564 obj_priv->gtt_offset,
2565 obj_priv->agp_type);
673a394b 2566 if (obj_priv->agp_mem == NULL) {
856fa198 2567 i915_gem_object_put_pages(obj);
673a394b
EA		 2568 drm_mm_put_block(obj_priv->gtt_space);
2569 obj_priv->gtt_space = NULL;
07f73f69 2570
0108a3ed 2571 ret = i915_gem_evict_something(dev, obj->size, alignment);
9731129c 2572 if (ret)
07f73f69 2573 return ret;
07f73f69
CW		 2574
2575 goto search_free;
673a394b
EA		 2576 }
2577 atomic_inc(&dev->gtt_count);
2578 atomic_add(obj->size, &dev->gtt_memory);
2579
bf1a1092
CW		 2580 /* keep track of bounds object by adding it to the inactive list */
2581 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2582
673a394b
EA		 2583 /* Assert that the object is not currently in any GPU domain. As it
2584 * wasn't in the GTT, there shouldn't be any way it could have been in
2585 * a GPU cache
2586 */
21d509e3
CW		 2587 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2588 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2589
1c5d22f7
CW		 2590 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2591
673a394b
EA		 2592 return 0;
2593}
2594
2595void
2596i915_gem_clflush_object(struct drm_gem_object *obj)
2597{
23010e43 2598 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2599
2600 /* If we don't have a page list set up, then we're not pinned
2601 * to GPU, and we can ignore the cache flush because it'll happen
2602 * again at bind time.
2603 */
856fa198 2604 if (obj_priv->pages == NULL)
673a394b
EA		 2605 return;
2606
1c5d22f7 2607 trace_i915_gem_object_clflush(obj);
cfa16a0d 2608
856fa198 2609 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2610}
2611
e47c68e9 2612/** Flushes any GPU write domain for the object if it's dirty. */
2dafb1e0 2613static int
e47c68e9
EA		 2614i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2615{
2616 struct drm_device *dev = obj->dev;
1c5d22f7 2617 uint32_t old_write_domain;
852835f3 2618 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
e47c68e9
EA		 2619
2620 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2dafb1e0 2621 return 0;
e47c68e9
EA		 2622
2623 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2624 old_write_domain = obj->write_domain;
e47c68e9 2625 i915_gem_flush(dev, 0, obj->write_domain);
8a1a49f9 2626 if (i915_add_request(dev, NULL, obj_priv->ring) == 0)
2dafb1e0 2627 return -ENOMEM;
1c5d22f7
CW		 2628
2629 trace_i915_gem_object_change_domain(obj,
2630 obj->read_domains,
2631 old_write_domain);
2dafb1e0 2632 return 0;
e47c68e9
EA		 2633}
2634
2635/** Flushes the GTT write domain for the object if it's dirty. */
2636static void
2637i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2638{
1c5d22f7
CW		 2639 uint32_t old_write_domain;
2640
e47c68e9
EA		 2641 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2642 return;
2643
2644 /* No actual flushing is required for the GTT write domain. Writes
2645 * to it immediately go to main memory as far as we know, so there's
2646 * no chipset flush. It also doesn't land in render cache.
2647 */
1c5d22f7 2648 old_write_domain = obj->write_domain;
e47c68e9 2649 obj->write_domain = 0;
1c5d22f7
CW		 2650
2651 trace_i915_gem_object_change_domain(obj,
2652 obj->read_domains,
2653 old_write_domain);
e47c68e9
EA		 2654}
2655
2656/** Flushes the CPU write domain for the object if it's dirty. */
2657static void
2658i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2659{
2660 struct drm_device *dev = obj->dev;
1c5d22f7 2661 uint32_t old_write_domain;
e47c68e9
EA		 2662
2663 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2664 return;
2665
2666 i915_gem_clflush_object(obj);
2667 drm_agp_chipset_flush(dev);
1c5d22f7 2668 old_write_domain = obj->write_domain;
e47c68e9 2669 obj->write_domain = 0;
1c5d22f7
CW		 2670
2671 trace_i915_gem_object_change_domain(obj,
2672 obj->read_domains,
2673 old_write_domain);
e47c68e9
EA		 2674}
2675
2dafb1e0 2676int
6b95a207
KH		 2677i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2678{
2dafb1e0
CW		 2679 int ret = 0;
2680
6b95a207
KH		 2681 switch (obj->write_domain) {
2682 case I915_GEM_DOMAIN_GTT:
2683 i915_gem_object_flush_gtt_write_domain(obj);
2684 break;
2685 case I915_GEM_DOMAIN_CPU:
2686 i915_gem_object_flush_cpu_write_domain(obj);
2687 break;
2688 default:
2dafb1e0 2689 ret = i915_gem_object_flush_gpu_write_domain(obj);
6b95a207
KH		 2690 break;
2691 }
2dafb1e0
CW		 2692
2693 return ret;
6b95a207
KH		 2694}
2695
2ef7eeaa
EA		 2696/**
2697 * Moves a single object to the GTT read, and possibly write domain.
2698 *
2699 * This function returns when the move is complete, including waiting on
2700 * flushes to occur.
2701 */
79e53945 2702int
2ef7eeaa
EA		 2703i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2704{
23010e43 2705 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2706 uint32_t old_write_domain, old_read_domains;
e47c68e9 2707 int ret;
2ef7eeaa 2708
02354392
EA		 2709 /* Not valid to be called on unbound objects. */
2710 if (obj_priv->gtt_space == NULL)
2711 return -EINVAL;
2712
2dafb1e0
CW		 2713 ret = i915_gem_object_flush_gpu_write_domain(obj);
2714 if (ret != 0)
2715 return ret;
2716
e47c68e9 2717 /* Wait on any GPU rendering and flushing to occur. */
e35a41de 2718 ret = i915_gem_object_wait_rendering(obj, true);
e47c68e9
EA		 2719 if (ret != 0)
2720 return ret;
2721
1c5d22f7
CW		 2722 old_write_domain = obj->write_domain;
2723 old_read_domains = obj->read_domains;
2724
e47c68e9
EA		 2725 /* If we're writing through the GTT domain, then CPU and GPU caches
2726 * will need to be invalidated at next use.
2ef7eeaa 2727 */
e47c68e9
EA		 2728 if (write)
2729 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2730
e47c68e9 2731 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2732
e47c68e9
EA		 2733 /* It should now be out of any other write domains, and we can update
2734 * the domain values for our changes.
2735 */
2736 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2737 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2738 if (write) {
2739 obj->write_domain = I915_GEM_DOMAIN_GTT;
2740 obj_priv->dirty = 1;
2ef7eeaa
EA		 2741 }
2742
1c5d22f7
CW		 2743 trace_i915_gem_object_change_domain(obj,
2744 old_read_domains,
2745 old_write_domain);
2746
e47c68e9
EA		 2747 return 0;
2748}
2749
b9241ea3
ZW		 2750/*
2751 * Prepare buffer for display plane. Use uninterruptible for possible flush
2752 * wait, as in modesetting process we're not supposed to be interrupted.
2753 */
2754int
2755i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2756{
23010e43 2757 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2758 uint32_t old_write_domain, old_read_domains;
2759 int ret;
2760
2761 /* Not valid to be called on unbound objects. */
2762 if (obj_priv->gtt_space == NULL)
2763 return -EINVAL;
2764
2dafb1e0
CW		 2765 ret = i915_gem_object_flush_gpu_write_domain(obj);
2766 if (ret)
2767 return ret;
b9241ea3
ZW		 2768
2769 /* Wait on any GPU rendering and flushing to occur. */
e35a41de
DV		 2770 ret = i915_gem_object_wait_rendering(obj, false);
2771 if (ret != 0)
2772 return ret;
b9241ea3 2773
b118c1e3
CW		 2774 i915_gem_object_flush_cpu_write_domain(obj);
2775
b9241ea3
ZW		 2776 old_write_domain = obj->write_domain;
2777 old_read_domains = obj->read_domains;
2778
b9241ea3
ZW		 2779 /* It should now be out of any other write domains, and we can update
2780 * the domain values for our changes.
2781 */
2782 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
b118c1e3 2783 obj->read_domains = I915_GEM_DOMAIN_GTT;
b9241ea3
ZW		 2784 obj->write_domain = I915_GEM_DOMAIN_GTT;
2785 obj_priv->dirty = 1;
2786
2787 trace_i915_gem_object_change_domain(obj,
2788 old_read_domains,
2789 old_write_domain);
2790
2791 return 0;
2792}
2793
e47c68e9
EA		 2794/**
2795 * Moves a single object to the CPU read, and possibly write domain.
2796 *
2797 * This function returns when the move is complete, including waiting on
2798 * flushes to occur.
2799 */
2800static int
2801i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2802{
1c5d22f7 2803 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2804 int ret;
2805
2dafb1e0
CW		 2806 ret = i915_gem_object_flush_gpu_write_domain(obj);
2807 if (ret)
2808 return ret;
2809
2ef7eeaa 2810 /* Wait on any GPU rendering and flushing to occur. */
e35a41de 2811 ret = i915_gem_object_wait_rendering(obj, true);
e47c68e9
EA		 2812 if (ret != 0)
2813 return ret;
2ef7eeaa 2814
e47c68e9 2815 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2816
e47c68e9
EA		 2817 /* If we have a partially-valid cache of the object in the CPU,
2818 * finish invalidating it and free the per-page flags.
2ef7eeaa 2819 */
e47c68e9 2820 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2821
1c5d22f7
CW		 2822 old_write_domain = obj->write_domain;
2823 old_read_domains = obj->read_domains;
2824
e47c68e9
EA		 2825 /* Flush the CPU cache if it's still invalid. */
2826 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2827 i915_gem_clflush_object(obj);
2ef7eeaa 2828
e47c68e9 2829 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2830 }
2831
2832 /* It should now be out of any other write domains, and we can update
2833 * the domain values for our changes.
2834 */
e47c68e9
EA		 2835 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2836
2837 /* If we're writing through the CPU, then the GPU read domains will
2838 * need to be invalidated at next use.
2839 */
2840 if (write) {
2841 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2842 obj->write_domain = I915_GEM_DOMAIN_CPU;
2843 }
2ef7eeaa 2844
1c5d22f7
CW		 2845 trace_i915_gem_object_change_domain(obj,
2846 old_read_domains,
2847 old_write_domain);
2848
2ef7eeaa
EA		 2849 return 0;
2850}
2851
673a394b
EA		 2852/*
2853 * Set the next domain for the specified object. This
2854 * may not actually perform the necessary flushing/invaliding though,
2855 * as that may want to be batched with other set_domain operations
2856 *
2857 * This is (we hope) the only really tricky part of gem. The goal
2858 * is fairly simple -- track which caches hold bits of the object
2859 * and make sure they remain coherent. A few concrete examples may
2860 * help to explain how it works. For shorthand, we use the notation
2861 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2862 * a pair of read and write domain masks.
2863 *
2864 * Case 1: the batch buffer
2865 *
2866 * 1. Allocated
2867 * 2. Written by CPU
2868 * 3. Mapped to GTT
2869 * 4. Read by GPU
2870 * 5. Unmapped from GTT
2871 * 6. Freed
2872 *
2873 * Let's take these a step at a time
2874 *
2875 * 1. Allocated
2876 * Pages allocated from the kernel may still have
2877 * cache contents, so we set them to (CPU, CPU) always.
2878 * 2. Written by CPU (using pwrite)
2879 * The pwrite function calls set_domain (CPU, CPU) and
2880 * this function does nothing (as nothing changes)
2881 * 3. Mapped by GTT
2882 * This function asserts that the object is not
2883 * currently in any GPU-based read or write domains
2884 * 4. Read by GPU
2885 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2886 * As write_domain is zero, this function adds in the
2887 * current read domains (CPU+COMMAND, 0).
2888 * flush_domains is set to CPU.
2889 * invalidate_domains is set to COMMAND
2890 * clflush is run to get data out of the CPU caches
2891 * then i915_dev_set_domain calls i915_gem_flush to
2892 * emit an MI_FLUSH and drm_agp_chipset_flush
2893 * 5. Unmapped from GTT
2894 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2895 * flush_domains and invalidate_domains end up both zero
2896 * so no flushing/invalidating happens
2897 * 6. Freed
2898 * yay, done
2899 *
2900 * Case 2: The shared render buffer
2901 *
2902 * 1. Allocated
2903 * 2. Mapped to GTT
2904 * 3. Read/written by GPU
2905 * 4. set_domain to (CPU,CPU)
2906 * 5. Read/written by CPU
2907 * 6. Read/written by GPU
2908 *
2909 * 1. Allocated
2910 * Same as last example, (CPU, CPU)
2911 * 2. Mapped to GTT
2912 * Nothing changes (assertions find that it is not in the GPU)
2913 * 3. Read/written by GPU
2914 * execbuffer calls set_domain (RENDER, RENDER)
2915 * flush_domains gets CPU
2916 * invalidate_domains gets GPU
2917 * clflush (obj)
2918 * MI_FLUSH and drm_agp_chipset_flush
2919 * 4. set_domain (CPU, CPU)
2920 * flush_domains gets GPU
2921 * invalidate_domains gets CPU
2922 * wait_rendering (obj) to make sure all drawing is complete.
2923 * This will include an MI_FLUSH to get the data from GPU
2924 * to memory
2925 * clflush (obj) to invalidate the CPU cache
2926 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2927 * 5. Read/written by CPU
2928 * cache lines are loaded and dirtied
2929 * 6. Read written by GPU
2930 * Same as last GPU access
2931 *
2932 * Case 3: The constant buffer
2933 *
2934 * 1. Allocated
2935 * 2. Written by CPU
2936 * 3. Read by GPU
2937 * 4. Updated (written) by CPU again
2938 * 5. Read by GPU
2939 *
2940 * 1. Allocated
2941 * (CPU, CPU)
2942 * 2. Written by CPU
2943 * (CPU, CPU)
2944 * 3. Read by GPU
2945 * (CPU+RENDER, 0)
2946 * flush_domains = CPU
2947 * invalidate_domains = RENDER
2948 * clflush (obj)
2949 * MI_FLUSH
2950 * drm_agp_chipset_flush
2951 * 4. Updated (written) by CPU again
2952 * (CPU, CPU)
2953 * flush_domains = 0 (no previous write domain)
2954 * invalidate_domains = 0 (no new read domains)
2955 * 5. Read by GPU
2956 * (CPU+RENDER, 0)
2957 * flush_domains = CPU
2958 * invalidate_domains = RENDER
2959 * clflush (obj)
2960 * MI_FLUSH
2961 * drm_agp_chipset_flush
2962 */
c0d90829 2963static void
8b0e378a 2964i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 2965{
2966 struct drm_device *dev = obj->dev;
23010e43 2967 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2968 uint32_t invalidate_domains = 0;
2969 uint32_t flush_domains = 0;
1c5d22f7 2970 uint32_t old_read_domains;
e47c68e9 2971
8b0e378a
EA		 2972 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2973 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 2974
652c393a
JB		 2975 intel_mark_busy(dev, obj);
2976
673a394b
EA		 2977#if WATCH_BUF
2978 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2979 __func__, obj,
8b0e378a
EA		 2980 obj->read_domains, obj->pending_read_domains,
2981 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 2982#endif
2983 /*
2984 * If the object isn't moving to a new write domain,
2985 * let the object stay in multiple read domains
2986 */
8b0e378a
EA		 2987 if (obj->pending_write_domain == 0)
2988 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 2989 else
2990 obj_priv->dirty = 1;
2991
2992 /*
2993 * Flush the current write domain if
2994 * the new read domains don't match. Invalidate
2995 * any read domains which differ from the old
2996 * write domain
2997 */
8b0e378a
EA		 2998 if (obj->write_domain &&
2999 obj->write_domain != obj->pending_read_domains) {
673a394b 3000 flush_domains |= obj->write_domain;
8b0e378a
EA		 3001 invalidate_domains |=
3002 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3003 }
3004 /*
3005 * Invalidate any read caches which may have
3006 * stale data. That is, any new read domains.
3007 */
8b0e378a 3008 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3009 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3010#if WATCH_BUF
3011 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3012 __func__, flush_domains, invalidate_domains);
3013#endif
673a394b
EA		 3014 i915_gem_clflush_object(obj);
3015 }
3016
1c5d22f7
CW		 3017 old_read_domains = obj->read_domains;
3018
efbeed96
EA		 3019 /* The actual obj->write_domain will be updated with
3020 * pending_write_domain after we emit the accumulated flush for all
3021 * of our domain changes in execbuffers (which clears objects'
3022 * write_domains). So if we have a current write domain that we
3023 * aren't changing, set pending_write_domain to that.
3024 */
3025 if (flush_domains == 0 && obj->pending_write_domain == 0)
3026 obj->pending_write_domain = obj->write_domain;
8b0e378a 3027 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3028
3029 dev->invalidate_domains |= invalidate_domains;
3030 dev->flush_domains |= flush_domains;
3031#if WATCH_BUF
3032 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3033 __func__,
3034 obj->read_domains, obj->write_domain,
3035 dev->invalidate_domains, dev->flush_domains);
3036#endif
1c5d22f7
CW		 3037
3038 trace_i915_gem_object_change_domain(obj,
3039 old_read_domains,
3040 obj->write_domain);
673a394b
EA		 3041}
3042
3043/**
e47c68e9 3044 * Moves the object from a partially CPU read to a full one.
673a394b 3045 *
e47c68e9
EA		 3046 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3047 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3048 */
e47c68e9
EA		 3049static void
3050i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3051{
23010e43 3052 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3053
e47c68e9
EA		 3054 if (!obj_priv->page_cpu_valid)
3055 return;
3056
3057 /* If we're partially in the CPU read domain, finish moving it in.
3058 */
3059 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3060 int i;
3061
3062 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3063 if (obj_priv->page_cpu_valid[i])
3064 continue;
856fa198 3065 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3066 }
e47c68e9
EA		 3067 }
3068
3069 /* Free the page_cpu_valid mappings which are now stale, whether
3070 * or not we've got I915_GEM_DOMAIN_CPU.
3071 */
9a298b2a 3072 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3073 obj_priv->page_cpu_valid = NULL;
3074}
3075
3076/**
3077 * Set the CPU read domain on a range of the object.
3078 *
3079 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3080 * not entirely valid. The page_cpu_valid member of the object flags which
3081 * pages have been flushed, and will be respected by
3082 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3083 * of the whole object.
3084 *
3085 * This function returns when the move is complete, including waiting on
3086 * flushes to occur.
3087 */
3088static int
3089i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3090 uint64_t offset, uint64_t size)
3091{
23010e43 3092 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3093 uint32_t old_read_domains;
e47c68e9 3094 int i, ret;
673a394b 3095
e47c68e9
EA		 3096 if (offset == 0 && size == obj->size)
3097 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3098
2dafb1e0
CW		 3099 ret = i915_gem_object_flush_gpu_write_domain(obj);
3100 if (ret)
3101 return ret;
3102
e47c68e9 3103 /* Wait on any GPU rendering and flushing to occur. */
e35a41de 3104 ret = i915_gem_object_wait_rendering(obj, true);
e47c68e9 3105 if (ret != 0)
6a47baa6 3106 return ret;
e47c68e9
EA		 3107 i915_gem_object_flush_gtt_write_domain(obj);
3108
3109 /* If we're already fully in the CPU read domain, we're done. */
3110 if (obj_priv->page_cpu_valid == NULL &&
3111 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3112 return 0;
673a394b 3113
e47c68e9
EA		 3114 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3115 * newly adding I915_GEM_DOMAIN_CPU
3116 */
673a394b 3117 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3118 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3119 GFP_KERNEL);
e47c68e9
EA		 3120 if (obj_priv->page_cpu_valid == NULL)
3121 return -ENOMEM;
3122 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3123 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3124
3125 /* Flush the cache on any pages that are still invalid from the CPU's
3126 * perspective.
3127 */
e47c68e9
EA		 3128 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3129 i++) {
673a394b
EA		 3130 if (obj_priv->page_cpu_valid[i])
3131 continue;
3132
856fa198 3133 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3134
3135 obj_priv->page_cpu_valid[i] = 1;
3136 }
3137
e47c68e9
EA		 3138 /* It should now be out of any other write domains, and we can update
3139 * the domain values for our changes.
3140 */
3141 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3142
1c5d22f7 3143 old_read_domains = obj->read_domains;
e47c68e9
EA		 3144 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3145
1c5d22f7
CW		 3146 trace_i915_gem_object_change_domain(obj,
3147 old_read_domains,
3148 obj->write_domain);
3149
673a394b
EA		 3150 return 0;
3151}
3152
673a394b
EA		 3153/**
3154 * Pin an object to the GTT and evaluate the relocations landing in it.
3155 */
3156static int
3157i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3158 struct drm_file *file_priv,
76446cac 3159 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3160 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3161{
3162 struct drm_device *dev = obj->dev;
0839ccb8 3163 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3165 int i, ret;
0839ccb8 3166 void __iomem *reloc_page;
76446cac
JB		 3167 bool need_fence;
3168
3169 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3170 obj_priv->tiling_mode != I915_TILING_NONE;
3171
3172 /* Check fence reg constraints and rebind if necessary */
808b24d6
CW		 3173 if (need_fence &&
3174 !i915_gem_object_fence_offset_ok(obj,
3175 obj_priv->tiling_mode)) {
3176 ret = i915_gem_object_unbind(obj);
3177 if (ret)
3178 return ret;
3179 }
673a394b
EA		 3180
3181 /* Choose the GTT offset for our buffer and put it there. */
3182 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3183 if (ret)
3184 return ret;
3185
76446cac
JB		 3186 /*
3187 * Pre-965 chips need a fence register set up in order to
3188 * properly handle blits to/from tiled surfaces.
3189 */
3190 if (need_fence) {
3191 ret = i915_gem_object_get_fence_reg(obj);
3192 if (ret != 0) {
76446cac
JB		 3193 i915_gem_object_unpin(obj);
3194 return ret;
3195 }
3196 }
3197
673a394b
EA		 3198 entry->offset = obj_priv->gtt_offset;
3199
673a394b
EA		 3200 /* Apply the relocations, using the GTT aperture to avoid cache
3201 * flushing requirements.
3202 */
3203 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3204 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3205 struct drm_gem_object *target_obj;
3206 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3207 uint32_t reloc_val, reloc_offset;
3208 uint32_t __iomem *reloc_entry;
673a394b 3209
673a394b 3210 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3211 reloc->target_handle);
673a394b
EA		 3212 if (target_obj == NULL) {
3213 i915_gem_object_unpin(obj);
bf79cb91 3214 return -ENOENT;
673a394b 3215 }
23010e43 3216 target_obj_priv = to_intel_bo(target_obj);
673a394b 3217
8542a0bb
CW		 3218#if WATCH_RELOC
3219 DRM_INFO("%s: obj %p offset %08x target %d "
3220 "read %08x write %08x gtt %08x "
3221 "presumed %08x delta %08x\n",
3222 __func__,
3223 obj,
3224 (int) reloc->offset,
3225 (int) reloc->target_handle,
3226 (int) reloc->read_domains,
3227 (int) reloc->write_domain,
3228 (int) target_obj_priv->gtt_offset,
3229 (int) reloc->presumed_offset,
3230 reloc->delta);
3231#endif
3232
673a394b
EA		 3233 /* The target buffer should have appeared before us in the
3234 * exec_object list, so it should have a GTT space bound by now.
3235 */
3236 if (target_obj_priv->gtt_space == NULL) {
3237 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3238 reloc->target_handle);
673a394b
EA		 3239 drm_gem_object_unreference(target_obj);
3240 i915_gem_object_unpin(obj);
3241 return -EINVAL;
3242 }
3243
8542a0bb 3244 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3245 if (reloc->write_domain & (reloc->write_domain - 1)) {
3246 DRM_ERROR("reloc with multiple write domains: "
3247 "obj %p target %d offset %d "
3248 "read %08x write %08x",
3249 obj, reloc->target_handle,
3250 (int) reloc->offset,
3251 reloc->read_domains,
3252 reloc->write_domain);
3253 return -EINVAL;
3254 }
40a5f0de
EA		 3255 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3256 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3257 DRM_ERROR("reloc with read/write CPU domains: "
3258 "obj %p target %d offset %d "
3259 "read %08x write %08x",
40a5f0de
EA		 3260 obj, reloc->target_handle,
3261 (int) reloc->offset,
3262 reloc->read_domains,
3263 reloc->write_domain);
491152b8
CW		 3264 drm_gem_object_unreference(target_obj);
3265 i915_gem_object_unpin(obj);
e47c68e9
EA		 3266 return -EINVAL;
3267 }
40a5f0de
EA		 3268 if (reloc->write_domain && target_obj->pending_write_domain &&
3269 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3270 DRM_ERROR("Write domain conflict: "
3271 "obj %p target %d offset %d "
3272 "new %08x old %08x\n",
40a5f0de
EA		 3273 obj, reloc->target_handle,
3274 (int) reloc->offset,
3275 reloc->write_domain,
673a394b
EA		 3276 target_obj->pending_write_domain);
3277 drm_gem_object_unreference(target_obj);
3278 i915_gem_object_unpin(obj);
3279 return -EINVAL;
3280 }
3281
40a5f0de
EA		 3282 target_obj->pending_read_domains |= reloc->read_domains;
3283 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3284
3285 /* If the relocation already has the right value in it, no
3286 * more work needs to be done.
3287 */
40a5f0de 3288 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3289 drm_gem_object_unreference(target_obj);
3290 continue;
3291 }
3292
8542a0bb
CW		 3293 /* Check that the relocation address is valid... */
3294 if (reloc->offset > obj->size - 4) {
3295 DRM_ERROR("Relocation beyond object bounds: "
3296 "obj %p target %d offset %d size %d.\n",
3297 obj, reloc->target_handle,
3298 (int) reloc->offset, (int) obj->size);
3299 drm_gem_object_unreference(target_obj);
3300 i915_gem_object_unpin(obj);
3301 return -EINVAL;
3302 }
3303 if (reloc->offset & 3) {
3304 DRM_ERROR("Relocation not 4-byte aligned: "
3305 "obj %p target %d offset %d.\n",
3306 obj, reloc->target_handle,
3307 (int) reloc->offset);
3308 drm_gem_object_unreference(target_obj);
3309 i915_gem_object_unpin(obj);
3310 return -EINVAL;
3311 }
3312
3313 /* and points to somewhere within the target object. */
3314 if (reloc->delta >= target_obj->size) {
3315 DRM_ERROR("Relocation beyond target object bounds: "
3316 "obj %p target %d delta %d size %d.\n",
3317 obj, reloc->target_handle,
3318 (int) reloc->delta, (int) target_obj->size);
3319 drm_gem_object_unreference(target_obj);
3320 i915_gem_object_unpin(obj);
3321 return -EINVAL;
3322 }
3323
2ef7eeaa
EA		 3324 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3325 if (ret != 0) {
3326 drm_gem_object_unreference(target_obj);
3327 i915_gem_object_unpin(obj);
3328 return -EINVAL;
673a394b
EA		 3329 }
3330
3331 /* Map the page containing the relocation we're going to
3332 * perform.
3333 */
40a5f0de 3334 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3335 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3336 (reloc_offset &
fca3ec01
CW		 3337 ~(PAGE_SIZE - 1)),
3338 KM_USER0);
3043c60c 3339 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3340 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3341 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3342
3343#if WATCH_BUF
3344 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3345 obj, (unsigned int) reloc->offset,
673a394b
EA		 3346 readl(reloc_entry), reloc_val);
3347#endif
3348 writel(reloc_val, reloc_entry);
fca3ec01 3349 io_mapping_unmap_atomic(reloc_page, KM_USER0);
673a394b 3350
40a5f0de
EA		 3351 /* The updated presumed offset for this entry will be
3352 * copied back out to the user.
673a394b 3353 */
40a5f0de 3354 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3355
3356 drm_gem_object_unreference(target_obj);
3357 }
3358
673a394b
EA		 3359#if WATCH_BUF
3360 if (0)
3361 i915_gem_dump_object(obj, 128, __func__, ~0);
3362#endif
3363 return 0;
3364}
3365
673a394b
EA		 3366/* Throttle our rendering by waiting until the ring has completed our requests
3367 * emitted over 20 msec ago.
3368 *
b962442e
EA		 3369 * Note that if we were to use the current jiffies each time around the loop,
3370 * we wouldn't escape the function with any frames outstanding if the time to
3371 * render a frame was over 20ms.
3372 *
673a394b
EA		 3373 * This should get us reasonable parallelism between CPU and GPU but also
3374 * relatively low latency when blocking on a particular request to finish.
3375 */
3376static int
3377i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3378{
3379 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3380 int ret = 0;
b962442e 3381 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3382
3383 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3384 while (!list_empty(&i915_file_priv->mm.request_list)) {
3385 struct drm_i915_gem_request *request;
3386
3387 request = list_first_entry(&i915_file_priv->mm.request_list,
3388 struct drm_i915_gem_request,
3389 client_list);
3390
3391 if (time_after_eq(request->emitted_jiffies, recent_enough))
3392 break;
3393
852835f3 3394 ret = i915_wait_request(dev, request->seqno, request->ring);
b962442e
EA		 3395 if (ret != 0)
3396 break;
3397 }
673a394b 3398 mutex_unlock(&dev->struct_mutex);
b962442e 3399
673a394b
EA		 3400 return ret;
3401}
3402
40a5f0de 3403static int
76446cac 3404i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3405 uint32_t buffer_count,
3406 struct drm_i915_gem_relocation_entry **relocs)
3407{
3408 uint32_t reloc_count = 0, reloc_index = 0, i;
3409 int ret;
3410
3411 *relocs = NULL;
3412 for (i = 0; i < buffer_count; i++) {
3413 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3414 return -EINVAL;
3415 reloc_count += exec_list[i].relocation_count;
3416 }
3417
8e7d2b2c 3418 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3419 if (*relocs == NULL) {
3420 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3421 return -ENOMEM;
76446cac 3422 }
40a5f0de
EA		 3423
3424 for (i = 0; i < buffer_count; i++) {
3425 struct drm_i915_gem_relocation_entry __user *user_relocs;
3426
3427 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3428
3429 ret = copy_from_user(&(*relocs)[reloc_index],
3430 user_relocs,
3431 exec_list[i].relocation_count *
3432 sizeof(**relocs));
3433 if (ret != 0) {
8e7d2b2c 3434 drm_free_large(*relocs);
40a5f0de 3435 *relocs = NULL;
2bc43b5c 3436 return -EFAULT;
40a5f0de
EA		 3437 }
3438
3439 reloc_index += exec_list[i].relocation_count;
3440 }
3441
2bc43b5c 3442 return 0;
40a5f0de
EA		 3443}
3444
3445static int
76446cac 3446i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3447 uint32_t buffer_count,
3448 struct drm_i915_gem_relocation_entry *relocs)
3449{
3450 uint32_t reloc_count = 0, i;
2bc43b5c 3451 int ret = 0;
40a5f0de 3452
93533c29
CW		 3453 if (relocs == NULL)
3454 return 0;
3455
40a5f0de
EA		 3456 for (i = 0; i < buffer_count; i++) {
3457 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3458 int unwritten;
40a5f0de
EA		 3459
3460 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3461
2bc43b5c
FM		 3462 unwritten = copy_to_user(user_relocs,
3463 &relocs[reloc_count],
3464 exec_list[i].relocation_count *
3465 sizeof(*relocs));
3466
3467 if (unwritten) {
3468 ret = -EFAULT;
3469 goto err;
40a5f0de
EA		 3470 }
3471
3472 reloc_count += exec_list[i].relocation_count;
3473 }
3474
2bc43b5c 3475err:
8e7d2b2c 3476 drm_free_large(relocs);
40a5f0de
EA		 3477
3478 return ret;
3479}
3480
83d60795 3481static int
76446cac 3482i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3483 uint64_t exec_offset)
3484{
3485 uint32_t exec_start, exec_len;
3486
3487 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3488 exec_len = (uint32_t) exec->batch_len;
3489
3490 if ((exec_start | exec_len) & 0x7)
3491 return -EINVAL;
3492
3493 if (!exec_start)
3494 return -EINVAL;
3495
3496 return 0;
3497}
3498
6b95a207
KH		 3499static int
3500i915_gem_wait_for_pending_flip(struct drm_device *dev,
3501 struct drm_gem_object **object_list,
3502 int count)
3503{
3504 drm_i915_private_t *dev_priv = dev->dev_private;
3505 struct drm_i915_gem_object *obj_priv;
3506 DEFINE_WAIT(wait);
3507 int i, ret = 0;
3508
3509 for (;;) {
3510 prepare_to_wait(&dev_priv->pending_flip_queue,
3511 &wait, TASK_INTERRUPTIBLE);
3512 for (i = 0; i < count; i++) {
23010e43 3513 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3514 if (atomic_read(&obj_priv->pending_flip) > 0)
3515 break;
3516 }
3517 if (i == count)
3518 break;
3519
3520 if (!signal_pending(current)) {
3521 mutex_unlock(&dev->struct_mutex);
3522 schedule();
3523 mutex_lock(&dev->struct_mutex);
3524 continue;
3525 }
3526 ret = -ERESTARTSYS;
3527 break;
3528 }
3529 finish_wait(&dev_priv->pending_flip_queue, &wait);
3530
3531 return ret;
3532}
3533
43b27f40 3534
673a394b 3535int
76446cac
JB		 3536i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3537 struct drm_file *file_priv,
3538 struct drm_i915_gem_execbuffer2 *args,
3539 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3540{
3541 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3542 struct drm_gem_object **object_list = NULL;
3543 struct drm_gem_object *batch_obj;
b70d11da 3544 struct drm_i915_gem_object *obj_priv;
201361a5 3545 struct drm_clip_rect *cliprects = NULL;
93533c29 3546 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3547 int ret = 0, ret2, i, pinned = 0;
673a394b 3548 uint64_t exec_offset;
8a1a49f9 3549 uint32_t seqno, reloc_index;
6b95a207 3550 int pin_tries, flips;
673a394b 3551
852835f3
ZN		 3552 struct intel_ring_buffer *ring = NULL;
3553
673a394b
EA		 3554#if WATCH_EXEC
3555 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3556 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3557#endif
d1b851fc
ZN		 3558 if (args->flags & I915_EXEC_BSD) {
3559 if (!HAS_BSD(dev)) {
3560 DRM_ERROR("execbuf with wrong flag\n");
3561 return -EINVAL;
3562 }
3563 ring = &dev_priv->bsd_ring;
3564 } else {
3565 ring = &dev_priv->render_ring;
3566 }
3567
4f481ed2
EA		 3568 if (args->buffer_count < 1) {
3569 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3570 return -EINVAL;
3571 }
c8e0f93a 3572 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3573 if (object_list == NULL) {
3574 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3575 args->buffer_count);
3576 ret = -ENOMEM;
3577 goto pre_mutex_err;
3578 }
673a394b 3579
201361a5 3580 if (args->num_cliprects != 0) {
9a298b2a
EA		 3581 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3582 GFP_KERNEL);
a40e8d31
OA		 3583 if (cliprects == NULL) {
3584 ret = -ENOMEM;
201361a5 3585 goto pre_mutex_err;
a40e8d31 3586 }
201361a5
EA		 3587
3588 ret = copy_from_user(cliprects,
3589 (struct drm_clip_rect __user *)
3590 (uintptr_t) args->cliprects_ptr,
3591 sizeof(*cliprects) * args->num_cliprects);
3592 if (ret != 0) {
3593 DRM_ERROR("copy %d cliprects failed: %d\n",
3594 args->num_cliprects, ret);
c877cdce 3595 ret = -EFAULT;
201361a5
EA		 3596 goto pre_mutex_err;
3597 }
3598 }
3599
40a5f0de
EA		 3600 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3601 &relocs);
3602 if (ret != 0)
3603 goto pre_mutex_err;
3604
673a394b
EA		 3605 mutex_lock(&dev->struct_mutex);
3606
3607 i915_verify_inactive(dev, __FILE__, __LINE__);
3608
ba1234d1 3609 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3610 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3611 ret = -EIO;
3612 goto pre_mutex_err;
673a394b
EA		 3613 }
3614
3615 if (dev_priv->mm.suspended) {
673a394b 3616 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3617 ret = -EBUSY;
3618 goto pre_mutex_err;
673a394b
EA		 3619 }
3620
ac94a962 3621 /* Look up object handles */
6b95a207 3622 flips = 0;
673a394b
EA		 3623 for (i = 0; i < args->buffer_count; i++) {
3624 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3625 exec_list[i].handle);
3626 if (object_list[i] == NULL) {
3627 DRM_ERROR("Invalid object handle %d at index %d\n",
3628 exec_list[i].handle, i);
0ce907f8
CW		 3629 /* prevent error path from reading uninitialized data */
3630 args->buffer_count = i + 1;
bf79cb91 3631 ret = -ENOENT;
673a394b
EA		 3632 goto err;
3633 }
b70d11da 3634
23010e43 3635 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3636 if (obj_priv->in_execbuffer) {
3637 DRM_ERROR("Object %p appears more than once in object list\n",
3638 object_list[i]);
0ce907f8
CW		 3639 /* prevent error path from reading uninitialized data */
3640 args->buffer_count = i + 1;
bf79cb91 3641 ret = -EINVAL;
b70d11da
KH		 3642 goto err;
3643 }
3644 obj_priv->in_execbuffer = true;
6b95a207
KH		 3645 flips += atomic_read(&obj_priv->pending_flip);
3646 }
3647
3648 if (flips > 0) {
3649 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3650 args->buffer_count);
3651 if (ret)
3652 goto err;
ac94a962 3653 }
673a394b 3654
ac94a962
KP		 3655 /* Pin and relocate */
3656 for (pin_tries = 0; ; pin_tries++) {
3657 ret = 0;
40a5f0de
EA		 3658 reloc_index = 0;
3659
ac94a962
KP		 3660 for (i = 0; i < args->buffer_count; i++) {
3661 object_list[i]->pending_read_domains = 0;
3662 object_list[i]->pending_write_domain = 0;
3663 ret = i915_gem_object_pin_and_relocate(object_list[i],
3664 file_priv,
40a5f0de
EA		 3665 &exec_list[i],
3666 &relocs[reloc_index]);
ac94a962
KP		 3667 if (ret)
3668 break;
3669 pinned = i + 1;
40a5f0de 3670 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3671 }
3672 /* success */
3673 if (ret == 0)
3674 break;
3675
3676 /* error other than GTT full, or we've already tried again */
2939e1f5 3677 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3678 if (ret != -ERESTARTSYS) {
3679 unsigned long long total_size = 0;
3d1cc470
CW		 3680 int num_fences = 0;
3681 for (i = 0; i < args->buffer_count; i++) {
43b27f40 3682 obj_priv = to_intel_bo(object_list[i]);
3d1cc470 3683
07f73f69 3684 total_size += object_list[i]->size;
3d1cc470
CW		 3685 num_fences +=
3686 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3687 obj_priv->tiling_mode != I915_TILING_NONE;
3688 }
3689 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
07f73f69 3690 pinned+1, args->buffer_count,
3d1cc470
CW		 3691 total_size, num_fences,
3692 ret);
07f73f69
CW		 3693 DRM_ERROR("%d objects [%d pinned], "
3694 "%d object bytes [%d pinned], "
3695 "%d/%d gtt bytes\n",
3696 atomic_read(&dev->object_count),
3697 atomic_read(&dev->pin_count),
3698 atomic_read(&dev->object_memory),
3699 atomic_read(&dev->pin_memory),
3700 atomic_read(&dev->gtt_memory),
3701 dev->gtt_total);
3702 }
673a394b
EA		 3703 goto err;
3704 }
ac94a962
KP		 3705
3706 /* unpin all of our buffers */
3707 for (i = 0; i < pinned; i++)
3708 i915_gem_object_unpin(object_list[i]);
b1177636 3709 pinned = 0;
ac94a962
KP		 3710
3711 /* evict everyone we can from the aperture */
3712 ret = i915_gem_evict_everything(dev);
07f73f69 3713 if (ret && ret != -ENOSPC)
ac94a962 3714 goto err;
673a394b
EA		 3715 }
3716
3717 /* Set the pending read domains for the batch buffer to COMMAND */
3718 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3719 if (batch_obj->pending_write_domain) {
3720 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3721 ret = -EINVAL;
3722 goto err;
3723 }
3724 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3725
83d60795
CW		 3726 /* Sanity check the batch buffer, prior to moving objects */
3727 exec_offset = exec_list[args->buffer_count - 1].offset;
3728 ret = i915_gem_check_execbuffer (args, exec_offset);
3729 if (ret != 0) {
3730 DRM_ERROR("execbuf with invalid offset/length\n");
3731 goto err;
3732 }
3733
673a394b
EA		 3734 i915_verify_inactive(dev, __FILE__, __LINE__);
3735
646f0f6e
KP		 3736 /* Zero the global flush/invalidate flags. These
3737 * will be modified as new domains are computed
3738 * for each object
3739 */
3740 dev->invalidate_domains = 0;
3741 dev->flush_domains = 0;
3742
673a394b
EA		 3743 for (i = 0; i < args->buffer_count; i++) {
3744 struct drm_gem_object *obj = object_list[i];
673a394b 3745
646f0f6e 3746 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3747 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3748 }
3749
3750 i915_verify_inactive(dev, __FILE__, __LINE__);
3751
646f0f6e
KP		 3752 if (dev->invalidate_domains | dev->flush_domains) {
3753#if WATCH_EXEC
3754 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3755 __func__,
3756 dev->invalidate_domains,
3757 dev->flush_domains);
3758#endif
3759 i915_gem_flush(dev,
3760 dev->invalidate_domains,
3761 dev->flush_domains);
a6910434
DV		 3762 }
3763
3764 if (dev_priv->render_ring.outstanding_lazy_request) {
8a1a49f9 3765 (void)i915_add_request(dev, file_priv, &dev_priv->render_ring);
a6910434
DV		 3766 dev_priv->render_ring.outstanding_lazy_request = false;
3767 }
3768 if (dev_priv->bsd_ring.outstanding_lazy_request) {
8a1a49f9 3769 (void)i915_add_request(dev, file_priv, &dev_priv->bsd_ring);
a6910434 3770 dev_priv->bsd_ring.outstanding_lazy_request = false;
646f0f6e 3771 }
673a394b 3772
efbeed96
EA		 3773 for (i = 0; i < args->buffer_count; i++) {
3774 struct drm_gem_object *obj = object_list[i];
23010e43 3775 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3776 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3777
3778 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3779 if (obj->write_domain)
3780 list_move_tail(&obj_priv->gpu_write_list,
3781 &dev_priv->mm.gpu_write_list);
3782 else
3783 list_del_init(&obj_priv->gpu_write_list);
3784
1c5d22f7
CW		 3785 trace_i915_gem_object_change_domain(obj,
3786 obj->read_domains,
3787 old_write_domain);
efbeed96
EA		 3788 }
3789
673a394b
EA		 3790 i915_verify_inactive(dev, __FILE__, __LINE__);
3791
3792#if WATCH_COHERENCY
3793 for (i = 0; i < args->buffer_count; i++) {
3794 i915_gem_object_check_coherency(object_list[i],
3795 exec_list[i].handle);
3796 }
3797#endif
3798
673a394b 3799#if WATCH_EXEC
6911a9b8 3800 i915_gem_dump_object(batch_obj,
673a394b
EA		 3801 args->batch_len,
3802 __func__,
3803 ~0);
3804#endif
3805
673a394b 3806 /* Exec the batchbuffer */
852835f3
ZN		 3807 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3808 cliprects, exec_offset);
673a394b
EA		 3809 if (ret) {
3810 DRM_ERROR("dispatch failed %d\n", ret);
3811 goto err;
3812 }
3813
3814 /*
3815 * Ensure that the commands in the batch buffer are
3816 * finished before the interrupt fires
3817 */
8a1a49f9 3818 i915_retire_commands(dev, ring);
673a394b
EA		 3819
3820 i915_verify_inactive(dev, __FILE__, __LINE__);
3821
3822 /*
3823 * Get a seqno representing the execution of the current buffer,
3824 * which we can wait on. We would like to mitigate these interrupts,
3825 * likely by only creating seqnos occasionally (so that we have
3826 * *some* interrupts representing completion of buffers that we can
3827 * wait on when trying to clear up gtt space).
3828 */
8a1a49f9 3829 seqno = i915_add_request(dev, file_priv, ring);
673a394b
EA		 3830 for (i = 0; i < args->buffer_count; i++) {
3831 struct drm_gem_object *obj = object_list[i];
852835f3 3832 obj_priv = to_intel_bo(obj);
673a394b 3833
852835f3 3834 i915_gem_object_move_to_active(obj, seqno, ring);
673a394b
EA		 3835#if WATCH_LRU
3836 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3837#endif
3838 }
3839#if WATCH_LRU
3840 i915_dump_lru(dev, __func__);
3841#endif
3842
3843 i915_verify_inactive(dev, __FILE__, __LINE__);
3844
673a394b 3845err:
aad87dff
JL		 3846 for (i = 0; i < pinned; i++)
3847 i915_gem_object_unpin(object_list[i]);
3848
b70d11da
KH		 3849 for (i = 0; i < args->buffer_count; i++) {
3850 if (object_list[i]) {
23010e43 3851 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3852 obj_priv->in_execbuffer = false;
3853 }
aad87dff 3854 drm_gem_object_unreference(object_list[i]);
b70d11da 3855 }
673a394b 3856
673a394b
EA		 3857 mutex_unlock(&dev->struct_mutex);
3858
93533c29 3859pre_mutex_err:
40a5f0de
EA		 3860 /* Copy the updated relocations out regardless of current error
3861 * state. Failure to update the relocs would mean that the next
3862 * time userland calls execbuf, it would do so with presumed offset
3863 * state that didn't match the actual object state.
3864 */
3865 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3866 relocs);
3867 if (ret2 != 0) {
3868 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3869
3870 if (ret == 0)
3871 ret = ret2;
3872 }
3873
8e7d2b2c 3874 drm_free_large(object_list);
9a298b2a 3875 kfree(cliprects);
673a394b
EA		 3876
3877 return ret;
3878}
3879
76446cac
JB		 3880/*
3881 * Legacy execbuffer just creates an exec2 list from the original exec object
3882 * list array and passes it to the real function.
3883 */
3884int
3885i915_gem_execbuffer(struct drm_device *dev, void *data,
3886 struct drm_file *file_priv)
3887{
3888 struct drm_i915_gem_execbuffer *args = data;
3889 struct drm_i915_gem_execbuffer2 exec2;
3890 struct drm_i915_gem_exec_object *exec_list = NULL;
3891 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3892 int ret, i;
3893
3894#if WATCH_EXEC
3895 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3896 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3897#endif
3898
3899 if (args->buffer_count < 1) {
3900 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3901 return -EINVAL;
3902 }
3903
3904 /* Copy in the exec list from userland */
3905 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3906 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3907 if (exec_list == NULL || exec2_list == NULL) {
3908 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3909 args->buffer_count);
3910 drm_free_large(exec_list);
3911 drm_free_large(exec2_list);
3912 return -ENOMEM;
3913 }
3914 ret = copy_from_user(exec_list,
3915 (struct drm_i915_relocation_entry __user *)
3916 (uintptr_t) args->buffers_ptr,
3917 sizeof(*exec_list) * args->buffer_count);
3918 if (ret != 0) {
3919 DRM_ERROR("copy %d exec entries failed %d\n",
3920 args->buffer_count, ret);
3921 drm_free_large(exec_list);
3922 drm_free_large(exec2_list);
3923 return -EFAULT;
3924 }
3925
3926 for (i = 0; i < args->buffer_count; i++) {
3927 exec2_list[i].handle = exec_list[i].handle;
3928 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3929 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3930 exec2_list[i].alignment = exec_list[i].alignment;
3931 exec2_list[i].offset = exec_list[i].offset;
3932 if (!IS_I965G(dev))
3933 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3934 else
3935 exec2_list[i].flags = 0;
3936 }
3937
3938 exec2.buffers_ptr = args->buffers_ptr;
3939 exec2.buffer_count = args->buffer_count;
3940 exec2.batch_start_offset = args->batch_start_offset;
3941 exec2.batch_len = args->batch_len;
3942 exec2.DR1 = args->DR1;
3943 exec2.DR4 = args->DR4;
3944 exec2.num_cliprects = args->num_cliprects;
3945 exec2.cliprects_ptr = args->cliprects_ptr;
852835f3 3946 exec2.flags = I915_EXEC_RENDER;
76446cac
JB		 3947
3948 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3949 if (!ret) {
3950 /* Copy the new buffer offsets back to the user's exec list. */
3951 for (i = 0; i < args->buffer_count; i++)
3952 exec_list[i].offset = exec2_list[i].offset;
3953 /* ... and back out to userspace */
3954 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3955 (uintptr_t) args->buffers_ptr,
3956 exec_list,
3957 sizeof(*exec_list) * args->buffer_count);
3958 if (ret) {
3959 ret = -EFAULT;
3960 DRM_ERROR("failed to copy %d exec entries "
3961 "back to user (%d)\n",
3962 args->buffer_count, ret);
3963 }
76446cac
JB		 3964 }
3965
3966 drm_free_large(exec_list);
3967 drm_free_large(exec2_list);
3968 return ret;
3969}
3970
3971int
3972i915_gem_execbuffer2(struct drm_device *dev, void *data,
3973 struct drm_file *file_priv)
3974{
3975 struct drm_i915_gem_execbuffer2 *args = data;
3976 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3977 int ret;
3978
3979#if WATCH_EXEC
3980 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3981 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3982#endif
3983
3984 if (args->buffer_count < 1) {
3985 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3986 return -EINVAL;
3987 }
3988
3989 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3990 if (exec2_list == NULL) {
3991 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3992 args->buffer_count);
3993 return -ENOMEM;
3994 }
3995 ret = copy_from_user(exec2_list,
3996 (struct drm_i915_relocation_entry __user *)
3997 (uintptr_t) args->buffers_ptr,
3998 sizeof(*exec2_list) * args->buffer_count);
3999 if (ret != 0) {
4000 DRM_ERROR("copy %d exec entries failed %d\n",
4001 args->buffer_count, ret);
4002 drm_free_large(exec2_list);
4003 return -EFAULT;
4004 }
4005
4006 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4007 if (!ret) {
4008 /* Copy the new buffer offsets back to the user's exec list. */
4009 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4010 (uintptr_t) args->buffers_ptr,
4011 exec2_list,
4012 sizeof(*exec2_list) * args->buffer_count);
4013 if (ret) {
4014 ret = -EFAULT;
4015 DRM_ERROR("failed to copy %d exec entries "
4016 "back to user (%d)\n",
4017 args->buffer_count, ret);
4018 }
4019 }
4020
4021 drm_free_large(exec2_list);
4022 return ret;
4023}
4024
673a394b
EA		 4025int
4026i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4027{
4028 struct drm_device *dev = obj->dev;
23010e43 4029 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4030 int ret;
4031
778c3544
DV		 4032 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4033
673a394b 4034 i915_verify_inactive(dev, __FILE__, __LINE__);
ac0c6b5a
CW		 4035
4036 if (obj_priv->gtt_space != NULL) {
4037 if (alignment == 0)
4038 alignment = i915_gem_get_gtt_alignment(obj);
4039 if (obj_priv->gtt_offset & (alignment - 1)) {
ae7d49d8
CW		 4040 WARN(obj_priv->pin_count,
4041 "bo is already pinned with incorrect alignment:"
4042 " offset=%x, req.alignment=%x\n",
4043 obj_priv->gtt_offset, alignment);
ac0c6b5a
CW		 4044 ret = i915_gem_object_unbind(obj);
4045 if (ret)
4046 return ret;
4047 }
4048 }
4049
673a394b
EA		 4050 if (obj_priv->gtt_space == NULL) {
4051 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4052 if (ret)
673a394b 4053 return ret;
22c344e9 4054 }
76446cac 4055
673a394b
EA		 4056 obj_priv->pin_count++;
4057
4058 /* If the object is not active and not pending a flush,
4059 * remove it from the inactive list
4060 */
4061 if (obj_priv->pin_count == 1) {
4062 atomic_inc(&dev->pin_count);
4063 atomic_add(obj->size, &dev->pin_memory);
4064 if (!obj_priv->active &&
bf1a1092 4065 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4066 list_del_init(&obj_priv->list);
4067 }
4068 i915_verify_inactive(dev, __FILE__, __LINE__);
4069
4070 return 0;
4071}
4072
4073void
4074i915_gem_object_unpin(struct drm_gem_object *obj)
4075{
4076 struct drm_device *dev = obj->dev;
4077 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4078 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4079
4080 i915_verify_inactive(dev, __FILE__, __LINE__);
4081 obj_priv->pin_count--;
4082 BUG_ON(obj_priv->pin_count < 0);
4083 BUG_ON(obj_priv->gtt_space == NULL);
4084
4085 /* If the object is no longer pinned, and is
4086 * neither active nor being flushed, then stick it on
4087 * the inactive list
4088 */
4089 if (obj_priv->pin_count == 0) {
4090 if (!obj_priv->active &&
21d509e3 4091 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4092 list_move_tail(&obj_priv->list,
4093 &dev_priv->mm.inactive_list);
4094 atomic_dec(&dev->pin_count);
4095 atomic_sub(obj->size, &dev->pin_memory);
4096 }
4097 i915_verify_inactive(dev, __FILE__, __LINE__);
4098}
4099
4100int
4101i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4102 struct drm_file *file_priv)
4103{
4104 struct drm_i915_gem_pin *args = data;
4105 struct drm_gem_object *obj;
4106 struct drm_i915_gem_object *obj_priv;
4107 int ret;
4108
4109 mutex_lock(&dev->struct_mutex);
4110
4111 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4112 if (obj == NULL) {
4113 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4114 args->handle);
4115 mutex_unlock(&dev->struct_mutex);
bf79cb91 4116 return -ENOENT;
673a394b 4117 }
23010e43 4118 obj_priv = to_intel_bo(obj);
673a394b 4119
bb6baf76
CW		 4120 if (obj_priv->madv != I915_MADV_WILLNEED) {
4121 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4122 drm_gem_object_unreference(obj);
4123 mutex_unlock(&dev->struct_mutex);
4124 return -EINVAL;
4125 }
4126
79e53945
JB		 4127 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4128 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4129 args->handle);
96dec61d 4130 drm_gem_object_unreference(obj);
673a394b 4131 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4132 return -EINVAL;
4133 }
4134
4135 obj_priv->user_pin_count++;
4136 obj_priv->pin_filp = file_priv;
4137 if (obj_priv->user_pin_count == 1) {
4138 ret = i915_gem_object_pin(obj, args->alignment);
4139 if (ret != 0) {
4140 drm_gem_object_unreference(obj);
4141 mutex_unlock(&dev->struct_mutex);
4142 return ret;
4143 }
673a394b
EA		 4144 }
4145
4146 /* XXX - flush the CPU caches for pinned objects
4147 * as the X server doesn't manage domains yet
4148 */
e47c68e9 4149 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4150 args->offset = obj_priv->gtt_offset;
4151 drm_gem_object_unreference(obj);
4152 mutex_unlock(&dev->struct_mutex);
4153
4154 return 0;
4155}
4156
4157int
4158i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4159 struct drm_file *file_priv)
4160{
4161 struct drm_i915_gem_pin *args = data;
4162 struct drm_gem_object *obj;
79e53945 4163 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4164
4165 mutex_lock(&dev->struct_mutex);
4166
4167 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4168 if (obj == NULL) {
4169 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4170 args->handle);
4171 mutex_unlock(&dev->struct_mutex);
bf79cb91 4172 return -ENOENT;
673a394b
EA		 4173 }
4174
23010e43 4175 obj_priv = to_intel_bo(obj);
79e53945
JB		 4176 if (obj_priv->pin_filp != file_priv) {
4177 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4178 args->handle);
4179 drm_gem_object_unreference(obj);
4180 mutex_unlock(&dev->struct_mutex);
4181 return -EINVAL;
4182 }
4183 obj_priv->user_pin_count--;
4184 if (obj_priv->user_pin_count == 0) {
4185 obj_priv->pin_filp = NULL;
4186 i915_gem_object_unpin(obj);
4187 }
673a394b
EA		 4188
4189 drm_gem_object_unreference(obj);
4190 mutex_unlock(&dev->struct_mutex);
4191 return 0;
4192}
4193
4194int
4195i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4196 struct drm_file *file_priv)
4197{
4198 struct drm_i915_gem_busy *args = data;
4199 struct drm_gem_object *obj;
4200 struct drm_i915_gem_object *obj_priv;
4201
673a394b
EA		 4202 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4203 if (obj == NULL) {
4204 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4205 args->handle);
bf79cb91 4206 return -ENOENT;
673a394b
EA		 4207 }
4208
b1ce786c 4209 mutex_lock(&dev->struct_mutex);
d1b851fc 4210
0be555b6
CW		 4211 /* Count all active objects as busy, even if they are currently not used
4212 * by the gpu. Users of this interface expect objects to eventually
4213 * become non-busy without any further actions, therefore emit any
4214 * necessary flushes here.
c4de0a5d 4215 */
0be555b6
CW		 4216 obj_priv = to_intel_bo(obj);
4217 args->busy = obj_priv->active;
4218 if (args->busy) {
4219 /* Unconditionally flush objects, even when the gpu still uses this
4220 * object. Userspace calling this function indicates that it wants to
4221 * use this buffer rather sooner than later, so issuing the required
4222 * flush earlier is beneficial.
4223 */
4224 if (obj->write_domain) {
4225 i915_gem_flush(dev, 0, obj->write_domain);
8a1a49f9 4226 (void)i915_add_request(dev, file_priv, obj_priv->ring);
0be555b6
CW		 4227 }
4228
4229 /* Update the active list for the hardware's current position.
4230 * Otherwise this only updates on a delayed timer or when irqs
4231 * are actually unmasked, and our working set ends up being
4232 * larger than required.
4233 */
4234 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4235
4236 args->busy = obj_priv->active;
4237 }
673a394b
EA		 4238
4239 drm_gem_object_unreference(obj);
4240 mutex_unlock(&dev->struct_mutex);
4241 return 0;
4242}
4243
4244int
4245i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4246 struct drm_file *file_priv)
4247{
4248 return i915_gem_ring_throttle(dev, file_priv);
4249}
4250
3ef94daa
CW		 4251int
4252i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4253 struct drm_file *file_priv)
4254{
4255 struct drm_i915_gem_madvise *args = data;
4256 struct drm_gem_object *obj;
4257 struct drm_i915_gem_object *obj_priv;
4258
4259 switch (args->madv) {
4260 case I915_MADV_DONTNEED:
4261 case I915_MADV_WILLNEED:
4262 break;
4263 default:
4264 return -EINVAL;
4265 }
4266
4267 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4268 if (obj == NULL) {
4269 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4270 args->handle);
bf79cb91 4271 return -ENOENT;
3ef94daa
CW		 4272 }
4273
4274 mutex_lock(&dev->struct_mutex);
23010e43 4275 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4276
4277 if (obj_priv->pin_count) {
4278 drm_gem_object_unreference(obj);
4279 mutex_unlock(&dev->struct_mutex);
4280
4281 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4282 return -EINVAL;
4283 }
4284
bb6baf76
CW		 4285 if (obj_priv->madv != __I915_MADV_PURGED)
4286 obj_priv->madv = args->madv;
3ef94daa 4287
2d7ef395
CW		 4288 /* if the object is no longer bound, discard its backing storage */
4289 if (i915_gem_object_is_purgeable(obj_priv) &&
4290 obj_priv->gtt_space == NULL)
4291 i915_gem_object_truncate(obj);
4292
bb6baf76
CW		 4293 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4294
3ef94daa
CW		 4295 drm_gem_object_unreference(obj);
4296 mutex_unlock(&dev->struct_mutex);
4297
4298 return 0;
4299}
4300
ac52bc56
DV		 4301struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4302 size_t size)
4303{
c397b908 4304 struct drm_i915_gem_object *obj;
ac52bc56 4305
c397b908
DV		 4306 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4307 if (obj == NULL)
4308 return NULL;
673a394b 4309
c397b908
DV		 4310 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4311 kfree(obj);
4312 return NULL;
4313 }
673a394b 4314
c397b908
DV		 4315 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4316 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4317
c397b908 4318 obj->agp_type = AGP_USER_MEMORY;
62b8b215 4319 obj->base.driver_private = NULL;
c397b908
DV		 4320 obj->fence_reg = I915_FENCE_REG_NONE;
4321 INIT_LIST_HEAD(&obj->list);
4322 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 4323 obj->madv = I915_MADV_WILLNEED;
de151cf6 4324
c397b908
DV		 4325 trace_i915_gem_object_create(&obj->base);
4326
4327 return &obj->base;
4328}
4329
4330int i915_gem_init_object(struct drm_gem_object *obj)
4331{
4332 BUG();
de151cf6 4333
673a394b
EA		 4334 return 0;
4335}
4336
be72615b 4337static void i915_gem_free_object_tail(struct drm_gem_object *obj)
673a394b 4338{
de151cf6 4339 struct drm_device *dev = obj->dev;
be72615b 4340 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4341 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
be72615b 4342 int ret;
673a394b 4343
be72615b
CW		 4344 ret = i915_gem_object_unbind(obj);
4345 if (ret == -ERESTARTSYS) {
4346 list_move(&obj_priv->list,
4347 &dev_priv->mm.deferred_free_list);
4348 return;
4349 }
673a394b 4350
7e616158
CW		 4351 if (obj_priv->mmap_offset)
4352 i915_gem_free_mmap_offset(obj);
de151cf6 4353
c397b908
DV		 4354 drm_gem_object_release(obj);
4355
9a298b2a 4356 kfree(obj_priv->page_cpu_valid);
280b713b 4357 kfree(obj_priv->bit_17);
c397b908 4358 kfree(obj_priv);
673a394b
EA		 4359}
4360
be72615b
CW		 4361void i915_gem_free_object(struct drm_gem_object *obj)
4362{
4363 struct drm_device *dev = obj->dev;
4364 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4365
4366 trace_i915_gem_object_destroy(obj);
4367
4368 while (obj_priv->pin_count > 0)
4369 i915_gem_object_unpin(obj);
4370
4371 if (obj_priv->phys_obj)
4372 i915_gem_detach_phys_object(dev, obj);
4373
4374 i915_gem_free_object_tail(obj);
4375}
4376
29105ccc
CW		 4377int
4378i915_gem_idle(struct drm_device *dev)
4379{
4380 drm_i915_private_t *dev_priv = dev->dev_private;
4381 int ret;
28dfe52a 4382
29105ccc 4383 mutex_lock(&dev->struct_mutex);
1c5d22f7 4384
8187a2b7 4385 if (dev_priv->mm.suspended ||
d1b851fc
ZN		 4386 (dev_priv->render_ring.gem_object == NULL) ||
4387 (HAS_BSD(dev) &&
4388 dev_priv->bsd_ring.gem_object == NULL)) {
29105ccc
CW		 4389 mutex_unlock(&dev->struct_mutex);
4390 return 0;
28dfe52a
EA		 4391 }
4392
29105ccc 4393 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4394 if (ret) {
4395 mutex_unlock(&dev->struct_mutex);
673a394b 4396 return ret;
6dbe2772 4397 }
673a394b 4398
29105ccc
CW		 4399 /* Under UMS, be paranoid and evict. */
4400 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
b47eb4a2 4401 ret = i915_gem_evict_inactive(dev);
29105ccc
CW		 4402 if (ret) {
4403 mutex_unlock(&dev->struct_mutex);
4404 return ret;
4405 }
4406 }
4407
4408 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4409 * We need to replace this with a semaphore, or something.
4410 * And not confound mm.suspended!
4411 */
4412 dev_priv->mm.suspended = 1;
bc0c7f14 4413 del_timer_sync(&dev_priv->hangcheck_timer);
29105ccc
CW		 4414
4415 i915_kernel_lost_context(dev);
6dbe2772 4416 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4417
6dbe2772
KP		 4418 mutex_unlock(&dev->struct_mutex);
4419
29105ccc
CW		 4420 /* Cancel the retire work handler, which should be idle now. */
4421 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4422
673a394b
EA		 4423 return 0;
4424}
4425
e552eb70
JB		 4426/*
4427 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4428 * over cache flushing.
4429 */
8187a2b7 4430static int
e552eb70
JB		 4431i915_gem_init_pipe_control(struct drm_device *dev)
4432{
4433 drm_i915_private_t *dev_priv = dev->dev_private;
4434 struct drm_gem_object *obj;
4435 struct drm_i915_gem_object *obj_priv;
4436 int ret;
4437
34dc4d44 4438 obj = i915_gem_alloc_object(dev, 4096);
e552eb70
JB		 4439 if (obj == NULL) {
4440 DRM_ERROR("Failed to allocate seqno page\n");
4441 ret = -ENOMEM;
4442 goto err;
4443 }
4444 obj_priv = to_intel_bo(obj);
4445 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4446
4447 ret = i915_gem_object_pin(obj, 4096);
4448 if (ret)
4449 goto err_unref;
4450
4451 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4452 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4453 if (dev_priv->seqno_page == NULL)
4454 goto err_unpin;
4455
4456 dev_priv->seqno_obj = obj;
4457 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4458
4459 return 0;
4460
4461err_unpin:
4462 i915_gem_object_unpin(obj);
4463err_unref:
4464 drm_gem_object_unreference(obj);
4465err:
4466 return ret;
4467}
4468
8187a2b7
ZN		 4469
4470static void
e552eb70
JB		 4471i915_gem_cleanup_pipe_control(struct drm_device *dev)
4472{
4473 drm_i915_private_t *dev_priv = dev->dev_private;
4474 struct drm_gem_object *obj;
4475 struct drm_i915_gem_object *obj_priv;
4476
4477 obj = dev_priv->seqno_obj;
4478 obj_priv = to_intel_bo(obj);
4479 kunmap(obj_priv->pages[0]);
4480 i915_gem_object_unpin(obj);
4481 drm_gem_object_unreference(obj);
4482 dev_priv->seqno_obj = NULL;
4483
4484 dev_priv->seqno_page = NULL;
673a394b
EA		 4485}
4486
8187a2b7
ZN		 4487int
4488i915_gem_init_ringbuffer(struct drm_device *dev)
4489{
4490 drm_i915_private_t *dev_priv = dev->dev_private;
4491 int ret;
68f95ba9 4492
8187a2b7 4493 dev_priv->render_ring = render_ring;
68f95ba9 4494
8187a2b7
ZN		 4495 if (!I915_NEED_GFX_HWS(dev)) {
4496 dev_priv->render_ring.status_page.page_addr
4497 = dev_priv->status_page_dmah->vaddr;
4498 memset(dev_priv->render_ring.status_page.page_addr,
4499 0, PAGE_SIZE);
4500 }
68f95ba9 4501
8187a2b7
ZN		 4502 if (HAS_PIPE_CONTROL(dev)) {
4503 ret = i915_gem_init_pipe_control(dev);
4504 if (ret)
4505 return ret;
4506 }
68f95ba9 4507
8187a2b7 4508 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
68f95ba9
CW		 4509 if (ret)
4510 goto cleanup_pipe_control;
4511
4512 if (HAS_BSD(dev)) {
d1b851fc
ZN		 4513 dev_priv->bsd_ring = bsd_ring;
4514 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
68f95ba9
CW		 4515 if (ret)
4516 goto cleanup_render_ring;
d1b851fc 4517 }
68f95ba9 4518
6f392d54
CW		 4519 dev_priv->next_seqno = 1;
4520
68f95ba9
CW		 4521 return 0;
4522
4523cleanup_render_ring:
4524 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4525cleanup_pipe_control:
4526 if (HAS_PIPE_CONTROL(dev))
4527 i915_gem_cleanup_pipe_control(dev);
8187a2b7
ZN		 4528 return ret;
4529}
4530
4531void
4532i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4533{
4534 drm_i915_private_t *dev_priv = dev->dev_private;
4535
4536 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 4537 if (HAS_BSD(dev))
4538 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
8187a2b7
ZN		 4539 if (HAS_PIPE_CONTROL(dev))
4540 i915_gem_cleanup_pipe_control(dev);
4541}
4542
673a394b
EA		 4543int
4544i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4545 struct drm_file *file_priv)
4546{
4547 drm_i915_private_t *dev_priv = dev->dev_private;
4548 int ret;
4549
79e53945
JB		 4550 if (drm_core_check_feature(dev, DRIVER_MODESET))
4551 return 0;
4552
ba1234d1 4553 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4554 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4555 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4556 }
4557
673a394b 4558 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4559 dev_priv->mm.suspended = 0;
4560
4561 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4562 if (ret != 0) {
4563 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4564 return ret;
d816f6ac 4565 }
9bb2d6f9 4566
5e118f41 4567 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 4568 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
d1b851fc 4569 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
5e118f41
CW		 4570 spin_unlock(&dev_priv->mm.active_list_lock);
4571
673a394b
EA		 4572 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4573 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
852835f3 4574 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
d1b851fc 4575 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
673a394b 4576 mutex_unlock(&dev->struct_mutex);
dbb19d30 4577
5f35308b
CW		 4578 ret = drm_irq_install(dev);
4579 if (ret)
4580 goto cleanup_ringbuffer;
dbb19d30 4581
673a394b 4582 return 0;
5f35308b
CW		 4583
4584cleanup_ringbuffer:
4585 mutex_lock(&dev->struct_mutex);
4586 i915_gem_cleanup_ringbuffer(dev);
4587 dev_priv->mm.suspended = 1;
4588 mutex_unlock(&dev->struct_mutex);
4589
4590 return ret;
673a394b
EA		 4591}
4592
4593int
4594i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4595 struct drm_file *file_priv)
4596{
79e53945
JB		 4597 if (drm_core_check_feature(dev, DRIVER_MODESET))
4598 return 0;
4599
dbb19d30 4600 drm_irq_uninstall(dev);
e6890f6f 4601 return i915_gem_idle(dev);
673a394b
EA		 4602}
4603
4604void
4605i915_gem_lastclose(struct drm_device *dev)
4606{
4607 int ret;
673a394b 4608
e806b495
EA		 4609 if (drm_core_check_feature(dev, DRIVER_MODESET))
4610 return;
4611
6dbe2772
KP		 4612 ret = i915_gem_idle(dev);
4613 if (ret)
4614 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4615}
4616
4617void
4618i915_gem_load(struct drm_device *dev)
4619{
b5aa8a0f 4620 int i;
673a394b
EA		 4621 drm_i915_private_t *dev_priv = dev->dev_private;
4622
5e118f41 4623 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b 4624 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4625 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b 4626 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
a09ba7fa 4627 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
be72615b 4628 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
852835f3
ZN		 4629 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4630 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
d1b851fc
ZN		 4631 if (HAS_BSD(dev)) {
4632 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4633 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4634 }
007cc8ac
DV		 4635 for (i = 0; i < 16; i++)
4636 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 4637 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4638 i915_gem_retire_work_handler);
31169714
CW		 4639 spin_lock(&shrink_list_lock);
4640 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4641 spin_unlock(&shrink_list_lock);
4642
94400120
DA		 4643 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4644 if (IS_GEN3(dev)) {
4645 u32 tmp = I915_READ(MI_ARB_STATE);
4646 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4647 /* arb state is a masked write, so set bit + bit in mask */
4648 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4649 I915_WRITE(MI_ARB_STATE, tmp);
4650 }
4651 }
4652
de151cf6 4653 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4654 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4655 dev_priv->fence_reg_start = 3;
de151cf6 4656
0f973f27 4657 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4658 dev_priv->num_fence_regs = 16;
4659 else
4660 dev_priv->num_fence_regs = 8;
4661
b5aa8a0f
GH		 4662 /* Initialize fence registers to zero */
4663 if (IS_I965G(dev)) {
4664 for (i = 0; i < 16; i++)
4665 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4666 } else {
4667 for (i = 0; i < 8; i++)
4668 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4669 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4670 for (i = 0; i < 8; i++)
4671 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4672 }
673a394b 4673 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4674 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4675}
71acb5eb
DA		 4676
4677/*
4678 * Create a physically contiguous memory object for this object
4679 * e.g. for cursor + overlay regs
4680 */
4681int i915_gem_init_phys_object(struct drm_device *dev,
6eeefaf3 4682 int id, int size, int align)
71acb5eb
DA		 4683{
4684 drm_i915_private_t *dev_priv = dev->dev_private;
4685 struct drm_i915_gem_phys_object *phys_obj;
4686 int ret;
4687
4688 if (dev_priv->mm.phys_objs[id - 1] || !size)
4689 return 0;
4690
9a298b2a 4691 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4692 if (!phys_obj)
4693 return -ENOMEM;
4694
4695 phys_obj->id = id;
4696
6eeefaf3 4697 phys_obj->handle = drm_pci_alloc(dev, size, align);
71acb5eb
DA		 4698 if (!phys_obj->handle) {
4699 ret = -ENOMEM;
4700 goto kfree_obj;
4701 }
4702#ifdef CONFIG_X86
4703 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4704#endif
4705
4706 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4707
4708 return 0;
4709kfree_obj:
9a298b2a 4710 kfree(phys_obj);
71acb5eb
DA		 4711 return ret;
4712}
4713
4714void i915_gem_free_phys_object(struct drm_device *dev, int id)
4715{
4716 drm_i915_private_t *dev_priv = dev->dev_private;
4717 struct drm_i915_gem_phys_object *phys_obj;
4718
4719 if (!dev_priv->mm.phys_objs[id - 1])
4720 return;
4721
4722 phys_obj = dev_priv->mm.phys_objs[id - 1];
4723 if (phys_obj->cur_obj) {
4724 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4725 }
4726
4727#ifdef CONFIG_X86
4728 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4729#endif
4730 drm_pci_free(dev, phys_obj->handle);
4731 kfree(phys_obj);
4732 dev_priv->mm.phys_objs[id - 1] = NULL;
4733}
4734
4735void i915_gem_free_all_phys_object(struct drm_device *dev)
4736{
4737 int i;
4738
260883c8 4739 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4740 i915_gem_free_phys_object(dev, i);
4741}
4742
4743void i915_gem_detach_phys_object(struct drm_device *dev,
4744 struct drm_gem_object *obj)
4745{
4746 struct drm_i915_gem_object *obj_priv;
4747 int i;
4748 int ret;
4749 int page_count;
4750
23010e43 4751 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4752 if (!obj_priv->phys_obj)
4753 return;
4754
4bdadb97 4755 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4756 if (ret)
4757 goto out;
4758
4759 page_count = obj->size / PAGE_SIZE;
4760
4761 for (i = 0; i < page_count; i++) {
856fa198 4762 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4763 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4764
4765 memcpy(dst, src, PAGE_SIZE);
4766 kunmap_atomic(dst, KM_USER0);
4767 }
856fa198 4768 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4769 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4770
4771 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4772out:
4773 obj_priv->phys_obj->cur_obj = NULL;
4774 obj_priv->phys_obj = NULL;
4775}
4776
4777int
4778i915_gem_attach_phys_object(struct drm_device *dev,
6eeefaf3
CW		 4779 struct drm_gem_object *obj,
4780 int id,
4781 int align)
71acb5eb
DA		 4782{
4783 drm_i915_private_t *dev_priv = dev->dev_private;
4784 struct drm_i915_gem_object *obj_priv;
4785 int ret = 0;
4786 int page_count;
4787 int i;
4788
4789 if (id > I915_MAX_PHYS_OBJECT)
4790 return -EINVAL;
4791
23010e43 4792 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4793
4794 if (obj_priv->phys_obj) {
4795 if (obj_priv->phys_obj->id == id)
4796 return 0;
4797 i915_gem_detach_phys_object(dev, obj);
4798 }
4799
71acb5eb
DA		 4800 /* create a new object */
4801 if (!dev_priv->mm.phys_objs[id - 1]) {
4802 ret = i915_gem_init_phys_object(dev, id,
6eeefaf3 4803 obj->size, align);
71acb5eb 4804 if (ret) {
aeb565df 4805 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4806 goto out;
4807 }
4808 }
4809
4810 /* bind to the object */
4811 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4812 obj_priv->phys_obj->cur_obj = obj;
4813
4bdadb97 4814 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4815 if (ret) {
4816 DRM_ERROR("failed to get page list\n");
4817 goto out;
4818 }
4819
4820 page_count = obj->size / PAGE_SIZE;
4821
4822 for (i = 0; i < page_count; i++) {
856fa198 4823 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4824 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4825
4826 memcpy(dst, src, PAGE_SIZE);
4827 kunmap_atomic(src, KM_USER0);
4828 }
4829
d78b47b9
CW		 4830 i915_gem_object_put_pages(obj);
4831
71acb5eb
DA		 4832 return 0;
4833out:
4834 return ret;
4835}
4836
4837static int
4838i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4839 struct drm_i915_gem_pwrite *args,
4840 struct drm_file *file_priv)
4841{
23010e43 4842 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4843 void *obj_addr;
4844 int ret;
4845 char __user *user_data;
4846
4847 user_data = (char __user *) (uintptr_t) args->data_ptr;
4848 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4849
44d98a61 4850 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4851 ret = copy_from_user(obj_addr, user_data, args->size);
4852 if (ret)
4853 return -EFAULT;
4854
4855 drm_agp_chipset_flush(dev);
4856 return 0;
4857}
b962442e
EA		 4858
4859void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4860{
4861 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4862
4863 /* Clean up our request list when the client is going away, so that
4864 * later retire_requests won't dereference our soon-to-be-gone
4865 * file_priv.
4866 */
4867 mutex_lock(&dev->struct_mutex);
4868 while (!list_empty(&i915_file_priv->mm.request_list))
4869 list_del_init(i915_file_priv->mm.request_list.next);
4870 mutex_unlock(&dev->struct_mutex);
4871}
31169714 4872
1637ef41
CW		 4873static int
4874i915_gpu_is_active(struct drm_device *dev)
4875{
4876 drm_i915_private_t *dev_priv = dev->dev_private;
4877 int lists_empty;
4878
4879 spin_lock(&dev_priv->mm.active_list_lock);
4880 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
852835f3 4881 list_empty(&dev_priv->render_ring.active_list);
d1b851fc
ZN		 4882 if (HAS_BSD(dev))
4883 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
1637ef41
CW		 4884 spin_unlock(&dev_priv->mm.active_list_lock);
4885
4886 return !lists_empty;
4887}
4888
31169714 4889static int
7f8275d0 4890i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
31169714
CW		 4891{
4892 drm_i915_private_t *dev_priv, *next_dev;
4893 struct drm_i915_gem_object *obj_priv, *next_obj;
4894 int cnt = 0;
4895 int would_deadlock = 1;
4896
4897 /* "fast-path" to count number of available objects */
4898 if (nr_to_scan == 0) {
4899 spin_lock(&shrink_list_lock);
4900 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4901 struct drm_device *dev = dev_priv->dev;
4902
4903 if (mutex_trylock(&dev->struct_mutex)) {
4904 list_for_each_entry(obj_priv,
4905 &dev_priv->mm.inactive_list,
4906 list)
4907 cnt++;
4908 mutex_unlock(&dev->struct_mutex);
4909 }
4910 }
4911 spin_unlock(&shrink_list_lock);
4912
4913 return (cnt / 100) * sysctl_vfs_cache_pressure;
4914 }
4915
4916 spin_lock(&shrink_list_lock);
4917
1637ef41 4918rescan:
31169714
CW		 4919 /* first scan for clean buffers */
4920 list_for_each_entry_safe(dev_priv, next_dev,
4921 &shrink_list, mm.shrink_list) {
4922 struct drm_device *dev = dev_priv->dev;
4923
4924 if (! mutex_trylock(&dev->struct_mutex))
4925 continue;
4926
4927 spin_unlock(&shrink_list_lock);
b09a1fec 4928 i915_gem_retire_requests(dev);
31169714
CW		 4929
4930 list_for_each_entry_safe(obj_priv, next_obj,
4931 &dev_priv->mm.inactive_list,
4932 list) {
4933 if (i915_gem_object_is_purgeable(obj_priv)) {
a8089e84 4934 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 4935 if (--nr_to_scan <= 0)
4936 break;
4937 }
4938 }
4939
4940 spin_lock(&shrink_list_lock);
4941 mutex_unlock(&dev->struct_mutex);
4942
963b4836
CW		 4943 would_deadlock = 0;
4944
31169714
CW		 4945 if (nr_to_scan <= 0)
4946 break;
4947 }
4948
4949 /* second pass, evict/count anything still on the inactive list */
4950 list_for_each_entry_safe(dev_priv, next_dev,
4951 &shrink_list, mm.shrink_list) {
4952 struct drm_device *dev = dev_priv->dev;
4953
4954 if (! mutex_trylock(&dev->struct_mutex))
4955 continue;
4956
4957 spin_unlock(&shrink_list_lock);
4958
4959 list_for_each_entry_safe(obj_priv, next_obj,
4960 &dev_priv->mm.inactive_list,
4961 list) {
4962 if (nr_to_scan > 0) {
a8089e84 4963 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 4964 nr_to_scan--;
4965 } else
4966 cnt++;
4967 }
4968
4969 spin_lock(&shrink_list_lock);
4970 mutex_unlock(&dev->struct_mutex);
4971
4972 would_deadlock = 0;
4973 }
4974
1637ef41
CW		 4975 if (nr_to_scan) {
4976 int active = 0;
4977
4978 /*
4979 * We are desperate for pages, so as a last resort, wait
4980 * for the GPU to finish and discard whatever we can.
4981 * This has a dramatic impact to reduce the number of
4982 * OOM-killer events whilst running the GPU aggressively.
4983 */
4984 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4985 struct drm_device *dev = dev_priv->dev;
4986
4987 if (!mutex_trylock(&dev->struct_mutex))
4988 continue;
4989
4990 spin_unlock(&shrink_list_lock);
4991
4992 if (i915_gpu_is_active(dev)) {
4993 i915_gpu_idle(dev);
4994 active++;
4995 }
4996
4997 spin_lock(&shrink_list_lock);
4998 mutex_unlock(&dev->struct_mutex);
4999 }
5000
5001 if (active)
5002 goto rescan;
5003 }
5004
31169714
CW		 5005 spin_unlock(&shrink_list_lock);
5006
5007 if (would_deadlock)
5008 return -1;
5009 else if (cnt > 0)
5010 return (cnt / 100) * sysctl_vfs_cache_pressure;
5011 else
5012 return 0;
5013}
5014
5015static struct shrinker shrinker = {
5016 .shrink = i915_gem_shrink,
5017 .seeks = DEFAULT_SEEKS,
5018};
5019
5020__init void
5021i915_gem_shrinker_init(void)
5022{
5023 register_shrinker(&shrinker);
5024}
5025
5026__exit void
5027i915_gem_shrinker_exit(void)
5028{
5029 unregister_shrinker(&shrinker);
5030}
Clone of davem's net-next-2.6 tree