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drm/i915: framebuffer compression for GM45+
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
652c393a 32#include "intel_drv.h"
673a394b 33#include <linux/swap.h>
79e53945 34#include <linux/pci.h>
673a394b 35
28dfe52a
EA		 36#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
37
e47c68e9
EA		 38static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 41static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 int write);
43static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
44 uint64_t offset,
45 uint64_t size);
46static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 47static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 48static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment);
de151cf6 50static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69
CW		 51static int i915_gem_evict_something(struct drm_device *dev, int min_size);
52static int i915_gem_evict_from_list(struct drm_device *dev,
53 struct list_head *head);
71acb5eb
DA		 54static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
673a394b 57
31169714
CW		 58static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
79e53945
JB		 61int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
673a394b
EA		 63{
64 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 65
79e53945
JB		 66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 69 return -EINVAL;
70 }
71
79e53945
JB		 72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
673a394b 74
79e53945
JB		 75 dev->gtt_total = (uint32_t) (end - start);
76
77 return 0;
78}
673a394b 79
79e53945
JB		 80int
81i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
83{
84 struct drm_i915_gem_init *args = data;
85 int ret;
86
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 89 mutex_unlock(&dev->struct_mutex);
90
79e53945 91 return ret;
673a394b
EA		 92}
93
5a125c3c
EA		 94int
95i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
97{
5a125c3c 98 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 99
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
102
103 args->aper_size = dev->gtt_total;
2678d9d6
KP		 104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
5a125c3c
EA		 106
107 return 0;
108}
109
673a394b
EA		 110
111/**
112 * Creates a new mm object and returns a handle to it.
113 */
114int
115i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
117{
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
a1a2d1d3
PP		 120 int ret;
121 u32 handle;
673a394b
EA		 122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
134
135 if (ret)
136 return ret;
137
138 args->handle = handle;
139
140 return 0;
141}
142
eb01459f
EA		 143static inline int
144fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
146 char __user *data,
147 int length)
148{
149 char __iomem *vaddr;
2bc43b5c 150 int unwritten;
eb01459f
EA		 151
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 if (vaddr == NULL)
154 return -ENOMEM;
2bc43b5c 155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 156 kunmap_atomic(vaddr, KM_USER0);
157
2bc43b5c
FM		 158 if (unwritten)
159 return -EFAULT;
160
161 return 0;
eb01459f
EA		 162}
163
280b713b
EA		 164static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165{
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
171}
172
40123c1f
EA		 173static inline int
174slow_shmem_copy(struct page *dst_page,
175 int dst_offset,
176 struct page *src_page,
177 int src_offset,
178 int length)
179{
180 char *dst_vaddr, *src_vaddr;
181
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
184 return -ENOMEM;
185
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
189 return -ENOMEM;
190 }
191
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
196
197 return 0;
198}
199
280b713b
EA		 200static inline int
201slow_shmem_bit17_copy(struct page *gpu_page,
202 int gpu_offset,
203 struct page *cpu_page,
204 int cpu_offset,
205 int length,
206 int is_read)
207{
208 char *gpu_vaddr, *cpu_vaddr;
209
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 if (is_read)
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
215 else
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
218 }
219
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
222 return -ENOMEM;
223
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
227 return -ENOMEM;
228 }
229
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 */
233 while (length > 0) {
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238 if (is_read) {
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
241 this_length);
242 } else {
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
245 this_length);
246 }
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
250 }
251
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
254
255 return 0;
256}
257
eb01459f
EA		 258/**
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 */
263static int
264i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
267{
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
269 ssize_t remain;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
273 int ret;
274
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 remain = args->size;
277
278 mutex_lock(&dev->struct_mutex);
279
280 ret = i915_gem_object_get_pages(obj);
281 if (ret != 0)
282 goto fail_unlock;
283
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285 args->size);
286 if (ret != 0)
287 goto fail_put_pages;
288
289 obj_priv = obj->driver_private;
290 offset = args->offset;
291
292 while (remain > 0) {
293 /* Operation in this page
294 *
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
298 */
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
304
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
308 if (ret)
309 goto fail_put_pages;
310
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
314 }
315
316fail_put_pages:
317 i915_gem_object_put_pages(obj);
318fail_unlock:
319 mutex_unlock(&dev->struct_mutex);
320
321 return ret;
322}
323
07f73f69
CW		 324static inline gfp_t
325i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
326{
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
328}
329
330static inline void
331i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
332{
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
334}
335
336static int
337i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
338{
339 int ret;
340
341 ret = i915_gem_object_get_pages(obj);
342
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
345 */
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
348 gfp_t gfp;
349
350 ret = i915_gem_evict_something(dev, obj->size);
351 if (ret)
352 return ret;
353
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
358 }
359
360 return ret;
361}
362
eb01459f
EA		 363/**
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
368 */
369static int
370i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
373{
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
377 ssize_t remain;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
382 int page_length;
383 int ret;
384 uint64_t data_ptr = args->data_ptr;
280b713b 385 int do_bit17_swizzling;
eb01459f
EA		 386
387 remain = args->size;
388
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
392 */
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
396
8e7d2b2c 397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 398 if (user_pages == NULL)
399 return -ENOMEM;
400
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 403 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
406 ret = -EFAULT;
407 goto fail_put_user_pages;
408 }
409
280b713b
EA		 410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
411
eb01459f
EA		 412 mutex_lock(&dev->struct_mutex);
413
07f73f69
CW		 414 ret = i915_gem_object_get_pages_or_evict(obj);
415 if (ret)
eb01459f
EA		 416 goto fail_unlock;
417
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
419 args->size);
420 if (ret != 0)
421 goto fail_put_pages;
422
423 obj_priv = obj->driver_private;
424 offset = args->offset;
425
426 while (remain > 0) {
427 /* Operation in this page
428 *
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
434 */
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
439
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
445
280b713b
EA		 446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
448 shmem_page_offset,
449 user_pages[data_page_index],
450 data_page_offset,
451 page_length,
452 1);
453 } else {
454 ret = slow_shmem_copy(user_pages[data_page_index],
455 data_page_offset,
456 obj_priv->pages[shmem_page_index],
457 shmem_page_offset,
458 page_length);
459 }
eb01459f
EA		 460 if (ret)
461 goto fail_put_pages;
462
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
466 }
467
468fail_put_pages:
469 i915_gem_object_put_pages(obj);
470fail_unlock:
471 mutex_unlock(&dev->struct_mutex);
472fail_put_user_pages:
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
476 }
8e7d2b2c 477 drm_free_large(user_pages);
eb01459f
EA		 478
479 return ret;
480}
481
673a394b
EA		 482/**
483 * Reads data from the object referenced by handle.
484 *
485 * On error, the contents of *data are undefined.
486 */
487int
488i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
490{
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 494 int ret;
495
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
497 if (obj == NULL)
498 return -EBADF;
499 obj_priv = obj->driver_private;
500
501 /* Bounds check source.
502 *
503 * XXX: This could use review for overflow issues...
504 */
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
508 return -EINVAL;
509 }
510
280b713b 511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 513 } else {
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
515 if (ret != 0)
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
517 file_priv);
518 }
673a394b
EA		 519
520 drm_gem_object_unreference(obj);
673a394b 521
eb01459f 522 return ret;
673a394b
EA		 523}
524
0839ccb8
KP		 525/* This is the fast write path which cannot handle
526 * page faults in the source data
9b7530cc 527 */
0839ccb8
KP		 528
529static inline int
530fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
533 int length)
9b7530cc 534{
9b7530cc 535 char *vaddr_atomic;
0839ccb8 536 unsigned long unwritten;
9b7530cc 537
0839ccb8
KP		 538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
540 user_data, length);
541 io_mapping_unmap_atomic(vaddr_atomic);
542 if (unwritten)
543 return -EFAULT;
544 return 0;
545}
546
547/* Here's the write path which can sleep for
548 * page faults
549 */
550
551static inline int
3de09aa3
EA		 552slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
555 int length)
0839ccb8 556{
3de09aa3 557 char *src_vaddr, *dst_vaddr;
0839ccb8
KP		 558 unsigned long unwritten;
559
3de09aa3
EA		 560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
564 length);
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
0839ccb8
KP		 567 if (unwritten)
568 return -EFAULT;
9b7530cc 569 return 0;
9b7530cc
LT		 570}
571
40123c1f
EA		 572static inline int
573fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
575 char __user *data,
576 int length)
577{
578 char __iomem *vaddr;
d0088775 579 unsigned long unwritten;
40123c1f
EA		 580
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
582 if (vaddr == NULL)
583 return -ENOMEM;
d0088775 584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 585 kunmap_atomic(vaddr, KM_USER0);
586
d0088775
DA		 587 if (unwritten)
588 return -EFAULT;
40123c1f
EA		 589 return 0;
590}
591
3de09aa3
EA		 592/**
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
595 */
673a394b 596static int
3de09aa3
EA		 597i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
673a394b
EA		 600{
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
0839ccb8 602 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 603 ssize_t remain;
0839ccb8 604 loff_t offset, page_base;
673a394b 605 char __user *user_data;
0839ccb8
KP		 606 int page_offset, page_length;
607 int ret;
673a394b
EA		 608
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
610 remain = args->size;
611 if (!access_ok(VERIFY_READ, user_data, remain))
612 return -EFAULT;
613
614
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
617 if (ret) {
618 mutex_unlock(&dev->struct_mutex);
619 return ret;
620 }
2ef7eeaa 621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 622 if (ret)
623 goto fail;
624
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 627
628 while (remain > 0) {
629 /* Operation in this page
630 *
0839ccb8
KP		 631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
673a394b 634 */
0839ccb8
KP		 635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
640
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
643
644 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
0839ccb8 647 */
3de09aa3
EA		 648 if (ret)
649 goto fail;
673a394b 650
0839ccb8
KP		 651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
673a394b 654 }
673a394b
EA		 655
656fail:
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
659
660 return ret;
661}
662
3de09aa3
EA		 663/**
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
666 *
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
669 */
3043c60c 670static int
3de09aa3
EA		 671i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
673a394b 674{
3de09aa3
EA		 675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
677 ssize_t remain;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 684 int ret;
3de09aa3
EA		 685 uint64_t data_ptr = args->data_ptr;
686
687 remain = args->size;
688
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
692 */
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
696
8e7d2b2c 697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 698 if (user_pages == NULL)
699 return -ENOMEM;
700
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
706 ret = -EFAULT;
707 goto out_unpin_pages;
708 }
673a394b
EA		 709
710 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 711 ret = i915_gem_object_pin(obj, 0);
712 if (ret)
713 goto out_unlock;
714
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
716 if (ret)
717 goto out_unpin_object;
718
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
721
722 while (remain > 0) {
723 /* Operation in this page
724 *
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
730 */
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
735
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
741
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
745 data_page_offset,
746 page_length);
747
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
751 */
752 if (ret)
753 goto out_unpin_object;
754
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
758 }
759
760out_unpin_object:
761 i915_gem_object_unpin(obj);
762out_unlock:
763 mutex_unlock(&dev->struct_mutex);
764out_unpin_pages:
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
8e7d2b2c 767 drm_free_large(user_pages);
3de09aa3
EA		 768
769 return ret;
770}
771
40123c1f
EA		 772/**
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
775 */
3043c60c 776static int
40123c1f
EA		 777i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
673a394b 780{
40123c1f
EA		 781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
782 ssize_t remain;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
673a394b 786 int ret;
40123c1f
EA		 787
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
789 remain = args->size;
673a394b
EA		 790
791 mutex_lock(&dev->struct_mutex);
792
40123c1f
EA		 793 ret = i915_gem_object_get_pages(obj);
794 if (ret != 0)
795 goto fail_unlock;
673a394b 796
e47c68e9 797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 798 if (ret != 0)
799 goto fail_put_pages;
800
801 obj_priv = obj->driver_private;
802 offset = args->offset;
803 obj_priv->dirty = 1;
804
805 while (remain > 0) {
806 /* Operation in this page
807 *
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
811 */
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
817
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
821 if (ret)
822 goto fail_put_pages;
823
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
827 }
828
829fail_put_pages:
830 i915_gem_object_put_pages(obj);
831fail_unlock:
832 mutex_unlock(&dev->struct_mutex);
833
834 return ret;
835}
836
837/**
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
840 *
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
843 */
844static int
845i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
848{
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
852 ssize_t remain;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
857 int page_length;
858 int ret;
859 uint64_t data_ptr = args->data_ptr;
280b713b 860 int do_bit17_swizzling;
40123c1f
EA		 861
862 remain = args->size;
863
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
867 */
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
871
8e7d2b2c 872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 873 if (user_pages == NULL)
874 return -ENOMEM;
875
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
881 ret = -EFAULT;
882 goto fail_put_user_pages;
673a394b
EA		 883 }
884
280b713b
EA		 885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
886
40123c1f
EA		 887 mutex_lock(&dev->struct_mutex);
888
07f73f69
CW		 889 ret = i915_gem_object_get_pages_or_evict(obj);
890 if (ret)
40123c1f
EA		 891 goto fail_unlock;
892
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
894 if (ret != 0)
895 goto fail_put_pages;
896
897 obj_priv = obj->driver_private;
673a394b 898 offset = args->offset;
40123c1f 899 obj_priv->dirty = 1;
673a394b 900
40123c1f
EA		 901 while (remain > 0) {
902 /* Operation in this page
903 *
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
909 */
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
914
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
920
280b713b
EA		 921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
923 shmem_page_offset,
924 user_pages[data_page_index],
925 data_page_offset,
926 page_length,
927 0);
928 } else {
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
930 shmem_page_offset,
931 user_pages[data_page_index],
932 data_page_offset,
933 page_length);
934 }
40123c1f
EA		 935 if (ret)
936 goto fail_put_pages;
937
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
673a394b
EA		 941 }
942
40123c1f
EA		 943fail_put_pages:
944 i915_gem_object_put_pages(obj);
945fail_unlock:
673a394b 946 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 947fail_put_user_pages:
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
8e7d2b2c 950 drm_free_large(user_pages);
673a394b 951
40123c1f 952 return ret;
673a394b
EA		 953}
954
955/**
956 * Writes data to the object referenced by handle.
957 *
958 * On error, the contents of the buffer that were to be modified are undefined.
959 */
960int
961i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
963{
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
967 int ret = 0;
968
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
970 if (obj == NULL)
971 return -EBADF;
972 obj_priv = obj->driver_private;
973
974 /* Bounds check destination.
975 *
976 * XXX: This could use review for overflow issues...
977 */
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
981 return -EINVAL;
982 }
983
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
989 */
71acb5eb
DA		 990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
3de09aa3
EA		 993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
997 file_priv);
998 }
280b713b
EA		 999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 1001 } else {
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1005 file_priv);
1006 }
1007 }
673a394b
EA		 1008
1009#if WATCH_PWRITE
1010 if (ret)
1011 DRM_INFO("pwrite failed %d\n", ret);
1012#endif
1013
1014 drm_gem_object_unreference(obj);
1015
1016 return ret;
1017}
1018
1019/**
2ef7eeaa
EA		 1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1022 */
1023int
1024i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1026{
a09ba7fa 1027 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
652c393a 1030 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
673a394b
EA		 1033 int ret;
1034
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1036 return -ENODEV;
1037
2ef7eeaa 1038 /* Only handle setting domains to types used by the CPU. */
21d509e3 1039 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1040 return -EINVAL;
1041
21d509e3 1042 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1043 return -EINVAL;
1044
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1047 */
1048 if (write_domain != 0 && read_domains != write_domain)
1049 return -EINVAL;
1050
673a394b
EA		 1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1052 if (obj == NULL)
1053 return -EBADF;
652c393a 1054 obj_priv = obj->driver_private;
673a394b
EA		 1055
1056 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1057
1058 intel_mark_busy(dev, obj);
1059
673a394b 1060#if WATCH_BUF
cfd43c02 1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1062 obj, obj->size, read_domains, write_domain);
673a394b 1063#endif
2ef7eeaa
EA		 1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1066
a09ba7fa
EA		 1067 /* Update the LRU on the fence for the CPU access that's
1068 * about to occur.
1069 */
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1073 }
1074
02354392
EA		 1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1078 */
1079 if (ret == -EINVAL)
1080 ret = 0;
2ef7eeaa 1081 } else {
e47c68e9 1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1083 }
1084
673a394b
EA		 1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1087 return ret;
1088}
1089
1090/**
1091 * Called when user space has done writes to this buffer
1092 */
1093int
1094i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1096{
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1100 int ret = 0;
1101
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1103 return -ENODEV;
1104
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1107 if (obj == NULL) {
1108 mutex_unlock(&dev->struct_mutex);
1109 return -EBADF;
1110 }
1111
1112#if WATCH_BUF
cfd43c02 1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1114 __func__, args->handle, obj, obj->size);
1115#endif
1116 obj_priv = obj->driver_private;
1117
1118 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1121
673a394b
EA		 1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1124 return ret;
1125}
1126
1127/**
1128 * Maps the contents of an object, returning the address it is mapped
1129 * into.
1130 *
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1133 */
1134int
1135i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1137{
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1140 loff_t offset;
1141 unsigned long addr;
1142
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1144 return -ENODEV;
1145
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1147 if (obj == NULL)
1148 return -EBADF;
1149
1150 offset = args->offset;
1151
1152 down_write(&current->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1155 args->offset);
1156 up_write(&current->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1161 return addr;
1162
1163 args->addr_ptr = (uint64_t) addr;
1164
1165 return 0;
1166}
1167
de151cf6
JB		 1168/**
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1171 * vmf: fault info
1172 *
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1178 *
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1182 * left.
1183 */
1184int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1185{
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1191 unsigned long pfn;
1192 int ret = 0;
0f973f27 1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1194
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1197 PAGE_SHIFT;
1198
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
e67b8ce1 1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1203 if (ret) {
1204 mutex_unlock(&dev->struct_mutex);
1205 return VM_FAULT_SIGBUS;
1206 }
4960aaca 1207 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1208
1209 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1210 if (ret) {
1211 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_SIGBUS;
1213 }
de151cf6
JB		 1214 }
1215
1216 /* Need a new fence register? */
a09ba7fa 1217 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1218 ret = i915_gem_object_get_fence_reg(obj);
7d8d58b2
CW		 1219 if (ret) {
1220 mutex_unlock(&dev->struct_mutex);
d9ddcb96 1221 return VM_FAULT_SIGBUS;
7d8d58b2 1222 }
d9ddcb96 1223 }
de151cf6
JB		 1224
1225 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1226 page_offset;
1227
1228 /* Finally, remap it using the new GTT offset */
1229 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1230
1231 mutex_unlock(&dev->struct_mutex);
1232
1233 switch (ret) {
1234 case -ENOMEM:
1235 case -EAGAIN:
1236 return VM_FAULT_OOM;
1237 case -EFAULT:
959b887c 1238 case -EINVAL:
de151cf6
JB		 1239 return VM_FAULT_SIGBUS;
1240 default:
1241 return VM_FAULT_NOPAGE;
1242 }
1243}
1244
1245/**
1246 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1247 * @obj: obj in question
1248 *
1249 * GEM memory mapping works by handing back to userspace a fake mmap offset
1250 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1251 * up the object based on the offset and sets up the various memory mapping
1252 * structures.
1253 *
1254 * This routine allocates and attaches a fake offset for @obj.
1255 */
1256static int
1257i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1258{
1259 struct drm_device *dev = obj->dev;
1260 struct drm_gem_mm *mm = dev->mm_private;
1261 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1262 struct drm_map_list *list;
f77d390c 1263 struct drm_local_map *map;
de151cf6
JB		 1264 int ret = 0;
1265
1266 /* Set the object up for mmap'ing */
1267 list = &obj->map_list;
9a298b2a 1268 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1269 if (!list->map)
1270 return -ENOMEM;
1271
1272 map = list->map;
1273 map->type = _DRM_GEM;
1274 map->size = obj->size;
1275 map->handle = obj;
1276
1277 /* Get a DRM GEM mmap offset allocated... */
1278 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1279 obj->size / PAGE_SIZE, 0, 0);
1280 if (!list->file_offset_node) {
1281 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1282 ret = -ENOMEM;
1283 goto out_free_list;
1284 }
1285
1286 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1287 obj->size / PAGE_SIZE, 0);
1288 if (!list->file_offset_node) {
1289 ret = -ENOMEM;
1290 goto out_free_list;
1291 }
1292
1293 list->hash.key = list->file_offset_node->start;
1294 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1295 DRM_ERROR("failed to add to map hash\n");
1296 goto out_free_mm;
1297 }
1298
1299 /* By now we should be all set, any drm_mmap request on the offset
1300 * below will get to our mmap & fault handler */
1301 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1302
1303 return 0;
1304
1305out_free_mm:
1306 drm_mm_put_block(list->file_offset_node);
1307out_free_list:
9a298b2a 1308 kfree(list->map);
de151cf6
JB		 1309
1310 return ret;
1311}
1312
901782b2
CW		 1313/**
1314 * i915_gem_release_mmap - remove physical page mappings
1315 * @obj: obj in question
1316 *
1317 * Preserve the reservation of the mmaping with the DRM core code, but
1318 * relinquish ownership of the pages back to the system.
1319 *
1320 * It is vital that we remove the page mapping if we have mapped a tiled
1321 * object through the GTT and then lose the fence register due to
1322 * resource pressure. Similarly if the object has been moved out of the
1323 * aperture, than pages mapped into userspace must be revoked. Removing the
1324 * mapping will then trigger a page fault on the next user access, allowing
1325 * fixup by i915_gem_fault().
1326 */
d05ca301 1327void
901782b2
CW		 1328i915_gem_release_mmap(struct drm_gem_object *obj)
1329{
1330 struct drm_device *dev = obj->dev;
1331 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1332
1333 if (dev->dev_mapping)
1334 unmap_mapping_range(dev->dev_mapping,
1335 obj_priv->mmap_offset, obj->size, 1);
1336}
1337
ab00b3e5
JB		 1338static void
1339i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1340{
1341 struct drm_device *dev = obj->dev;
1342 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1343 struct drm_gem_mm *mm = dev->mm_private;
1344 struct drm_map_list *list;
1345
1346 list = &obj->map_list;
1347 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1348
1349 if (list->file_offset_node) {
1350 drm_mm_put_block(list->file_offset_node);
1351 list->file_offset_node = NULL;
1352 }
1353
1354 if (list->map) {
9a298b2a 1355 kfree(list->map);
ab00b3e5
JB		 1356 list->map = NULL;
1357 }
1358
1359 obj_priv->mmap_offset = 0;
1360}
1361
de151cf6
JB		 1362/**
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1365 *
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping if needed.
1368 */
1369static uint32_t
1370i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1371{
1372 struct drm_device *dev = obj->dev;
1373 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1374 int start, i;
1375
1376 /*
1377 * Minimum alignment is 4k (GTT page size), but might be greater
1378 * if a fence register is needed for the object.
1379 */
1380 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1381 return 4096;
1382
1383 /*
1384 * Previous chips need to be aligned to the size of the smallest
1385 * fence register that can contain the object.
1386 */
1387 if (IS_I9XX(dev))
1388 start = 1024*1024;
1389 else
1390 start = 512*1024;
1391
1392 for (i = start; i < obj->size; i <<= 1)
1393 ;
1394
1395 return i;
1396}
1397
1398/**
1399 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1400 * @dev: DRM device
1401 * @data: GTT mapping ioctl data
1402 * @file_priv: GEM object info
1403 *
1404 * Simply returns the fake offset to userspace so it can mmap it.
1405 * The mmap call will end up in drm_gem_mmap(), which will set things
1406 * up so we can get faults in the handler above.
1407 *
1408 * The fault handler will take care of binding the object into the GTT
1409 * (since it may have been evicted to make room for something), allocating
1410 * a fence register, and mapping the appropriate aperture address into
1411 * userspace.
1412 */
1413int
1414i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv)
1416{
1417 struct drm_i915_gem_mmap_gtt *args = data;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 struct drm_gem_object *obj;
1420 struct drm_i915_gem_object *obj_priv;
1421 int ret;
1422
1423 if (!(dev->driver->driver_features & DRIVER_GEM))
1424 return -ENODEV;
1425
1426 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1427 if (obj == NULL)
1428 return -EBADF;
1429
1430 mutex_lock(&dev->struct_mutex);
1431
1432 obj_priv = obj->driver_private;
1433
1434 if (!obj_priv->mmap_offset) {
1435 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1436 if (ret) {
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
de151cf6 1439 return ret;
13af1062 1440 }
de151cf6
JB		 1441 }
1442
1443 args->offset = obj_priv->mmap_offset;
1444
de151cf6
JB		 1445 /*
1446 * Pull it into the GTT so that we have a page list (makes the
1447 * initial fault faster and any subsequent flushing possible).
1448 */
1449 if (!obj_priv->agp_mem) {
e67b8ce1 1450 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1451 if (ret) {
1452 drm_gem_object_unreference(obj);
1453 mutex_unlock(&dev->struct_mutex);
1454 return ret;
1455 }
14b60391 1456 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1457 }
1458
1459 drm_gem_object_unreference(obj);
1460 mutex_unlock(&dev->struct_mutex);
1461
1462 return 0;
1463}
1464
6911a9b8 1465void
856fa198 1466i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b
EA		 1467{
1468 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1469 int page_count = obj->size / PAGE_SIZE;
1470 int i;
1471
856fa198 1472 BUG_ON(obj_priv->pages_refcount == 0);
673a394b 1473
856fa198
EA		 1474 if (--obj_priv->pages_refcount != 0)
1475 return;
673a394b 1476
280b713b
EA		 1477 if (obj_priv->tiling_mode != I915_TILING_NONE)
1478 i915_gem_object_save_bit_17_swizzle(obj);
1479
3ef94daa
CW		 1480 if (obj_priv->madv == I915_MADV_DONTNEED)
1481 obj_priv->dirty = 0;
1482
1483 for (i = 0; i < page_count; i++) {
1484 if (obj_priv->pages[i] == NULL)
1485 break;
1486
1487 if (obj_priv->dirty)
1488 set_page_dirty(obj_priv->pages[i]);
1489
1490 if (obj_priv->madv == I915_MADV_WILLNEED)
1491 mark_page_accessed(obj_priv->pages[i]);
1492
1493 page_cache_release(obj_priv->pages[i]);
1494 }
673a394b
EA		 1495 obj_priv->dirty = 0;
1496
8e7d2b2c 1497 drm_free_large(obj_priv->pages);
856fa198 1498 obj_priv->pages = NULL;
673a394b
EA		 1499}
1500
1501static void
ce44b0ea 1502i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
673a394b
EA		 1503{
1504 struct drm_device *dev = obj->dev;
1505 drm_i915_private_t *dev_priv = dev->dev_private;
1506 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1507
1508 /* Add a reference if we're newly entering the active list. */
1509 if (!obj_priv->active) {
1510 drm_gem_object_reference(obj);
1511 obj_priv->active = 1;
1512 }
1513 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1514 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1515 list_move_tail(&obj_priv->list,
1516 &dev_priv->mm.active_list);
5e118f41 1517 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1518 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1519}
1520
ce44b0ea
EA		 1521static void
1522i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1523{
1524 struct drm_device *dev = obj->dev;
1525 drm_i915_private_t *dev_priv = dev->dev_private;
1526 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1527
1528 BUG_ON(!obj_priv->active);
1529 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1530 obj_priv->last_rendering_seqno = 0;
1531}
673a394b
EA		 1532
1533static void
1534i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1535{
1536 struct drm_device *dev = obj->dev;
1537 drm_i915_private_t *dev_priv = dev->dev_private;
1538 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1539
1540 i915_verify_inactive(dev, __FILE__, __LINE__);
1541 if (obj_priv->pin_count != 0)
1542 list_del_init(&obj_priv->list);
1543 else
1544 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1545
ce44b0ea 1546 obj_priv->last_rendering_seqno = 0;
673a394b
EA		 1547 if (obj_priv->active) {
1548 obj_priv->active = 0;
1549 drm_gem_object_unreference(obj);
1550 }
1551 i915_verify_inactive(dev, __FILE__, __LINE__);
1552}
1553
1554/**
1555 * Creates a new sequence number, emitting a write of it to the status page
1556 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1557 *
1558 * Must be called with struct_lock held.
1559 *
1560 * Returned sequence numbers are nonzero on success.
1561 */
1562static uint32_t
b962442e
EA		 1563i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1564 uint32_t flush_domains)
673a394b
EA		 1565{
1566 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1567 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1568 struct drm_i915_gem_request *request;
1569 uint32_t seqno;
1570 int was_empty;
1571 RING_LOCALS;
1572
b962442e
EA		 1573 if (file_priv != NULL)
1574 i915_file_priv = file_priv->driver_priv;
1575
9a298b2a 1576 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1577 if (request == NULL)
1578 return 0;
1579
1580 /* Grab the seqno we're going to make this request be, and bump the
1581 * next (skipping 0 so it can be the reserved no-seqno value).
1582 */
1583 seqno = dev_priv->mm.next_gem_seqno;
1584 dev_priv->mm.next_gem_seqno++;
1585 if (dev_priv->mm.next_gem_seqno == 0)
1586 dev_priv->mm.next_gem_seqno++;
1587
1588 BEGIN_LP_RING(4);
1589 OUT_RING(MI_STORE_DWORD_INDEX);
1590 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1591 OUT_RING(seqno);
1592
1593 OUT_RING(MI_USER_INTERRUPT);
1594 ADVANCE_LP_RING();
1595
1596 DRM_DEBUG("%d\n", seqno);
1597
1598 request->seqno = seqno;
1599 request->emitted_jiffies = jiffies;
673a394b
EA		 1600 was_empty = list_empty(&dev_priv->mm.request_list);
1601 list_add_tail(&request->list, &dev_priv->mm.request_list);
b962442e
EA		 1602 if (i915_file_priv) {
1603 list_add_tail(&request->client_list,
1604 &i915_file_priv->mm.request_list);
1605 } else {
1606 INIT_LIST_HEAD(&request->client_list);
1607 }
673a394b 1608
ce44b0ea
EA		 1609 /* Associate any objects on the flushing list matching the write
1610 * domain we're flushing with our flush.
1611 */
1612 if (flush_domains != 0) {
1613 struct drm_i915_gem_object *obj_priv, *next;
1614
1615 list_for_each_entry_safe(obj_priv, next,
1616 &dev_priv->mm.flushing_list, list) {
1617 struct drm_gem_object *obj = obj_priv->obj;
1618
1619 if ((obj->write_domain & flush_domains) ==
1620 obj->write_domain) {
1621 obj->write_domain = 0;
1622 i915_gem_object_move_to_active(obj, seqno);
1623 }
1624 }
1625
1626 }
1627
f65d9421
BG		 1628 if (!dev_priv->mm.suspended) {
1629 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1630 if (was_empty)
1631 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1632 }
673a394b
EA		 1633 return seqno;
1634}
1635
1636/**
1637 * Command execution barrier
1638 *
1639 * Ensures that all commands in the ring are finished
1640 * before signalling the CPU
1641 */
3043c60c 1642static uint32_t
673a394b
EA		 1643i915_retire_commands(struct drm_device *dev)
1644{
1645 drm_i915_private_t *dev_priv = dev->dev_private;
1646 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1647 uint32_t flush_domains = 0;
1648 RING_LOCALS;
1649
1650 /* The sampler always gets flushed on i965 (sigh) */
1651 if (IS_I965G(dev))
1652 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1653 BEGIN_LP_RING(2);
1654 OUT_RING(cmd);
1655 OUT_RING(0); /* noop */
1656 ADVANCE_LP_RING();
1657 return flush_domains;
1658}
1659
1660/**
1661 * Moves buffers associated only with the given active seqno from the active
1662 * to inactive list, potentially freeing them.
1663 */
1664static void
1665i915_gem_retire_request(struct drm_device *dev,
1666 struct drm_i915_gem_request *request)
1667{
1668 drm_i915_private_t *dev_priv = dev->dev_private;
1669
1670 /* Move any buffers on the active list that are no longer referenced
1671 * by the ringbuffer to the flushing/inactive lists as appropriate.
1672 */
5e118f41 1673 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1674 while (!list_empty(&dev_priv->mm.active_list)) {
1675 struct drm_gem_object *obj;
1676 struct drm_i915_gem_object *obj_priv;
1677
1678 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1679 struct drm_i915_gem_object,
1680 list);
1681 obj = obj_priv->obj;
1682
1683 /* If the seqno being retired doesn't match the oldest in the
1684 * list, then the oldest in the list must still be newer than
1685 * this seqno.
1686 */
1687 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1688 goto out;
de151cf6 1689
673a394b
EA		 1690#if WATCH_LRU
1691 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1692 __func__, request->seqno, obj);
1693#endif
1694
ce44b0ea
EA		 1695 if (obj->write_domain != 0)
1696 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1697 else {
1698 /* Take a reference on the object so it won't be
1699 * freed while the spinlock is held. The list
1700 * protection for this spinlock is safe when breaking
1701 * the lock like this since the next thing we do
1702 * is just get the head of the list again.
1703 */
1704 drm_gem_object_reference(obj);
673a394b 1705 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1706 spin_unlock(&dev_priv->mm.active_list_lock);
1707 drm_gem_object_unreference(obj);
1708 spin_lock(&dev_priv->mm.active_list_lock);
1709 }
673a394b 1710 }
5e118f41
CW		 1711out:
1712 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1713}
1714
1715/**
1716 * Returns true if seq1 is later than seq2.
1717 */
22be1724 1718bool
673a394b
EA		 1719i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1720{
1721 return (int32_t)(seq1 - seq2) >= 0;
1722}
1723
1724uint32_t
1725i915_get_gem_seqno(struct drm_device *dev)
1726{
1727 drm_i915_private_t *dev_priv = dev->dev_private;
1728
1729 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1730}
1731
1732/**
1733 * This function clears the request list as sequence numbers are passed.
1734 */
1735void
1736i915_gem_retire_requests(struct drm_device *dev)
1737{
1738 drm_i915_private_t *dev_priv = dev->dev_private;
1739 uint32_t seqno;
1740
6c0594a3
KW		 1741 if (!dev_priv->hw_status_page)
1742 return;
1743
673a394b
EA		 1744 seqno = i915_get_gem_seqno(dev);
1745
1746 while (!list_empty(&dev_priv->mm.request_list)) {
1747 struct drm_i915_gem_request *request;
1748 uint32_t retiring_seqno;
1749
1750 request = list_first_entry(&dev_priv->mm.request_list,
1751 struct drm_i915_gem_request,
1752 list);
1753 retiring_seqno = request->seqno;
1754
1755 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1756 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1757 i915_gem_retire_request(dev, request);
1758
1759 list_del(&request->list);
b962442e 1760 list_del(&request->client_list);
9a298b2a 1761 kfree(request);
673a394b
EA		 1762 } else
1763 break;
1764 }
1765}
1766
1767void
1768i915_gem_retire_work_handler(struct work_struct *work)
1769{
1770 drm_i915_private_t *dev_priv;
1771 struct drm_device *dev;
1772
1773 dev_priv = container_of(work, drm_i915_private_t,
1774 mm.retire_work.work);
1775 dev = dev_priv->dev;
1776
1777 mutex_lock(&dev->struct_mutex);
1778 i915_gem_retire_requests(dev);
6dbe2772
KP		 1779 if (!dev_priv->mm.suspended &&
1780 !list_empty(&dev_priv->mm.request_list))
9c9fe1f8 1781 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1782 mutex_unlock(&dev->struct_mutex);
1783}
1784
1785/**
1786 * Waits for a sequence number to be signaled, and cleans up the
1787 * request and object lists appropriately for that event.
1788 */
3043c60c 1789static int
673a394b
EA		 1790i915_wait_request(struct drm_device *dev, uint32_t seqno)
1791{
1792 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1793 u32 ier;
673a394b
EA		 1794 int ret = 0;
1795
1796 BUG_ON(seqno == 0);
1797
ba1234d1 1798 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1799 return -EIO;
1800
673a394b 1801 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
036a4a7d
ZW		 1802 if (IS_IGDNG(dev))
1803 ier = I915_READ(DEIER) | I915_READ(GTIER);
1804 else
1805 ier = I915_READ(IER);
802c7eb6
JB		 1806 if (!ier) {
1807 DRM_ERROR("something (likely vbetool) disabled "
1808 "interrupts, re-enabling\n");
1809 i915_driver_irq_preinstall(dev);
1810 i915_driver_irq_postinstall(dev);
1811 }
1812
673a394b
EA		 1813 dev_priv->mm.waiting_gem_seqno = seqno;
1814 i915_user_irq_get(dev);
1815 ret = wait_event_interruptible(dev_priv->irq_queue,
1816 i915_seqno_passed(i915_get_gem_seqno(dev),
1817 seqno) ||
ba1234d1 1818 atomic_read(&dev_priv->mm.wedged));
673a394b
EA		 1819 i915_user_irq_put(dev);
1820 dev_priv->mm.waiting_gem_seqno = 0;
1821 }
ba1234d1 1822 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1823 ret = -EIO;
1824
1825 if (ret && ret != -ERESTARTSYS)
1826 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1827 __func__, ret, seqno, i915_get_gem_seqno(dev));
1828
1829 /* Directly dispatch request retiring. While we have the work queue
1830 * to handle this, the waiter on a request often wants an associated
1831 * buffer to have made it to the inactive list, and we would need
1832 * a separate wait queue to handle that.
1833 */
1834 if (ret == 0)
1835 i915_gem_retire_requests(dev);
1836
1837 return ret;
1838}
1839
1840static void
1841i915_gem_flush(struct drm_device *dev,
1842 uint32_t invalidate_domains,
1843 uint32_t flush_domains)
1844{
1845 drm_i915_private_t *dev_priv = dev->dev_private;
1846 uint32_t cmd;
1847 RING_LOCALS;
1848
1849#if WATCH_EXEC
1850 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1851 invalidate_domains, flush_domains);
1852#endif
1853
1854 if (flush_domains & I915_GEM_DOMAIN_CPU)
1855 drm_agp_chipset_flush(dev);
1856
21d509e3 1857 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
673a394b
EA		 1858 /*
1859 * read/write caches:
1860 *
1861 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1862 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1863 * also flushed at 2d versus 3d pipeline switches.
1864 *
1865 * read-only caches:
1866 *
1867 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1868 * MI_READ_FLUSH is set, and is always flushed on 965.
1869 *
1870 * I915_GEM_DOMAIN_COMMAND may not exist?
1871 *
1872 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1873 * invalidated when MI_EXE_FLUSH is set.
1874 *
1875 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1876 * invalidated with every MI_FLUSH.
1877 *
1878 * TLBs:
1879 *
1880 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1881 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1882 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1883 * are flushed at any MI_FLUSH.
1884 */
1885
1886 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1887 if ((invalidate_domains|flush_domains) &
1888 I915_GEM_DOMAIN_RENDER)
1889 cmd &= ~MI_NO_WRITE_FLUSH;
1890 if (!IS_I965G(dev)) {
1891 /*
1892 * On the 965, the sampler cache always gets flushed
1893 * and this bit is reserved.
1894 */
1895 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1896 cmd |= MI_READ_FLUSH;
1897 }
1898 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1899 cmd |= MI_EXE_FLUSH;
1900
1901#if WATCH_EXEC
1902 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1903#endif
1904 BEGIN_LP_RING(2);
1905 OUT_RING(cmd);
1906 OUT_RING(0); /* noop */
1907 ADVANCE_LP_RING();
1908 }
1909}
1910
1911/**
1912 * Ensures that all rendering to the object has completed and the object is
1913 * safe to unbind from the GTT or access from the CPU.
1914 */
1915static int
1916i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1917{
1918 struct drm_device *dev = obj->dev;
1919 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1920 int ret;
1921
e47c68e9
EA		 1922 /* This function only exists to support waiting for existing rendering,
1923 * not for emitting required flushes.
673a394b 1924 */
e47c68e9 1925 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1926
1927 /* If there is rendering queued on the buffer being evicted, wait for
1928 * it.
1929 */
1930 if (obj_priv->active) {
1931#if WATCH_BUF
1932 DRM_INFO("%s: object %p wait for seqno %08x\n",
1933 __func__, obj, obj_priv->last_rendering_seqno);
1934#endif
1935 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1936 if (ret != 0)
1937 return ret;
1938 }
1939
1940 return 0;
1941}
1942
1943/**
1944 * Unbinds an object from the GTT aperture.
1945 */
0f973f27 1946int
673a394b
EA		 1947i915_gem_object_unbind(struct drm_gem_object *obj)
1948{
1949 struct drm_device *dev = obj->dev;
1950 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1951 int ret = 0;
1952
1953#if WATCH_BUF
1954 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1955 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1956#endif
1957 if (obj_priv->gtt_space == NULL)
1958 return 0;
1959
1960 if (obj_priv->pin_count != 0) {
1961 DRM_ERROR("Attempting to unbind pinned buffer\n");
1962 return -EINVAL;
1963 }
1964
5323fd04
EA		 1965 /* blow away mappings if mapped through GTT */
1966 i915_gem_release_mmap(obj);
1967
1968 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1969 i915_gem_clear_fence_reg(obj);
1970
673a394b
EA		 1971 /* Move the object to the CPU domain to ensure that
1972 * any possible CPU writes while it's not in the GTT
1973 * are flushed when we go to remap it. This will
1974 * also ensure that all pending GPU writes are finished
1975 * before we unbind.
1976 */
e47c68e9 1977 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 1978 if (ret) {
e47c68e9
EA		 1979 if (ret != -ERESTARTSYS)
1980 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 1981 return ret;
1982 }
1983
5323fd04
EA		 1984 BUG_ON(obj_priv->active);
1985
673a394b
EA		 1986 if (obj_priv->agp_mem != NULL) {
1987 drm_unbind_agp(obj_priv->agp_mem);
1988 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1989 obj_priv->agp_mem = NULL;
1990 }
1991
856fa198 1992 i915_gem_object_put_pages(obj);
673a394b
EA		 1993
1994 if (obj_priv->gtt_space) {
1995 atomic_dec(&dev->gtt_count);
1996 atomic_sub(obj->size, &dev->gtt_memory);
1997
1998 drm_mm_put_block(obj_priv->gtt_space);
1999 obj_priv->gtt_space = NULL;
2000 }
2001
2002 /* Remove ourselves from the LRU list if present. */
2003 if (!list_empty(&obj_priv->list))
2004 list_del_init(&obj_priv->list);
2005
2006 return 0;
2007}
2008
07f73f69
CW		 2009static inline int
2010i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
2011{
2012 return !obj_priv->dirty || obj_priv->madv == I915_MADV_DONTNEED;
2013}
2014
2015static struct drm_gem_object *
2016i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2017{
2018 drm_i915_private_t *dev_priv = dev->dev_private;
2019 struct drm_i915_gem_object *obj_priv;
2020 struct drm_gem_object *best = NULL;
2021 struct drm_gem_object *first = NULL;
2022
2023 /* Try to find the smallest clean object */
2024 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2025 struct drm_gem_object *obj = obj_priv->obj;
2026 if (obj->size >= min_size) {
2027 if (i915_gem_object_is_purgeable(obj_priv) &&
2028 (!best || obj->size < best->size)) {
2029 best = obj;
2030 if (best->size == min_size)
2031 return best;
2032 }
2033 if (!first)
2034 first = obj;
2035 }
2036 }
2037
2038 return best ? best : first;
2039}
2040
2041static int
2042i915_gem_evict_everything(struct drm_device *dev)
2043{
2044 drm_i915_private_t *dev_priv = dev->dev_private;
2045 uint32_t seqno;
2046 int ret;
2047 bool lists_empty;
2048
2049 DRM_INFO("GTT full, evicting everything: "
2050 "%d objects [%d pinned], "
2051 "%d object bytes [%d pinned], "
2052 "%d/%d gtt bytes\n",
2053 atomic_read(&dev->object_count),
2054 atomic_read(&dev->pin_count),
2055 atomic_read(&dev->object_memory),
2056 atomic_read(&dev->pin_memory),
2057 atomic_read(&dev->gtt_memory),
2058 dev->gtt_total);
2059
2060 spin_lock(&dev_priv->mm.active_list_lock);
2061 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2062 list_empty(&dev_priv->mm.flushing_list) &&
2063 list_empty(&dev_priv->mm.active_list));
2064 spin_unlock(&dev_priv->mm.active_list_lock);
2065
2066 if (lists_empty) {
2067 DRM_ERROR("GTT full, but lists empty!\n");
2068 return -ENOSPC;
2069 }
2070
2071 /* Flush everything (on to the inactive lists) and evict */
2072 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2073 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2074 if (seqno == 0)
2075 return -ENOMEM;
2076
2077 ret = i915_wait_request(dev, seqno);
2078 if (ret)
2079 return ret;
2080
2081 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2082 if (ret)
2083 return ret;
2084
2085 spin_lock(&dev_priv->mm.active_list_lock);
2086 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2087 list_empty(&dev_priv->mm.flushing_list) &&
2088 list_empty(&dev_priv->mm.active_list));
2089 spin_unlock(&dev_priv->mm.active_list_lock);
2090 BUG_ON(!lists_empty);
2091
2092 return 0;
2093}
2094
673a394b 2095static int
07f73f69 2096i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2097{
2098 drm_i915_private_t *dev_priv = dev->dev_private;
2099 struct drm_gem_object *obj;
07f73f69
CW		 2100 int have_waited = 0;
2101 int ret;
673a394b
EA		 2102
2103 for (;;) {
07f73f69
CW		 2104 i915_gem_retire_requests(dev);
2105
673a394b
EA		 2106 /* If there's an inactive buffer available now, grab it
2107 * and be done.
2108 */
07f73f69
CW		 2109 obj = i915_gem_find_inactive_object(dev, min_size);
2110 if (obj) {
2111 struct drm_i915_gem_object *obj_priv;
2112
673a394b
EA		 2113#if WATCH_LRU
2114 DRM_INFO("%s: evicting %p\n", __func__, obj);
2115#endif
07f73f69
CW		 2116 obj_priv = obj->driver_private;
2117 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2118 BUG_ON(obj_priv->active);
2119
2120 /* Wait on the rendering and unbind the buffer. */
07f73f69 2121 return i915_gem_object_unbind(obj);
673a394b
EA		 2122 }
2123
07f73f69
CW		 2124 if (have_waited)
2125 return 0;
2126
673a394b 2127 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2128 * things, wait for the next to finish and hopefully leave us
2129 * a buffer to evict.
673a394b
EA		 2130 */
2131 if (!list_empty(&dev_priv->mm.request_list)) {
2132 struct drm_i915_gem_request *request;
2133
2134 request = list_first_entry(&dev_priv->mm.request_list,
2135 struct drm_i915_gem_request,
2136 list);
2137
2138 ret = i915_wait_request(dev, request->seqno);
2139 if (ret)
07f73f69 2140 return ret;
673a394b 2141
07f73f69
CW		 2142 have_waited = 1;
2143 continue;
673a394b
EA		 2144 }
2145
2146 /* If we didn't have anything on the request list but there
2147 * are buffers awaiting a flush, emit one and try again.
2148 * When we wait on it, those buffers waiting for that flush
2149 * will get moved to inactive.
2150 */
2151 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69
CW		 2152 struct drm_i915_gem_object *obj_priv;
2153 uint32_t seqno;
2154
673a394b
EA		 2155 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2156 struct drm_i915_gem_object,
2157 list);
2158 obj = obj_priv->obj;
2159
2160 i915_gem_flush(dev,
2161 obj->write_domain,
2162 obj->write_domain);
07f73f69
CW		 2163 seqno = i915_add_request(dev, NULL, obj->write_domain);
2164 if (seqno == 0)
2165 return -ENOMEM;
2166
2167 ret = i915_wait_request(dev, seqno);
2168 if (ret)
2169 return ret;
673a394b 2170
07f73f69 2171 have_waited = 1;
673a394b
EA		 2172 continue;
2173 }
2174
07f73f69
CW		 2175 /* If we didn't do any of the above, there's no single buffer
2176 * large enough to swap out for the new one, so just evict
2177 * everything and start again. (This should be rare.)
673a394b 2178 */
07f73f69
CW		 2179 if (!list_empty (&dev_priv->mm.inactive_list)) {
2180 DRM_INFO("GTT full, evicting inactive buffers\n");
2181 return i915_gem_evict_from_list(dev,
2182 &dev_priv->mm.inactive_list);
2183 } else
2184 return i915_gem_evict_everything(dev);
ac94a962 2185 }
ac94a962
KP		 2186}
2187
6911a9b8 2188int
856fa198 2189i915_gem_object_get_pages(struct drm_gem_object *obj)
673a394b
EA		 2190{
2191 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2192 int page_count, i;
2193 struct address_space *mapping;
2194 struct inode *inode;
2195 struct page *page;
2196 int ret;
2197
856fa198 2198 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2199 return 0;
2200
2201 /* Get the list of pages out of our struct file. They'll be pinned
2202 * at this point until we release them.
2203 */
2204 page_count = obj->size / PAGE_SIZE;
856fa198 2205 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2206 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2207 if (obj_priv->pages == NULL) {
07f73f69 2208 DRM_ERROR("Failed to allocate page list\n");
856fa198 2209 obj_priv->pages_refcount--;
673a394b
EA		 2210 return -ENOMEM;
2211 }
2212
2213 inode = obj->filp->f_path.dentry->d_inode;
2214 mapping = inode->i_mapping;
2215 for (i = 0; i < page_count; i++) {
2216 page = read_mapping_page(mapping, i, NULL);
2217 if (IS_ERR(page)) {
2218 ret = PTR_ERR(page);
856fa198 2219 i915_gem_object_put_pages(obj);
673a394b
EA		 2220 return ret;
2221 }
856fa198 2222 obj_priv->pages[i] = page;
673a394b 2223 }
280b713b
EA		 2224
2225 if (obj_priv->tiling_mode != I915_TILING_NONE)
2226 i915_gem_object_do_bit_17_swizzle(obj);
2227
673a394b
EA		 2228 return 0;
2229}
2230
de151cf6
JB		 2231static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2232{
2233 struct drm_gem_object *obj = reg->obj;
2234 struct drm_device *dev = obj->dev;
2235 drm_i915_private_t *dev_priv = dev->dev_private;
2236 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2237 int regnum = obj_priv->fence_reg;
2238 uint64_t val;
2239
2240 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2241 0xfffff000) << 32;
2242 val |= obj_priv->gtt_offset & 0xfffff000;
2243 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2244 if (obj_priv->tiling_mode == I915_TILING_Y)
2245 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2246 val |= I965_FENCE_REG_VALID;
2247
2248 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2249}
2250
2251static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2252{
2253 struct drm_gem_object *obj = reg->obj;
2254 struct drm_device *dev = obj->dev;
2255 drm_i915_private_t *dev_priv = dev->dev_private;
2256 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2257 int regnum = obj_priv->fence_reg;
0f973f27 2258 int tile_width;
dc529a4f 2259 uint32_t fence_reg, val;
de151cf6
JB		 2260 uint32_t pitch_val;
2261
2262 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2263 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2264 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2265 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2266 return;
2267 }
2268
0f973f27
JB		 2269 if (obj_priv->tiling_mode == I915_TILING_Y &&
2270 HAS_128_BYTE_Y_TILING(dev))
2271 tile_width = 128;
de151cf6 2272 else
0f973f27
JB		 2273 tile_width = 512;
2274
2275 /* Note: pitch better be a power of two tile widths */
2276 pitch_val = obj_priv->stride / tile_width;
2277 pitch_val = ffs(pitch_val) - 1;
de151cf6
JB		 2278
2279 val = obj_priv->gtt_offset;
2280 if (obj_priv->tiling_mode == I915_TILING_Y)
2281 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2282 val |= I915_FENCE_SIZE_BITS(obj->size);
2283 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2284 val |= I830_FENCE_REG_VALID;
2285
dc529a4f
EA		 2286 if (regnum < 8)
2287 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2288 else
2289 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2290 I915_WRITE(fence_reg, val);
de151cf6
JB		 2291}
2292
2293static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2294{
2295 struct drm_gem_object *obj = reg->obj;
2296 struct drm_device *dev = obj->dev;
2297 drm_i915_private_t *dev_priv = dev->dev_private;
2298 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2299 int regnum = obj_priv->fence_reg;
2300 uint32_t val;
2301 uint32_t pitch_val;
8d7773a3 2302 uint32_t fence_size_bits;
de151cf6 2303
8d7773a3 2304 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2305 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2306 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2307 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2308 return;
2309 }
2310
e76a16de
EA		 2311 pitch_val = obj_priv->stride / 128;
2312 pitch_val = ffs(pitch_val) - 1;
2313 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2314
de151cf6
JB		 2315 val = obj_priv->gtt_offset;
2316 if (obj_priv->tiling_mode == I915_TILING_Y)
2317 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2318 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2319 WARN_ON(fence_size_bits & ~0x00000f00);
2320 val |= fence_size_bits;
de151cf6
JB		 2321 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2322 val |= I830_FENCE_REG_VALID;
2323
2324 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2325}
2326
2327/**
2328 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2329 * @obj: object to map through a fence reg
2330 *
2331 * When mapping objects through the GTT, userspace wants to be able to write
2332 * to them without having to worry about swizzling if the object is tiled.
2333 *
2334 * This function walks the fence regs looking for a free one for @obj,
2335 * stealing one if it can't find any.
2336 *
2337 * It then sets up the reg based on the object's properties: address, pitch
2338 * and tiling format.
2339 */
8c4b8c3f
CW		 2340int
2341i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2342{
2343 struct drm_device *dev = obj->dev;
79e53945 2344 struct drm_i915_private *dev_priv = dev->dev_private;
de151cf6
JB		 2345 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2346 struct drm_i915_fence_reg *reg = NULL;
fc7170ba
CW		 2347 struct drm_i915_gem_object *old_obj_priv = NULL;
2348 int i, ret, avail;
de151cf6 2349
a09ba7fa
EA		 2350 /* Just update our place in the LRU if our fence is getting used. */
2351 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2352 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2353 return 0;
2354 }
2355
de151cf6
JB		 2356 switch (obj_priv->tiling_mode) {
2357 case I915_TILING_NONE:
2358 WARN(1, "allocating a fence for non-tiled object?\n");
2359 break;
2360 case I915_TILING_X:
0f973f27
JB		 2361 if (!obj_priv->stride)
2362 return -EINVAL;
2363 WARN((obj_priv->stride & (512 - 1)),
2364 "object 0x%08x is X tiled but has non-512B pitch\n",
2365 obj_priv->gtt_offset);
de151cf6
JB		 2366 break;
2367 case I915_TILING_Y:
0f973f27
JB		 2368 if (!obj_priv->stride)
2369 return -EINVAL;
2370 WARN((obj_priv->stride & (128 - 1)),
2371 "object 0x%08x is Y tiled but has non-128B pitch\n",
2372 obj_priv->gtt_offset);
de151cf6
JB		 2373 break;
2374 }
2375
2376 /* First try to find a free reg */
fc7170ba 2377 avail = 0;
de151cf6
JB		 2378 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2379 reg = &dev_priv->fence_regs[i];
2380 if (!reg->obj)
2381 break;
fc7170ba
CW		 2382
2383 old_obj_priv = reg->obj->driver_private;
2384 if (!old_obj_priv->pin_count)
2385 avail++;
de151cf6
JB		 2386 }
2387
2388 /* None available, try to steal one or wait for a user to finish */
2389 if (i == dev_priv->num_fence_regs) {
a09ba7fa 2390 struct drm_gem_object *old_obj = NULL;
de151cf6 2391
fc7170ba 2392 if (avail == 0)
2939e1f5 2393 return -ENOSPC;
fc7170ba 2394
a09ba7fa
EA		 2395 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2396 fence_list) {
2397 old_obj = old_obj_priv->obj;
d7619c4b
CW		 2398
2399 if (old_obj_priv->pin_count)
2400 continue;
2401
a09ba7fa
EA		 2402 /* Take a reference, as otherwise the wait_rendering
2403 * below may cause the object to get freed out from
2404 * under us.
2405 */
2406 drm_gem_object_reference(old_obj);
2407
d7619c4b
CW		 2408 /* i915 uses fences for GPU access to tiled buffers */
2409 if (IS_I965G(dev) || !old_obj_priv->active)
de151cf6 2410 break;
d7619c4b 2411
a09ba7fa
EA		 2412 /* This brings the object to the head of the LRU if it
2413 * had been written to. The only way this should
2414 * result in us waiting longer than the expected
2415 * optimal amount of time is if there was a
2416 * fence-using buffer later that was read-only.
2417 */
2418 i915_gem_object_flush_gpu_write_domain(old_obj);
2419 ret = i915_gem_object_wait_rendering(old_obj);
58c2fb64
CW		 2420 if (ret != 0) {
2421 drm_gem_object_unreference(old_obj);
d7619c4b 2422 return ret;
de151cf6 2423 }
d7619c4b 2424
a09ba7fa 2425 break;
de151cf6
JB		 2426 }
2427
2428 /*
2429 * Zap this virtual mapping so we can set up a fence again
2430 * for this object next time we need it.
2431 */
58c2fb64
CW		 2432 i915_gem_release_mmap(old_obj);
2433
a09ba7fa 2434 i = old_obj_priv->fence_reg;
58c2fb64
CW		 2435 reg = &dev_priv->fence_regs[i];
2436
de151cf6 2437 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2438 list_del_init(&old_obj_priv->fence_list);
58c2fb64 2439
a09ba7fa 2440 drm_gem_object_unreference(old_obj);
de151cf6
JB		 2441 }
2442
2443 obj_priv->fence_reg = i;
a09ba7fa
EA		 2444 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2445
de151cf6
JB		 2446 reg->obj = obj;
2447
2448 if (IS_I965G(dev))
2449 i965_write_fence_reg(reg);
2450 else if (IS_I9XX(dev))
2451 i915_write_fence_reg(reg);
2452 else
2453 i830_write_fence_reg(reg);
d9ddcb96
EA		 2454
2455 return 0;
de151cf6
JB		 2456}
2457
2458/**
2459 * i915_gem_clear_fence_reg - clear out fence register info
2460 * @obj: object to clear
2461 *
2462 * Zeroes out the fence register itself and clears out the associated
2463 * data structures in dev_priv and obj_priv.
2464 */
2465static void
2466i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2467{
2468 struct drm_device *dev = obj->dev;
79e53945 2469 drm_i915_private_t *dev_priv = dev->dev_private;
de151cf6
JB		 2470 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2471
2472 if (IS_I965G(dev))
2473 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
dc529a4f
EA		 2474 else {
2475 uint32_t fence_reg;
2476
2477 if (obj_priv->fence_reg < 8)
2478 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2479 else
2480 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2481 8) * 4;
2482
2483 I915_WRITE(fence_reg, 0);
2484 }
de151cf6
JB		 2485
2486 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2487 obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2488 list_del_init(&obj_priv->fence_list);
de151cf6
JB		 2489}
2490
52dc7d32
CW		 2491/**
2492 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2493 * to the buffer to finish, and then resets the fence register.
2494 * @obj: tiled object holding a fence register.
2495 *
2496 * Zeroes out the fence register itself and clears out the associated
2497 * data structures in dev_priv and obj_priv.
2498 */
2499int
2500i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2501{
2502 struct drm_device *dev = obj->dev;
2503 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2504
2505 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2506 return 0;
2507
2508 /* On the i915, GPU access to tiled buffers is via a fence,
2509 * therefore we must wait for any outstanding access to complete
2510 * before clearing the fence.
2511 */
2512 if (!IS_I965G(dev)) {
2513 int ret;
2514
2515 i915_gem_object_flush_gpu_write_domain(obj);
2516 i915_gem_object_flush_gtt_write_domain(obj);
2517 ret = i915_gem_object_wait_rendering(obj);
2518 if (ret != 0)
2519 return ret;
2520 }
2521
2522 i915_gem_clear_fence_reg (obj);
2523
2524 return 0;
2525}
2526
673a394b
EA		 2527/**
2528 * Finds free space in the GTT aperture and binds the object there.
2529 */
2530static int
2531i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2532{
2533 struct drm_device *dev = obj->dev;
2534 drm_i915_private_t *dev_priv = dev->dev_private;
2535 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2536 struct drm_mm_node *free_space;
07f73f69
CW		 2537 bool retry_alloc = false;
2538 int ret;
673a394b 2539
9bb2d6f9
EA		 2540 if (dev_priv->mm.suspended)
2541 return -EBUSY;
3ef94daa
CW		 2542
2543 if (obj_priv->madv == I915_MADV_DONTNEED) {
2544 DRM_ERROR("Attempting to bind a purgeable object\n");
2545 return -EINVAL;
2546 }
2547
673a394b 2548 if (alignment == 0)
0f973f27 2549 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2550 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2551 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2552 return -EINVAL;
2553 }
2554
2555 search_free:
2556 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2557 obj->size, alignment, 0);
2558 if (free_space != NULL) {
2559 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2560 alignment);
2561 if (obj_priv->gtt_space != NULL) {
2562 obj_priv->gtt_space->private = obj;
2563 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2564 }
2565 }
2566 if (obj_priv->gtt_space == NULL) {
2567 /* If the gtt is empty and we're still having trouble
2568 * fitting our object in, we're out of memory.
2569 */
2570#if WATCH_LRU
2571 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2572#endif
07f73f69 2573 ret = i915_gem_evict_something(dev, obj->size);
673a394b 2574 if (ret != 0) {
ac94a962
KP		 2575 if (ret != -ERESTARTSYS)
2576 DRM_ERROR("Failed to evict a buffer %d\n", ret);
673a394b
EA		 2577 return ret;
2578 }
2579 goto search_free;
2580 }
2581
2582#if WATCH_BUF
cfd43c02 2583 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2584 obj->size, obj_priv->gtt_offset);
2585#endif
07f73f69
CW		 2586 if (retry_alloc) {
2587 i915_gem_object_set_page_gfp_mask (obj,
2588 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2589 }
856fa198 2590 ret = i915_gem_object_get_pages(obj);
07f73f69
CW		 2591 if (retry_alloc) {
2592 i915_gem_object_set_page_gfp_mask (obj,
2593 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2594 }
673a394b
EA		 2595 if (ret) {
2596 drm_mm_put_block(obj_priv->gtt_space);
2597 obj_priv->gtt_space = NULL;
07f73f69
CW		 2598
2599 if (ret == -ENOMEM) {
2600 /* first try to clear up some space from the GTT */
2601 ret = i915_gem_evict_something(dev, obj->size);
2602 if (ret) {
2603 if (ret != -ERESTARTSYS)
2604 DRM_ERROR("Failed to allocate space for backing pages %d\n", ret);
2605
2606 /* now try to shrink everyone else */
2607 if (! retry_alloc) {
2608 retry_alloc = true;
2609 goto search_free;
2610 }
2611
2612 return ret;
2613 }
2614
2615 goto search_free;
2616 }
2617
673a394b
EA		 2618 return ret;
2619 }
2620
673a394b
EA		 2621 /* Create an AGP memory structure pointing at our pages, and bind it
2622 * into the GTT.
2623 */
2624 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2625 obj_priv->pages,
07f73f69 2626 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2627 obj_priv->gtt_offset,
2628 obj_priv->agp_type);
673a394b 2629 if (obj_priv->agp_mem == NULL) {
856fa198 2630 i915_gem_object_put_pages(obj);
673a394b
EA		 2631 drm_mm_put_block(obj_priv->gtt_space);
2632 obj_priv->gtt_space = NULL;
07f73f69
CW		 2633
2634 ret = i915_gem_evict_something(dev, obj->size);
2635 if (ret) {
2636 if (ret != -ERESTARTSYS)
2637 DRM_ERROR("Failed to allocate space to bind AGP: %d\n", ret);
2638 return ret;
2639 }
2640
2641 goto search_free;
673a394b
EA		 2642 }
2643 atomic_inc(&dev->gtt_count);
2644 atomic_add(obj->size, &dev->gtt_memory);
2645
2646 /* Assert that the object is not currently in any GPU domain. As it
2647 * wasn't in the GTT, there shouldn't be any way it could have been in
2648 * a GPU cache
2649 */
21d509e3
CW		 2650 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2651 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b
EA		 2652
2653 return 0;
2654}
2655
2656void
2657i915_gem_clflush_object(struct drm_gem_object *obj)
2658{
2659 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2660
2661 /* If we don't have a page list set up, then we're not pinned
2662 * to GPU, and we can ignore the cache flush because it'll happen
2663 * again at bind time.
2664 */
856fa198 2665 if (obj_priv->pages == NULL)
673a394b
EA		 2666 return;
2667
856fa198 2668 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2669}
2670
e47c68e9
EA		 2671/** Flushes any GPU write domain for the object if it's dirty. */
2672static void
2673i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2674{
2675 struct drm_device *dev = obj->dev;
2676 uint32_t seqno;
2677
2678 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2679 return;
2680
2681 /* Queue the GPU write cache flushing we need. */
2682 i915_gem_flush(dev, 0, obj->write_domain);
b962442e 2683 seqno = i915_add_request(dev, NULL, obj->write_domain);
e47c68e9
EA		 2684 obj->write_domain = 0;
2685 i915_gem_object_move_to_active(obj, seqno);
2686}
2687
2688/** Flushes the GTT write domain for the object if it's dirty. */
2689static void
2690i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2691{
2692 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2693 return;
2694
2695 /* No actual flushing is required for the GTT write domain. Writes
2696 * to it immediately go to main memory as far as we know, so there's
2697 * no chipset flush. It also doesn't land in render cache.
2698 */
2699 obj->write_domain = 0;
2700}
2701
2702/** Flushes the CPU write domain for the object if it's dirty. */
2703static void
2704i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2705{
2706 struct drm_device *dev = obj->dev;
2707
2708 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2709 return;
2710
2711 i915_gem_clflush_object(obj);
2712 drm_agp_chipset_flush(dev);
2713 obj->write_domain = 0;
2714}
2715
2ef7eeaa
EA		 2716/**
2717 * Moves a single object to the GTT read, and possibly write domain.
2718 *
2719 * This function returns when the move is complete, including waiting on
2720 * flushes to occur.
2721 */
79e53945 2722int
2ef7eeaa
EA		 2723i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2724{
2ef7eeaa 2725 struct drm_i915_gem_object *obj_priv = obj->driver_private;
e47c68e9 2726 int ret;
2ef7eeaa 2727
02354392
EA		 2728 /* Not valid to be called on unbound objects. */
2729 if (obj_priv->gtt_space == NULL)
2730 return -EINVAL;
2731
e47c68e9
EA		 2732 i915_gem_object_flush_gpu_write_domain(obj);
2733 /* Wait on any GPU rendering and flushing to occur. */
2734 ret = i915_gem_object_wait_rendering(obj);
2735 if (ret != 0)
2736 return ret;
2737
2738 /* If we're writing through the GTT domain, then CPU and GPU caches
2739 * will need to be invalidated at next use.
2ef7eeaa 2740 */
e47c68e9
EA		 2741 if (write)
2742 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2743
e47c68e9 2744 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2745
e47c68e9
EA		 2746 /* It should now be out of any other write domains, and we can update
2747 * the domain values for our changes.
2748 */
2749 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2750 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2751 if (write) {
2752 obj->write_domain = I915_GEM_DOMAIN_GTT;
2753 obj_priv->dirty = 1;
2ef7eeaa
EA		 2754 }
2755
e47c68e9
EA		 2756 return 0;
2757}
2758
2759/**
2760 * Moves a single object to the CPU read, and possibly write domain.
2761 *
2762 * This function returns when the move is complete, including waiting on
2763 * flushes to occur.
2764 */
2765static int
2766i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2767{
e47c68e9
EA		 2768 int ret;
2769
2770 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2771 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2772 ret = i915_gem_object_wait_rendering(obj);
2773 if (ret != 0)
2774 return ret;
2ef7eeaa 2775
e47c68e9 2776 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2777
e47c68e9
EA		 2778 /* If we have a partially-valid cache of the object in the CPU,
2779 * finish invalidating it and free the per-page flags.
2ef7eeaa 2780 */
e47c68e9 2781 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2782
e47c68e9
EA		 2783 /* Flush the CPU cache if it's still invalid. */
2784 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2785 i915_gem_clflush_object(obj);
2ef7eeaa 2786
e47c68e9 2787 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2788 }
2789
2790 /* It should now be out of any other write domains, and we can update
2791 * the domain values for our changes.
2792 */
e47c68e9
EA		 2793 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2794
2795 /* If we're writing through the CPU, then the GPU read domains will
2796 * need to be invalidated at next use.
2797 */
2798 if (write) {
2799 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2800 obj->write_domain = I915_GEM_DOMAIN_CPU;
2801 }
2ef7eeaa
EA		 2802
2803 return 0;
2804}
2805
673a394b
EA		 2806/*
2807 * Set the next domain for the specified object. This
2808 * may not actually perform the necessary flushing/invaliding though,
2809 * as that may want to be batched with other set_domain operations
2810 *
2811 * This is (we hope) the only really tricky part of gem. The goal
2812 * is fairly simple -- track which caches hold bits of the object
2813 * and make sure they remain coherent. A few concrete examples may
2814 * help to explain how it works. For shorthand, we use the notation
2815 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2816 * a pair of read and write domain masks.
2817 *
2818 * Case 1: the batch buffer
2819 *
2820 * 1. Allocated
2821 * 2. Written by CPU
2822 * 3. Mapped to GTT
2823 * 4. Read by GPU
2824 * 5. Unmapped from GTT
2825 * 6. Freed
2826 *
2827 * Let's take these a step at a time
2828 *
2829 * 1. Allocated
2830 * Pages allocated from the kernel may still have
2831 * cache contents, so we set them to (CPU, CPU) always.
2832 * 2. Written by CPU (using pwrite)
2833 * The pwrite function calls set_domain (CPU, CPU) and
2834 * this function does nothing (as nothing changes)
2835 * 3. Mapped by GTT
2836 * This function asserts that the object is not
2837 * currently in any GPU-based read or write domains
2838 * 4. Read by GPU
2839 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2840 * As write_domain is zero, this function adds in the
2841 * current read domains (CPU+COMMAND, 0).
2842 * flush_domains is set to CPU.
2843 * invalidate_domains is set to COMMAND
2844 * clflush is run to get data out of the CPU caches
2845 * then i915_dev_set_domain calls i915_gem_flush to
2846 * emit an MI_FLUSH and drm_agp_chipset_flush
2847 * 5. Unmapped from GTT
2848 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2849 * flush_domains and invalidate_domains end up both zero
2850 * so no flushing/invalidating happens
2851 * 6. Freed
2852 * yay, done
2853 *
2854 * Case 2: The shared render buffer
2855 *
2856 * 1. Allocated
2857 * 2. Mapped to GTT
2858 * 3. Read/written by GPU
2859 * 4. set_domain to (CPU,CPU)
2860 * 5. Read/written by CPU
2861 * 6. Read/written by GPU
2862 *
2863 * 1. Allocated
2864 * Same as last example, (CPU, CPU)
2865 * 2. Mapped to GTT
2866 * Nothing changes (assertions find that it is not in the GPU)
2867 * 3. Read/written by GPU
2868 * execbuffer calls set_domain (RENDER, RENDER)
2869 * flush_domains gets CPU
2870 * invalidate_domains gets GPU
2871 * clflush (obj)
2872 * MI_FLUSH and drm_agp_chipset_flush
2873 * 4. set_domain (CPU, CPU)
2874 * flush_domains gets GPU
2875 * invalidate_domains gets CPU
2876 * wait_rendering (obj) to make sure all drawing is complete.
2877 * This will include an MI_FLUSH to get the data from GPU
2878 * to memory
2879 * clflush (obj) to invalidate the CPU cache
2880 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2881 * 5. Read/written by CPU
2882 * cache lines are loaded and dirtied
2883 * 6. Read written by GPU
2884 * Same as last GPU access
2885 *
2886 * Case 3: The constant buffer
2887 *
2888 * 1. Allocated
2889 * 2. Written by CPU
2890 * 3. Read by GPU
2891 * 4. Updated (written) by CPU again
2892 * 5. Read by GPU
2893 *
2894 * 1. Allocated
2895 * (CPU, CPU)
2896 * 2. Written by CPU
2897 * (CPU, CPU)
2898 * 3. Read by GPU
2899 * (CPU+RENDER, 0)
2900 * flush_domains = CPU
2901 * invalidate_domains = RENDER
2902 * clflush (obj)
2903 * MI_FLUSH
2904 * drm_agp_chipset_flush
2905 * 4. Updated (written) by CPU again
2906 * (CPU, CPU)
2907 * flush_domains = 0 (no previous write domain)
2908 * invalidate_domains = 0 (no new read domains)
2909 * 5. Read by GPU
2910 * (CPU+RENDER, 0)
2911 * flush_domains = CPU
2912 * invalidate_domains = RENDER
2913 * clflush (obj)
2914 * MI_FLUSH
2915 * drm_agp_chipset_flush
2916 */
c0d90829 2917static void
8b0e378a 2918i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 2919{
2920 struct drm_device *dev = obj->dev;
2921 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2922 uint32_t invalidate_domains = 0;
2923 uint32_t flush_domains = 0;
e47c68e9 2924
8b0e378a
EA		 2925 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2926 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 2927
652c393a
JB		 2928 intel_mark_busy(dev, obj);
2929
673a394b
EA		 2930#if WATCH_BUF
2931 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2932 __func__, obj,
8b0e378a
EA		 2933 obj->read_domains, obj->pending_read_domains,
2934 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 2935#endif
2936 /*
2937 * If the object isn't moving to a new write domain,
2938 * let the object stay in multiple read domains
2939 */
8b0e378a
EA		 2940 if (obj->pending_write_domain == 0)
2941 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 2942 else
2943 obj_priv->dirty = 1;
2944
2945 /*
2946 * Flush the current write domain if
2947 * the new read domains don't match. Invalidate
2948 * any read domains which differ from the old
2949 * write domain
2950 */
8b0e378a
EA		 2951 if (obj->write_domain &&
2952 obj->write_domain != obj->pending_read_domains) {
673a394b 2953 flush_domains |= obj->write_domain;
8b0e378a
EA		 2954 invalidate_domains |=
2955 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 2956 }
2957 /*
2958 * Invalidate any read caches which may have
2959 * stale data. That is, any new read domains.
2960 */
8b0e378a 2961 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 2962 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2963#if WATCH_BUF
2964 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2965 __func__, flush_domains, invalidate_domains);
2966#endif
673a394b
EA		 2967 i915_gem_clflush_object(obj);
2968 }
2969
efbeed96
EA		 2970 /* The actual obj->write_domain will be updated with
2971 * pending_write_domain after we emit the accumulated flush for all
2972 * of our domain changes in execbuffers (which clears objects'
2973 * write_domains). So if we have a current write domain that we
2974 * aren't changing, set pending_write_domain to that.
2975 */
2976 if (flush_domains == 0 && obj->pending_write_domain == 0)
2977 obj->pending_write_domain = obj->write_domain;
8b0e378a 2978 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 2979
2980 dev->invalidate_domains |= invalidate_domains;
2981 dev->flush_domains |= flush_domains;
2982#if WATCH_BUF
2983 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2984 __func__,
2985 obj->read_domains, obj->write_domain,
2986 dev->invalidate_domains, dev->flush_domains);
2987#endif
673a394b
EA		 2988}
2989
2990/**
e47c68e9 2991 * Moves the object from a partially CPU read to a full one.
673a394b 2992 *
e47c68e9
EA		 2993 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2994 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 2995 */
e47c68e9
EA		 2996static void
2997i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b
EA		 2998{
2999 struct drm_i915_gem_object *obj_priv = obj->driver_private;
673a394b 3000
e47c68e9
EA		 3001 if (!obj_priv->page_cpu_valid)
3002 return;
3003
3004 /* If we're partially in the CPU read domain, finish moving it in.
3005 */
3006 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3007 int i;
3008
3009 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3010 if (obj_priv->page_cpu_valid[i])
3011 continue;
856fa198 3012 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3013 }
e47c68e9
EA		 3014 }
3015
3016 /* Free the page_cpu_valid mappings which are now stale, whether
3017 * or not we've got I915_GEM_DOMAIN_CPU.
3018 */
9a298b2a 3019 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3020 obj_priv->page_cpu_valid = NULL;
3021}
3022
3023/**
3024 * Set the CPU read domain on a range of the object.
3025 *
3026 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3027 * not entirely valid. The page_cpu_valid member of the object flags which
3028 * pages have been flushed, and will be respected by
3029 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3030 * of the whole object.
3031 *
3032 * This function returns when the move is complete, including waiting on
3033 * flushes to occur.
3034 */
3035static int
3036i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3037 uint64_t offset, uint64_t size)
3038{
3039 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3040 int i, ret;
673a394b 3041
e47c68e9
EA		 3042 if (offset == 0 && size == obj->size)
3043 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3044
e47c68e9
EA		 3045 i915_gem_object_flush_gpu_write_domain(obj);
3046 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3047 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3048 if (ret != 0)
6a47baa6 3049 return ret;
e47c68e9
EA		 3050 i915_gem_object_flush_gtt_write_domain(obj);
3051
3052 /* If we're already fully in the CPU read domain, we're done. */
3053 if (obj_priv->page_cpu_valid == NULL &&
3054 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3055 return 0;
673a394b 3056
e47c68e9
EA		 3057 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3058 * newly adding I915_GEM_DOMAIN_CPU
3059 */
673a394b 3060 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3061 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3062 GFP_KERNEL);
e47c68e9
EA		 3063 if (obj_priv->page_cpu_valid == NULL)
3064 return -ENOMEM;
3065 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3066 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3067
3068 /* Flush the cache on any pages that are still invalid from the CPU's
3069 * perspective.
3070 */
e47c68e9
EA		 3071 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3072 i++) {
673a394b
EA		 3073 if (obj_priv->page_cpu_valid[i])
3074 continue;
3075
856fa198 3076 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3077
3078 obj_priv->page_cpu_valid[i] = 1;
3079 }
3080
e47c68e9
EA		 3081 /* It should now be out of any other write domains, and we can update
3082 * the domain values for our changes.
3083 */
3084 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3085
3086 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3087
673a394b
EA		 3088 return 0;
3089}
3090
673a394b
EA		 3091/**
3092 * Pin an object to the GTT and evaluate the relocations landing in it.
3093 */
3094static int
3095i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3096 struct drm_file *file_priv,
40a5f0de
EA		 3097 struct drm_i915_gem_exec_object *entry,
3098 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3099{
3100 struct drm_device *dev = obj->dev;
0839ccb8 3101 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3102 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3103 int i, ret;
0839ccb8 3104 void __iomem *reloc_page;
673a394b
EA		 3105
3106 /* Choose the GTT offset for our buffer and put it there. */
3107 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3108 if (ret)
3109 return ret;
3110
3111 entry->offset = obj_priv->gtt_offset;
3112
673a394b
EA		 3113 /* Apply the relocations, using the GTT aperture to avoid cache
3114 * flushing requirements.
3115 */
3116 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3117 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3118 struct drm_gem_object *target_obj;
3119 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3120 uint32_t reloc_val, reloc_offset;
3121 uint32_t __iomem *reloc_entry;
673a394b 3122
673a394b 3123 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3124 reloc->target_handle);
673a394b
EA		 3125 if (target_obj == NULL) {
3126 i915_gem_object_unpin(obj);
3127 return -EBADF;
3128 }
3129 target_obj_priv = target_obj->driver_private;
3130
8542a0bb
CW		 3131#if WATCH_RELOC
3132 DRM_INFO("%s: obj %p offset %08x target %d "
3133 "read %08x write %08x gtt %08x "
3134 "presumed %08x delta %08x\n",
3135 __func__,
3136 obj,
3137 (int) reloc->offset,
3138 (int) reloc->target_handle,
3139 (int) reloc->read_domains,
3140 (int) reloc->write_domain,
3141 (int) target_obj_priv->gtt_offset,
3142 (int) reloc->presumed_offset,
3143 reloc->delta);
3144#endif
3145
673a394b
EA		 3146 /* The target buffer should have appeared before us in the
3147 * exec_object list, so it should have a GTT space bound by now.
3148 */
3149 if (target_obj_priv->gtt_space == NULL) {
3150 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3151 reloc->target_handle);
673a394b
EA		 3152 drm_gem_object_unreference(target_obj);
3153 i915_gem_object_unpin(obj);
3154 return -EINVAL;
3155 }
3156
8542a0bb 3157 /* Validate that the target is in a valid r/w GPU domain */
40a5f0de
EA		 3158 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3159 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3160 DRM_ERROR("reloc with read/write CPU domains: "
3161 "obj %p target %d offset %d "
3162 "read %08x write %08x",
40a5f0de
EA		 3163 obj, reloc->target_handle,
3164 (int) reloc->offset,
3165 reloc->read_domains,
3166 reloc->write_domain);
491152b8
CW		 3167 drm_gem_object_unreference(target_obj);
3168 i915_gem_object_unpin(obj);
e47c68e9
EA		 3169 return -EINVAL;
3170 }
40a5f0de
EA		 3171 if (reloc->write_domain && target_obj->pending_write_domain &&
3172 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3173 DRM_ERROR("Write domain conflict: "
3174 "obj %p target %d offset %d "
3175 "new %08x old %08x\n",
40a5f0de
EA		 3176 obj, reloc->target_handle,
3177 (int) reloc->offset,
3178 reloc->write_domain,
673a394b
EA		 3179 target_obj->pending_write_domain);
3180 drm_gem_object_unreference(target_obj);
3181 i915_gem_object_unpin(obj);
3182 return -EINVAL;
3183 }
3184
40a5f0de
EA		 3185 target_obj->pending_read_domains |= reloc->read_domains;
3186 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3187
3188 /* If the relocation already has the right value in it, no
3189 * more work needs to be done.
3190 */
40a5f0de 3191 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3192 drm_gem_object_unreference(target_obj);
3193 continue;
3194 }
3195
8542a0bb
CW		 3196 /* Check that the relocation address is valid... */
3197 if (reloc->offset > obj->size - 4) {
3198 DRM_ERROR("Relocation beyond object bounds: "
3199 "obj %p target %d offset %d size %d.\n",
3200 obj, reloc->target_handle,
3201 (int) reloc->offset, (int) obj->size);
3202 drm_gem_object_unreference(target_obj);
3203 i915_gem_object_unpin(obj);
3204 return -EINVAL;
3205 }
3206 if (reloc->offset & 3) {
3207 DRM_ERROR("Relocation not 4-byte aligned: "
3208 "obj %p target %d offset %d.\n",
3209 obj, reloc->target_handle,
3210 (int) reloc->offset);
3211 drm_gem_object_unreference(target_obj);
3212 i915_gem_object_unpin(obj);
3213 return -EINVAL;
3214 }
3215
3216 /* and points to somewhere within the target object. */
3217 if (reloc->delta >= target_obj->size) {
3218 DRM_ERROR("Relocation beyond target object bounds: "
3219 "obj %p target %d delta %d size %d.\n",
3220 obj, reloc->target_handle,
3221 (int) reloc->delta, (int) target_obj->size);
3222 drm_gem_object_unreference(target_obj);
3223 i915_gem_object_unpin(obj);
3224 return -EINVAL;
3225 }
3226
2ef7eeaa
EA		 3227 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3228 if (ret != 0) {
3229 drm_gem_object_unreference(target_obj);
3230 i915_gem_object_unpin(obj);
3231 return -EINVAL;
673a394b
EA		 3232 }
3233
3234 /* Map the page containing the relocation we're going to
3235 * perform.
3236 */
40a5f0de 3237 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3238 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3239 (reloc_offset &
3240 ~(PAGE_SIZE - 1)));
3043c60c 3241 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3242 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3243 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3244
3245#if WATCH_BUF
3246 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3247 obj, (unsigned int) reloc->offset,
673a394b
EA		 3248 readl(reloc_entry), reloc_val);
3249#endif
3250 writel(reloc_val, reloc_entry);
0839ccb8 3251 io_mapping_unmap_atomic(reloc_page);
673a394b 3252
40a5f0de
EA		 3253 /* The updated presumed offset for this entry will be
3254 * copied back out to the user.
673a394b 3255 */
40a5f0de 3256 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3257
3258 drm_gem_object_unreference(target_obj);
3259 }
3260
673a394b
EA		 3261#if WATCH_BUF
3262 if (0)
3263 i915_gem_dump_object(obj, 128, __func__, ~0);
3264#endif
3265 return 0;
3266}
3267
3268/** Dispatch a batchbuffer to the ring
3269 */
3270static int
3271i915_dispatch_gem_execbuffer(struct drm_device *dev,
3272 struct drm_i915_gem_execbuffer *exec,
201361a5 3273 struct drm_clip_rect *cliprects,
673a394b
EA		 3274 uint64_t exec_offset)
3275{
3276 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3277 int nbox = exec->num_cliprects;
3278 int i = 0, count;
83d60795 3279 uint32_t exec_start, exec_len;
673a394b
EA		 3280 RING_LOCALS;
3281
3282 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3283 exec_len = (uint32_t) exec->batch_len;
3284
673a394b
EA		 3285 count = nbox ? nbox : 1;
3286
3287 for (i = 0; i < count; i++) {
3288 if (i < nbox) {
201361a5 3289 int ret = i915_emit_box(dev, cliprects, i,
673a394b
EA		 3290 exec->DR1, exec->DR4);
3291 if (ret)
3292 return ret;
3293 }
3294
3295 if (IS_I830(dev) || IS_845G(dev)) {
3296 BEGIN_LP_RING(4);
3297 OUT_RING(MI_BATCH_BUFFER);
3298 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3299 OUT_RING(exec_start + exec_len - 4);
3300 OUT_RING(0);
3301 ADVANCE_LP_RING();
3302 } else {
3303 BEGIN_LP_RING(2);
3304 if (IS_I965G(dev)) {
3305 OUT_RING(MI_BATCH_BUFFER_START |
3306 (2 << 6) |
3307 MI_BATCH_NON_SECURE_I965);
3308 OUT_RING(exec_start);
3309 } else {
3310 OUT_RING(MI_BATCH_BUFFER_START |
3311 (2 << 6));
3312 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3313 }
3314 ADVANCE_LP_RING();
3315 }
3316 }
3317
3318 /* XXX breadcrumb */
3319 return 0;
3320}
3321
3322/* Throttle our rendering by waiting until the ring has completed our requests
3323 * emitted over 20 msec ago.
3324 *
b962442e
EA		 3325 * Note that if we were to use the current jiffies each time around the loop,
3326 * we wouldn't escape the function with any frames outstanding if the time to
3327 * render a frame was over 20ms.
3328 *
673a394b
EA		 3329 * This should get us reasonable parallelism between CPU and GPU but also
3330 * relatively low latency when blocking on a particular request to finish.
3331 */
3332static int
3333i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3334{
3335 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3336 int ret = 0;
b962442e 3337 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3338
3339 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3340 while (!list_empty(&i915_file_priv->mm.request_list)) {
3341 struct drm_i915_gem_request *request;
3342
3343 request = list_first_entry(&i915_file_priv->mm.request_list,
3344 struct drm_i915_gem_request,
3345 client_list);
3346
3347 if (time_after_eq(request->emitted_jiffies, recent_enough))
3348 break;
3349
3350 ret = i915_wait_request(dev, request->seqno);
3351 if (ret != 0)
3352 break;
3353 }
673a394b 3354 mutex_unlock(&dev->struct_mutex);
b962442e 3355
673a394b
EA		 3356 return ret;
3357}
3358
40a5f0de
EA		 3359static int
3360i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3361 uint32_t buffer_count,
3362 struct drm_i915_gem_relocation_entry **relocs)
3363{
3364 uint32_t reloc_count = 0, reloc_index = 0, i;
3365 int ret;
3366
3367 *relocs = NULL;
3368 for (i = 0; i < buffer_count; i++) {
3369 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3370 return -EINVAL;
3371 reloc_count += exec_list[i].relocation_count;
3372 }
3373
8e7d2b2c 3374 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
40a5f0de
EA		 3375 if (*relocs == NULL)
3376 return -ENOMEM;
3377
3378 for (i = 0; i < buffer_count; i++) {
3379 struct drm_i915_gem_relocation_entry __user *user_relocs;
3380
3381 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3382
3383 ret = copy_from_user(&(*relocs)[reloc_index],
3384 user_relocs,
3385 exec_list[i].relocation_count *
3386 sizeof(**relocs));
3387 if (ret != 0) {
8e7d2b2c 3388 drm_free_large(*relocs);
40a5f0de 3389 *relocs = NULL;
2bc43b5c 3390 return -EFAULT;
40a5f0de
EA		 3391 }
3392
3393 reloc_index += exec_list[i].relocation_count;
3394 }
3395
2bc43b5c 3396 return 0;
40a5f0de
EA		 3397}
3398
3399static int
3400i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3401 uint32_t buffer_count,
3402 struct drm_i915_gem_relocation_entry *relocs)
3403{
3404 uint32_t reloc_count = 0, i;
2bc43b5c 3405 int ret = 0;
40a5f0de
EA		 3406
3407 for (i = 0; i < buffer_count; i++) {
3408 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3409 int unwritten;
40a5f0de
EA		 3410
3411 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3412
2bc43b5c
FM		 3413 unwritten = copy_to_user(user_relocs,
3414 &relocs[reloc_count],
3415 exec_list[i].relocation_count *
3416 sizeof(*relocs));
3417
3418 if (unwritten) {
3419 ret = -EFAULT;
3420 goto err;
40a5f0de
EA		 3421 }
3422
3423 reloc_count += exec_list[i].relocation_count;
3424 }
3425
2bc43b5c 3426err:
8e7d2b2c 3427 drm_free_large(relocs);
40a5f0de
EA		 3428
3429 return ret;
3430}
3431
83d60795
CW		 3432static int
3433i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3434 uint64_t exec_offset)
3435{
3436 uint32_t exec_start, exec_len;
3437
3438 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3439 exec_len = (uint32_t) exec->batch_len;
3440
3441 if ((exec_start | exec_len) & 0x7)
3442 return -EINVAL;
3443
3444 if (!exec_start)
3445 return -EINVAL;
3446
3447 return 0;
3448}
3449
673a394b
EA		 3450int
3451i915_gem_execbuffer(struct drm_device *dev, void *data,
3452 struct drm_file *file_priv)
3453{
3454 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3455 struct drm_i915_gem_execbuffer *args = data;
3456 struct drm_i915_gem_exec_object *exec_list = NULL;
3457 struct drm_gem_object **object_list = NULL;
3458 struct drm_gem_object *batch_obj;
b70d11da 3459 struct drm_i915_gem_object *obj_priv;
201361a5 3460 struct drm_clip_rect *cliprects = NULL;
40a5f0de
EA		 3461 struct drm_i915_gem_relocation_entry *relocs;
3462 int ret, ret2, i, pinned = 0;
673a394b 3463 uint64_t exec_offset;
40a5f0de 3464 uint32_t seqno, flush_domains, reloc_index;
ac94a962 3465 int pin_tries;
673a394b
EA		 3466
3467#if WATCH_EXEC
3468 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3469 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3470#endif
3471
4f481ed2
EA		 3472 if (args->buffer_count < 1) {
3473 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3474 return -EINVAL;
3475 }
673a394b 3476 /* Copy in the exec list from userland */
8e7d2b2c
JB		 3477 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3478 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
673a394b
EA		 3479 if (exec_list == NULL || object_list == NULL) {
3480 DRM_ERROR("Failed to allocate exec or object list "
3481 "for %d buffers\n",
3482 args->buffer_count);
3483 ret = -ENOMEM;
3484 goto pre_mutex_err;
3485 }
3486 ret = copy_from_user(exec_list,
3487 (struct drm_i915_relocation_entry __user *)
3488 (uintptr_t) args->buffers_ptr,
3489 sizeof(*exec_list) * args->buffer_count);
3490 if (ret != 0) {
3491 DRM_ERROR("copy %d exec entries failed %d\n",
3492 args->buffer_count, ret);
3493 goto pre_mutex_err;
3494 }
3495
201361a5 3496 if (args->num_cliprects != 0) {
9a298b2a
EA		 3497 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3498 GFP_KERNEL);
201361a5
EA		 3499 if (cliprects == NULL)
3500 goto pre_mutex_err;
3501
3502 ret = copy_from_user(cliprects,
3503 (struct drm_clip_rect __user *)
3504 (uintptr_t) args->cliprects_ptr,
3505 sizeof(*cliprects) * args->num_cliprects);
3506 if (ret != 0) {
3507 DRM_ERROR("copy %d cliprects failed: %d\n",
3508 args->num_cliprects, ret);
3509 goto pre_mutex_err;
3510 }
3511 }
3512
40a5f0de
EA		 3513 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3514 &relocs);
3515 if (ret != 0)
3516 goto pre_mutex_err;
3517
673a394b
EA		 3518 mutex_lock(&dev->struct_mutex);
3519
3520 i915_verify_inactive(dev, __FILE__, __LINE__);
3521
ba1234d1 3522 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 3523 DRM_ERROR("Execbuf while wedged\n");
3524 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3525 ret = -EIO;
3526 goto pre_mutex_err;
673a394b
EA		 3527 }
3528
3529 if (dev_priv->mm.suspended) {
3530 DRM_ERROR("Execbuf while VT-switched.\n");
3531 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3532 ret = -EBUSY;
3533 goto pre_mutex_err;
673a394b
EA		 3534 }
3535
ac94a962 3536 /* Look up object handles */
673a394b
EA		 3537 for (i = 0; i < args->buffer_count; i++) {
3538 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3539 exec_list[i].handle);
3540 if (object_list[i] == NULL) {
3541 DRM_ERROR("Invalid object handle %d at index %d\n",
3542 exec_list[i].handle, i);
3543 ret = -EBADF;
3544 goto err;
3545 }
b70d11da
KH		 3546
3547 obj_priv = object_list[i]->driver_private;
3548 if (obj_priv->in_execbuffer) {
3549 DRM_ERROR("Object %p appears more than once in object list\n",
3550 object_list[i]);
3551 ret = -EBADF;
3552 goto err;
3553 }
3554 obj_priv->in_execbuffer = true;
ac94a962 3555 }
673a394b 3556
ac94a962
KP		 3557 /* Pin and relocate */
3558 for (pin_tries = 0; ; pin_tries++) {
3559 ret = 0;
40a5f0de
EA		 3560 reloc_index = 0;
3561
ac94a962
KP		 3562 for (i = 0; i < args->buffer_count; i++) {
3563 object_list[i]->pending_read_domains = 0;
3564 object_list[i]->pending_write_domain = 0;
3565 ret = i915_gem_object_pin_and_relocate(object_list[i],
3566 file_priv,
40a5f0de
EA		 3567 &exec_list[i],
3568 &relocs[reloc_index]);
ac94a962
KP		 3569 if (ret)
3570 break;
3571 pinned = i + 1;
40a5f0de 3572 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3573 }
3574 /* success */
3575 if (ret == 0)
3576 break;
3577
3578 /* error other than GTT full, or we've already tried again */
2939e1f5 3579 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3580 if (ret != -ERESTARTSYS) {
3581 unsigned long long total_size = 0;
3582 for (i = 0; i < args->buffer_count; i++)
3583 total_size += object_list[i]->size;
3584 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3585 pinned+1, args->buffer_count,
3586 total_size, ret);
3587 DRM_ERROR("%d objects [%d pinned], "
3588 "%d object bytes [%d pinned], "
3589 "%d/%d gtt bytes\n",
3590 atomic_read(&dev->object_count),
3591 atomic_read(&dev->pin_count),
3592 atomic_read(&dev->object_memory),
3593 atomic_read(&dev->pin_memory),
3594 atomic_read(&dev->gtt_memory),
3595 dev->gtt_total);
3596 }
673a394b
EA		 3597 goto err;
3598 }
ac94a962
KP		 3599
3600 /* unpin all of our buffers */
3601 for (i = 0; i < pinned; i++)
3602 i915_gem_object_unpin(object_list[i]);
b1177636 3603 pinned = 0;
ac94a962
KP		 3604
3605 /* evict everyone we can from the aperture */
3606 ret = i915_gem_evict_everything(dev);
07f73f69 3607 if (ret && ret != -ENOSPC)
ac94a962 3608 goto err;
673a394b
EA		 3609 }
3610
3611 /* Set the pending read domains for the batch buffer to COMMAND */
3612 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3613 if (batch_obj->pending_write_domain) {
3614 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3615 ret = -EINVAL;
3616 goto err;
3617 }
3618 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3619
83d60795
CW		 3620 /* Sanity check the batch buffer, prior to moving objects */
3621 exec_offset = exec_list[args->buffer_count - 1].offset;
3622 ret = i915_gem_check_execbuffer (args, exec_offset);
3623 if (ret != 0) {
3624 DRM_ERROR("execbuf with invalid offset/length\n");
3625 goto err;
3626 }
3627
673a394b
EA		 3628 i915_verify_inactive(dev, __FILE__, __LINE__);
3629
646f0f6e
KP		 3630 /* Zero the global flush/invalidate flags. These
3631 * will be modified as new domains are computed
3632 * for each object
3633 */
3634 dev->invalidate_domains = 0;
3635 dev->flush_domains = 0;
3636
673a394b
EA		 3637 for (i = 0; i < args->buffer_count; i++) {
3638 struct drm_gem_object *obj = object_list[i];
673a394b 3639
646f0f6e 3640 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3641 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3642 }
3643
3644 i915_verify_inactive(dev, __FILE__, __LINE__);
3645
646f0f6e
KP		 3646 if (dev->invalidate_domains | dev->flush_domains) {
3647#if WATCH_EXEC
3648 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3649 __func__,
3650 dev->invalidate_domains,
3651 dev->flush_domains);
3652#endif
3653 i915_gem_flush(dev,
3654 dev->invalidate_domains,
3655 dev->flush_domains);
3656 if (dev->flush_domains)
b962442e
EA		 3657 (void)i915_add_request(dev, file_priv,
3658 dev->flush_domains);
646f0f6e 3659 }
673a394b 3660
efbeed96
EA		 3661 for (i = 0; i < args->buffer_count; i++) {
3662 struct drm_gem_object *obj = object_list[i];
3663
3664 obj->write_domain = obj->pending_write_domain;
3665 }
3666
673a394b
EA		 3667 i915_verify_inactive(dev, __FILE__, __LINE__);
3668
3669#if WATCH_COHERENCY
3670 for (i = 0; i < args->buffer_count; i++) {
3671 i915_gem_object_check_coherency(object_list[i],
3672 exec_list[i].handle);
3673 }
3674#endif
3675
673a394b 3676#if WATCH_EXEC
6911a9b8 3677 i915_gem_dump_object(batch_obj,
673a394b
EA		 3678 args->batch_len,
3679 __func__,
3680 ~0);
3681#endif
3682
673a394b 3683 /* Exec the batchbuffer */
201361a5 3684 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
673a394b
EA		 3685 if (ret) {
3686 DRM_ERROR("dispatch failed %d\n", ret);
3687 goto err;
3688 }
3689
3690 /*
3691 * Ensure that the commands in the batch buffer are
3692 * finished before the interrupt fires
3693 */
3694 flush_domains = i915_retire_commands(dev);
3695
3696 i915_verify_inactive(dev, __FILE__, __LINE__);
3697
3698 /*
3699 * Get a seqno representing the execution of the current buffer,
3700 * which we can wait on. We would like to mitigate these interrupts,
3701 * likely by only creating seqnos occasionally (so that we have
3702 * *some* interrupts representing completion of buffers that we can
3703 * wait on when trying to clear up gtt space).
3704 */
b962442e 3705 seqno = i915_add_request(dev, file_priv, flush_domains);
673a394b 3706 BUG_ON(seqno == 0);
673a394b
EA		 3707 for (i = 0; i < args->buffer_count; i++) {
3708 struct drm_gem_object *obj = object_list[i];
673a394b 3709
ce44b0ea 3710 i915_gem_object_move_to_active(obj, seqno);
673a394b
EA		 3711#if WATCH_LRU
3712 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3713#endif
3714 }
3715#if WATCH_LRU
3716 i915_dump_lru(dev, __func__);
3717#endif
3718
3719 i915_verify_inactive(dev, __FILE__, __LINE__);
3720
673a394b 3721err:
aad87dff
JL		 3722 for (i = 0; i < pinned; i++)
3723 i915_gem_object_unpin(object_list[i]);
3724
b70d11da
KH		 3725 for (i = 0; i < args->buffer_count; i++) {
3726 if (object_list[i]) {
3727 obj_priv = object_list[i]->driver_private;
3728 obj_priv->in_execbuffer = false;
3729 }
aad87dff 3730 drm_gem_object_unreference(object_list[i]);
b70d11da 3731 }
673a394b 3732
673a394b
EA		 3733 mutex_unlock(&dev->struct_mutex);
3734
a35f2e2b
RD		 3735 if (!ret) {
3736 /* Copy the new buffer offsets back to the user's exec list. */
3737 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3738 (uintptr_t) args->buffers_ptr,
3739 exec_list,
3740 sizeof(*exec_list) * args->buffer_count);
2bc43b5c
FM		 3741 if (ret) {
3742 ret = -EFAULT;
a35f2e2b
RD		 3743 DRM_ERROR("failed to copy %d exec entries "
3744 "back to user (%d)\n",
3745 args->buffer_count, ret);
2bc43b5c 3746 }
a35f2e2b
RD		 3747 }
3748
40a5f0de
EA		 3749 /* Copy the updated relocations out regardless of current error
3750 * state. Failure to update the relocs would mean that the next
3751 * time userland calls execbuf, it would do so with presumed offset
3752 * state that didn't match the actual object state.
3753 */
3754 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3755 relocs);
3756 if (ret2 != 0) {
3757 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3758
3759 if (ret == 0)
3760 ret = ret2;
3761 }
3762
673a394b 3763pre_mutex_err:
8e7d2b2c
JB		 3764 drm_free_large(object_list);
3765 drm_free_large(exec_list);
9a298b2a 3766 kfree(cliprects);
673a394b
EA		 3767
3768 return ret;
3769}
3770
3771int
3772i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3773{
3774 struct drm_device *dev = obj->dev;
3775 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3776 int ret;
3777
3778 i915_verify_inactive(dev, __FILE__, __LINE__);
3779 if (obj_priv->gtt_space == NULL) {
3780 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3781 if (ret != 0) {
9bb2d6f9 3782 if (ret != -EBUSY && ret != -ERESTARTSYS)
0fce81e3 3783 DRM_ERROR("Failure to bind: %d\n", ret);
673a394b
EA		 3784 return ret;
3785 }
22c344e9
CW		 3786 }
3787 /*
3788 * Pre-965 chips need a fence register set up in order to
3789 * properly handle tiled surfaces.
3790 */
a09ba7fa 3791 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 3792 ret = i915_gem_object_get_fence_reg(obj);
22c344e9
CW		 3793 if (ret != 0) {
3794 if (ret != -EBUSY && ret != -ERESTARTSYS)
3795 DRM_ERROR("Failure to install fence: %d\n",
3796 ret);
3797 return ret;
3798 }
673a394b
EA		 3799 }
3800 obj_priv->pin_count++;
3801
3802 /* If the object is not active and not pending a flush,
3803 * remove it from the inactive list
3804 */
3805 if (obj_priv->pin_count == 1) {
3806 atomic_inc(&dev->pin_count);
3807 atomic_add(obj->size, &dev->pin_memory);
3808 if (!obj_priv->active &&
21d509e3 3809 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 3810 !list_empty(&obj_priv->list))
3811 list_del_init(&obj_priv->list);
3812 }
3813 i915_verify_inactive(dev, __FILE__, __LINE__);
3814
3815 return 0;
3816}
3817
3818void
3819i915_gem_object_unpin(struct drm_gem_object *obj)
3820{
3821 struct drm_device *dev = obj->dev;
3822 drm_i915_private_t *dev_priv = dev->dev_private;
3823 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3824
3825 i915_verify_inactive(dev, __FILE__, __LINE__);
3826 obj_priv->pin_count--;
3827 BUG_ON(obj_priv->pin_count < 0);
3828 BUG_ON(obj_priv->gtt_space == NULL);
3829
3830 /* If the object is no longer pinned, and is
3831 * neither active nor being flushed, then stick it on
3832 * the inactive list
3833 */
3834 if (obj_priv->pin_count == 0) {
3835 if (!obj_priv->active &&
21d509e3 3836 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 3837 list_move_tail(&obj_priv->list,
3838 &dev_priv->mm.inactive_list);
3839 atomic_dec(&dev->pin_count);
3840 atomic_sub(obj->size, &dev->pin_memory);
3841 }
3842 i915_verify_inactive(dev, __FILE__, __LINE__);
3843}
3844
3845int
3846i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3847 struct drm_file *file_priv)
3848{
3849 struct drm_i915_gem_pin *args = data;
3850 struct drm_gem_object *obj;
3851 struct drm_i915_gem_object *obj_priv;
3852 int ret;
3853
3854 mutex_lock(&dev->struct_mutex);
3855
3856 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3857 if (obj == NULL) {
3858 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3859 args->handle);
3860 mutex_unlock(&dev->struct_mutex);
3861 return -EBADF;
3862 }
3863 obj_priv = obj->driver_private;
3864
3ef94daa
CW		 3865 if (obj_priv->madv == I915_MADV_DONTNEED) {
3866 DRM_ERROR("Attempting to pin a I915_MADV_DONTNEED buffer\n");
3867 drm_gem_object_unreference(obj);
3868 mutex_unlock(&dev->struct_mutex);
3869 return -EINVAL;
3870 }
3871
79e53945
JB		 3872 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3873 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3874 args->handle);
96dec61d 3875 drm_gem_object_unreference(obj);
673a394b 3876 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 3877 return -EINVAL;
3878 }
3879
3880 obj_priv->user_pin_count++;
3881 obj_priv->pin_filp = file_priv;
3882 if (obj_priv->user_pin_count == 1) {
3883 ret = i915_gem_object_pin(obj, args->alignment);
3884 if (ret != 0) {
3885 drm_gem_object_unreference(obj);
3886 mutex_unlock(&dev->struct_mutex);
3887 return ret;
3888 }
673a394b
EA		 3889 }
3890
3891 /* XXX - flush the CPU caches for pinned objects
3892 * as the X server doesn't manage domains yet
3893 */
e47c68e9 3894 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 3895 args->offset = obj_priv->gtt_offset;
3896 drm_gem_object_unreference(obj);
3897 mutex_unlock(&dev->struct_mutex);
3898
3899 return 0;
3900}
3901
3902int
3903i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3904 struct drm_file *file_priv)
3905{
3906 struct drm_i915_gem_pin *args = data;
3907 struct drm_gem_object *obj;
79e53945 3908 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 3909
3910 mutex_lock(&dev->struct_mutex);
3911
3912 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3913 if (obj == NULL) {
3914 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3915 args->handle);
3916 mutex_unlock(&dev->struct_mutex);
3917 return -EBADF;
3918 }
3919
79e53945
JB		 3920 obj_priv = obj->driver_private;
3921 if (obj_priv->pin_filp != file_priv) {
3922 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3923 args->handle);
3924 drm_gem_object_unreference(obj);
3925 mutex_unlock(&dev->struct_mutex);
3926 return -EINVAL;
3927 }
3928 obj_priv->user_pin_count--;
3929 if (obj_priv->user_pin_count == 0) {
3930 obj_priv->pin_filp = NULL;
3931 i915_gem_object_unpin(obj);
3932 }
673a394b
EA		 3933
3934 drm_gem_object_unreference(obj);
3935 mutex_unlock(&dev->struct_mutex);
3936 return 0;
3937}
3938
3939int
3940i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3941 struct drm_file *file_priv)
3942{
3943 struct drm_i915_gem_busy *args = data;
3944 struct drm_gem_object *obj;
3945 struct drm_i915_gem_object *obj_priv;
3946
673a394b
EA		 3947 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3948 if (obj == NULL) {
3949 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3950 args->handle);
673a394b
EA		 3951 return -EBADF;
3952 }
3953
b1ce786c 3954 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 3955 /* Update the active list for the hardware's current position.
3956 * Otherwise this only updates on a delayed timer or when irqs are
3957 * actually unmasked, and our working set ends up being larger than
3958 * required.
3959 */
3960 i915_gem_retire_requests(dev);
3961
673a394b 3962 obj_priv = obj->driver_private;
c4de0a5d
EA		 3963 /* Don't count being on the flushing list against the object being
3964 * done. Otherwise, a buffer left on the flushing list but not getting
3965 * flushed (because nobody's flushing that domain) won't ever return
3966 * unbusy and get reused by libdrm's bo cache. The other expected
3967 * consumer of this interface, OpenGL's occlusion queries, also specs
3968 * that the objects get unbusy "eventually" without any interference.
3969 */
3970 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 3971
3972 drm_gem_object_unreference(obj);
3973 mutex_unlock(&dev->struct_mutex);
3974 return 0;
3975}
3976
3977int
3978i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3979 struct drm_file *file_priv)
3980{
3981 return i915_gem_ring_throttle(dev, file_priv);
3982}
3983
3ef94daa
CW		 3984int
3985i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3986 struct drm_file *file_priv)
3987{
3988 struct drm_i915_gem_madvise *args = data;
3989 struct drm_gem_object *obj;
3990 struct drm_i915_gem_object *obj_priv;
3991
3992 switch (args->madv) {
3993 case I915_MADV_DONTNEED:
3994 case I915_MADV_WILLNEED:
3995 break;
3996 default:
3997 return -EINVAL;
3998 }
3999
4000 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4001 if (obj == NULL) {
4002 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4003 args->handle);
4004 return -EBADF;
4005 }
4006
4007 mutex_lock(&dev->struct_mutex);
4008 obj_priv = obj->driver_private;
4009
4010 if (obj_priv->pin_count) {
4011 drm_gem_object_unreference(obj);
4012 mutex_unlock(&dev->struct_mutex);
4013
4014 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4015 return -EINVAL;
4016 }
4017
4018 obj_priv->madv = args->madv;
4019 args->retained = obj_priv->gtt_space != NULL;
4020
4021 drm_gem_object_unreference(obj);
4022 mutex_unlock(&dev->struct_mutex);
4023
4024 return 0;
4025}
4026
673a394b
EA		 4027int i915_gem_init_object(struct drm_gem_object *obj)
4028{
4029 struct drm_i915_gem_object *obj_priv;
4030
9a298b2a 4031 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
673a394b
EA		 4032 if (obj_priv == NULL)
4033 return -ENOMEM;
4034
4035 /*
4036 * We've just allocated pages from the kernel,
4037 * so they've just been written by the CPU with
4038 * zeros. They'll need to be clflushed before we
4039 * use them with the GPU.
4040 */
4041 obj->write_domain = I915_GEM_DOMAIN_CPU;
4042 obj->read_domains = I915_GEM_DOMAIN_CPU;
4043
ba1eb1d8
KP		 4044 obj_priv->agp_type = AGP_USER_MEMORY;
4045
673a394b
EA		 4046 obj->driver_private = obj_priv;
4047 obj_priv->obj = obj;
de151cf6 4048 obj_priv->fence_reg = I915_FENCE_REG_NONE;
673a394b 4049 INIT_LIST_HEAD(&obj_priv->list);
a09ba7fa 4050 INIT_LIST_HEAD(&obj_priv->fence_list);
3ef94daa 4051 obj_priv->madv = I915_MADV_WILLNEED;
de151cf6 4052
673a394b
EA		 4053 return 0;
4054}
4055
4056void i915_gem_free_object(struct drm_gem_object *obj)
4057{
de151cf6 4058 struct drm_device *dev = obj->dev;
673a394b
EA		 4059 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4060
4061 while (obj_priv->pin_count > 0)
4062 i915_gem_object_unpin(obj);
4063
71acb5eb
DA		 4064 if (obj_priv->phys_obj)
4065 i915_gem_detach_phys_object(dev, obj);
4066
673a394b
EA		 4067 i915_gem_object_unbind(obj);
4068
7e616158
CW		 4069 if (obj_priv->mmap_offset)
4070 i915_gem_free_mmap_offset(obj);
de151cf6 4071
9a298b2a 4072 kfree(obj_priv->page_cpu_valid);
280b713b 4073 kfree(obj_priv->bit_17);
9a298b2a 4074 kfree(obj->driver_private);
673a394b
EA		 4075}
4076
673a394b
EA		 4077/** Unbinds all objects that are on the given buffer list. */
4078static int
4079i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
4080{
4081 struct drm_gem_object *obj;
4082 struct drm_i915_gem_object *obj_priv;
4083 int ret;
4084
4085 while (!list_empty(head)) {
4086 obj_priv = list_first_entry(head,
4087 struct drm_i915_gem_object,
4088 list);
4089 obj = obj_priv->obj;
4090
4091 if (obj_priv->pin_count != 0) {
4092 DRM_ERROR("Pinned object in unbind list\n");
4093 mutex_unlock(&dev->struct_mutex);
4094 return -EINVAL;
4095 }
4096
4097 ret = i915_gem_object_unbind(obj);
4098 if (ret != 0) {
4099 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
4100 ret);
4101 mutex_unlock(&dev->struct_mutex);
4102 return ret;
4103 }
4104 }
4105
4106
4107 return 0;
4108}
4109
5669fcac 4110int
673a394b
EA		 4111i915_gem_idle(struct drm_device *dev)
4112{
4113 drm_i915_private_t *dev_priv = dev->dev_private;
4114 uint32_t seqno, cur_seqno, last_seqno;
4115 int stuck, ret;
4116
6dbe2772
KP		 4117 mutex_lock(&dev->struct_mutex);
4118
4119 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4120 mutex_unlock(&dev->struct_mutex);
673a394b 4121 return 0;
6dbe2772 4122 }
673a394b
EA		 4123
4124 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4125 * We need to replace this with a semaphore, or something.
4126 */
4127 dev_priv->mm.suspended = 1;
f65d9421 4128 del_timer(&dev_priv->hangcheck_timer);
673a394b 4129
6dbe2772
KP		 4130 /* Cancel the retire work handler, wait for it to finish if running
4131 */
4132 mutex_unlock(&dev->struct_mutex);
4133 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4134 mutex_lock(&dev->struct_mutex);
4135
673a394b
EA		 4136 i915_kernel_lost_context(dev);
4137
4138 /* Flush the GPU along with all non-CPU write domains
4139 */
21d509e3
CW		 4140 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4141 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
673a394b
EA		 4142
4143 if (seqno == 0) {
4144 mutex_unlock(&dev->struct_mutex);
4145 return -ENOMEM;
4146 }
4147
4148 dev_priv->mm.waiting_gem_seqno = seqno;
4149 last_seqno = 0;
4150 stuck = 0;
4151 for (;;) {
4152 cur_seqno = i915_get_gem_seqno(dev);
4153 if (i915_seqno_passed(cur_seqno, seqno))
4154 break;
4155 if (last_seqno == cur_seqno) {
4156 if (stuck++ > 100) {
4157 DRM_ERROR("hardware wedged\n");
ba1234d1 4158 atomic_set(&dev_priv->mm.wedged, 1);
673a394b
EA		 4159 DRM_WAKEUP(&dev_priv->irq_queue);
4160 break;
4161 }
4162 }
4163 msleep(10);
4164 last_seqno = cur_seqno;
4165 }
4166 dev_priv->mm.waiting_gem_seqno = 0;
4167
4168 i915_gem_retire_requests(dev);
4169
5e118f41 4170 spin_lock(&dev_priv->mm.active_list_lock);
ba1234d1 4171 if (!atomic_read(&dev_priv->mm.wedged)) {
28dfe52a
EA		 4172 /* Active and flushing should now be empty as we've
4173 * waited for a sequence higher than any pending execbuffer
4174 */
4175 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4176 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4177 /* Request should now be empty as we've also waited
4178 * for the last request in the list
4179 */
4180 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4181 }
673a394b 4182
28dfe52a
EA		 4183 /* Empty the active and flushing lists to inactive. If there's
4184 * anything left at this point, it means that we're wedged and
4185 * nothing good's going to happen by leaving them there. So strip
4186 * the GPU domains and just stuff them onto inactive.
673a394b 4187 */
28dfe52a
EA		 4188 while (!list_empty(&dev_priv->mm.active_list)) {
4189 struct drm_i915_gem_object *obj_priv;
673a394b 4190
28dfe52a
EA		 4191 obj_priv = list_first_entry(&dev_priv->mm.active_list,
4192 struct drm_i915_gem_object,
4193 list);
4194 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4195 i915_gem_object_move_to_inactive(obj_priv->obj);
4196 }
5e118f41 4197 spin_unlock(&dev_priv->mm.active_list_lock);
28dfe52a
EA		 4198
4199 while (!list_empty(&dev_priv->mm.flushing_list)) {
4200 struct drm_i915_gem_object *obj_priv;
4201
151903d5 4202 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
28dfe52a
EA		 4203 struct drm_i915_gem_object,
4204 list);
4205 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4206 i915_gem_object_move_to_inactive(obj_priv->obj);
4207 }
4208
4209
4210 /* Move all inactive buffers out of the GTT. */
673a394b 4211 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
28dfe52a 4212 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
6dbe2772
KP		 4213 if (ret) {
4214 mutex_unlock(&dev->struct_mutex);
673a394b 4215 return ret;
6dbe2772 4216 }
673a394b 4217
6dbe2772
KP		 4218 i915_gem_cleanup_ringbuffer(dev);
4219 mutex_unlock(&dev->struct_mutex);
4220
673a394b
EA		 4221 return 0;
4222}
4223
4224static int
4225i915_gem_init_hws(struct drm_device *dev)
4226{
4227 drm_i915_private_t *dev_priv = dev->dev_private;
4228 struct drm_gem_object *obj;
4229 struct drm_i915_gem_object *obj_priv;
4230 int ret;
4231
4232 /* If we need a physical address for the status page, it's already
4233 * initialized at driver load time.
4234 */
4235 if (!I915_NEED_GFX_HWS(dev))
4236 return 0;
4237
4238 obj = drm_gem_object_alloc(dev, 4096);
4239 if (obj == NULL) {
4240 DRM_ERROR("Failed to allocate status page\n");
4241 return -ENOMEM;
4242 }
4243 obj_priv = obj->driver_private;
ba1eb1d8 4244 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
673a394b
EA		 4245
4246 ret = i915_gem_object_pin(obj, 4096);
4247 if (ret != 0) {
4248 drm_gem_object_unreference(obj);
4249 return ret;
4250 }
4251
4252 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
673a394b 4253
856fa198 4254 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
ba1eb1d8 4255 if (dev_priv->hw_status_page == NULL) {
673a394b
EA		 4256 DRM_ERROR("Failed to map status page.\n");
4257 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3eb2ee77 4258 i915_gem_object_unpin(obj);
673a394b
EA		 4259 drm_gem_object_unreference(obj);
4260 return -EINVAL;
4261 }
4262 dev_priv->hws_obj = obj;
673a394b
EA		 4263 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4264 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
ba1eb1d8 4265 I915_READ(HWS_PGA); /* posting read */
673a394b
EA		 4266 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4267
4268 return 0;
4269}
4270
85a7bb98
CW		 4271static void
4272i915_gem_cleanup_hws(struct drm_device *dev)
4273{
4274 drm_i915_private_t *dev_priv = dev->dev_private;
bab2d1f6
CW		 4275 struct drm_gem_object *obj;
4276 struct drm_i915_gem_object *obj_priv;
85a7bb98
CW		 4277
4278 if (dev_priv->hws_obj == NULL)
4279 return;
4280
bab2d1f6
CW		 4281 obj = dev_priv->hws_obj;
4282 obj_priv = obj->driver_private;
4283
856fa198 4284 kunmap(obj_priv->pages[0]);
85a7bb98
CW		 4285 i915_gem_object_unpin(obj);
4286 drm_gem_object_unreference(obj);
4287 dev_priv->hws_obj = NULL;
bab2d1f6 4288
85a7bb98
CW		 4289 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4290 dev_priv->hw_status_page = NULL;
4291
4292 /* Write high address into HWS_PGA when disabling. */
4293 I915_WRITE(HWS_PGA, 0x1ffff000);
4294}
4295
79e53945 4296int
673a394b
EA		 4297i915_gem_init_ringbuffer(struct drm_device *dev)
4298{
4299 drm_i915_private_t *dev_priv = dev->dev_private;
4300 struct drm_gem_object *obj;
4301 struct drm_i915_gem_object *obj_priv;
79e53945 4302 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
673a394b 4303 int ret;
50aa253d 4304 u32 head;
673a394b
EA		 4305
4306 ret = i915_gem_init_hws(dev);
4307 if (ret != 0)
4308 return ret;
4309
4310 obj = drm_gem_object_alloc(dev, 128 * 1024);
4311 if (obj == NULL) {
4312 DRM_ERROR("Failed to allocate ringbuffer\n");
85a7bb98 4313 i915_gem_cleanup_hws(dev);
673a394b
EA		 4314 return -ENOMEM;
4315 }
4316 obj_priv = obj->driver_private;
4317
4318 ret = i915_gem_object_pin(obj, 4096);
4319 if (ret != 0) {
4320 drm_gem_object_unreference(obj);
85a7bb98 4321 i915_gem_cleanup_hws(dev);
673a394b
EA		 4322 return ret;
4323 }
4324
4325 /* Set up the kernel mapping for the ring. */
79e53945 4326 ring->Size = obj->size;
673a394b 4327
79e53945
JB		 4328 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4329 ring->map.size = obj->size;
4330 ring->map.type = 0;
4331 ring->map.flags = 0;
4332 ring->map.mtrr = 0;
673a394b 4333
79e53945
JB		 4334 drm_core_ioremap_wc(&ring->map, dev);
4335 if (ring->map.handle == NULL) {
673a394b
EA		 4336 DRM_ERROR("Failed to map ringbuffer.\n");
4337 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
47ed185a 4338 i915_gem_object_unpin(obj);
673a394b 4339 drm_gem_object_unreference(obj);
85a7bb98 4340 i915_gem_cleanup_hws(dev);
673a394b
EA		 4341 return -EINVAL;
4342 }
79e53945
JB		 4343 ring->ring_obj = obj;
4344 ring->virtual_start = ring->map.handle;
673a394b
EA		 4345
4346 /* Stop the ring if it's running. */
4347 I915_WRITE(PRB0_CTL, 0);
673a394b 4348 I915_WRITE(PRB0_TAIL, 0);
50aa253d 4349 I915_WRITE(PRB0_HEAD, 0);
673a394b
EA		 4350
4351 /* Initialize the ring. */
4352 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
50aa253d
KP		 4353 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4354
4355 /* G45 ring initialization fails to reset head to zero */
4356 if (head != 0) {
4357 DRM_ERROR("Ring head not reset to zero "
4358 "ctl %08x head %08x tail %08x start %08x\n",
4359 I915_READ(PRB0_CTL),
4360 I915_READ(PRB0_HEAD),
4361 I915_READ(PRB0_TAIL),
4362 I915_READ(PRB0_START));
4363 I915_WRITE(PRB0_HEAD, 0);
4364
4365 DRM_ERROR("Ring head forced to zero "
4366 "ctl %08x head %08x tail %08x start %08x\n",
4367 I915_READ(PRB0_CTL),
4368 I915_READ(PRB0_HEAD),
4369 I915_READ(PRB0_TAIL),
4370 I915_READ(PRB0_START));
4371 }
4372
673a394b
EA		 4373 I915_WRITE(PRB0_CTL,
4374 ((obj->size - 4096) & RING_NR_PAGES) |
4375 RING_NO_REPORT |
4376 RING_VALID);
4377
50aa253d
KP		 4378 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4379
4380 /* If the head is still not zero, the ring is dead */
4381 if (head != 0) {
4382 DRM_ERROR("Ring initialization failed "
4383 "ctl %08x head %08x tail %08x start %08x\n",
4384 I915_READ(PRB0_CTL),
4385 I915_READ(PRB0_HEAD),
4386 I915_READ(PRB0_TAIL),
4387 I915_READ(PRB0_START));
4388 return -EIO;
4389 }
4390
673a394b 4391 /* Update our cache of the ring state */
79e53945
JB		 4392 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4393 i915_kernel_lost_context(dev);
4394 else {
4395 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4396 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4397 ring->space = ring->head - (ring->tail + 8);
4398 if (ring->space < 0)
4399 ring->space += ring->Size;
4400 }
673a394b
EA		 4401
4402 return 0;
4403}
4404
79e53945 4405void
673a394b
EA		 4406i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4407{
4408 drm_i915_private_t *dev_priv = dev->dev_private;
4409
4410 if (dev_priv->ring.ring_obj == NULL)
4411 return;
4412
4413 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4414
4415 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4416 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4417 dev_priv->ring.ring_obj = NULL;
4418 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4419
85a7bb98 4420 i915_gem_cleanup_hws(dev);
673a394b
EA		 4421}
4422
4423int
4424i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4425 struct drm_file *file_priv)
4426{
4427 drm_i915_private_t *dev_priv = dev->dev_private;
4428 int ret;
4429
79e53945
JB		 4430 if (drm_core_check_feature(dev, DRIVER_MODESET))
4431 return 0;
4432
ba1234d1 4433 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4434 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4435 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4436 }
4437
673a394b 4438 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4439 dev_priv->mm.suspended = 0;
4440
4441 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4442 if (ret != 0) {
4443 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4444 return ret;
d816f6ac 4445 }
9bb2d6f9 4446
5e118f41 4447 spin_lock(&dev_priv->mm.active_list_lock);
673a394b 4448 BUG_ON(!list_empty(&dev_priv->mm.active_list));
5e118f41
CW		 4449 spin_unlock(&dev_priv->mm.active_list_lock);
4450
673a394b
EA		 4451 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4452 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4453 BUG_ON(!list_empty(&dev_priv->mm.request_list));
673a394b 4454 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4455
4456 drm_irq_install(dev);
4457
673a394b
EA		 4458 return 0;
4459}
4460
4461int
4462i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4463 struct drm_file *file_priv)
4464{
4465 int ret;
4466
79e53945
JB		 4467 if (drm_core_check_feature(dev, DRIVER_MODESET))
4468 return 0;
4469
673a394b 4470 ret = i915_gem_idle(dev);
dbb19d30
KH		 4471 drm_irq_uninstall(dev);
4472
6dbe2772 4473 return ret;
673a394b
EA		 4474}
4475
4476void
4477i915_gem_lastclose(struct drm_device *dev)
4478{
4479 int ret;
673a394b 4480
e806b495
EA		 4481 if (drm_core_check_feature(dev, DRIVER_MODESET))
4482 return;
4483
6dbe2772
KP		 4484 ret = i915_gem_idle(dev);
4485 if (ret)
4486 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4487}
4488
4489void
4490i915_gem_load(struct drm_device *dev)
4491{
b5aa8a0f 4492 int i;
673a394b
EA		 4493 drm_i915_private_t *dev_priv = dev->dev_private;
4494
5e118f41 4495 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b
EA		 4496 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4497 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4498 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4499 INIT_LIST_HEAD(&dev_priv->mm.request_list);
a09ba7fa 4500 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
673a394b
EA		 4501 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4502 i915_gem_retire_work_handler);
4503 dev_priv->mm.next_gem_seqno = 1;
4504
31169714
CW		 4505 spin_lock(&shrink_list_lock);
4506 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4507 spin_unlock(&shrink_list_lock);
4508
de151cf6
JB		 4509 /* Old X drivers will take 0-2 for front, back, depth buffers */
4510 dev_priv->fence_reg_start = 3;
4511
0f973f27 4512 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4513 dev_priv->num_fence_regs = 16;
4514 else
4515 dev_priv->num_fence_regs = 8;
4516
b5aa8a0f
GH		 4517 /* Initialize fence registers to zero */
4518 if (IS_I965G(dev)) {
4519 for (i = 0; i < 16; i++)
4520 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4521 } else {
4522 for (i = 0; i < 8; i++)
4523 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4524 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4525 for (i = 0; i < 8; i++)
4526 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4527 }
4528
673a394b
EA		 4529 i915_gem_detect_bit_6_swizzle(dev);
4530}
71acb5eb
DA		 4531
4532/*
4533 * Create a physically contiguous memory object for this object
4534 * e.g. for cursor + overlay regs
4535 */
4536int i915_gem_init_phys_object(struct drm_device *dev,
4537 int id, int size)
4538{
4539 drm_i915_private_t *dev_priv = dev->dev_private;
4540 struct drm_i915_gem_phys_object *phys_obj;
4541 int ret;
4542
4543 if (dev_priv->mm.phys_objs[id - 1] || !size)
4544 return 0;
4545
9a298b2a 4546 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4547 if (!phys_obj)
4548 return -ENOMEM;
4549
4550 phys_obj->id = id;
4551
4552 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4553 if (!phys_obj->handle) {
4554 ret = -ENOMEM;
4555 goto kfree_obj;
4556 }
4557#ifdef CONFIG_X86
4558 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4559#endif
4560
4561 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4562
4563 return 0;
4564kfree_obj:
9a298b2a 4565 kfree(phys_obj);
71acb5eb
DA		 4566 return ret;
4567}
4568
4569void i915_gem_free_phys_object(struct drm_device *dev, int id)
4570{
4571 drm_i915_private_t *dev_priv = dev->dev_private;
4572 struct drm_i915_gem_phys_object *phys_obj;
4573
4574 if (!dev_priv->mm.phys_objs[id - 1])
4575 return;
4576
4577 phys_obj = dev_priv->mm.phys_objs[id - 1];
4578 if (phys_obj->cur_obj) {
4579 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4580 }
4581
4582#ifdef CONFIG_X86
4583 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4584#endif
4585 drm_pci_free(dev, phys_obj->handle);
4586 kfree(phys_obj);
4587 dev_priv->mm.phys_objs[id - 1] = NULL;
4588}
4589
4590void i915_gem_free_all_phys_object(struct drm_device *dev)
4591{
4592 int i;
4593
260883c8 4594 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4595 i915_gem_free_phys_object(dev, i);
4596}
4597
4598void i915_gem_detach_phys_object(struct drm_device *dev,
4599 struct drm_gem_object *obj)
4600{
4601 struct drm_i915_gem_object *obj_priv;
4602 int i;
4603 int ret;
4604 int page_count;
4605
4606 obj_priv = obj->driver_private;
4607 if (!obj_priv->phys_obj)
4608 return;
4609
856fa198 4610 ret = i915_gem_object_get_pages(obj);
71acb5eb
DA		 4611 if (ret)
4612 goto out;
4613
4614 page_count = obj->size / PAGE_SIZE;
4615
4616 for (i = 0; i < page_count; i++) {
856fa198 4617 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4618 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4619
4620 memcpy(dst, src, PAGE_SIZE);
4621 kunmap_atomic(dst, KM_USER0);
4622 }
856fa198 4623 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4624 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4625
4626 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4627out:
4628 obj_priv->phys_obj->cur_obj = NULL;
4629 obj_priv->phys_obj = NULL;
4630}
4631
4632int
4633i915_gem_attach_phys_object(struct drm_device *dev,
4634 struct drm_gem_object *obj, int id)
4635{
4636 drm_i915_private_t *dev_priv = dev->dev_private;
4637 struct drm_i915_gem_object *obj_priv;
4638 int ret = 0;
4639 int page_count;
4640 int i;
4641
4642 if (id > I915_MAX_PHYS_OBJECT)
4643 return -EINVAL;
4644
4645 obj_priv = obj->driver_private;
4646
4647 if (obj_priv->phys_obj) {
4648 if (obj_priv->phys_obj->id == id)
4649 return 0;
4650 i915_gem_detach_phys_object(dev, obj);
4651 }
4652
4653
4654 /* create a new object */
4655 if (!dev_priv->mm.phys_objs[id - 1]) {
4656 ret = i915_gem_init_phys_object(dev, id,
4657 obj->size);
4658 if (ret) {
aeb565df 4659 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4660 goto out;
4661 }
4662 }
4663
4664 /* bind to the object */
4665 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4666 obj_priv->phys_obj->cur_obj = obj;
4667
856fa198 4668 ret = i915_gem_object_get_pages(obj);
71acb5eb
DA		 4669 if (ret) {
4670 DRM_ERROR("failed to get page list\n");
4671 goto out;
4672 }
4673
4674 page_count = obj->size / PAGE_SIZE;
4675
4676 for (i = 0; i < page_count; i++) {
856fa198 4677 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4678 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4679
4680 memcpy(dst, src, PAGE_SIZE);
4681 kunmap_atomic(src, KM_USER0);
4682 }
4683
d78b47b9
CW		 4684 i915_gem_object_put_pages(obj);
4685
71acb5eb
DA		 4686 return 0;
4687out:
4688 return ret;
4689}
4690
4691static int
4692i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4693 struct drm_i915_gem_pwrite *args,
4694 struct drm_file *file_priv)
4695{
4696 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4697 void *obj_addr;
4698 int ret;
4699 char __user *user_data;
4700
4701 user_data = (char __user *) (uintptr_t) args->data_ptr;
4702 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4703
e08fb4f6 4704 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4705 ret = copy_from_user(obj_addr, user_data, args->size);
4706 if (ret)
4707 return -EFAULT;
4708
4709 drm_agp_chipset_flush(dev);
4710 return 0;
4711}
b962442e
EA		 4712
4713void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4714{
4715 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4716
4717 /* Clean up our request list when the client is going away, so that
4718 * later retire_requests won't dereference our soon-to-be-gone
4719 * file_priv.
4720 */
4721 mutex_lock(&dev->struct_mutex);
4722 while (!list_empty(&i915_file_priv->mm.request_list))
4723 list_del_init(i915_file_priv->mm.request_list.next);
4724 mutex_unlock(&dev->struct_mutex);
4725}
31169714
CW		 4726
4727/* Immediately discard the backing storage */
4728static void
4729i915_gem_object_truncate(struct drm_gem_object *obj)
4730{
4731 struct inode *inode;
4732
4733 inode = obj->filp->f_path.dentry->d_inode;
4734
4735 mutex_lock(&inode->i_mutex);
4736 truncate_inode_pages(inode->i_mapping, 0);
4737 mutex_unlock(&inode->i_mutex);
4738}
4739
31169714
CW		 4740static int
4741i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4742{
4743 drm_i915_private_t *dev_priv, *next_dev;
4744 struct drm_i915_gem_object *obj_priv, *next_obj;
4745 int cnt = 0;
4746 int would_deadlock = 1;
4747
4748 /* "fast-path" to count number of available objects */
4749 if (nr_to_scan == 0) {
4750 spin_lock(&shrink_list_lock);
4751 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4752 struct drm_device *dev = dev_priv->dev;
4753
4754 if (mutex_trylock(&dev->struct_mutex)) {
4755 list_for_each_entry(obj_priv,
4756 &dev_priv->mm.inactive_list,
4757 list)
4758 cnt++;
4759 mutex_unlock(&dev->struct_mutex);
4760 }
4761 }
4762 spin_unlock(&shrink_list_lock);
4763
4764 return (cnt / 100) * sysctl_vfs_cache_pressure;
4765 }
4766
4767 spin_lock(&shrink_list_lock);
4768
4769 /* first scan for clean buffers */
4770 list_for_each_entry_safe(dev_priv, next_dev,
4771 &shrink_list, mm.shrink_list) {
4772 struct drm_device *dev = dev_priv->dev;
4773
4774 if (! mutex_trylock(&dev->struct_mutex))
4775 continue;
4776
4777 spin_unlock(&shrink_list_lock);
4778
4779 i915_gem_retire_requests(dev);
4780
4781 list_for_each_entry_safe(obj_priv, next_obj,
4782 &dev_priv->mm.inactive_list,
4783 list) {
4784 if (i915_gem_object_is_purgeable(obj_priv)) {
4785 struct drm_gem_object *obj = obj_priv->obj;
4786 i915_gem_object_unbind(obj);
4787 i915_gem_object_truncate(obj);
4788
4789 if (--nr_to_scan <= 0)
4790 break;
4791 }
4792 }
4793
4794 spin_lock(&shrink_list_lock);
4795 mutex_unlock(&dev->struct_mutex);
4796
4797 if (nr_to_scan <= 0)
4798 break;
4799 }
4800
4801 /* second pass, evict/count anything still on the inactive list */
4802 list_for_each_entry_safe(dev_priv, next_dev,
4803 &shrink_list, mm.shrink_list) {
4804 struct drm_device *dev = dev_priv->dev;
4805
4806 if (! mutex_trylock(&dev->struct_mutex))
4807 continue;
4808
4809 spin_unlock(&shrink_list_lock);
4810
4811 list_for_each_entry_safe(obj_priv, next_obj,
4812 &dev_priv->mm.inactive_list,
4813 list) {
4814 if (nr_to_scan > 0) {
4815 struct drm_gem_object *obj = obj_priv->obj;
4816 i915_gem_object_unbind(obj);
4817 if (i915_gem_object_is_purgeable(obj_priv))
4818 i915_gem_object_truncate(obj);
4819
4820 nr_to_scan--;
4821 } else
4822 cnt++;
4823 }
4824
4825 spin_lock(&shrink_list_lock);
4826 mutex_unlock(&dev->struct_mutex);
4827
4828 would_deadlock = 0;
4829 }
4830
4831 spin_unlock(&shrink_list_lock);
4832
4833 if (would_deadlock)
4834 return -1;
4835 else if (cnt > 0)
4836 return (cnt / 100) * sysctl_vfs_cache_pressure;
4837 else
4838 return 0;
4839}
4840
4841static struct shrinker shrinker = {
4842 .shrink = i915_gem_shrink,
4843 .seeks = DEFAULT_SEEKS,
4844};
4845
4846__init void
4847i915_gem_shrinker_init(void)
4848{
4849 register_shrinker(&shrinker);
4850}
4851
4852__exit void
4853i915_gem_shrinker_exit(void)
4854{
4855 unregister_shrinker(&shrinker);
4856}
Clone of davem's net-next-2.6 tree