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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
673a394b | 37 | |
e47c68e9 EA |
38 | static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); | |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
41 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
42 | int write); | |
43 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
44 | uint64_t offset, | |
45 | uint64_t size); | |
46 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
673a394b | 47 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
de151cf6 JB |
48 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
49 | unsigned alignment); | |
de151cf6 | 50 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
07f73f69 | 51 | static int i915_gem_evict_something(struct drm_device *dev, int min_size); |
ab5ee576 | 52 | static int i915_gem_evict_from_inactive_list(struct drm_device *dev); |
71acb5eb DA |
53 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
54 | struct drm_i915_gem_pwrite *args, | |
55 | struct drm_file *file_priv); | |
673a394b | 56 | |
31169714 CW |
57 | static LIST_HEAD(shrink_list); |
58 | static DEFINE_SPINLOCK(shrink_list_lock); | |
59 | ||
79e53945 JB |
60 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
61 | unsigned long end) | |
673a394b EA |
62 | { |
63 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 64 | |
79e53945 JB |
65 | if (start >= end || |
66 | (start & (PAGE_SIZE - 1)) != 0 || | |
67 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
68 | return -EINVAL; |
69 | } | |
70 | ||
79e53945 JB |
71 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
72 | end - start); | |
673a394b | 73 | |
79e53945 JB |
74 | dev->gtt_total = (uint32_t) (end - start); |
75 | ||
76 | return 0; | |
77 | } | |
673a394b | 78 | |
79e53945 JB |
79 | int |
80 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
81 | struct drm_file *file_priv) | |
82 | { | |
83 | struct drm_i915_gem_init *args = data; | |
84 | int ret; | |
85 | ||
86 | mutex_lock(&dev->struct_mutex); | |
87 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
88 | mutex_unlock(&dev->struct_mutex); |
89 | ||
79e53945 | 90 | return ret; |
673a394b EA |
91 | } |
92 | ||
5a125c3c EA |
93 | int |
94 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
95 | struct drm_file *file_priv) | |
96 | { | |
5a125c3c | 97 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
98 | |
99 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
100 | return -ENODEV; | |
101 | ||
102 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
103 | args->aper_available_size = (args->aper_size - |
104 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
105 | |
106 | return 0; | |
107 | } | |
108 | ||
673a394b EA |
109 | |
110 | /** | |
111 | * Creates a new mm object and returns a handle to it. | |
112 | */ | |
113 | int | |
114 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
115 | struct drm_file *file_priv) | |
116 | { | |
117 | struct drm_i915_gem_create *args = data; | |
118 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
119 | int ret; |
120 | u32 handle; | |
673a394b EA |
121 | |
122 | args->size = roundup(args->size, PAGE_SIZE); | |
123 | ||
124 | /* Allocate the new object */ | |
ac52bc56 | 125 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
126 | if (obj == NULL) |
127 | return -ENOMEM; | |
128 | ||
129 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
bc9025bd | 130 | drm_gem_object_handle_unreference_unlocked(obj); |
673a394b EA |
131 | |
132 | if (ret) | |
133 | return ret; | |
134 | ||
135 | args->handle = handle; | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
eb01459f EA |
140 | static inline int |
141 | fast_shmem_read(struct page **pages, | |
142 | loff_t page_base, int page_offset, | |
143 | char __user *data, | |
144 | int length) | |
145 | { | |
146 | char __iomem *vaddr; | |
2bc43b5c | 147 | int unwritten; |
eb01459f EA |
148 | |
149 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
150 | if (vaddr == NULL) | |
151 | return -ENOMEM; | |
2bc43b5c | 152 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
153 | kunmap_atomic(vaddr, KM_USER0); |
154 | ||
2bc43b5c FM |
155 | if (unwritten) |
156 | return -EFAULT; | |
157 | ||
158 | return 0; | |
eb01459f EA |
159 | } |
160 | ||
280b713b EA |
161 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
162 | { | |
163 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 164 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
165 | |
166 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
167 | obj_priv->tiling_mode != I915_TILING_NONE; | |
168 | } | |
169 | ||
40123c1f EA |
170 | static inline int |
171 | slow_shmem_copy(struct page *dst_page, | |
172 | int dst_offset, | |
173 | struct page *src_page, | |
174 | int src_offset, | |
175 | int length) | |
176 | { | |
177 | char *dst_vaddr, *src_vaddr; | |
178 | ||
179 | dst_vaddr = kmap_atomic(dst_page, KM_USER0); | |
180 | if (dst_vaddr == NULL) | |
181 | return -ENOMEM; | |
182 | ||
183 | src_vaddr = kmap_atomic(src_page, KM_USER1); | |
184 | if (src_vaddr == NULL) { | |
185 | kunmap_atomic(dst_vaddr, KM_USER0); | |
186 | return -ENOMEM; | |
187 | } | |
188 | ||
189 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
190 | ||
191 | kunmap_atomic(src_vaddr, KM_USER1); | |
192 | kunmap_atomic(dst_vaddr, KM_USER0); | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
280b713b EA |
197 | static inline int |
198 | slow_shmem_bit17_copy(struct page *gpu_page, | |
199 | int gpu_offset, | |
200 | struct page *cpu_page, | |
201 | int cpu_offset, | |
202 | int length, | |
203 | int is_read) | |
204 | { | |
205 | char *gpu_vaddr, *cpu_vaddr; | |
206 | ||
207 | /* Use the unswizzled path if this page isn't affected. */ | |
208 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
209 | if (is_read) | |
210 | return slow_shmem_copy(cpu_page, cpu_offset, | |
211 | gpu_page, gpu_offset, length); | |
212 | else | |
213 | return slow_shmem_copy(gpu_page, gpu_offset, | |
214 | cpu_page, cpu_offset, length); | |
215 | } | |
216 | ||
217 | gpu_vaddr = kmap_atomic(gpu_page, KM_USER0); | |
218 | if (gpu_vaddr == NULL) | |
219 | return -ENOMEM; | |
220 | ||
221 | cpu_vaddr = kmap_atomic(cpu_page, KM_USER1); | |
222 | if (cpu_vaddr == NULL) { | |
223 | kunmap_atomic(gpu_vaddr, KM_USER0); | |
224 | return -ENOMEM; | |
225 | } | |
226 | ||
227 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
228 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
229 | */ | |
230 | while (length > 0) { | |
231 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
232 | int this_length = min(cacheline_end - gpu_offset, length); | |
233 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
234 | ||
235 | if (is_read) { | |
236 | memcpy(cpu_vaddr + cpu_offset, | |
237 | gpu_vaddr + swizzled_gpu_offset, | |
238 | this_length); | |
239 | } else { | |
240 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
241 | cpu_vaddr + cpu_offset, | |
242 | this_length); | |
243 | } | |
244 | cpu_offset += this_length; | |
245 | gpu_offset += this_length; | |
246 | length -= this_length; | |
247 | } | |
248 | ||
249 | kunmap_atomic(cpu_vaddr, KM_USER1); | |
250 | kunmap_atomic(gpu_vaddr, KM_USER0); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
eb01459f EA |
255 | /** |
256 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
257 | * from the backing pages of the object to the user's address space. On a | |
258 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
259 | */ | |
260 | static int | |
261 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
262 | struct drm_i915_gem_pread *args, | |
263 | struct drm_file *file_priv) | |
264 | { | |
23010e43 | 265 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
266 | ssize_t remain; |
267 | loff_t offset, page_base; | |
268 | char __user *user_data; | |
269 | int page_offset, page_length; | |
270 | int ret; | |
271 | ||
272 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
273 | remain = args->size; | |
274 | ||
275 | mutex_lock(&dev->struct_mutex); | |
276 | ||
4bdadb97 | 277 | ret = i915_gem_object_get_pages(obj, 0); |
eb01459f EA |
278 | if (ret != 0) |
279 | goto fail_unlock; | |
280 | ||
281 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
282 | args->size); | |
283 | if (ret != 0) | |
284 | goto fail_put_pages; | |
285 | ||
23010e43 | 286 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
287 | offset = args->offset; |
288 | ||
289 | while (remain > 0) { | |
290 | /* Operation in this page | |
291 | * | |
292 | * page_base = page offset within aperture | |
293 | * page_offset = offset within page | |
294 | * page_length = bytes to copy for this page | |
295 | */ | |
296 | page_base = (offset & ~(PAGE_SIZE-1)); | |
297 | page_offset = offset & (PAGE_SIZE-1); | |
298 | page_length = remain; | |
299 | if ((page_offset + remain) > PAGE_SIZE) | |
300 | page_length = PAGE_SIZE - page_offset; | |
301 | ||
302 | ret = fast_shmem_read(obj_priv->pages, | |
303 | page_base, page_offset, | |
304 | user_data, page_length); | |
305 | if (ret) | |
306 | goto fail_put_pages; | |
307 | ||
308 | remain -= page_length; | |
309 | user_data += page_length; | |
310 | offset += page_length; | |
311 | } | |
312 | ||
313 | fail_put_pages: | |
314 | i915_gem_object_put_pages(obj); | |
315 | fail_unlock: | |
316 | mutex_unlock(&dev->struct_mutex); | |
317 | ||
318 | return ret; | |
319 | } | |
320 | ||
07f73f69 CW |
321 | static int |
322 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
323 | { | |
324 | int ret; | |
325 | ||
4bdadb97 | 326 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
327 | |
328 | /* If we've insufficient memory to map in the pages, attempt | |
329 | * to make some space by throwing out some old buffers. | |
330 | */ | |
331 | if (ret == -ENOMEM) { | |
332 | struct drm_device *dev = obj->dev; | |
07f73f69 CW |
333 | |
334 | ret = i915_gem_evict_something(dev, obj->size); | |
335 | if (ret) | |
336 | return ret; | |
337 | ||
4bdadb97 | 338 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
339 | } |
340 | ||
341 | return ret; | |
342 | } | |
343 | ||
eb01459f EA |
344 | /** |
345 | * This is the fallback shmem pread path, which allocates temporary storage | |
346 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
347 | * can copy out of the object's backing pages while holding the struct mutex | |
348 | * and not take page faults. | |
349 | */ | |
350 | static int | |
351 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
352 | struct drm_i915_gem_pread *args, | |
353 | struct drm_file *file_priv) | |
354 | { | |
23010e43 | 355 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
356 | struct mm_struct *mm = current->mm; |
357 | struct page **user_pages; | |
358 | ssize_t remain; | |
359 | loff_t offset, pinned_pages, i; | |
360 | loff_t first_data_page, last_data_page, num_pages; | |
361 | int shmem_page_index, shmem_page_offset; | |
362 | int data_page_index, data_page_offset; | |
363 | int page_length; | |
364 | int ret; | |
365 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 366 | int do_bit17_swizzling; |
eb01459f EA |
367 | |
368 | remain = args->size; | |
369 | ||
370 | /* Pin the user pages containing the data. We can't fault while | |
371 | * holding the struct mutex, yet we want to hold it while | |
372 | * dereferencing the user data. | |
373 | */ | |
374 | first_data_page = data_ptr / PAGE_SIZE; | |
375 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
376 | num_pages = last_data_page - first_data_page + 1; | |
377 | ||
8e7d2b2c | 378 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
379 | if (user_pages == NULL) |
380 | return -ENOMEM; | |
381 | ||
382 | down_read(&mm->mmap_sem); | |
383 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 384 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
385 | up_read(&mm->mmap_sem); |
386 | if (pinned_pages < num_pages) { | |
387 | ret = -EFAULT; | |
388 | goto fail_put_user_pages; | |
389 | } | |
390 | ||
280b713b EA |
391 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
392 | ||
eb01459f EA |
393 | mutex_lock(&dev->struct_mutex); |
394 | ||
07f73f69 CW |
395 | ret = i915_gem_object_get_pages_or_evict(obj); |
396 | if (ret) | |
eb01459f EA |
397 | goto fail_unlock; |
398 | ||
399 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
400 | args->size); | |
401 | if (ret != 0) | |
402 | goto fail_put_pages; | |
403 | ||
23010e43 | 404 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
405 | offset = args->offset; |
406 | ||
407 | while (remain > 0) { | |
408 | /* Operation in this page | |
409 | * | |
410 | * shmem_page_index = page number within shmem file | |
411 | * shmem_page_offset = offset within page in shmem file | |
412 | * data_page_index = page number in get_user_pages return | |
413 | * data_page_offset = offset with data_page_index page. | |
414 | * page_length = bytes to copy for this page | |
415 | */ | |
416 | shmem_page_index = offset / PAGE_SIZE; | |
417 | shmem_page_offset = offset & ~PAGE_MASK; | |
418 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
419 | data_page_offset = data_ptr & ~PAGE_MASK; | |
420 | ||
421 | page_length = remain; | |
422 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
423 | page_length = PAGE_SIZE - shmem_page_offset; | |
424 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
425 | page_length = PAGE_SIZE - data_page_offset; | |
426 | ||
280b713b EA |
427 | if (do_bit17_swizzling) { |
428 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], | |
429 | shmem_page_offset, | |
430 | user_pages[data_page_index], | |
431 | data_page_offset, | |
432 | page_length, | |
433 | 1); | |
434 | } else { | |
435 | ret = slow_shmem_copy(user_pages[data_page_index], | |
436 | data_page_offset, | |
437 | obj_priv->pages[shmem_page_index], | |
438 | shmem_page_offset, | |
439 | page_length); | |
440 | } | |
eb01459f EA |
441 | if (ret) |
442 | goto fail_put_pages; | |
443 | ||
444 | remain -= page_length; | |
445 | data_ptr += page_length; | |
446 | offset += page_length; | |
447 | } | |
448 | ||
449 | fail_put_pages: | |
450 | i915_gem_object_put_pages(obj); | |
451 | fail_unlock: | |
452 | mutex_unlock(&dev->struct_mutex); | |
453 | fail_put_user_pages: | |
454 | for (i = 0; i < pinned_pages; i++) { | |
455 | SetPageDirty(user_pages[i]); | |
456 | page_cache_release(user_pages[i]); | |
457 | } | |
8e7d2b2c | 458 | drm_free_large(user_pages); |
eb01459f EA |
459 | |
460 | return ret; | |
461 | } | |
462 | ||
673a394b EA |
463 | /** |
464 | * Reads data from the object referenced by handle. | |
465 | * | |
466 | * On error, the contents of *data are undefined. | |
467 | */ | |
468 | int | |
469 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
470 | struct drm_file *file_priv) | |
471 | { | |
472 | struct drm_i915_gem_pread *args = data; | |
473 | struct drm_gem_object *obj; | |
474 | struct drm_i915_gem_object *obj_priv; | |
673a394b EA |
475 | int ret; |
476 | ||
477 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
478 | if (obj == NULL) | |
479 | return -EBADF; | |
23010e43 | 480 | obj_priv = to_intel_bo(obj); |
673a394b EA |
481 | |
482 | /* Bounds check source. | |
483 | * | |
484 | * XXX: This could use review for overflow issues... | |
485 | */ | |
486 | if (args->offset > obj->size || args->size > obj->size || | |
487 | args->offset + args->size > obj->size) { | |
bc9025bd | 488 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
489 | return -EINVAL; |
490 | } | |
491 | ||
280b713b | 492 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 493 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
494 | } else { |
495 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
496 | if (ret != 0) | |
497 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
498 | file_priv); | |
499 | } | |
673a394b | 500 | |
bc9025bd | 501 | drm_gem_object_unreference_unlocked(obj); |
673a394b | 502 | |
eb01459f | 503 | return ret; |
673a394b EA |
504 | } |
505 | ||
0839ccb8 KP |
506 | /* This is the fast write path which cannot handle |
507 | * page faults in the source data | |
9b7530cc | 508 | */ |
0839ccb8 KP |
509 | |
510 | static inline int | |
511 | fast_user_write(struct io_mapping *mapping, | |
512 | loff_t page_base, int page_offset, | |
513 | char __user *user_data, | |
514 | int length) | |
9b7530cc | 515 | { |
9b7530cc | 516 | char *vaddr_atomic; |
0839ccb8 | 517 | unsigned long unwritten; |
9b7530cc | 518 | |
0839ccb8 KP |
519 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
520 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, | |
521 | user_data, length); | |
522 | io_mapping_unmap_atomic(vaddr_atomic); | |
523 | if (unwritten) | |
524 | return -EFAULT; | |
525 | return 0; | |
526 | } | |
527 | ||
528 | /* Here's the write path which can sleep for | |
529 | * page faults | |
530 | */ | |
531 | ||
532 | static inline int | |
3de09aa3 EA |
533 | slow_kernel_write(struct io_mapping *mapping, |
534 | loff_t gtt_base, int gtt_offset, | |
535 | struct page *user_page, int user_offset, | |
536 | int length) | |
0839ccb8 | 537 | { |
3de09aa3 | 538 | char *src_vaddr, *dst_vaddr; |
0839ccb8 KP |
539 | unsigned long unwritten; |
540 | ||
3de09aa3 EA |
541 | dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base); |
542 | src_vaddr = kmap_atomic(user_page, KM_USER1); | |
543 | unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset, | |
544 | src_vaddr + user_offset, | |
545 | length); | |
546 | kunmap_atomic(src_vaddr, KM_USER1); | |
547 | io_mapping_unmap_atomic(dst_vaddr); | |
0839ccb8 KP |
548 | if (unwritten) |
549 | return -EFAULT; | |
9b7530cc | 550 | return 0; |
9b7530cc LT |
551 | } |
552 | ||
40123c1f EA |
553 | static inline int |
554 | fast_shmem_write(struct page **pages, | |
555 | loff_t page_base, int page_offset, | |
556 | char __user *data, | |
557 | int length) | |
558 | { | |
559 | char __iomem *vaddr; | |
d0088775 | 560 | unsigned long unwritten; |
40123c1f EA |
561 | |
562 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
563 | if (vaddr == NULL) | |
564 | return -ENOMEM; | |
d0088775 | 565 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
566 | kunmap_atomic(vaddr, KM_USER0); |
567 | ||
d0088775 DA |
568 | if (unwritten) |
569 | return -EFAULT; | |
40123c1f EA |
570 | return 0; |
571 | } | |
572 | ||
3de09aa3 EA |
573 | /** |
574 | * This is the fast pwrite path, where we copy the data directly from the | |
575 | * user into the GTT, uncached. | |
576 | */ | |
673a394b | 577 | static int |
3de09aa3 EA |
578 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
579 | struct drm_i915_gem_pwrite *args, | |
580 | struct drm_file *file_priv) | |
673a394b | 581 | { |
23010e43 | 582 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 583 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 584 | ssize_t remain; |
0839ccb8 | 585 | loff_t offset, page_base; |
673a394b | 586 | char __user *user_data; |
0839ccb8 KP |
587 | int page_offset, page_length; |
588 | int ret; | |
673a394b EA |
589 | |
590 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
591 | remain = args->size; | |
592 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
593 | return -EFAULT; | |
594 | ||
595 | ||
596 | mutex_lock(&dev->struct_mutex); | |
597 | ret = i915_gem_object_pin(obj, 0); | |
598 | if (ret) { | |
599 | mutex_unlock(&dev->struct_mutex); | |
600 | return ret; | |
601 | } | |
2ef7eeaa | 602 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
603 | if (ret) |
604 | goto fail; | |
605 | ||
23010e43 | 606 | obj_priv = to_intel_bo(obj); |
673a394b | 607 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
608 | |
609 | while (remain > 0) { | |
610 | /* Operation in this page | |
611 | * | |
0839ccb8 KP |
612 | * page_base = page offset within aperture |
613 | * page_offset = offset within page | |
614 | * page_length = bytes to copy for this page | |
673a394b | 615 | */ |
0839ccb8 KP |
616 | page_base = (offset & ~(PAGE_SIZE-1)); |
617 | page_offset = offset & (PAGE_SIZE-1); | |
618 | page_length = remain; | |
619 | if ((page_offset + remain) > PAGE_SIZE) | |
620 | page_length = PAGE_SIZE - page_offset; | |
621 | ||
622 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
623 | page_offset, user_data, page_length); | |
624 | ||
625 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
626 | * source page isn't available. Return the error and we'll |
627 | * retry in the slow path. | |
0839ccb8 | 628 | */ |
3de09aa3 EA |
629 | if (ret) |
630 | goto fail; | |
673a394b | 631 | |
0839ccb8 KP |
632 | remain -= page_length; |
633 | user_data += page_length; | |
634 | offset += page_length; | |
673a394b | 635 | } |
673a394b EA |
636 | |
637 | fail: | |
638 | i915_gem_object_unpin(obj); | |
639 | mutex_unlock(&dev->struct_mutex); | |
640 | ||
641 | return ret; | |
642 | } | |
643 | ||
3de09aa3 EA |
644 | /** |
645 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
646 | * the memory and maps it using kmap_atomic for copying. | |
647 | * | |
648 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
649 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
650 | */ | |
3043c60c | 651 | static int |
3de09aa3 EA |
652 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
653 | struct drm_i915_gem_pwrite *args, | |
654 | struct drm_file *file_priv) | |
673a394b | 655 | { |
23010e43 | 656 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
657 | drm_i915_private_t *dev_priv = dev->dev_private; |
658 | ssize_t remain; | |
659 | loff_t gtt_page_base, offset; | |
660 | loff_t first_data_page, last_data_page, num_pages; | |
661 | loff_t pinned_pages, i; | |
662 | struct page **user_pages; | |
663 | struct mm_struct *mm = current->mm; | |
664 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 665 | int ret; |
3de09aa3 EA |
666 | uint64_t data_ptr = args->data_ptr; |
667 | ||
668 | remain = args->size; | |
669 | ||
670 | /* Pin the user pages containing the data. We can't fault while | |
671 | * holding the struct mutex, and all of the pwrite implementations | |
672 | * want to hold it while dereferencing the user data. | |
673 | */ | |
674 | first_data_page = data_ptr / PAGE_SIZE; | |
675 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
676 | num_pages = last_data_page - first_data_page + 1; | |
677 | ||
8e7d2b2c | 678 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
679 | if (user_pages == NULL) |
680 | return -ENOMEM; | |
681 | ||
682 | down_read(&mm->mmap_sem); | |
683 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
684 | num_pages, 0, 0, user_pages, NULL); | |
685 | up_read(&mm->mmap_sem); | |
686 | if (pinned_pages < num_pages) { | |
687 | ret = -EFAULT; | |
688 | goto out_unpin_pages; | |
689 | } | |
673a394b EA |
690 | |
691 | mutex_lock(&dev->struct_mutex); | |
3de09aa3 EA |
692 | ret = i915_gem_object_pin(obj, 0); |
693 | if (ret) | |
694 | goto out_unlock; | |
695 | ||
696 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
697 | if (ret) | |
698 | goto out_unpin_object; | |
699 | ||
23010e43 | 700 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
701 | offset = obj_priv->gtt_offset + args->offset; |
702 | ||
703 | while (remain > 0) { | |
704 | /* Operation in this page | |
705 | * | |
706 | * gtt_page_base = page offset within aperture | |
707 | * gtt_page_offset = offset within page in aperture | |
708 | * data_page_index = page number in get_user_pages return | |
709 | * data_page_offset = offset with data_page_index page. | |
710 | * page_length = bytes to copy for this page | |
711 | */ | |
712 | gtt_page_base = offset & PAGE_MASK; | |
713 | gtt_page_offset = offset & ~PAGE_MASK; | |
714 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
715 | data_page_offset = data_ptr & ~PAGE_MASK; | |
716 | ||
717 | page_length = remain; | |
718 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
719 | page_length = PAGE_SIZE - gtt_page_offset; | |
720 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
721 | page_length = PAGE_SIZE - data_page_offset; | |
722 | ||
723 | ret = slow_kernel_write(dev_priv->mm.gtt_mapping, | |
724 | gtt_page_base, gtt_page_offset, | |
725 | user_pages[data_page_index], | |
726 | data_page_offset, | |
727 | page_length); | |
728 | ||
729 | /* If we get a fault while copying data, then (presumably) our | |
730 | * source page isn't available. Return the error and we'll | |
731 | * retry in the slow path. | |
732 | */ | |
733 | if (ret) | |
734 | goto out_unpin_object; | |
735 | ||
736 | remain -= page_length; | |
737 | offset += page_length; | |
738 | data_ptr += page_length; | |
739 | } | |
740 | ||
741 | out_unpin_object: | |
742 | i915_gem_object_unpin(obj); | |
743 | out_unlock: | |
744 | mutex_unlock(&dev->struct_mutex); | |
745 | out_unpin_pages: | |
746 | for (i = 0; i < pinned_pages; i++) | |
747 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 748 | drm_free_large(user_pages); |
3de09aa3 EA |
749 | |
750 | return ret; | |
751 | } | |
752 | ||
40123c1f EA |
753 | /** |
754 | * This is the fast shmem pwrite path, which attempts to directly | |
755 | * copy_from_user into the kmapped pages backing the object. | |
756 | */ | |
3043c60c | 757 | static int |
40123c1f EA |
758 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
759 | struct drm_i915_gem_pwrite *args, | |
760 | struct drm_file *file_priv) | |
673a394b | 761 | { |
23010e43 | 762 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
763 | ssize_t remain; |
764 | loff_t offset, page_base; | |
765 | char __user *user_data; | |
766 | int page_offset, page_length; | |
673a394b | 767 | int ret; |
40123c1f EA |
768 | |
769 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
770 | remain = args->size; | |
673a394b EA |
771 | |
772 | mutex_lock(&dev->struct_mutex); | |
773 | ||
4bdadb97 | 774 | ret = i915_gem_object_get_pages(obj, 0); |
40123c1f EA |
775 | if (ret != 0) |
776 | goto fail_unlock; | |
673a394b | 777 | |
e47c68e9 | 778 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
779 | if (ret != 0) |
780 | goto fail_put_pages; | |
781 | ||
23010e43 | 782 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
783 | offset = args->offset; |
784 | obj_priv->dirty = 1; | |
785 | ||
786 | while (remain > 0) { | |
787 | /* Operation in this page | |
788 | * | |
789 | * page_base = page offset within aperture | |
790 | * page_offset = offset within page | |
791 | * page_length = bytes to copy for this page | |
792 | */ | |
793 | page_base = (offset & ~(PAGE_SIZE-1)); | |
794 | page_offset = offset & (PAGE_SIZE-1); | |
795 | page_length = remain; | |
796 | if ((page_offset + remain) > PAGE_SIZE) | |
797 | page_length = PAGE_SIZE - page_offset; | |
798 | ||
799 | ret = fast_shmem_write(obj_priv->pages, | |
800 | page_base, page_offset, | |
801 | user_data, page_length); | |
802 | if (ret) | |
803 | goto fail_put_pages; | |
804 | ||
805 | remain -= page_length; | |
806 | user_data += page_length; | |
807 | offset += page_length; | |
808 | } | |
809 | ||
810 | fail_put_pages: | |
811 | i915_gem_object_put_pages(obj); | |
812 | fail_unlock: | |
813 | mutex_unlock(&dev->struct_mutex); | |
814 | ||
815 | return ret; | |
816 | } | |
817 | ||
818 | /** | |
819 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
820 | * the memory and maps it using kmap_atomic for copying. | |
821 | * | |
822 | * This avoids taking mmap_sem for faulting on the user's address while the | |
823 | * struct_mutex is held. | |
824 | */ | |
825 | static int | |
826 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
827 | struct drm_i915_gem_pwrite *args, | |
828 | struct drm_file *file_priv) | |
829 | { | |
23010e43 | 830 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
831 | struct mm_struct *mm = current->mm; |
832 | struct page **user_pages; | |
833 | ssize_t remain; | |
834 | loff_t offset, pinned_pages, i; | |
835 | loff_t first_data_page, last_data_page, num_pages; | |
836 | int shmem_page_index, shmem_page_offset; | |
837 | int data_page_index, data_page_offset; | |
838 | int page_length; | |
839 | int ret; | |
840 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 841 | int do_bit17_swizzling; |
40123c1f EA |
842 | |
843 | remain = args->size; | |
844 | ||
845 | /* Pin the user pages containing the data. We can't fault while | |
846 | * holding the struct mutex, and all of the pwrite implementations | |
847 | * want to hold it while dereferencing the user data. | |
848 | */ | |
849 | first_data_page = data_ptr / PAGE_SIZE; | |
850 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
851 | num_pages = last_data_page - first_data_page + 1; | |
852 | ||
8e7d2b2c | 853 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
854 | if (user_pages == NULL) |
855 | return -ENOMEM; | |
856 | ||
857 | down_read(&mm->mmap_sem); | |
858 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
859 | num_pages, 0, 0, user_pages, NULL); | |
860 | up_read(&mm->mmap_sem); | |
861 | if (pinned_pages < num_pages) { | |
862 | ret = -EFAULT; | |
863 | goto fail_put_user_pages; | |
673a394b EA |
864 | } |
865 | ||
280b713b EA |
866 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
867 | ||
40123c1f EA |
868 | mutex_lock(&dev->struct_mutex); |
869 | ||
07f73f69 CW |
870 | ret = i915_gem_object_get_pages_or_evict(obj); |
871 | if (ret) | |
40123c1f EA |
872 | goto fail_unlock; |
873 | ||
874 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
875 | if (ret != 0) | |
876 | goto fail_put_pages; | |
877 | ||
23010e43 | 878 | obj_priv = to_intel_bo(obj); |
673a394b | 879 | offset = args->offset; |
40123c1f | 880 | obj_priv->dirty = 1; |
673a394b | 881 | |
40123c1f EA |
882 | while (remain > 0) { |
883 | /* Operation in this page | |
884 | * | |
885 | * shmem_page_index = page number within shmem file | |
886 | * shmem_page_offset = offset within page in shmem file | |
887 | * data_page_index = page number in get_user_pages return | |
888 | * data_page_offset = offset with data_page_index page. | |
889 | * page_length = bytes to copy for this page | |
890 | */ | |
891 | shmem_page_index = offset / PAGE_SIZE; | |
892 | shmem_page_offset = offset & ~PAGE_MASK; | |
893 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
894 | data_page_offset = data_ptr & ~PAGE_MASK; | |
895 | ||
896 | page_length = remain; | |
897 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
898 | page_length = PAGE_SIZE - shmem_page_offset; | |
899 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
900 | page_length = PAGE_SIZE - data_page_offset; | |
901 | ||
280b713b EA |
902 | if (do_bit17_swizzling) { |
903 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], | |
904 | shmem_page_offset, | |
905 | user_pages[data_page_index], | |
906 | data_page_offset, | |
907 | page_length, | |
908 | 0); | |
909 | } else { | |
910 | ret = slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
911 | shmem_page_offset, | |
912 | user_pages[data_page_index], | |
913 | data_page_offset, | |
914 | page_length); | |
915 | } | |
40123c1f EA |
916 | if (ret) |
917 | goto fail_put_pages; | |
918 | ||
919 | remain -= page_length; | |
920 | data_ptr += page_length; | |
921 | offset += page_length; | |
673a394b EA |
922 | } |
923 | ||
40123c1f EA |
924 | fail_put_pages: |
925 | i915_gem_object_put_pages(obj); | |
926 | fail_unlock: | |
673a394b | 927 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
928 | fail_put_user_pages: |
929 | for (i = 0; i < pinned_pages; i++) | |
930 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 931 | drm_free_large(user_pages); |
673a394b | 932 | |
40123c1f | 933 | return ret; |
673a394b EA |
934 | } |
935 | ||
936 | /** | |
937 | * Writes data to the object referenced by handle. | |
938 | * | |
939 | * On error, the contents of the buffer that were to be modified are undefined. | |
940 | */ | |
941 | int | |
942 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
943 | struct drm_file *file_priv) | |
944 | { | |
945 | struct drm_i915_gem_pwrite *args = data; | |
946 | struct drm_gem_object *obj; | |
947 | struct drm_i915_gem_object *obj_priv; | |
948 | int ret = 0; | |
949 | ||
950 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
951 | if (obj == NULL) | |
952 | return -EBADF; | |
23010e43 | 953 | obj_priv = to_intel_bo(obj); |
673a394b EA |
954 | |
955 | /* Bounds check destination. | |
956 | * | |
957 | * XXX: This could use review for overflow issues... | |
958 | */ | |
959 | if (args->offset > obj->size || args->size > obj->size || | |
960 | args->offset + args->size > obj->size) { | |
bc9025bd | 961 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
962 | return -EINVAL; |
963 | } | |
964 | ||
965 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
966 | * it would end up going through the fenced access, and we'll get | |
967 | * different detiling behavior between reading and writing. | |
968 | * pread/pwrite currently are reading and writing from the CPU | |
969 | * perspective, requiring manual detiling by the client. | |
970 | */ | |
71acb5eb DA |
971 | if (obj_priv->phys_obj) |
972 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
973 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
3de09aa3 EA |
974 | dev->gtt_total != 0) { |
975 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); | |
976 | if (ret == -EFAULT) { | |
977 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
978 | file_priv); | |
979 | } | |
280b713b EA |
980 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
981 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
982 | } else { |
983 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
984 | if (ret == -EFAULT) { | |
985 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
986 | file_priv); | |
987 | } | |
988 | } | |
673a394b EA |
989 | |
990 | #if WATCH_PWRITE | |
991 | if (ret) | |
992 | DRM_INFO("pwrite failed %d\n", ret); | |
993 | #endif | |
994 | ||
bc9025bd | 995 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
996 | |
997 | return ret; | |
998 | } | |
999 | ||
1000 | /** | |
2ef7eeaa EA |
1001 | * Called when user space prepares to use an object with the CPU, either |
1002 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1003 | */ |
1004 | int | |
1005 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1006 | struct drm_file *file_priv) | |
1007 | { | |
a09ba7fa | 1008 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1009 | struct drm_i915_gem_set_domain *args = data; |
1010 | struct drm_gem_object *obj; | |
652c393a | 1011 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1012 | uint32_t read_domains = args->read_domains; |
1013 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1014 | int ret; |
1015 | ||
1016 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1017 | return -ENODEV; | |
1018 | ||
2ef7eeaa | 1019 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1020 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1021 | return -EINVAL; |
1022 | ||
21d509e3 | 1023 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1024 | return -EINVAL; |
1025 | ||
1026 | /* Having something in the write domain implies it's in the read | |
1027 | * domain, and only that read domain. Enforce that in the request. | |
1028 | */ | |
1029 | if (write_domain != 0 && read_domains != write_domain) | |
1030 | return -EINVAL; | |
1031 | ||
673a394b EA |
1032 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1033 | if (obj == NULL) | |
1034 | return -EBADF; | |
23010e43 | 1035 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1036 | |
1037 | mutex_lock(&dev->struct_mutex); | |
652c393a JB |
1038 | |
1039 | intel_mark_busy(dev, obj); | |
1040 | ||
673a394b | 1041 | #if WATCH_BUF |
cfd43c02 | 1042 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
2ef7eeaa | 1043 | obj, obj->size, read_domains, write_domain); |
673a394b | 1044 | #endif |
2ef7eeaa EA |
1045 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1046 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1047 | |
a09ba7fa EA |
1048 | /* Update the LRU on the fence for the CPU access that's |
1049 | * about to occur. | |
1050 | */ | |
1051 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1052 | struct drm_i915_fence_reg *reg = |
1053 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1054 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1055 | &dev_priv->mm.fence_list); |
1056 | } | |
1057 | ||
02354392 EA |
1058 | /* Silently promote "you're not bound, there was nothing to do" |
1059 | * to success, since the client was just asking us to | |
1060 | * make sure everything was done. | |
1061 | */ | |
1062 | if (ret == -EINVAL) | |
1063 | ret = 0; | |
2ef7eeaa | 1064 | } else { |
e47c68e9 | 1065 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1066 | } |
1067 | ||
673a394b EA |
1068 | drm_gem_object_unreference(obj); |
1069 | mutex_unlock(&dev->struct_mutex); | |
1070 | return ret; | |
1071 | } | |
1072 | ||
1073 | /** | |
1074 | * Called when user space has done writes to this buffer | |
1075 | */ | |
1076 | int | |
1077 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1078 | struct drm_file *file_priv) | |
1079 | { | |
1080 | struct drm_i915_gem_sw_finish *args = data; | |
1081 | struct drm_gem_object *obj; | |
1082 | struct drm_i915_gem_object *obj_priv; | |
1083 | int ret = 0; | |
1084 | ||
1085 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1086 | return -ENODEV; | |
1087 | ||
1088 | mutex_lock(&dev->struct_mutex); | |
1089 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1090 | if (obj == NULL) { | |
1091 | mutex_unlock(&dev->struct_mutex); | |
1092 | return -EBADF; | |
1093 | } | |
1094 | ||
1095 | #if WATCH_BUF | |
cfd43c02 | 1096 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
673a394b EA |
1097 | __func__, args->handle, obj, obj->size); |
1098 | #endif | |
23010e43 | 1099 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1100 | |
1101 | /* Pinned buffers may be scanout, so flush the cache */ | |
e47c68e9 EA |
1102 | if (obj_priv->pin_count) |
1103 | i915_gem_object_flush_cpu_write_domain(obj); | |
1104 | ||
673a394b EA |
1105 | drm_gem_object_unreference(obj); |
1106 | mutex_unlock(&dev->struct_mutex); | |
1107 | return ret; | |
1108 | } | |
1109 | ||
1110 | /** | |
1111 | * Maps the contents of an object, returning the address it is mapped | |
1112 | * into. | |
1113 | * | |
1114 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1115 | * imply a ref on the object itself. | |
1116 | */ | |
1117 | int | |
1118 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1119 | struct drm_file *file_priv) | |
1120 | { | |
1121 | struct drm_i915_gem_mmap *args = data; | |
1122 | struct drm_gem_object *obj; | |
1123 | loff_t offset; | |
1124 | unsigned long addr; | |
1125 | ||
1126 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1127 | return -ENODEV; | |
1128 | ||
1129 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1130 | if (obj == NULL) | |
1131 | return -EBADF; | |
1132 | ||
1133 | offset = args->offset; | |
1134 | ||
1135 | down_write(¤t->mm->mmap_sem); | |
1136 | addr = do_mmap(obj->filp, 0, args->size, | |
1137 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1138 | args->offset); | |
1139 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1140 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1141 | if (IS_ERR((void *)addr)) |
1142 | return addr; | |
1143 | ||
1144 | args->addr_ptr = (uint64_t) addr; | |
1145 | ||
1146 | return 0; | |
1147 | } | |
1148 | ||
de151cf6 JB |
1149 | /** |
1150 | * i915_gem_fault - fault a page into the GTT | |
1151 | * vma: VMA in question | |
1152 | * vmf: fault info | |
1153 | * | |
1154 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1155 | * from userspace. The fault handler takes care of binding the object to | |
1156 | * the GTT (if needed), allocating and programming a fence register (again, | |
1157 | * only if needed based on whether the old reg is still valid or the object | |
1158 | * is tiled) and inserting a new PTE into the faulting process. | |
1159 | * | |
1160 | * Note that the faulting process may involve evicting existing objects | |
1161 | * from the GTT and/or fence registers to make room. So performance may | |
1162 | * suffer if the GTT working set is large or there are few fence registers | |
1163 | * left. | |
1164 | */ | |
1165 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1166 | { | |
1167 | struct drm_gem_object *obj = vma->vm_private_data; | |
1168 | struct drm_device *dev = obj->dev; | |
1169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23010e43 | 1170 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1171 | pgoff_t page_offset; |
1172 | unsigned long pfn; | |
1173 | int ret = 0; | |
0f973f27 | 1174 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1175 | |
1176 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1177 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1178 | PAGE_SHIFT; | |
1179 | ||
1180 | /* Now bind it into the GTT if needed */ | |
1181 | mutex_lock(&dev->struct_mutex); | |
1182 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1183 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1184 | if (ret) |
1185 | goto unlock; | |
07f4f3e8 | 1186 | |
14b60391 | 1187 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
07f4f3e8 KH |
1188 | |
1189 | ret = i915_gem_object_set_to_gtt_domain(obj, write); | |
c715089f CW |
1190 | if (ret) |
1191 | goto unlock; | |
de151cf6 JB |
1192 | } |
1193 | ||
1194 | /* Need a new fence register? */ | |
a09ba7fa | 1195 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
8c4b8c3f | 1196 | ret = i915_gem_object_get_fence_reg(obj); |
c715089f CW |
1197 | if (ret) |
1198 | goto unlock; | |
d9ddcb96 | 1199 | } |
de151cf6 JB |
1200 | |
1201 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + | |
1202 | page_offset; | |
1203 | ||
1204 | /* Finally, remap it using the new GTT offset */ | |
1205 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1206 | unlock: |
de151cf6 JB |
1207 | mutex_unlock(&dev->struct_mutex); |
1208 | ||
1209 | switch (ret) { | |
c715089f CW |
1210 | case 0: |
1211 | case -ERESTARTSYS: | |
1212 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1213 | case -ENOMEM: |
1214 | case -EAGAIN: | |
1215 | return VM_FAULT_OOM; | |
de151cf6 | 1216 | default: |
c715089f | 1217 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1218 | } |
1219 | } | |
1220 | ||
1221 | /** | |
1222 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1223 | * @obj: obj in question | |
1224 | * | |
1225 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1226 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1227 | * up the object based on the offset and sets up the various memory mapping | |
1228 | * structures. | |
1229 | * | |
1230 | * This routine allocates and attaches a fake offset for @obj. | |
1231 | */ | |
1232 | static int | |
1233 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1234 | { | |
1235 | struct drm_device *dev = obj->dev; | |
1236 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1237 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1238 | struct drm_map_list *list; |
f77d390c | 1239 | struct drm_local_map *map; |
de151cf6 JB |
1240 | int ret = 0; |
1241 | ||
1242 | /* Set the object up for mmap'ing */ | |
1243 | list = &obj->map_list; | |
9a298b2a | 1244 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1245 | if (!list->map) |
1246 | return -ENOMEM; | |
1247 | ||
1248 | map = list->map; | |
1249 | map->type = _DRM_GEM; | |
1250 | map->size = obj->size; | |
1251 | map->handle = obj; | |
1252 | ||
1253 | /* Get a DRM GEM mmap offset allocated... */ | |
1254 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1255 | obj->size / PAGE_SIZE, 0, 0); | |
1256 | if (!list->file_offset_node) { | |
1257 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
1258 | ret = -ENOMEM; | |
1259 | goto out_free_list; | |
1260 | } | |
1261 | ||
1262 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1263 | obj->size / PAGE_SIZE, 0); | |
1264 | if (!list->file_offset_node) { | |
1265 | ret = -ENOMEM; | |
1266 | goto out_free_list; | |
1267 | } | |
1268 | ||
1269 | list->hash.key = list->file_offset_node->start; | |
1270 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { | |
1271 | DRM_ERROR("failed to add to map hash\n"); | |
5618ca6a | 1272 | ret = -ENOMEM; |
de151cf6 JB |
1273 | goto out_free_mm; |
1274 | } | |
1275 | ||
1276 | /* By now we should be all set, any drm_mmap request on the offset | |
1277 | * below will get to our mmap & fault handler */ | |
1278 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1279 | ||
1280 | return 0; | |
1281 | ||
1282 | out_free_mm: | |
1283 | drm_mm_put_block(list->file_offset_node); | |
1284 | out_free_list: | |
9a298b2a | 1285 | kfree(list->map); |
de151cf6 JB |
1286 | |
1287 | return ret; | |
1288 | } | |
1289 | ||
901782b2 CW |
1290 | /** |
1291 | * i915_gem_release_mmap - remove physical page mappings | |
1292 | * @obj: obj in question | |
1293 | * | |
af901ca1 | 1294 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1295 | * relinquish ownership of the pages back to the system. |
1296 | * | |
1297 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1298 | * object through the GTT and then lose the fence register due to | |
1299 | * resource pressure. Similarly if the object has been moved out of the | |
1300 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1301 | * mapping will then trigger a page fault on the next user access, allowing | |
1302 | * fixup by i915_gem_fault(). | |
1303 | */ | |
d05ca301 | 1304 | void |
901782b2 CW |
1305 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1306 | { | |
1307 | struct drm_device *dev = obj->dev; | |
23010e43 | 1308 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1309 | |
1310 | if (dev->dev_mapping) | |
1311 | unmap_mapping_range(dev->dev_mapping, | |
1312 | obj_priv->mmap_offset, obj->size, 1); | |
1313 | } | |
1314 | ||
ab00b3e5 JB |
1315 | static void |
1316 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1317 | { | |
1318 | struct drm_device *dev = obj->dev; | |
23010e43 | 1319 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1320 | struct drm_gem_mm *mm = dev->mm_private; |
1321 | struct drm_map_list *list; | |
1322 | ||
1323 | list = &obj->map_list; | |
1324 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1325 | ||
1326 | if (list->file_offset_node) { | |
1327 | drm_mm_put_block(list->file_offset_node); | |
1328 | list->file_offset_node = NULL; | |
1329 | } | |
1330 | ||
1331 | if (list->map) { | |
9a298b2a | 1332 | kfree(list->map); |
ab00b3e5 JB |
1333 | list->map = NULL; |
1334 | } | |
1335 | ||
1336 | obj_priv->mmap_offset = 0; | |
1337 | } | |
1338 | ||
de151cf6 JB |
1339 | /** |
1340 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1341 | * @obj: object to check | |
1342 | * | |
1343 | * Return the required GTT alignment for an object, taking into account | |
1344 | * potential fence register mapping if needed. | |
1345 | */ | |
1346 | static uint32_t | |
1347 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1348 | { | |
1349 | struct drm_device *dev = obj->dev; | |
23010e43 | 1350 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1351 | int start, i; |
1352 | ||
1353 | /* | |
1354 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1355 | * if a fence register is needed for the object. | |
1356 | */ | |
1357 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) | |
1358 | return 4096; | |
1359 | ||
1360 | /* | |
1361 | * Previous chips need to be aligned to the size of the smallest | |
1362 | * fence register that can contain the object. | |
1363 | */ | |
1364 | if (IS_I9XX(dev)) | |
1365 | start = 1024*1024; | |
1366 | else | |
1367 | start = 512*1024; | |
1368 | ||
1369 | for (i = start; i < obj->size; i <<= 1) | |
1370 | ; | |
1371 | ||
1372 | return i; | |
1373 | } | |
1374 | ||
1375 | /** | |
1376 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1377 | * @dev: DRM device | |
1378 | * @data: GTT mapping ioctl data | |
1379 | * @file_priv: GEM object info | |
1380 | * | |
1381 | * Simply returns the fake offset to userspace so it can mmap it. | |
1382 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1383 | * up so we can get faults in the handler above. | |
1384 | * | |
1385 | * The fault handler will take care of binding the object into the GTT | |
1386 | * (since it may have been evicted to make room for something), allocating | |
1387 | * a fence register, and mapping the appropriate aperture address into | |
1388 | * userspace. | |
1389 | */ | |
1390 | int | |
1391 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1392 | struct drm_file *file_priv) | |
1393 | { | |
1394 | struct drm_i915_gem_mmap_gtt *args = data; | |
1395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1396 | struct drm_gem_object *obj; | |
1397 | struct drm_i915_gem_object *obj_priv; | |
1398 | int ret; | |
1399 | ||
1400 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1401 | return -ENODEV; | |
1402 | ||
1403 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1404 | if (obj == NULL) | |
1405 | return -EBADF; | |
1406 | ||
1407 | mutex_lock(&dev->struct_mutex); | |
1408 | ||
23010e43 | 1409 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1410 | |
ab18282d CW |
1411 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1412 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1413 | drm_gem_object_unreference(obj); | |
1414 | mutex_unlock(&dev->struct_mutex); | |
1415 | return -EINVAL; | |
1416 | } | |
1417 | ||
1418 | ||
de151cf6 JB |
1419 | if (!obj_priv->mmap_offset) { |
1420 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1421 | if (ret) { |
1422 | drm_gem_object_unreference(obj); | |
1423 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1424 | return ret; |
13af1062 | 1425 | } |
de151cf6 JB |
1426 | } |
1427 | ||
1428 | args->offset = obj_priv->mmap_offset; | |
1429 | ||
de151cf6 JB |
1430 | /* |
1431 | * Pull it into the GTT so that we have a page list (makes the | |
1432 | * initial fault faster and any subsequent flushing possible). | |
1433 | */ | |
1434 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1435 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1436 | if (ret) { |
1437 | drm_gem_object_unreference(obj); | |
1438 | mutex_unlock(&dev->struct_mutex); | |
1439 | return ret; | |
1440 | } | |
14b60391 | 1441 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
de151cf6 JB |
1442 | } |
1443 | ||
1444 | drm_gem_object_unreference(obj); | |
1445 | mutex_unlock(&dev->struct_mutex); | |
1446 | ||
1447 | return 0; | |
1448 | } | |
1449 | ||
6911a9b8 | 1450 | void |
856fa198 | 1451 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1452 | { |
23010e43 | 1453 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1454 | int page_count = obj->size / PAGE_SIZE; |
1455 | int i; | |
1456 | ||
856fa198 | 1457 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1458 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1459 | |
856fa198 EA |
1460 | if (--obj_priv->pages_refcount != 0) |
1461 | return; | |
673a394b | 1462 | |
280b713b EA |
1463 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1464 | i915_gem_object_save_bit_17_swizzle(obj); | |
1465 | ||
3ef94daa | 1466 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1467 | obj_priv->dirty = 0; |
3ef94daa CW |
1468 | |
1469 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1470 | if (obj_priv->dirty) |
1471 | set_page_dirty(obj_priv->pages[i]); | |
1472 | ||
1473 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1474 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1475 | |
1476 | page_cache_release(obj_priv->pages[i]); | |
1477 | } | |
673a394b EA |
1478 | obj_priv->dirty = 0; |
1479 | ||
8e7d2b2c | 1480 | drm_free_large(obj_priv->pages); |
856fa198 | 1481 | obj_priv->pages = NULL; |
673a394b EA |
1482 | } |
1483 | ||
1484 | static void | |
852835f3 ZN |
1485 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno, |
1486 | struct intel_ring_buffer *ring) | |
673a394b EA |
1487 | { |
1488 | struct drm_device *dev = obj->dev; | |
1489 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1490 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
852835f3 ZN |
1491 | BUG_ON(ring == NULL); |
1492 | obj_priv->ring = ring; | |
673a394b EA |
1493 | |
1494 | /* Add a reference if we're newly entering the active list. */ | |
1495 | if (!obj_priv->active) { | |
1496 | drm_gem_object_reference(obj); | |
1497 | obj_priv->active = 1; | |
1498 | } | |
1499 | /* Move from whatever list we were on to the tail of execution. */ | |
5e118f41 | 1500 | spin_lock(&dev_priv->mm.active_list_lock); |
852835f3 | 1501 | list_move_tail(&obj_priv->list, &ring->active_list); |
5e118f41 | 1502 | spin_unlock(&dev_priv->mm.active_list_lock); |
ce44b0ea | 1503 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1504 | } |
1505 | ||
ce44b0ea EA |
1506 | static void |
1507 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1508 | { | |
1509 | struct drm_device *dev = obj->dev; | |
1510 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1511 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1512 | |
1513 | BUG_ON(!obj_priv->active); | |
1514 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1515 | obj_priv->last_rendering_seqno = 0; | |
1516 | } | |
673a394b | 1517 | |
963b4836 CW |
1518 | /* Immediately discard the backing storage */ |
1519 | static void | |
1520 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1521 | { | |
23010e43 | 1522 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1523 | struct inode *inode; |
963b4836 | 1524 | |
bb6baf76 CW |
1525 | inode = obj->filp->f_path.dentry->d_inode; |
1526 | if (inode->i_op->truncate) | |
1527 | inode->i_op->truncate (inode); | |
1528 | ||
1529 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1530 | } |
1531 | ||
1532 | static inline int | |
1533 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1534 | { | |
1535 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1536 | } | |
1537 | ||
673a394b EA |
1538 | static void |
1539 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1540 | { | |
1541 | struct drm_device *dev = obj->dev; | |
1542 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1543 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1544 | |
1545 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1546 | if (obj_priv->pin_count != 0) | |
1547 | list_del_init(&obj_priv->list); | |
1548 | else | |
1549 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1550 | ||
99fcb766 DV |
1551 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1552 | ||
ce44b0ea | 1553 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1554 | obj_priv->ring = NULL; |
673a394b EA |
1555 | if (obj_priv->active) { |
1556 | obj_priv->active = 0; | |
1557 | drm_gem_object_unreference(obj); | |
1558 | } | |
1559 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1560 | } | |
1561 | ||
63560396 DV |
1562 | static void |
1563 | i915_gem_process_flushing_list(struct drm_device *dev, | |
852835f3 ZN |
1564 | uint32_t flush_domains, uint32_t seqno, |
1565 | struct intel_ring_buffer *ring) | |
63560396 DV |
1566 | { |
1567 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1568 | struct drm_i915_gem_object *obj_priv, *next; | |
1569 | ||
1570 | list_for_each_entry_safe(obj_priv, next, | |
1571 | &dev_priv->mm.gpu_write_list, | |
1572 | gpu_write_list) { | |
a8089e84 | 1573 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 DV |
1574 | |
1575 | if ((obj->write_domain & flush_domains) == | |
852835f3 ZN |
1576 | obj->write_domain && |
1577 | obj_priv->ring->ring_flag == ring->ring_flag) { | |
63560396 DV |
1578 | uint32_t old_write_domain = obj->write_domain; |
1579 | ||
1580 | obj->write_domain = 0; | |
1581 | list_del_init(&obj_priv->gpu_write_list); | |
852835f3 | 1582 | i915_gem_object_move_to_active(obj, seqno, ring); |
63560396 DV |
1583 | |
1584 | /* update the fence lru list */ | |
007cc8ac DV |
1585 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1586 | struct drm_i915_fence_reg *reg = | |
1587 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1588 | list_move_tail(®->lru_list, | |
63560396 | 1589 | &dev_priv->mm.fence_list); |
007cc8ac | 1590 | } |
63560396 DV |
1591 | |
1592 | trace_i915_gem_object_change_domain(obj, | |
1593 | obj->read_domains, | |
1594 | old_write_domain); | |
1595 | } | |
1596 | } | |
1597 | } | |
8187a2b7 | 1598 | |
5a5a0c64 | 1599 | uint32_t |
b962442e | 1600 | i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
852835f3 | 1601 | uint32_t flush_domains, struct intel_ring_buffer *ring) |
673a394b EA |
1602 | { |
1603 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b962442e | 1604 | struct drm_i915_file_private *i915_file_priv = NULL; |
673a394b EA |
1605 | struct drm_i915_gem_request *request; |
1606 | uint32_t seqno; | |
1607 | int was_empty; | |
673a394b | 1608 | |
b962442e EA |
1609 | if (file_priv != NULL) |
1610 | i915_file_priv = file_priv->driver_priv; | |
1611 | ||
9a298b2a | 1612 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
673a394b EA |
1613 | if (request == NULL) |
1614 | return 0; | |
1615 | ||
852835f3 | 1616 | seqno = ring->add_request(dev, ring, file_priv, flush_domains); |
673a394b EA |
1617 | |
1618 | request->seqno = seqno; | |
852835f3 | 1619 | request->ring = ring; |
673a394b | 1620 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1621 | was_empty = list_empty(&ring->request_list); |
1622 | list_add_tail(&request->list, &ring->request_list); | |
1623 | ||
b962442e EA |
1624 | if (i915_file_priv) { |
1625 | list_add_tail(&request->client_list, | |
1626 | &i915_file_priv->mm.request_list); | |
1627 | } else { | |
1628 | INIT_LIST_HEAD(&request->client_list); | |
1629 | } | |
673a394b | 1630 | |
ce44b0ea EA |
1631 | /* Associate any objects on the flushing list matching the write |
1632 | * domain we're flushing with our flush. | |
1633 | */ | |
63560396 | 1634 | if (flush_domains != 0) |
852835f3 | 1635 | i915_gem_process_flushing_list(dev, flush_domains, seqno, ring); |
ce44b0ea | 1636 | |
f65d9421 BG |
1637 | if (!dev_priv->mm.suspended) { |
1638 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
1639 | if (was_empty) | |
1640 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1641 | } | |
673a394b EA |
1642 | return seqno; |
1643 | } | |
1644 | ||
1645 | /** | |
1646 | * Command execution barrier | |
1647 | * | |
1648 | * Ensures that all commands in the ring are finished | |
1649 | * before signalling the CPU | |
1650 | */ | |
3043c60c | 1651 | static uint32_t |
852835f3 | 1652 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1653 | { |
673a394b | 1654 | uint32_t flush_domains = 0; |
673a394b EA |
1655 | |
1656 | /* The sampler always gets flushed on i965 (sigh) */ | |
1657 | if (IS_I965G(dev)) | |
1658 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; | |
852835f3 ZN |
1659 | |
1660 | ring->flush(dev, ring, | |
1661 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1662 | return flush_domains; |
1663 | } | |
1664 | ||
1665 | /** | |
1666 | * Moves buffers associated only with the given active seqno from the active | |
1667 | * to inactive list, potentially freeing them. | |
1668 | */ | |
1669 | static void | |
1670 | i915_gem_retire_request(struct drm_device *dev, | |
1671 | struct drm_i915_gem_request *request) | |
1672 | { | |
1673 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1674 | ||
1c5d22f7 CW |
1675 | trace_i915_gem_request_retire(dev, request->seqno); |
1676 | ||
673a394b EA |
1677 | /* Move any buffers on the active list that are no longer referenced |
1678 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1679 | */ | |
5e118f41 | 1680 | spin_lock(&dev_priv->mm.active_list_lock); |
852835f3 | 1681 | while (!list_empty(&request->ring->active_list)) { |
673a394b EA |
1682 | struct drm_gem_object *obj; |
1683 | struct drm_i915_gem_object *obj_priv; | |
1684 | ||
852835f3 | 1685 | obj_priv = list_first_entry(&request->ring->active_list, |
673a394b EA |
1686 | struct drm_i915_gem_object, |
1687 | list); | |
a8089e84 | 1688 | obj = &obj_priv->base; |
673a394b EA |
1689 | |
1690 | /* If the seqno being retired doesn't match the oldest in the | |
1691 | * list, then the oldest in the list must still be newer than | |
1692 | * this seqno. | |
1693 | */ | |
1694 | if (obj_priv->last_rendering_seqno != request->seqno) | |
5e118f41 | 1695 | goto out; |
de151cf6 | 1696 | |
673a394b EA |
1697 | #if WATCH_LRU |
1698 | DRM_INFO("%s: retire %d moves to inactive list %p\n", | |
1699 | __func__, request->seqno, obj); | |
1700 | #endif | |
1701 | ||
ce44b0ea EA |
1702 | if (obj->write_domain != 0) |
1703 | i915_gem_object_move_to_flushing(obj); | |
68c84342 SL |
1704 | else { |
1705 | /* Take a reference on the object so it won't be | |
1706 | * freed while the spinlock is held. The list | |
1707 | * protection for this spinlock is safe when breaking | |
1708 | * the lock like this since the next thing we do | |
1709 | * is just get the head of the list again. | |
1710 | */ | |
1711 | drm_gem_object_reference(obj); | |
673a394b | 1712 | i915_gem_object_move_to_inactive(obj); |
68c84342 SL |
1713 | spin_unlock(&dev_priv->mm.active_list_lock); |
1714 | drm_gem_object_unreference(obj); | |
1715 | spin_lock(&dev_priv->mm.active_list_lock); | |
1716 | } | |
673a394b | 1717 | } |
5e118f41 CW |
1718 | out: |
1719 | spin_unlock(&dev_priv->mm.active_list_lock); | |
673a394b EA |
1720 | } |
1721 | ||
1722 | /** | |
1723 | * Returns true if seq1 is later than seq2. | |
1724 | */ | |
22be1724 | 1725 | bool |
673a394b EA |
1726 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1727 | { | |
1728 | return (int32_t)(seq1 - seq2) >= 0; | |
1729 | } | |
1730 | ||
1731 | uint32_t | |
852835f3 | 1732 | i915_get_gem_seqno(struct drm_device *dev, |
d1b851fc | 1733 | struct intel_ring_buffer *ring) |
673a394b | 1734 | { |
852835f3 | 1735 | return ring->get_gem_seqno(dev, ring); |
673a394b EA |
1736 | } |
1737 | ||
1738 | /** | |
1739 | * This function clears the request list as sequence numbers are passed. | |
1740 | */ | |
1741 | void | |
852835f3 ZN |
1742 | i915_gem_retire_requests(struct drm_device *dev, |
1743 | struct intel_ring_buffer *ring) | |
673a394b EA |
1744 | { |
1745 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1746 | uint32_t seqno; | |
1747 | ||
8187a2b7 | 1748 | if (!ring->status_page.page_addr |
852835f3 | 1749 | || list_empty(&ring->request_list)) |
6c0594a3 KW |
1750 | return; |
1751 | ||
852835f3 | 1752 | seqno = i915_get_gem_seqno(dev, ring); |
673a394b | 1753 | |
852835f3 | 1754 | while (!list_empty(&ring->request_list)) { |
673a394b EA |
1755 | struct drm_i915_gem_request *request; |
1756 | uint32_t retiring_seqno; | |
1757 | ||
852835f3 | 1758 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1759 | struct drm_i915_gem_request, |
1760 | list); | |
1761 | retiring_seqno = request->seqno; | |
1762 | ||
1763 | if (i915_seqno_passed(seqno, retiring_seqno) || | |
ba1234d1 | 1764 | atomic_read(&dev_priv->mm.wedged)) { |
673a394b EA |
1765 | i915_gem_retire_request(dev, request); |
1766 | ||
1767 | list_del(&request->list); | |
b962442e | 1768 | list_del(&request->client_list); |
9a298b2a | 1769 | kfree(request); |
673a394b EA |
1770 | } else |
1771 | break; | |
1772 | } | |
9d34e5db CW |
1773 | |
1774 | if (unlikely (dev_priv->trace_irq_seqno && | |
1775 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 ZN |
1776 | |
1777 | ring->user_irq_put(dev, ring); | |
9d34e5db CW |
1778 | dev_priv->trace_irq_seqno = 0; |
1779 | } | |
673a394b EA |
1780 | } |
1781 | ||
1782 | void | |
1783 | i915_gem_retire_work_handler(struct work_struct *work) | |
1784 | { | |
1785 | drm_i915_private_t *dev_priv; | |
1786 | struct drm_device *dev; | |
1787 | ||
1788 | dev_priv = container_of(work, drm_i915_private_t, | |
1789 | mm.retire_work.work); | |
1790 | dev = dev_priv->dev; | |
1791 | ||
1792 | mutex_lock(&dev->struct_mutex); | |
852835f3 ZN |
1793 | i915_gem_retire_requests(dev, &dev_priv->render_ring); |
1794 | ||
d1b851fc ZN |
1795 | if (HAS_BSD(dev)) |
1796 | i915_gem_retire_requests(dev, &dev_priv->bsd_ring); | |
1797 | ||
6dbe2772 | 1798 | if (!dev_priv->mm.suspended && |
d1b851fc ZN |
1799 | (!list_empty(&dev_priv->render_ring.request_list) || |
1800 | (HAS_BSD(dev) && | |
1801 | !list_empty(&dev_priv->bsd_ring.request_list)))) | |
9c9fe1f8 | 1802 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1803 | mutex_unlock(&dev->struct_mutex); |
1804 | } | |
1805 | ||
5a5a0c64 | 1806 | int |
852835f3 ZN |
1807 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
1808 | int interruptible, struct intel_ring_buffer *ring) | |
673a394b EA |
1809 | { |
1810 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1811 | u32 ier; |
673a394b EA |
1812 | int ret = 0; |
1813 | ||
1814 | BUG_ON(seqno == 0); | |
1815 | ||
ba1234d1 | 1816 | if (atomic_read(&dev_priv->mm.wedged)) |
ffed1d09 BG |
1817 | return -EIO; |
1818 | ||
852835f3 | 1819 | if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) { |
bad720ff | 1820 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1821 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1822 | else | |
1823 | ier = I915_READ(IER); | |
802c7eb6 JB |
1824 | if (!ier) { |
1825 | DRM_ERROR("something (likely vbetool) disabled " | |
1826 | "interrupts, re-enabling\n"); | |
1827 | i915_driver_irq_preinstall(dev); | |
1828 | i915_driver_irq_postinstall(dev); | |
1829 | } | |
1830 | ||
1c5d22f7 CW |
1831 | trace_i915_gem_request_wait_begin(dev, seqno); |
1832 | ||
852835f3 | 1833 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 1834 | ring->user_irq_get(dev, ring); |
48764bf4 | 1835 | if (interruptible) |
852835f3 ZN |
1836 | ret = wait_event_interruptible(ring->irq_queue, |
1837 | i915_seqno_passed( | |
1838 | ring->get_gem_seqno(dev, ring), seqno) | |
1839 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1840 | else |
852835f3 ZN |
1841 | wait_event(ring->irq_queue, |
1842 | i915_seqno_passed( | |
1843 | ring->get_gem_seqno(dev, ring), seqno) | |
1844 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1845 | |
8187a2b7 | 1846 | ring->user_irq_put(dev, ring); |
852835f3 | 1847 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
1848 | |
1849 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 1850 | } |
ba1234d1 | 1851 | if (atomic_read(&dev_priv->mm.wedged)) |
673a394b EA |
1852 | ret = -EIO; |
1853 | ||
1854 | if (ret && ret != -ERESTARTSYS) | |
1855 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", | |
852835f3 | 1856 | __func__, ret, seqno, ring->get_gem_seqno(dev, ring)); |
673a394b EA |
1857 | |
1858 | /* Directly dispatch request retiring. While we have the work queue | |
1859 | * to handle this, the waiter on a request often wants an associated | |
1860 | * buffer to have made it to the inactive list, and we would need | |
1861 | * a separate wait queue to handle that. | |
1862 | */ | |
1863 | if (ret == 0) | |
852835f3 | 1864 | i915_gem_retire_requests(dev, ring); |
673a394b EA |
1865 | |
1866 | return ret; | |
1867 | } | |
1868 | ||
48764bf4 DV |
1869 | /** |
1870 | * Waits for a sequence number to be signaled, and cleans up the | |
1871 | * request and object lists appropriately for that event. | |
1872 | */ | |
1873 | static int | |
852835f3 ZN |
1874 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
1875 | struct intel_ring_buffer *ring) | |
48764bf4 | 1876 | { |
852835f3 | 1877 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
1878 | } |
1879 | ||
8187a2b7 ZN |
1880 | static void |
1881 | i915_gem_flush(struct drm_device *dev, | |
1882 | uint32_t invalidate_domains, | |
1883 | uint32_t flush_domains) | |
1884 | { | |
1885 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1886 | if (flush_domains & I915_GEM_DOMAIN_CPU) | |
1887 | drm_agp_chipset_flush(dev); | |
1888 | dev_priv->render_ring.flush(dev, &dev_priv->render_ring, | |
1889 | invalidate_domains, | |
1890 | flush_domains); | |
d1b851fc ZN |
1891 | |
1892 | if (HAS_BSD(dev)) | |
1893 | dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring, | |
1894 | invalidate_domains, | |
1895 | flush_domains); | |
8187a2b7 ZN |
1896 | } |
1897 | ||
852835f3 ZN |
1898 | static void |
1899 | i915_gem_flush_ring(struct drm_device *dev, | |
1900 | uint32_t invalidate_domains, | |
1901 | uint32_t flush_domains, | |
1902 | struct intel_ring_buffer *ring) | |
1903 | { | |
1904 | if (flush_domains & I915_GEM_DOMAIN_CPU) | |
1905 | drm_agp_chipset_flush(dev); | |
1906 | ring->flush(dev, ring, | |
1907 | invalidate_domains, | |
1908 | flush_domains); | |
1909 | } | |
1910 | ||
673a394b EA |
1911 | /** |
1912 | * Ensures that all rendering to the object has completed and the object is | |
1913 | * safe to unbind from the GTT or access from the CPU. | |
1914 | */ | |
1915 | static int | |
1916 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) | |
1917 | { | |
1918 | struct drm_device *dev = obj->dev; | |
23010e43 | 1919 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1920 | int ret; |
1921 | ||
e47c68e9 EA |
1922 | /* This function only exists to support waiting for existing rendering, |
1923 | * not for emitting required flushes. | |
673a394b | 1924 | */ |
e47c68e9 | 1925 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1926 | |
1927 | /* If there is rendering queued on the buffer being evicted, wait for | |
1928 | * it. | |
1929 | */ | |
1930 | if (obj_priv->active) { | |
1931 | #if WATCH_BUF | |
1932 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
1933 | __func__, obj, obj_priv->last_rendering_seqno); | |
1934 | #endif | |
852835f3 ZN |
1935 | ret = i915_wait_request(dev, |
1936 | obj_priv->last_rendering_seqno, obj_priv->ring); | |
673a394b EA |
1937 | if (ret != 0) |
1938 | return ret; | |
1939 | } | |
1940 | ||
1941 | return 0; | |
1942 | } | |
1943 | ||
1944 | /** | |
1945 | * Unbinds an object from the GTT aperture. | |
1946 | */ | |
0f973f27 | 1947 | int |
673a394b EA |
1948 | i915_gem_object_unbind(struct drm_gem_object *obj) |
1949 | { | |
1950 | struct drm_device *dev = obj->dev; | |
4a87b8ca | 1951 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1952 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1953 | int ret = 0; |
1954 | ||
1955 | #if WATCH_BUF | |
1956 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); | |
1957 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); | |
1958 | #endif | |
1959 | if (obj_priv->gtt_space == NULL) | |
1960 | return 0; | |
1961 | ||
1962 | if (obj_priv->pin_count != 0) { | |
1963 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
1964 | return -EINVAL; | |
1965 | } | |
1966 | ||
5323fd04 EA |
1967 | /* blow away mappings if mapped through GTT */ |
1968 | i915_gem_release_mmap(obj); | |
1969 | ||
673a394b EA |
1970 | /* Move the object to the CPU domain to ensure that |
1971 | * any possible CPU writes while it's not in the GTT | |
1972 | * are flushed when we go to remap it. This will | |
1973 | * also ensure that all pending GPU writes are finished | |
1974 | * before we unbind. | |
1975 | */ | |
e47c68e9 | 1976 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
673a394b | 1977 | if (ret) { |
e47c68e9 EA |
1978 | if (ret != -ERESTARTSYS) |
1979 | DRM_ERROR("set_domain failed: %d\n", ret); | |
673a394b EA |
1980 | return ret; |
1981 | } | |
1982 | ||
5323fd04 EA |
1983 | BUG_ON(obj_priv->active); |
1984 | ||
96b47b65 DV |
1985 | /* release the fence reg _after_ flushing */ |
1986 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
1987 | i915_gem_clear_fence_reg(obj); | |
1988 | ||
673a394b EA |
1989 | if (obj_priv->agp_mem != NULL) { |
1990 | drm_unbind_agp(obj_priv->agp_mem); | |
1991 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
1992 | obj_priv->agp_mem = NULL; | |
1993 | } | |
1994 | ||
856fa198 | 1995 | i915_gem_object_put_pages(obj); |
a32808c0 | 1996 | BUG_ON(obj_priv->pages_refcount); |
673a394b EA |
1997 | |
1998 | if (obj_priv->gtt_space) { | |
1999 | atomic_dec(&dev->gtt_count); | |
2000 | atomic_sub(obj->size, &dev->gtt_memory); | |
2001 | ||
2002 | drm_mm_put_block(obj_priv->gtt_space); | |
2003 | obj_priv->gtt_space = NULL; | |
2004 | } | |
2005 | ||
2006 | /* Remove ourselves from the LRU list if present. */ | |
4a87b8ca | 2007 | spin_lock(&dev_priv->mm.active_list_lock); |
673a394b EA |
2008 | if (!list_empty(&obj_priv->list)) |
2009 | list_del_init(&obj_priv->list); | |
4a87b8ca | 2010 | spin_unlock(&dev_priv->mm.active_list_lock); |
673a394b | 2011 | |
963b4836 CW |
2012 | if (i915_gem_object_is_purgeable(obj_priv)) |
2013 | i915_gem_object_truncate(obj); | |
2014 | ||
1c5d22f7 CW |
2015 | trace_i915_gem_object_unbind(obj); |
2016 | ||
673a394b EA |
2017 | return 0; |
2018 | } | |
2019 | ||
07f73f69 CW |
2020 | static struct drm_gem_object * |
2021 | i915_gem_find_inactive_object(struct drm_device *dev, int min_size) | |
2022 | { | |
2023 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2024 | struct drm_i915_gem_object *obj_priv; | |
2025 | struct drm_gem_object *best = NULL; | |
2026 | struct drm_gem_object *first = NULL; | |
2027 | ||
2028 | /* Try to find the smallest clean object */ | |
2029 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { | |
a8089e84 | 2030 | struct drm_gem_object *obj = &obj_priv->base; |
07f73f69 | 2031 | if (obj->size >= min_size) { |
963b4836 CW |
2032 | if ((!obj_priv->dirty || |
2033 | i915_gem_object_is_purgeable(obj_priv)) && | |
07f73f69 CW |
2034 | (!best || obj->size < best->size)) { |
2035 | best = obj; | |
2036 | if (best->size == min_size) | |
2037 | return best; | |
2038 | } | |
2039 | if (!first) | |
2040 | first = obj; | |
2041 | } | |
2042 | } | |
2043 | ||
2044 | return best ? best : first; | |
2045 | } | |
2046 | ||
4df2faf4 DV |
2047 | static int |
2048 | i915_gpu_idle(struct drm_device *dev) | |
2049 | { | |
2050 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2051 | bool lists_empty; | |
d1b851fc | 2052 | uint32_t seqno1, seqno2; |
852835f3 | 2053 | int ret; |
4df2faf4 DV |
2054 | |
2055 | spin_lock(&dev_priv->mm.active_list_lock); | |
d1b851fc ZN |
2056 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2057 | list_empty(&dev_priv->render_ring.active_list) && | |
2058 | (!HAS_BSD(dev) || | |
2059 | list_empty(&dev_priv->bsd_ring.active_list))); | |
4df2faf4 DV |
2060 | spin_unlock(&dev_priv->mm.active_list_lock); |
2061 | ||
2062 | if (lists_empty) | |
2063 | return 0; | |
2064 | ||
2065 | /* Flush everything onto the inactive list. */ | |
2066 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
d1b851fc | 2067 | seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS, |
852835f3 | 2068 | &dev_priv->render_ring); |
d1b851fc | 2069 | if (seqno1 == 0) |
4df2faf4 | 2070 | return -ENOMEM; |
d1b851fc ZN |
2071 | ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring); |
2072 | ||
2073 | if (HAS_BSD(dev)) { | |
2074 | seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS, | |
2075 | &dev_priv->bsd_ring); | |
2076 | if (seqno2 == 0) | |
2077 | return -ENOMEM; | |
2078 | ||
2079 | ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring); | |
2080 | if (ret) | |
2081 | return ret; | |
2082 | } | |
2083 | ||
4df2faf4 | 2084 | |
852835f3 | 2085 | return ret; |
4df2faf4 DV |
2086 | } |
2087 | ||
673a394b | 2088 | static int |
07f73f69 CW |
2089 | i915_gem_evict_everything(struct drm_device *dev) |
2090 | { | |
2091 | drm_i915_private_t *dev_priv = dev->dev_private; | |
07f73f69 CW |
2092 | int ret; |
2093 | bool lists_empty; | |
2094 | ||
07f73f69 CW |
2095 | spin_lock(&dev_priv->mm.active_list_lock); |
2096 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && | |
2097 | list_empty(&dev_priv->mm.flushing_list) && | |
d1b851fc ZN |
2098 | list_empty(&dev_priv->render_ring.active_list) && |
2099 | (!HAS_BSD(dev) | |
2100 | || list_empty(&dev_priv->bsd_ring.active_list))); | |
07f73f69 CW |
2101 | spin_unlock(&dev_priv->mm.active_list_lock); |
2102 | ||
9731129c | 2103 | if (lists_empty) |
07f73f69 | 2104 | return -ENOSPC; |
07f73f69 CW |
2105 | |
2106 | /* Flush everything (on to the inactive lists) and evict */ | |
4df2faf4 | 2107 | ret = i915_gpu_idle(dev); |
07f73f69 CW |
2108 | if (ret) |
2109 | return ret; | |
2110 | ||
99fcb766 DV |
2111 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
2112 | ||
ab5ee576 | 2113 | ret = i915_gem_evict_from_inactive_list(dev); |
07f73f69 CW |
2114 | if (ret) |
2115 | return ret; | |
2116 | ||
2117 | spin_lock(&dev_priv->mm.active_list_lock); | |
2118 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && | |
2119 | list_empty(&dev_priv->mm.flushing_list) && | |
d1b851fc ZN |
2120 | list_empty(&dev_priv->render_ring.active_list) && |
2121 | (!HAS_BSD(dev) | |
2122 | || list_empty(&dev_priv->bsd_ring.active_list))); | |
07f73f69 CW |
2123 | spin_unlock(&dev_priv->mm.active_list_lock); |
2124 | BUG_ON(!lists_empty); | |
2125 | ||
2126 | return 0; | |
2127 | } | |
2128 | ||
673a394b | 2129 | static int |
07f73f69 | 2130 | i915_gem_evict_something(struct drm_device *dev, int min_size) |
673a394b EA |
2131 | { |
2132 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2133 | struct drm_gem_object *obj; | |
07f73f69 | 2134 | int ret; |
673a394b | 2135 | |
852835f3 | 2136 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
d1b851fc | 2137 | struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring; |
673a394b | 2138 | for (;;) { |
852835f3 | 2139 | i915_gem_retire_requests(dev, render_ring); |
07f73f69 | 2140 | |
d1b851fc ZN |
2141 | if (HAS_BSD(dev)) |
2142 | i915_gem_retire_requests(dev, bsd_ring); | |
2143 | ||
673a394b EA |
2144 | /* If there's an inactive buffer available now, grab it |
2145 | * and be done. | |
2146 | */ | |
07f73f69 CW |
2147 | obj = i915_gem_find_inactive_object(dev, min_size); |
2148 | if (obj) { | |
2149 | struct drm_i915_gem_object *obj_priv; | |
2150 | ||
673a394b EA |
2151 | #if WATCH_LRU |
2152 | DRM_INFO("%s: evicting %p\n", __func__, obj); | |
2153 | #endif | |
23010e43 | 2154 | obj_priv = to_intel_bo(obj); |
07f73f69 | 2155 | BUG_ON(obj_priv->pin_count != 0); |
673a394b EA |
2156 | BUG_ON(obj_priv->active); |
2157 | ||
2158 | /* Wait on the rendering and unbind the buffer. */ | |
07f73f69 | 2159 | return i915_gem_object_unbind(obj); |
673a394b EA |
2160 | } |
2161 | ||
2162 | /* If we didn't get anything, but the ring is still processing | |
07f73f69 CW |
2163 | * things, wait for the next to finish and hopefully leave us |
2164 | * a buffer to evict. | |
673a394b | 2165 | */ |
852835f3 | 2166 | if (!list_empty(&render_ring->request_list)) { |
673a394b EA |
2167 | struct drm_i915_gem_request *request; |
2168 | ||
852835f3 | 2169 | request = list_first_entry(&render_ring->request_list, |
673a394b EA |
2170 | struct drm_i915_gem_request, |
2171 | list); | |
2172 | ||
852835f3 ZN |
2173 | ret = i915_wait_request(dev, |
2174 | request->seqno, request->ring); | |
673a394b | 2175 | if (ret) |
07f73f69 | 2176 | return ret; |
673a394b | 2177 | |
07f73f69 | 2178 | continue; |
673a394b EA |
2179 | } |
2180 | ||
d1b851fc ZN |
2181 | if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) { |
2182 | struct drm_i915_gem_request *request; | |
2183 | ||
2184 | request = list_first_entry(&bsd_ring->request_list, | |
2185 | struct drm_i915_gem_request, | |
2186 | list); | |
2187 | ||
2188 | ret = i915_wait_request(dev, | |
2189 | request->seqno, request->ring); | |
2190 | if (ret) | |
2191 | return ret; | |
2192 | ||
2193 | continue; | |
2194 | } | |
2195 | ||
673a394b EA |
2196 | /* If we didn't have anything on the request list but there |
2197 | * are buffers awaiting a flush, emit one and try again. | |
2198 | * When we wait on it, those buffers waiting for that flush | |
2199 | * will get moved to inactive. | |
2200 | */ | |
2201 | if (!list_empty(&dev_priv->mm.flushing_list)) { | |
07f73f69 | 2202 | struct drm_i915_gem_object *obj_priv; |
673a394b | 2203 | |
9a1e2582 CW |
2204 | /* Find an object that we can immediately reuse */ |
2205 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { | |
a8089e84 | 2206 | obj = &obj_priv->base; |
9a1e2582 CW |
2207 | if (obj->size >= min_size) |
2208 | break; | |
673a394b | 2209 | |
9a1e2582 CW |
2210 | obj = NULL; |
2211 | } | |
673a394b | 2212 | |
9a1e2582 CW |
2213 | if (obj != NULL) { |
2214 | uint32_t seqno; | |
673a394b | 2215 | |
852835f3 ZN |
2216 | i915_gem_flush_ring(dev, |
2217 | obj->write_domain, | |
9a1e2582 | 2218 | obj->write_domain, |
852835f3 ZN |
2219 | obj_priv->ring); |
2220 | seqno = i915_add_request(dev, NULL, | |
2221 | obj->write_domain, | |
2222 | obj_priv->ring); | |
9a1e2582 CW |
2223 | if (seqno == 0) |
2224 | return -ENOMEM; | |
9a1e2582 CW |
2225 | continue; |
2226 | } | |
673a394b EA |
2227 | } |
2228 | ||
07f73f69 CW |
2229 | /* If we didn't do any of the above, there's no single buffer |
2230 | * large enough to swap out for the new one, so just evict | |
2231 | * everything and start again. (This should be rare.) | |
673a394b | 2232 | */ |
9731129c | 2233 | if (!list_empty (&dev_priv->mm.inactive_list)) |
ab5ee576 | 2234 | return i915_gem_evict_from_inactive_list(dev); |
9731129c | 2235 | else |
07f73f69 | 2236 | return i915_gem_evict_everything(dev); |
ac94a962 | 2237 | } |
ac94a962 KP |
2238 | } |
2239 | ||
6911a9b8 | 2240 | int |
4bdadb97 CW |
2241 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2242 | gfp_t gfpmask) | |
673a394b | 2243 | { |
23010e43 | 2244 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2245 | int page_count, i; |
2246 | struct address_space *mapping; | |
2247 | struct inode *inode; | |
2248 | struct page *page; | |
673a394b | 2249 | |
778c3544 DV |
2250 | BUG_ON(obj_priv->pages_refcount |
2251 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2252 | ||
856fa198 | 2253 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2254 | return 0; |
2255 | ||
2256 | /* Get the list of pages out of our struct file. They'll be pinned | |
2257 | * at this point until we release them. | |
2258 | */ | |
2259 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2260 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2261 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2262 | if (obj_priv->pages == NULL) { |
856fa198 | 2263 | obj_priv->pages_refcount--; |
673a394b EA |
2264 | return -ENOMEM; |
2265 | } | |
2266 | ||
2267 | inode = obj->filp->f_path.dentry->d_inode; | |
2268 | mapping = inode->i_mapping; | |
2269 | for (i = 0; i < page_count; i++) { | |
4bdadb97 CW |
2270 | page = read_cache_page_gfp(mapping, i, |
2271 | mapping_gfp_mask (mapping) | | |
2272 | __GFP_COLD | | |
2273 | gfpmask); | |
1f2b1013 CW |
2274 | if (IS_ERR(page)) |
2275 | goto err_pages; | |
2276 | ||
856fa198 | 2277 | obj_priv->pages[i] = page; |
673a394b | 2278 | } |
280b713b EA |
2279 | |
2280 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2281 | i915_gem_object_do_bit_17_swizzle(obj); | |
2282 | ||
673a394b | 2283 | return 0; |
1f2b1013 CW |
2284 | |
2285 | err_pages: | |
2286 | while (i--) | |
2287 | page_cache_release(obj_priv->pages[i]); | |
2288 | ||
2289 | drm_free_large(obj_priv->pages); | |
2290 | obj_priv->pages = NULL; | |
2291 | obj_priv->pages_refcount--; | |
2292 | return PTR_ERR(page); | |
673a394b EA |
2293 | } |
2294 | ||
4e901fdc EA |
2295 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2296 | { | |
2297 | struct drm_gem_object *obj = reg->obj; | |
2298 | struct drm_device *dev = obj->dev; | |
2299 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2300 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2301 | int regnum = obj_priv->fence_reg; |
2302 | uint64_t val; | |
2303 | ||
2304 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2305 | 0xfffff000) << 32; | |
2306 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2307 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2308 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2309 | ||
2310 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2311 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2312 | val |= I965_FENCE_REG_VALID; | |
2313 | ||
2314 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2315 | } | |
2316 | ||
de151cf6 JB |
2317 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2318 | { | |
2319 | struct drm_gem_object *obj = reg->obj; | |
2320 | struct drm_device *dev = obj->dev; | |
2321 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2322 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2323 | int regnum = obj_priv->fence_reg; |
2324 | uint64_t val; | |
2325 | ||
2326 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2327 | 0xfffff000) << 32; | |
2328 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2329 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2330 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2331 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2332 | val |= I965_FENCE_REG_VALID; | |
2333 | ||
2334 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2335 | } | |
2336 | ||
2337 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2338 | { | |
2339 | struct drm_gem_object *obj = reg->obj; | |
2340 | struct drm_device *dev = obj->dev; | |
2341 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2342 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2343 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2344 | int tile_width; |
dc529a4f | 2345 | uint32_t fence_reg, val; |
de151cf6 JB |
2346 | uint32_t pitch_val; |
2347 | ||
2348 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2349 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2350 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2351 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2352 | return; |
2353 | } | |
2354 | ||
0f973f27 JB |
2355 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2356 | HAS_128_BYTE_Y_TILING(dev)) | |
2357 | tile_width = 128; | |
de151cf6 | 2358 | else |
0f973f27 JB |
2359 | tile_width = 512; |
2360 | ||
2361 | /* Note: pitch better be a power of two tile widths */ | |
2362 | pitch_val = obj_priv->stride / tile_width; | |
2363 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2364 | |
c36a2a6d DV |
2365 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2366 | HAS_128_BYTE_Y_TILING(dev)) | |
2367 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2368 | else | |
2369 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2370 | ||
de151cf6 JB |
2371 | val = obj_priv->gtt_offset; |
2372 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2373 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2374 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2375 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2376 | val |= I830_FENCE_REG_VALID; | |
2377 | ||
dc529a4f EA |
2378 | if (regnum < 8) |
2379 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2380 | else | |
2381 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2382 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2383 | } |
2384 | ||
2385 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2386 | { | |
2387 | struct drm_gem_object *obj = reg->obj; | |
2388 | struct drm_device *dev = obj->dev; | |
2389 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2390 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2391 | int regnum = obj_priv->fence_reg; |
2392 | uint32_t val; | |
2393 | uint32_t pitch_val; | |
8d7773a3 | 2394 | uint32_t fence_size_bits; |
de151cf6 | 2395 | |
8d7773a3 | 2396 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2397 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2398 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2399 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2400 | return; |
2401 | } | |
2402 | ||
e76a16de EA |
2403 | pitch_val = obj_priv->stride / 128; |
2404 | pitch_val = ffs(pitch_val) - 1; | |
2405 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2406 | ||
de151cf6 JB |
2407 | val = obj_priv->gtt_offset; |
2408 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2409 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2410 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2411 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2412 | val |= fence_size_bits; | |
de151cf6 JB |
2413 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2414 | val |= I830_FENCE_REG_VALID; | |
2415 | ||
2416 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2417 | } |
2418 | ||
ae3db24a DV |
2419 | static int i915_find_fence_reg(struct drm_device *dev) |
2420 | { | |
2421 | struct drm_i915_fence_reg *reg = NULL; | |
2422 | struct drm_i915_gem_object *obj_priv = NULL; | |
2423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2424 | struct drm_gem_object *obj = NULL; | |
2425 | int i, avail, ret; | |
2426 | ||
2427 | /* First try to find a free reg */ | |
2428 | avail = 0; | |
2429 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2430 | reg = &dev_priv->fence_regs[i]; | |
2431 | if (!reg->obj) | |
2432 | return i; | |
2433 | ||
23010e43 | 2434 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2435 | if (!obj_priv->pin_count) |
2436 | avail++; | |
2437 | } | |
2438 | ||
2439 | if (avail == 0) | |
2440 | return -ENOSPC; | |
2441 | ||
2442 | /* None available, try to steal one or wait for a user to finish */ | |
2443 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2444 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2445 | lru_list) { | |
2446 | obj = reg->obj; | |
2447 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2448 | |
2449 | if (obj_priv->pin_count) | |
2450 | continue; | |
2451 | ||
2452 | /* found one! */ | |
2453 | i = obj_priv->fence_reg; | |
2454 | break; | |
2455 | } | |
2456 | ||
2457 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2458 | ||
2459 | /* We only have a reference on obj from the active list. put_fence_reg | |
2460 | * might drop that one, causing a use-after-free in it. So hold a | |
2461 | * private reference to obj like the other callers of put_fence_reg | |
2462 | * (set_tiling ioctl) do. */ | |
2463 | drm_gem_object_reference(obj); | |
2464 | ret = i915_gem_object_put_fence_reg(obj); | |
2465 | drm_gem_object_unreference(obj); | |
2466 | if (ret != 0) | |
2467 | return ret; | |
2468 | ||
2469 | return i; | |
2470 | } | |
2471 | ||
de151cf6 JB |
2472 | /** |
2473 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2474 | * @obj: object to map through a fence reg | |
2475 | * | |
2476 | * When mapping objects through the GTT, userspace wants to be able to write | |
2477 | * to them without having to worry about swizzling if the object is tiled. | |
2478 | * | |
2479 | * This function walks the fence regs looking for a free one for @obj, | |
2480 | * stealing one if it can't find any. | |
2481 | * | |
2482 | * It then sets up the reg based on the object's properties: address, pitch | |
2483 | * and tiling format. | |
2484 | */ | |
8c4b8c3f CW |
2485 | int |
2486 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) | |
de151cf6 JB |
2487 | { |
2488 | struct drm_device *dev = obj->dev; | |
79e53945 | 2489 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2490 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2491 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2492 | int ret; |
de151cf6 | 2493 | |
a09ba7fa EA |
2494 | /* Just update our place in the LRU if our fence is getting used. */ |
2495 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2496 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2497 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2498 | return 0; |
2499 | } | |
2500 | ||
de151cf6 JB |
2501 | switch (obj_priv->tiling_mode) { |
2502 | case I915_TILING_NONE: | |
2503 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2504 | break; | |
2505 | case I915_TILING_X: | |
0f973f27 JB |
2506 | if (!obj_priv->stride) |
2507 | return -EINVAL; | |
2508 | WARN((obj_priv->stride & (512 - 1)), | |
2509 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2510 | obj_priv->gtt_offset); | |
de151cf6 JB |
2511 | break; |
2512 | case I915_TILING_Y: | |
0f973f27 JB |
2513 | if (!obj_priv->stride) |
2514 | return -EINVAL; | |
2515 | WARN((obj_priv->stride & (128 - 1)), | |
2516 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2517 | obj_priv->gtt_offset); | |
de151cf6 JB |
2518 | break; |
2519 | } | |
2520 | ||
ae3db24a DV |
2521 | ret = i915_find_fence_reg(dev); |
2522 | if (ret < 0) | |
2523 | return ret; | |
de151cf6 | 2524 | |
ae3db24a DV |
2525 | obj_priv->fence_reg = ret; |
2526 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2527 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2528 | |
de151cf6 JB |
2529 | reg->obj = obj; |
2530 | ||
4e901fdc EA |
2531 | if (IS_GEN6(dev)) |
2532 | sandybridge_write_fence_reg(reg); | |
2533 | else if (IS_I965G(dev)) | |
de151cf6 JB |
2534 | i965_write_fence_reg(reg); |
2535 | else if (IS_I9XX(dev)) | |
2536 | i915_write_fence_reg(reg); | |
2537 | else | |
2538 | i830_write_fence_reg(reg); | |
d9ddcb96 | 2539 | |
ae3db24a DV |
2540 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2541 | obj_priv->tiling_mode); | |
1c5d22f7 | 2542 | |
d9ddcb96 | 2543 | return 0; |
de151cf6 JB |
2544 | } |
2545 | ||
2546 | /** | |
2547 | * i915_gem_clear_fence_reg - clear out fence register info | |
2548 | * @obj: object to clear | |
2549 | * | |
2550 | * Zeroes out the fence register itself and clears out the associated | |
2551 | * data structures in dev_priv and obj_priv. | |
2552 | */ | |
2553 | static void | |
2554 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2555 | { | |
2556 | struct drm_device *dev = obj->dev; | |
79e53945 | 2557 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2558 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2559 | struct drm_i915_fence_reg *reg = |
2560 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
de151cf6 | 2561 | |
4e901fdc EA |
2562 | if (IS_GEN6(dev)) { |
2563 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + | |
2564 | (obj_priv->fence_reg * 8), 0); | |
2565 | } else if (IS_I965G(dev)) { | |
de151cf6 | 2566 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
4e901fdc | 2567 | } else { |
dc529a4f EA |
2568 | uint32_t fence_reg; |
2569 | ||
2570 | if (obj_priv->fence_reg < 8) | |
2571 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
2572 | else | |
2573 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - | |
2574 | 8) * 4; | |
2575 | ||
2576 | I915_WRITE(fence_reg, 0); | |
2577 | } | |
de151cf6 | 2578 | |
007cc8ac | 2579 | reg->obj = NULL; |
de151cf6 | 2580 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2581 | list_del_init(®->lru_list); |
de151cf6 JB |
2582 | } |
2583 | ||
52dc7d32 CW |
2584 | /** |
2585 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2586 | * to the buffer to finish, and then resets the fence register. | |
2587 | * @obj: tiled object holding a fence register. | |
2588 | * | |
2589 | * Zeroes out the fence register itself and clears out the associated | |
2590 | * data structures in dev_priv and obj_priv. | |
2591 | */ | |
2592 | int | |
2593 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) | |
2594 | { | |
2595 | struct drm_device *dev = obj->dev; | |
23010e43 | 2596 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
52dc7d32 CW |
2597 | |
2598 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2599 | return 0; | |
2600 | ||
10ae9bd2 DV |
2601 | /* If we've changed tiling, GTT-mappings of the object |
2602 | * need to re-fault to ensure that the correct fence register | |
2603 | * setup is in place. | |
2604 | */ | |
2605 | i915_gem_release_mmap(obj); | |
2606 | ||
52dc7d32 CW |
2607 | /* On the i915, GPU access to tiled buffers is via a fence, |
2608 | * therefore we must wait for any outstanding access to complete | |
2609 | * before clearing the fence. | |
2610 | */ | |
2611 | if (!IS_I965G(dev)) { | |
2612 | int ret; | |
2613 | ||
2614 | i915_gem_object_flush_gpu_write_domain(obj); | |
52dc7d32 CW |
2615 | ret = i915_gem_object_wait_rendering(obj); |
2616 | if (ret != 0) | |
2617 | return ret; | |
2618 | } | |
2619 | ||
4a726612 | 2620 | i915_gem_object_flush_gtt_write_domain(obj); |
52dc7d32 CW |
2621 | i915_gem_clear_fence_reg (obj); |
2622 | ||
2623 | return 0; | |
2624 | } | |
2625 | ||
673a394b EA |
2626 | /** |
2627 | * Finds free space in the GTT aperture and binds the object there. | |
2628 | */ | |
2629 | static int | |
2630 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2631 | { | |
2632 | struct drm_device *dev = obj->dev; | |
2633 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2634 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2635 | struct drm_mm_node *free_space; |
4bdadb97 | 2636 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2637 | int ret; |
673a394b | 2638 | |
bb6baf76 | 2639 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2640 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2641 | return -EINVAL; | |
2642 | } | |
2643 | ||
673a394b | 2644 | if (alignment == 0) |
0f973f27 | 2645 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2646 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2647 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2648 | return -EINVAL; | |
2649 | } | |
2650 | ||
2651 | search_free: | |
2652 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2653 | obj->size, alignment, 0); | |
2654 | if (free_space != NULL) { | |
2655 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2656 | alignment); | |
2657 | if (obj_priv->gtt_space != NULL) { | |
2658 | obj_priv->gtt_space->private = obj; | |
2659 | obj_priv->gtt_offset = obj_priv->gtt_space->start; | |
2660 | } | |
2661 | } | |
2662 | if (obj_priv->gtt_space == NULL) { | |
2663 | /* If the gtt is empty and we're still having trouble | |
2664 | * fitting our object in, we're out of memory. | |
2665 | */ | |
2666 | #if WATCH_LRU | |
2667 | DRM_INFO("%s: GTT full, evicting something\n", __func__); | |
2668 | #endif | |
07f73f69 | 2669 | ret = i915_gem_evict_something(dev, obj->size); |
9731129c | 2670 | if (ret) |
673a394b | 2671 | return ret; |
9731129c | 2672 | |
673a394b EA |
2673 | goto search_free; |
2674 | } | |
2675 | ||
2676 | #if WATCH_BUF | |
cfd43c02 | 2677 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
673a394b EA |
2678 | obj->size, obj_priv->gtt_offset); |
2679 | #endif | |
4bdadb97 | 2680 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2681 | if (ret) { |
2682 | drm_mm_put_block(obj_priv->gtt_space); | |
2683 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2684 | |
2685 | if (ret == -ENOMEM) { | |
2686 | /* first try to clear up some space from the GTT */ | |
2687 | ret = i915_gem_evict_something(dev, obj->size); | |
2688 | if (ret) { | |
07f73f69 | 2689 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2690 | if (gfpmask) { |
2691 | gfpmask = 0; | |
2692 | goto search_free; | |
07f73f69 CW |
2693 | } |
2694 | ||
2695 | return ret; | |
2696 | } | |
2697 | ||
2698 | goto search_free; | |
2699 | } | |
2700 | ||
673a394b EA |
2701 | return ret; |
2702 | } | |
2703 | ||
673a394b EA |
2704 | /* Create an AGP memory structure pointing at our pages, and bind it |
2705 | * into the GTT. | |
2706 | */ | |
2707 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2708 | obj_priv->pages, |
07f73f69 | 2709 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2710 | obj_priv->gtt_offset, |
2711 | obj_priv->agp_type); | |
673a394b | 2712 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2713 | i915_gem_object_put_pages(obj); |
673a394b EA |
2714 | drm_mm_put_block(obj_priv->gtt_space); |
2715 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2716 | |
2717 | ret = i915_gem_evict_something(dev, obj->size); | |
9731129c | 2718 | if (ret) |
07f73f69 | 2719 | return ret; |
07f73f69 CW |
2720 | |
2721 | goto search_free; | |
673a394b EA |
2722 | } |
2723 | atomic_inc(&dev->gtt_count); | |
2724 | atomic_add(obj->size, &dev->gtt_memory); | |
2725 | ||
2726 | /* Assert that the object is not currently in any GPU domain. As it | |
2727 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2728 | * a GPU cache | |
2729 | */ | |
21d509e3 CW |
2730 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2731 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2732 | |
1c5d22f7 CW |
2733 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2734 | ||
673a394b EA |
2735 | return 0; |
2736 | } | |
2737 | ||
2738 | void | |
2739 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2740 | { | |
23010e43 | 2741 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2742 | |
2743 | /* If we don't have a page list set up, then we're not pinned | |
2744 | * to GPU, and we can ignore the cache flush because it'll happen | |
2745 | * again at bind time. | |
2746 | */ | |
856fa198 | 2747 | if (obj_priv->pages == NULL) |
673a394b EA |
2748 | return; |
2749 | ||
1c5d22f7 | 2750 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2751 | |
856fa198 | 2752 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2753 | } |
2754 | ||
e47c68e9 EA |
2755 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2756 | static void | |
2757 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) | |
2758 | { | |
2759 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2760 | uint32_t old_write_domain; |
852835f3 | 2761 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
e47c68e9 EA |
2762 | |
2763 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2764 | return; | |
2765 | ||
2766 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2767 | old_write_domain = obj->write_domain; |
e47c68e9 | 2768 | i915_gem_flush(dev, 0, obj->write_domain); |
852835f3 | 2769 | (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring); |
99fcb766 | 2770 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2771 | |
2772 | trace_i915_gem_object_change_domain(obj, | |
2773 | obj->read_domains, | |
2774 | old_write_domain); | |
e47c68e9 EA |
2775 | } |
2776 | ||
2777 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2778 | static void | |
2779 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2780 | { | |
1c5d22f7 CW |
2781 | uint32_t old_write_domain; |
2782 | ||
e47c68e9 EA |
2783 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2784 | return; | |
2785 | ||
2786 | /* No actual flushing is required for the GTT write domain. Writes | |
2787 | * to it immediately go to main memory as far as we know, so there's | |
2788 | * no chipset flush. It also doesn't land in render cache. | |
2789 | */ | |
1c5d22f7 | 2790 | old_write_domain = obj->write_domain; |
e47c68e9 | 2791 | obj->write_domain = 0; |
1c5d22f7 CW |
2792 | |
2793 | trace_i915_gem_object_change_domain(obj, | |
2794 | obj->read_domains, | |
2795 | old_write_domain); | |
e47c68e9 EA |
2796 | } |
2797 | ||
2798 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2799 | static void | |
2800 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2801 | { | |
2802 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2803 | uint32_t old_write_domain; |
e47c68e9 EA |
2804 | |
2805 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2806 | return; | |
2807 | ||
2808 | i915_gem_clflush_object(obj); | |
2809 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2810 | old_write_domain = obj->write_domain; |
e47c68e9 | 2811 | obj->write_domain = 0; |
1c5d22f7 CW |
2812 | |
2813 | trace_i915_gem_object_change_domain(obj, | |
2814 | obj->read_domains, | |
2815 | old_write_domain); | |
e47c68e9 EA |
2816 | } |
2817 | ||
6b95a207 KH |
2818 | void |
2819 | i915_gem_object_flush_write_domain(struct drm_gem_object *obj) | |
2820 | { | |
2821 | switch (obj->write_domain) { | |
2822 | case I915_GEM_DOMAIN_GTT: | |
2823 | i915_gem_object_flush_gtt_write_domain(obj); | |
2824 | break; | |
2825 | case I915_GEM_DOMAIN_CPU: | |
2826 | i915_gem_object_flush_cpu_write_domain(obj); | |
2827 | break; | |
2828 | default: | |
2829 | i915_gem_object_flush_gpu_write_domain(obj); | |
2830 | break; | |
2831 | } | |
2832 | } | |
2833 | ||
2ef7eeaa EA |
2834 | /** |
2835 | * Moves a single object to the GTT read, and possibly write domain. | |
2836 | * | |
2837 | * This function returns when the move is complete, including waiting on | |
2838 | * flushes to occur. | |
2839 | */ | |
79e53945 | 2840 | int |
2ef7eeaa EA |
2841 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2842 | { | |
23010e43 | 2843 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2844 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2845 | int ret; |
2ef7eeaa | 2846 | |
02354392 EA |
2847 | /* Not valid to be called on unbound objects. */ |
2848 | if (obj_priv->gtt_space == NULL) | |
2849 | return -EINVAL; | |
2850 | ||
e47c68e9 EA |
2851 | i915_gem_object_flush_gpu_write_domain(obj); |
2852 | /* Wait on any GPU rendering and flushing to occur. */ | |
2853 | ret = i915_gem_object_wait_rendering(obj); | |
2854 | if (ret != 0) | |
2855 | return ret; | |
2856 | ||
1c5d22f7 CW |
2857 | old_write_domain = obj->write_domain; |
2858 | old_read_domains = obj->read_domains; | |
2859 | ||
e47c68e9 EA |
2860 | /* If we're writing through the GTT domain, then CPU and GPU caches |
2861 | * will need to be invalidated at next use. | |
2ef7eeaa | 2862 | */ |
e47c68e9 EA |
2863 | if (write) |
2864 | obj->read_domains &= I915_GEM_DOMAIN_GTT; | |
2ef7eeaa | 2865 | |
e47c68e9 | 2866 | i915_gem_object_flush_cpu_write_domain(obj); |
2ef7eeaa | 2867 | |
e47c68e9 EA |
2868 | /* It should now be out of any other write domains, and we can update |
2869 | * the domain values for our changes. | |
2870 | */ | |
2871 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2872 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2873 | if (write) { | |
2874 | obj->write_domain = I915_GEM_DOMAIN_GTT; | |
2875 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2876 | } |
2877 | ||
1c5d22f7 CW |
2878 | trace_i915_gem_object_change_domain(obj, |
2879 | old_read_domains, | |
2880 | old_write_domain); | |
2881 | ||
e47c68e9 EA |
2882 | return 0; |
2883 | } | |
2884 | ||
b9241ea3 ZW |
2885 | /* |
2886 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2887 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2888 | */ | |
2889 | int | |
2890 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj) | |
2891 | { | |
2892 | struct drm_device *dev = obj->dev; | |
23010e43 | 2893 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
b9241ea3 ZW |
2894 | uint32_t old_write_domain, old_read_domains; |
2895 | int ret; | |
2896 | ||
2897 | /* Not valid to be called on unbound objects. */ | |
2898 | if (obj_priv->gtt_space == NULL) | |
2899 | return -EINVAL; | |
2900 | ||
2901 | i915_gem_object_flush_gpu_write_domain(obj); | |
2902 | ||
2903 | /* Wait on any GPU rendering and flushing to occur. */ | |
2904 | if (obj_priv->active) { | |
2905 | #if WATCH_BUF | |
2906 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
2907 | __func__, obj, obj_priv->last_rendering_seqno); | |
2908 | #endif | |
852835f3 ZN |
2909 | ret = i915_do_wait_request(dev, |
2910 | obj_priv->last_rendering_seqno, | |
2911 | 0, | |
2912 | obj_priv->ring); | |
b9241ea3 ZW |
2913 | if (ret != 0) |
2914 | return ret; | |
2915 | } | |
2916 | ||
2917 | old_write_domain = obj->write_domain; | |
2918 | old_read_domains = obj->read_domains; | |
2919 | ||
2920 | obj->read_domains &= I915_GEM_DOMAIN_GTT; | |
2921 | ||
2922 | i915_gem_object_flush_cpu_write_domain(obj); | |
2923 | ||
2924 | /* It should now be out of any other write domains, and we can update | |
2925 | * the domain values for our changes. | |
2926 | */ | |
2927 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2928 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2929 | obj->write_domain = I915_GEM_DOMAIN_GTT; | |
2930 | obj_priv->dirty = 1; | |
2931 | ||
2932 | trace_i915_gem_object_change_domain(obj, | |
2933 | old_read_domains, | |
2934 | old_write_domain); | |
2935 | ||
2936 | return 0; | |
2937 | } | |
2938 | ||
e47c68e9 EA |
2939 | /** |
2940 | * Moves a single object to the CPU read, and possibly write domain. | |
2941 | * | |
2942 | * This function returns when the move is complete, including waiting on | |
2943 | * flushes to occur. | |
2944 | */ | |
2945 | static int | |
2946 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2947 | { | |
1c5d22f7 | 2948 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2949 | int ret; |
2950 | ||
2951 | i915_gem_object_flush_gpu_write_domain(obj); | |
2ef7eeaa | 2952 | /* Wait on any GPU rendering and flushing to occur. */ |
e47c68e9 EA |
2953 | ret = i915_gem_object_wait_rendering(obj); |
2954 | if (ret != 0) | |
2955 | return ret; | |
2ef7eeaa | 2956 | |
e47c68e9 | 2957 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2958 | |
e47c68e9 EA |
2959 | /* If we have a partially-valid cache of the object in the CPU, |
2960 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2961 | */ |
e47c68e9 | 2962 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2963 | |
1c5d22f7 CW |
2964 | old_write_domain = obj->write_domain; |
2965 | old_read_domains = obj->read_domains; | |
2966 | ||
e47c68e9 EA |
2967 | /* Flush the CPU cache if it's still invalid. */ |
2968 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2969 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2970 | |
e47c68e9 | 2971 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2972 | } |
2973 | ||
2974 | /* It should now be out of any other write domains, and we can update | |
2975 | * the domain values for our changes. | |
2976 | */ | |
e47c68e9 EA |
2977 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2978 | ||
2979 | /* If we're writing through the CPU, then the GPU read domains will | |
2980 | * need to be invalidated at next use. | |
2981 | */ | |
2982 | if (write) { | |
2983 | obj->read_domains &= I915_GEM_DOMAIN_CPU; | |
2984 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2985 | } | |
2ef7eeaa | 2986 | |
1c5d22f7 CW |
2987 | trace_i915_gem_object_change_domain(obj, |
2988 | old_read_domains, | |
2989 | old_write_domain); | |
2990 | ||
2ef7eeaa EA |
2991 | return 0; |
2992 | } | |
2993 | ||
673a394b EA |
2994 | /* |
2995 | * Set the next domain for the specified object. This | |
2996 | * may not actually perform the necessary flushing/invaliding though, | |
2997 | * as that may want to be batched with other set_domain operations | |
2998 | * | |
2999 | * This is (we hope) the only really tricky part of gem. The goal | |
3000 | * is fairly simple -- track which caches hold bits of the object | |
3001 | * and make sure they remain coherent. A few concrete examples may | |
3002 | * help to explain how it works. For shorthand, we use the notation | |
3003 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3004 | * a pair of read and write domain masks. | |
3005 | * | |
3006 | * Case 1: the batch buffer | |
3007 | * | |
3008 | * 1. Allocated | |
3009 | * 2. Written by CPU | |
3010 | * 3. Mapped to GTT | |
3011 | * 4. Read by GPU | |
3012 | * 5. Unmapped from GTT | |
3013 | * 6. Freed | |
3014 | * | |
3015 | * Let's take these a step at a time | |
3016 | * | |
3017 | * 1. Allocated | |
3018 | * Pages allocated from the kernel may still have | |
3019 | * cache contents, so we set them to (CPU, CPU) always. | |
3020 | * 2. Written by CPU (using pwrite) | |
3021 | * The pwrite function calls set_domain (CPU, CPU) and | |
3022 | * this function does nothing (as nothing changes) | |
3023 | * 3. Mapped by GTT | |
3024 | * This function asserts that the object is not | |
3025 | * currently in any GPU-based read or write domains | |
3026 | * 4. Read by GPU | |
3027 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3028 | * As write_domain is zero, this function adds in the | |
3029 | * current read domains (CPU+COMMAND, 0). | |
3030 | * flush_domains is set to CPU. | |
3031 | * invalidate_domains is set to COMMAND | |
3032 | * clflush is run to get data out of the CPU caches | |
3033 | * then i915_dev_set_domain calls i915_gem_flush to | |
3034 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3035 | * 5. Unmapped from GTT | |
3036 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3037 | * flush_domains and invalidate_domains end up both zero | |
3038 | * so no flushing/invalidating happens | |
3039 | * 6. Freed | |
3040 | * yay, done | |
3041 | * | |
3042 | * Case 2: The shared render buffer | |
3043 | * | |
3044 | * 1. Allocated | |
3045 | * 2. Mapped to GTT | |
3046 | * 3. Read/written by GPU | |
3047 | * 4. set_domain to (CPU,CPU) | |
3048 | * 5. Read/written by CPU | |
3049 | * 6. Read/written by GPU | |
3050 | * | |
3051 | * 1. Allocated | |
3052 | * Same as last example, (CPU, CPU) | |
3053 | * 2. Mapped to GTT | |
3054 | * Nothing changes (assertions find that it is not in the GPU) | |
3055 | * 3. Read/written by GPU | |
3056 | * execbuffer calls set_domain (RENDER, RENDER) | |
3057 | * flush_domains gets CPU | |
3058 | * invalidate_domains gets GPU | |
3059 | * clflush (obj) | |
3060 | * MI_FLUSH and drm_agp_chipset_flush | |
3061 | * 4. set_domain (CPU, CPU) | |
3062 | * flush_domains gets GPU | |
3063 | * invalidate_domains gets CPU | |
3064 | * wait_rendering (obj) to make sure all drawing is complete. | |
3065 | * This will include an MI_FLUSH to get the data from GPU | |
3066 | * to memory | |
3067 | * clflush (obj) to invalidate the CPU cache | |
3068 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3069 | * 5. Read/written by CPU | |
3070 | * cache lines are loaded and dirtied | |
3071 | * 6. Read written by GPU | |
3072 | * Same as last GPU access | |
3073 | * | |
3074 | * Case 3: The constant buffer | |
3075 | * | |
3076 | * 1. Allocated | |
3077 | * 2. Written by CPU | |
3078 | * 3. Read by GPU | |
3079 | * 4. Updated (written) by CPU again | |
3080 | * 5. Read by GPU | |
3081 | * | |
3082 | * 1. Allocated | |
3083 | * (CPU, CPU) | |
3084 | * 2. Written by CPU | |
3085 | * (CPU, CPU) | |
3086 | * 3. Read by GPU | |
3087 | * (CPU+RENDER, 0) | |
3088 | * flush_domains = CPU | |
3089 | * invalidate_domains = RENDER | |
3090 | * clflush (obj) | |
3091 | * MI_FLUSH | |
3092 | * drm_agp_chipset_flush | |
3093 | * 4. Updated (written) by CPU again | |
3094 | * (CPU, CPU) | |
3095 | * flush_domains = 0 (no previous write domain) | |
3096 | * invalidate_domains = 0 (no new read domains) | |
3097 | * 5. Read by GPU | |
3098 | * (CPU+RENDER, 0) | |
3099 | * flush_domains = CPU | |
3100 | * invalidate_domains = RENDER | |
3101 | * clflush (obj) | |
3102 | * MI_FLUSH | |
3103 | * drm_agp_chipset_flush | |
3104 | */ | |
c0d90829 | 3105 | static void |
8b0e378a | 3106 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
3107 | { |
3108 | struct drm_device *dev = obj->dev; | |
23010e43 | 3109 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3110 | uint32_t invalidate_domains = 0; |
3111 | uint32_t flush_domains = 0; | |
1c5d22f7 | 3112 | uint32_t old_read_domains; |
e47c68e9 | 3113 | |
8b0e378a EA |
3114 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
3115 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 3116 | |
652c393a JB |
3117 | intel_mark_busy(dev, obj); |
3118 | ||
673a394b EA |
3119 | #if WATCH_BUF |
3120 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", | |
3121 | __func__, obj, | |
8b0e378a EA |
3122 | obj->read_domains, obj->pending_read_domains, |
3123 | obj->write_domain, obj->pending_write_domain); | |
673a394b EA |
3124 | #endif |
3125 | /* | |
3126 | * If the object isn't moving to a new write domain, | |
3127 | * let the object stay in multiple read domains | |
3128 | */ | |
8b0e378a EA |
3129 | if (obj->pending_write_domain == 0) |
3130 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3131 | else |
3132 | obj_priv->dirty = 1; | |
3133 | ||
3134 | /* | |
3135 | * Flush the current write domain if | |
3136 | * the new read domains don't match. Invalidate | |
3137 | * any read domains which differ from the old | |
3138 | * write domain | |
3139 | */ | |
8b0e378a EA |
3140 | if (obj->write_domain && |
3141 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3142 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3143 | invalidate_domains |= |
3144 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3145 | } |
3146 | /* | |
3147 | * Invalidate any read caches which may have | |
3148 | * stale data. That is, any new read domains. | |
3149 | */ | |
8b0e378a | 3150 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
673a394b EA |
3151 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
3152 | #if WATCH_BUF | |
3153 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", | |
3154 | __func__, flush_domains, invalidate_domains); | |
3155 | #endif | |
673a394b EA |
3156 | i915_gem_clflush_object(obj); |
3157 | } | |
3158 | ||
1c5d22f7 CW |
3159 | old_read_domains = obj->read_domains; |
3160 | ||
efbeed96 EA |
3161 | /* The actual obj->write_domain will be updated with |
3162 | * pending_write_domain after we emit the accumulated flush for all | |
3163 | * of our domain changes in execbuffers (which clears objects' | |
3164 | * write_domains). So if we have a current write domain that we | |
3165 | * aren't changing, set pending_write_domain to that. | |
3166 | */ | |
3167 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3168 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3169 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
3170 | |
3171 | dev->invalidate_domains |= invalidate_domains; | |
3172 | dev->flush_domains |= flush_domains; | |
3173 | #if WATCH_BUF | |
3174 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", | |
3175 | __func__, | |
3176 | obj->read_domains, obj->write_domain, | |
3177 | dev->invalidate_domains, dev->flush_domains); | |
3178 | #endif | |
1c5d22f7 CW |
3179 | |
3180 | trace_i915_gem_object_change_domain(obj, | |
3181 | old_read_domains, | |
3182 | obj->write_domain); | |
673a394b EA |
3183 | } |
3184 | ||
3185 | /** | |
e47c68e9 | 3186 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3187 | * |
e47c68e9 EA |
3188 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3189 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3190 | */ |
e47c68e9 EA |
3191 | static void |
3192 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3193 | { |
23010e43 | 3194 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3195 | |
e47c68e9 EA |
3196 | if (!obj_priv->page_cpu_valid) |
3197 | return; | |
3198 | ||
3199 | /* If we're partially in the CPU read domain, finish moving it in. | |
3200 | */ | |
3201 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3202 | int i; | |
3203 | ||
3204 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3205 | if (obj_priv->page_cpu_valid[i]) | |
3206 | continue; | |
856fa198 | 3207 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3208 | } |
e47c68e9 EA |
3209 | } |
3210 | ||
3211 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3212 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3213 | */ | |
9a298b2a | 3214 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3215 | obj_priv->page_cpu_valid = NULL; |
3216 | } | |
3217 | ||
3218 | /** | |
3219 | * Set the CPU read domain on a range of the object. | |
3220 | * | |
3221 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3222 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3223 | * pages have been flushed, and will be respected by | |
3224 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3225 | * of the whole object. | |
3226 | * | |
3227 | * This function returns when the move is complete, including waiting on | |
3228 | * flushes to occur. | |
3229 | */ | |
3230 | static int | |
3231 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3232 | uint64_t offset, uint64_t size) | |
3233 | { | |
23010e43 | 3234 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3235 | uint32_t old_read_domains; |
e47c68e9 | 3236 | int i, ret; |
673a394b | 3237 | |
e47c68e9 EA |
3238 | if (offset == 0 && size == obj->size) |
3239 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3240 | |
e47c68e9 EA |
3241 | i915_gem_object_flush_gpu_write_domain(obj); |
3242 | /* Wait on any GPU rendering and flushing to occur. */ | |
6a47baa6 | 3243 | ret = i915_gem_object_wait_rendering(obj); |
e47c68e9 | 3244 | if (ret != 0) |
6a47baa6 | 3245 | return ret; |
e47c68e9 EA |
3246 | i915_gem_object_flush_gtt_write_domain(obj); |
3247 | ||
3248 | /* If we're already fully in the CPU read domain, we're done. */ | |
3249 | if (obj_priv->page_cpu_valid == NULL && | |
3250 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3251 | return 0; | |
673a394b | 3252 | |
e47c68e9 EA |
3253 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3254 | * newly adding I915_GEM_DOMAIN_CPU | |
3255 | */ | |
673a394b | 3256 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3257 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3258 | GFP_KERNEL); | |
e47c68e9 EA |
3259 | if (obj_priv->page_cpu_valid == NULL) |
3260 | return -ENOMEM; | |
3261 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3262 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3263 | |
3264 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3265 | * perspective. | |
3266 | */ | |
e47c68e9 EA |
3267 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3268 | i++) { | |
673a394b EA |
3269 | if (obj_priv->page_cpu_valid[i]) |
3270 | continue; | |
3271 | ||
856fa198 | 3272 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3273 | |
3274 | obj_priv->page_cpu_valid[i] = 1; | |
3275 | } | |
3276 | ||
e47c68e9 EA |
3277 | /* It should now be out of any other write domains, and we can update |
3278 | * the domain values for our changes. | |
3279 | */ | |
3280 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3281 | ||
1c5d22f7 | 3282 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3283 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3284 | ||
1c5d22f7 CW |
3285 | trace_i915_gem_object_change_domain(obj, |
3286 | old_read_domains, | |
3287 | obj->write_domain); | |
3288 | ||
673a394b EA |
3289 | return 0; |
3290 | } | |
3291 | ||
673a394b EA |
3292 | /** |
3293 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3294 | */ | |
3295 | static int | |
3296 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3297 | struct drm_file *file_priv, | |
76446cac | 3298 | struct drm_i915_gem_exec_object2 *entry, |
40a5f0de | 3299 | struct drm_i915_gem_relocation_entry *relocs) |
673a394b EA |
3300 | { |
3301 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3302 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 3303 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3304 | int i, ret; |
0839ccb8 | 3305 | void __iomem *reloc_page; |
76446cac JB |
3306 | bool need_fence; |
3307 | ||
3308 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3309 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3310 | ||
3311 | /* Check fence reg constraints and rebind if necessary */ | |
f590d279 OA |
3312 | if (need_fence && !i915_gem_object_fence_offset_ok(obj, |
3313 | obj_priv->tiling_mode)) | |
76446cac | 3314 | i915_gem_object_unbind(obj); |
673a394b EA |
3315 | |
3316 | /* Choose the GTT offset for our buffer and put it there. */ | |
3317 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3318 | if (ret) | |
3319 | return ret; | |
3320 | ||
76446cac JB |
3321 | /* |
3322 | * Pre-965 chips need a fence register set up in order to | |
3323 | * properly handle blits to/from tiled surfaces. | |
3324 | */ | |
3325 | if (need_fence) { | |
3326 | ret = i915_gem_object_get_fence_reg(obj); | |
3327 | if (ret != 0) { | |
3328 | if (ret != -EBUSY && ret != -ERESTARTSYS) | |
3329 | DRM_ERROR("Failure to install fence: %d\n", | |
3330 | ret); | |
3331 | i915_gem_object_unpin(obj); | |
3332 | return ret; | |
3333 | } | |
3334 | } | |
3335 | ||
673a394b EA |
3336 | entry->offset = obj_priv->gtt_offset; |
3337 | ||
673a394b EA |
3338 | /* Apply the relocations, using the GTT aperture to avoid cache |
3339 | * flushing requirements. | |
3340 | */ | |
3341 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 3342 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
3343 | struct drm_gem_object *target_obj; |
3344 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
3345 | uint32_t reloc_val, reloc_offset; |
3346 | uint32_t __iomem *reloc_entry; | |
673a394b | 3347 | |
673a394b | 3348 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 3349 | reloc->target_handle); |
673a394b EA |
3350 | if (target_obj == NULL) { |
3351 | i915_gem_object_unpin(obj); | |
3352 | return -EBADF; | |
3353 | } | |
23010e43 | 3354 | target_obj_priv = to_intel_bo(target_obj); |
673a394b | 3355 | |
8542a0bb CW |
3356 | #if WATCH_RELOC |
3357 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3358 | "read %08x write %08x gtt %08x " | |
3359 | "presumed %08x delta %08x\n", | |
3360 | __func__, | |
3361 | obj, | |
3362 | (int) reloc->offset, | |
3363 | (int) reloc->target_handle, | |
3364 | (int) reloc->read_domains, | |
3365 | (int) reloc->write_domain, | |
3366 | (int) target_obj_priv->gtt_offset, | |
3367 | (int) reloc->presumed_offset, | |
3368 | reloc->delta); | |
3369 | #endif | |
3370 | ||
673a394b EA |
3371 | /* The target buffer should have appeared before us in the |
3372 | * exec_object list, so it should have a GTT space bound by now. | |
3373 | */ | |
3374 | if (target_obj_priv->gtt_space == NULL) { | |
3375 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 3376 | reloc->target_handle); |
673a394b EA |
3377 | drm_gem_object_unreference(target_obj); |
3378 | i915_gem_object_unpin(obj); | |
3379 | return -EINVAL; | |
3380 | } | |
3381 | ||
8542a0bb | 3382 | /* Validate that the target is in a valid r/w GPU domain */ |
16edd550 DV |
3383 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
3384 | DRM_ERROR("reloc with multiple write domains: " | |
3385 | "obj %p target %d offset %d " | |
3386 | "read %08x write %08x", | |
3387 | obj, reloc->target_handle, | |
3388 | (int) reloc->offset, | |
3389 | reloc->read_domains, | |
3390 | reloc->write_domain); | |
3391 | return -EINVAL; | |
3392 | } | |
40a5f0de EA |
3393 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3394 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3395 | DRM_ERROR("reloc with read/write CPU domains: " |
3396 | "obj %p target %d offset %d " | |
3397 | "read %08x write %08x", | |
40a5f0de EA |
3398 | obj, reloc->target_handle, |
3399 | (int) reloc->offset, | |
3400 | reloc->read_domains, | |
3401 | reloc->write_domain); | |
491152b8 CW |
3402 | drm_gem_object_unreference(target_obj); |
3403 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3404 | return -EINVAL; |
3405 | } | |
40a5f0de EA |
3406 | if (reloc->write_domain && target_obj->pending_write_domain && |
3407 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3408 | DRM_ERROR("Write domain conflict: " |
3409 | "obj %p target %d offset %d " | |
3410 | "new %08x old %08x\n", | |
40a5f0de EA |
3411 | obj, reloc->target_handle, |
3412 | (int) reloc->offset, | |
3413 | reloc->write_domain, | |
673a394b EA |
3414 | target_obj->pending_write_domain); |
3415 | drm_gem_object_unreference(target_obj); | |
3416 | i915_gem_object_unpin(obj); | |
3417 | return -EINVAL; | |
3418 | } | |
3419 | ||
40a5f0de EA |
3420 | target_obj->pending_read_domains |= reloc->read_domains; |
3421 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3422 | |
3423 | /* If the relocation already has the right value in it, no | |
3424 | * more work needs to be done. | |
3425 | */ | |
40a5f0de | 3426 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3427 | drm_gem_object_unreference(target_obj); |
3428 | continue; | |
3429 | } | |
3430 | ||
8542a0bb CW |
3431 | /* Check that the relocation address is valid... */ |
3432 | if (reloc->offset > obj->size - 4) { | |
3433 | DRM_ERROR("Relocation beyond object bounds: " | |
3434 | "obj %p target %d offset %d size %d.\n", | |
3435 | obj, reloc->target_handle, | |
3436 | (int) reloc->offset, (int) obj->size); | |
3437 | drm_gem_object_unreference(target_obj); | |
3438 | i915_gem_object_unpin(obj); | |
3439 | return -EINVAL; | |
3440 | } | |
3441 | if (reloc->offset & 3) { | |
3442 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3443 | "obj %p target %d offset %d.\n", | |
3444 | obj, reloc->target_handle, | |
3445 | (int) reloc->offset); | |
3446 | drm_gem_object_unreference(target_obj); | |
3447 | i915_gem_object_unpin(obj); | |
3448 | return -EINVAL; | |
3449 | } | |
3450 | ||
3451 | /* and points to somewhere within the target object. */ | |
3452 | if (reloc->delta >= target_obj->size) { | |
3453 | DRM_ERROR("Relocation beyond target object bounds: " | |
3454 | "obj %p target %d delta %d size %d.\n", | |
3455 | obj, reloc->target_handle, | |
3456 | (int) reloc->delta, (int) target_obj->size); | |
3457 | drm_gem_object_unreference(target_obj); | |
3458 | i915_gem_object_unpin(obj); | |
3459 | return -EINVAL; | |
3460 | } | |
3461 | ||
2ef7eeaa EA |
3462 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3463 | if (ret != 0) { | |
3464 | drm_gem_object_unreference(target_obj); | |
3465 | i915_gem_object_unpin(obj); | |
3466 | return -EINVAL; | |
673a394b EA |
3467 | } |
3468 | ||
3469 | /* Map the page containing the relocation we're going to | |
3470 | * perform. | |
3471 | */ | |
40a5f0de | 3472 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3473 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3474 | (reloc_offset & | |
3475 | ~(PAGE_SIZE - 1))); | |
3043c60c | 3476 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3477 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3478 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b EA |
3479 | |
3480 | #if WATCH_BUF | |
3481 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", | |
40a5f0de | 3482 | obj, (unsigned int) reloc->offset, |
673a394b EA |
3483 | readl(reloc_entry), reloc_val); |
3484 | #endif | |
3485 | writel(reloc_val, reloc_entry); | |
0839ccb8 | 3486 | io_mapping_unmap_atomic(reloc_page); |
673a394b | 3487 | |
40a5f0de EA |
3488 | /* The updated presumed offset for this entry will be |
3489 | * copied back out to the user. | |
673a394b | 3490 | */ |
40a5f0de | 3491 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3492 | |
3493 | drm_gem_object_unreference(target_obj); | |
3494 | } | |
3495 | ||
673a394b EA |
3496 | #if WATCH_BUF |
3497 | if (0) | |
3498 | i915_gem_dump_object(obj, 128, __func__, ~0); | |
3499 | #endif | |
3500 | return 0; | |
3501 | } | |
3502 | ||
673a394b EA |
3503 | /* Throttle our rendering by waiting until the ring has completed our requests |
3504 | * emitted over 20 msec ago. | |
3505 | * | |
b962442e EA |
3506 | * Note that if we were to use the current jiffies each time around the loop, |
3507 | * we wouldn't escape the function with any frames outstanding if the time to | |
3508 | * render a frame was over 20ms. | |
3509 | * | |
673a394b EA |
3510 | * This should get us reasonable parallelism between CPU and GPU but also |
3511 | * relatively low latency when blocking on a particular request to finish. | |
3512 | */ | |
3513 | static int | |
3514 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) | |
3515 | { | |
3516 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
3517 | int ret = 0; | |
b962442e | 3518 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
673a394b EA |
3519 | |
3520 | mutex_lock(&dev->struct_mutex); | |
b962442e EA |
3521 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
3522 | struct drm_i915_gem_request *request; | |
3523 | ||
3524 | request = list_first_entry(&i915_file_priv->mm.request_list, | |
3525 | struct drm_i915_gem_request, | |
3526 | client_list); | |
3527 | ||
3528 | if (time_after_eq(request->emitted_jiffies, recent_enough)) | |
3529 | break; | |
3530 | ||
852835f3 | 3531 | ret = i915_wait_request(dev, request->seqno, request->ring); |
b962442e EA |
3532 | if (ret != 0) |
3533 | break; | |
3534 | } | |
673a394b | 3535 | mutex_unlock(&dev->struct_mutex); |
b962442e | 3536 | |
673a394b EA |
3537 | return ret; |
3538 | } | |
3539 | ||
40a5f0de | 3540 | static int |
76446cac | 3541 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3542 | uint32_t buffer_count, |
3543 | struct drm_i915_gem_relocation_entry **relocs) | |
3544 | { | |
3545 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3546 | int ret; | |
3547 | ||
3548 | *relocs = NULL; | |
3549 | for (i = 0; i < buffer_count; i++) { | |
3550 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3551 | return -EINVAL; | |
3552 | reloc_count += exec_list[i].relocation_count; | |
3553 | } | |
3554 | ||
8e7d2b2c | 3555 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
76446cac JB |
3556 | if (*relocs == NULL) { |
3557 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); | |
40a5f0de | 3558 | return -ENOMEM; |
76446cac | 3559 | } |
40a5f0de EA |
3560 | |
3561 | for (i = 0; i < buffer_count; i++) { | |
3562 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3563 | ||
3564 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3565 | ||
3566 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3567 | user_relocs, | |
3568 | exec_list[i].relocation_count * | |
3569 | sizeof(**relocs)); | |
3570 | if (ret != 0) { | |
8e7d2b2c | 3571 | drm_free_large(*relocs); |
40a5f0de | 3572 | *relocs = NULL; |
2bc43b5c | 3573 | return -EFAULT; |
40a5f0de EA |
3574 | } |
3575 | ||
3576 | reloc_index += exec_list[i].relocation_count; | |
3577 | } | |
3578 | ||
2bc43b5c | 3579 | return 0; |
40a5f0de EA |
3580 | } |
3581 | ||
3582 | static int | |
76446cac | 3583 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3584 | uint32_t buffer_count, |
3585 | struct drm_i915_gem_relocation_entry *relocs) | |
3586 | { | |
3587 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3588 | int ret = 0; |
40a5f0de | 3589 | |
93533c29 CW |
3590 | if (relocs == NULL) |
3591 | return 0; | |
3592 | ||
40a5f0de EA |
3593 | for (i = 0; i < buffer_count; i++) { |
3594 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3595 | int unwritten; |
40a5f0de EA |
3596 | |
3597 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3598 | ||
2bc43b5c FM |
3599 | unwritten = copy_to_user(user_relocs, |
3600 | &relocs[reloc_count], | |
3601 | exec_list[i].relocation_count * | |
3602 | sizeof(*relocs)); | |
3603 | ||
3604 | if (unwritten) { | |
3605 | ret = -EFAULT; | |
3606 | goto err; | |
40a5f0de EA |
3607 | } |
3608 | ||
3609 | reloc_count += exec_list[i].relocation_count; | |
3610 | } | |
3611 | ||
2bc43b5c | 3612 | err: |
8e7d2b2c | 3613 | drm_free_large(relocs); |
40a5f0de EA |
3614 | |
3615 | return ret; | |
3616 | } | |
3617 | ||
83d60795 | 3618 | static int |
76446cac | 3619 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
83d60795 CW |
3620 | uint64_t exec_offset) |
3621 | { | |
3622 | uint32_t exec_start, exec_len; | |
3623 | ||
3624 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3625 | exec_len = (uint32_t) exec->batch_len; | |
3626 | ||
3627 | if ((exec_start | exec_len) & 0x7) | |
3628 | return -EINVAL; | |
3629 | ||
3630 | if (!exec_start) | |
3631 | return -EINVAL; | |
3632 | ||
3633 | return 0; | |
3634 | } | |
3635 | ||
6b95a207 KH |
3636 | static int |
3637 | i915_gem_wait_for_pending_flip(struct drm_device *dev, | |
3638 | struct drm_gem_object **object_list, | |
3639 | int count) | |
3640 | { | |
3641 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3642 | struct drm_i915_gem_object *obj_priv; | |
3643 | DEFINE_WAIT(wait); | |
3644 | int i, ret = 0; | |
3645 | ||
3646 | for (;;) { | |
3647 | prepare_to_wait(&dev_priv->pending_flip_queue, | |
3648 | &wait, TASK_INTERRUPTIBLE); | |
3649 | for (i = 0; i < count; i++) { | |
23010e43 | 3650 | obj_priv = to_intel_bo(object_list[i]); |
6b95a207 KH |
3651 | if (atomic_read(&obj_priv->pending_flip) > 0) |
3652 | break; | |
3653 | } | |
3654 | if (i == count) | |
3655 | break; | |
3656 | ||
3657 | if (!signal_pending(current)) { | |
3658 | mutex_unlock(&dev->struct_mutex); | |
3659 | schedule(); | |
3660 | mutex_lock(&dev->struct_mutex); | |
3661 | continue; | |
3662 | } | |
3663 | ret = -ERESTARTSYS; | |
3664 | break; | |
3665 | } | |
3666 | finish_wait(&dev_priv->pending_flip_queue, &wait); | |
3667 | ||
3668 | return ret; | |
3669 | } | |
3670 | ||
673a394b | 3671 | int |
76446cac JB |
3672 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
3673 | struct drm_file *file_priv, | |
3674 | struct drm_i915_gem_execbuffer2 *args, | |
3675 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3676 | { |
3677 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3678 | struct drm_gem_object **object_list = NULL; |
3679 | struct drm_gem_object *batch_obj; | |
b70d11da | 3680 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3681 | struct drm_clip_rect *cliprects = NULL; |
93533c29 | 3682 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
76446cac | 3683 | int ret = 0, ret2, i, pinned = 0; |
673a394b | 3684 | uint64_t exec_offset; |
40a5f0de | 3685 | uint32_t seqno, flush_domains, reloc_index; |
6b95a207 | 3686 | int pin_tries, flips; |
673a394b | 3687 | |
852835f3 ZN |
3688 | struct intel_ring_buffer *ring = NULL; |
3689 | ||
673a394b EA |
3690 | #if WATCH_EXEC |
3691 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3692 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3693 | #endif | |
d1b851fc ZN |
3694 | if (args->flags & I915_EXEC_BSD) { |
3695 | if (!HAS_BSD(dev)) { | |
3696 | DRM_ERROR("execbuf with wrong flag\n"); | |
3697 | return -EINVAL; | |
3698 | } | |
3699 | ring = &dev_priv->bsd_ring; | |
3700 | } else { | |
3701 | ring = &dev_priv->render_ring; | |
3702 | } | |
3703 | ||
673a394b | 3704 | |
4f481ed2 EA |
3705 | if (args->buffer_count < 1) { |
3706 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3707 | return -EINVAL; | |
3708 | } | |
c8e0f93a | 3709 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3710 | if (object_list == NULL) { |
3711 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3712 | args->buffer_count); |
3713 | ret = -ENOMEM; | |
3714 | goto pre_mutex_err; | |
3715 | } | |
673a394b | 3716 | |
201361a5 | 3717 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3718 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3719 | GFP_KERNEL); | |
a40e8d31 OA |
3720 | if (cliprects == NULL) { |
3721 | ret = -ENOMEM; | |
201361a5 | 3722 | goto pre_mutex_err; |
a40e8d31 | 3723 | } |
201361a5 EA |
3724 | |
3725 | ret = copy_from_user(cliprects, | |
3726 | (struct drm_clip_rect __user *) | |
3727 | (uintptr_t) args->cliprects_ptr, | |
3728 | sizeof(*cliprects) * args->num_cliprects); | |
3729 | if (ret != 0) { | |
3730 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3731 | args->num_cliprects, ret); | |
3732 | goto pre_mutex_err; | |
3733 | } | |
3734 | } | |
3735 | ||
40a5f0de EA |
3736 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3737 | &relocs); | |
3738 | if (ret != 0) | |
3739 | goto pre_mutex_err; | |
3740 | ||
673a394b EA |
3741 | mutex_lock(&dev->struct_mutex); |
3742 | ||
3743 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3744 | ||
ba1234d1 | 3745 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3746 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3747 | ret = -EIO; |
3748 | goto pre_mutex_err; | |
673a394b EA |
3749 | } |
3750 | ||
3751 | if (dev_priv->mm.suspended) { | |
673a394b | 3752 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3753 | ret = -EBUSY; |
3754 | goto pre_mutex_err; | |
673a394b EA |
3755 | } |
3756 | ||
ac94a962 | 3757 | /* Look up object handles */ |
6b95a207 | 3758 | flips = 0; |
673a394b EA |
3759 | for (i = 0; i < args->buffer_count; i++) { |
3760 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3761 | exec_list[i].handle); | |
3762 | if (object_list[i] == NULL) { | |
3763 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3764 | exec_list[i].handle, i); | |
0ce907f8 CW |
3765 | /* prevent error path from reading uninitialized data */ |
3766 | args->buffer_count = i + 1; | |
673a394b EA |
3767 | ret = -EBADF; |
3768 | goto err; | |
3769 | } | |
b70d11da | 3770 | |
23010e43 | 3771 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3772 | if (obj_priv->in_execbuffer) { |
3773 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3774 | object_list[i]); | |
0ce907f8 CW |
3775 | /* prevent error path from reading uninitialized data */ |
3776 | args->buffer_count = i + 1; | |
b70d11da KH |
3777 | ret = -EBADF; |
3778 | goto err; | |
3779 | } | |
3780 | obj_priv->in_execbuffer = true; | |
6b95a207 KH |
3781 | flips += atomic_read(&obj_priv->pending_flip); |
3782 | } | |
3783 | ||
3784 | if (flips > 0) { | |
3785 | ret = i915_gem_wait_for_pending_flip(dev, object_list, | |
3786 | args->buffer_count); | |
3787 | if (ret) | |
3788 | goto err; | |
ac94a962 | 3789 | } |
673a394b | 3790 | |
ac94a962 KP |
3791 | /* Pin and relocate */ |
3792 | for (pin_tries = 0; ; pin_tries++) { | |
3793 | ret = 0; | |
40a5f0de EA |
3794 | reloc_index = 0; |
3795 | ||
ac94a962 KP |
3796 | for (i = 0; i < args->buffer_count; i++) { |
3797 | object_list[i]->pending_read_domains = 0; | |
3798 | object_list[i]->pending_write_domain = 0; | |
3799 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3800 | file_priv, | |
40a5f0de EA |
3801 | &exec_list[i], |
3802 | &relocs[reloc_index]); | |
ac94a962 KP |
3803 | if (ret) |
3804 | break; | |
3805 | pinned = i + 1; | |
40a5f0de | 3806 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3807 | } |
3808 | /* success */ | |
3809 | if (ret == 0) | |
3810 | break; | |
3811 | ||
3812 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3813 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3814 | if (ret != -ERESTARTSYS) { |
3815 | unsigned long long total_size = 0; | |
3816 | for (i = 0; i < args->buffer_count; i++) | |
3817 | total_size += object_list[i]->size; | |
3818 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n", | |
3819 | pinned+1, args->buffer_count, | |
3820 | total_size, ret); | |
3821 | DRM_ERROR("%d objects [%d pinned], " | |
3822 | "%d object bytes [%d pinned], " | |
3823 | "%d/%d gtt bytes\n", | |
3824 | atomic_read(&dev->object_count), | |
3825 | atomic_read(&dev->pin_count), | |
3826 | atomic_read(&dev->object_memory), | |
3827 | atomic_read(&dev->pin_memory), | |
3828 | atomic_read(&dev->gtt_memory), | |
3829 | dev->gtt_total); | |
3830 | } | |
673a394b EA |
3831 | goto err; |
3832 | } | |
ac94a962 KP |
3833 | |
3834 | /* unpin all of our buffers */ | |
3835 | for (i = 0; i < pinned; i++) | |
3836 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3837 | pinned = 0; |
ac94a962 KP |
3838 | |
3839 | /* evict everyone we can from the aperture */ | |
3840 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3841 | if (ret && ret != -ENOSPC) |
ac94a962 | 3842 | goto err; |
673a394b EA |
3843 | } |
3844 | ||
3845 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3846 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3847 | if (batch_obj->pending_write_domain) { |
3848 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3849 | ret = -EINVAL; | |
3850 | goto err; | |
3851 | } | |
3852 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3853 | |
83d60795 CW |
3854 | /* Sanity check the batch buffer, prior to moving objects */ |
3855 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3856 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3857 | if (ret != 0) { | |
3858 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3859 | goto err; | |
3860 | } | |
3861 | ||
673a394b EA |
3862 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3863 | ||
646f0f6e KP |
3864 | /* Zero the global flush/invalidate flags. These |
3865 | * will be modified as new domains are computed | |
3866 | * for each object | |
3867 | */ | |
3868 | dev->invalidate_domains = 0; | |
3869 | dev->flush_domains = 0; | |
3870 | ||
673a394b EA |
3871 | for (i = 0; i < args->buffer_count; i++) { |
3872 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3873 | |
646f0f6e | 3874 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3875 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3876 | } |
3877 | ||
3878 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3879 | ||
646f0f6e KP |
3880 | if (dev->invalidate_domains | dev->flush_domains) { |
3881 | #if WATCH_EXEC | |
3882 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3883 | __func__, | |
3884 | dev->invalidate_domains, | |
3885 | dev->flush_domains); | |
3886 | #endif | |
3887 | i915_gem_flush(dev, | |
3888 | dev->invalidate_domains, | |
3889 | dev->flush_domains); | |
852835f3 | 3890 | if (dev->flush_domains & I915_GEM_GPU_DOMAINS) { |
b962442e | 3891 | (void)i915_add_request(dev, file_priv, |
852835f3 ZN |
3892 | dev->flush_domains, |
3893 | &dev_priv->render_ring); | |
3894 | ||
d1b851fc ZN |
3895 | if (HAS_BSD(dev)) |
3896 | (void)i915_add_request(dev, file_priv, | |
3897 | dev->flush_domains, | |
3898 | &dev_priv->bsd_ring); | |
852835f3 | 3899 | } |
646f0f6e | 3900 | } |
673a394b | 3901 | |
efbeed96 EA |
3902 | for (i = 0; i < args->buffer_count; i++) { |
3903 | struct drm_gem_object *obj = object_list[i]; | |
23010e43 | 3904 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3905 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3906 | |
3907 | obj->write_domain = obj->pending_write_domain; | |
99fcb766 DV |
3908 | if (obj->write_domain) |
3909 | list_move_tail(&obj_priv->gpu_write_list, | |
3910 | &dev_priv->mm.gpu_write_list); | |
3911 | else | |
3912 | list_del_init(&obj_priv->gpu_write_list); | |
3913 | ||
1c5d22f7 CW |
3914 | trace_i915_gem_object_change_domain(obj, |
3915 | obj->read_domains, | |
3916 | old_write_domain); | |
efbeed96 EA |
3917 | } |
3918 | ||
673a394b EA |
3919 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3920 | ||
3921 | #if WATCH_COHERENCY | |
3922 | for (i = 0; i < args->buffer_count; i++) { | |
3923 | i915_gem_object_check_coherency(object_list[i], | |
3924 | exec_list[i].handle); | |
3925 | } | |
3926 | #endif | |
3927 | ||
673a394b | 3928 | #if WATCH_EXEC |
6911a9b8 | 3929 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3930 | args->batch_len, |
3931 | __func__, | |
3932 | ~0); | |
3933 | #endif | |
3934 | ||
673a394b | 3935 | /* Exec the batchbuffer */ |
852835f3 ZN |
3936 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
3937 | cliprects, exec_offset); | |
673a394b EA |
3938 | if (ret) { |
3939 | DRM_ERROR("dispatch failed %d\n", ret); | |
3940 | goto err; | |
3941 | } | |
3942 | ||
3943 | /* | |
3944 | * Ensure that the commands in the batch buffer are | |
3945 | * finished before the interrupt fires | |
3946 | */ | |
852835f3 | 3947 | flush_domains = i915_retire_commands(dev, ring); |
673a394b EA |
3948 | |
3949 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3950 | ||
3951 | /* | |
3952 | * Get a seqno representing the execution of the current buffer, | |
3953 | * which we can wait on. We would like to mitigate these interrupts, | |
3954 | * likely by only creating seqnos occasionally (so that we have | |
3955 | * *some* interrupts representing completion of buffers that we can | |
3956 | * wait on when trying to clear up gtt space). | |
3957 | */ | |
852835f3 | 3958 | seqno = i915_add_request(dev, file_priv, flush_domains, ring); |
673a394b | 3959 | BUG_ON(seqno == 0); |
673a394b EA |
3960 | for (i = 0; i < args->buffer_count; i++) { |
3961 | struct drm_gem_object *obj = object_list[i]; | |
852835f3 | 3962 | obj_priv = to_intel_bo(obj); |
673a394b | 3963 | |
852835f3 | 3964 | i915_gem_object_move_to_active(obj, seqno, ring); |
673a394b EA |
3965 | #if WATCH_LRU |
3966 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); | |
3967 | #endif | |
3968 | } | |
3969 | #if WATCH_LRU | |
3970 | i915_dump_lru(dev, __func__); | |
3971 | #endif | |
3972 | ||
3973 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3974 | ||
673a394b | 3975 | err: |
aad87dff JL |
3976 | for (i = 0; i < pinned; i++) |
3977 | i915_gem_object_unpin(object_list[i]); | |
3978 | ||
b70d11da KH |
3979 | for (i = 0; i < args->buffer_count; i++) { |
3980 | if (object_list[i]) { | |
23010e43 | 3981 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3982 | obj_priv->in_execbuffer = false; |
3983 | } | |
aad87dff | 3984 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3985 | } |
673a394b | 3986 | |
673a394b EA |
3987 | mutex_unlock(&dev->struct_mutex); |
3988 | ||
93533c29 | 3989 | pre_mutex_err: |
40a5f0de EA |
3990 | /* Copy the updated relocations out regardless of current error |
3991 | * state. Failure to update the relocs would mean that the next | |
3992 | * time userland calls execbuf, it would do so with presumed offset | |
3993 | * state that didn't match the actual object state. | |
3994 | */ | |
3995 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3996 | relocs); | |
3997 | if (ret2 != 0) { | |
3998 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3999 | ||
4000 | if (ret == 0) | |
4001 | ret = ret2; | |
4002 | } | |
4003 | ||
8e7d2b2c | 4004 | drm_free_large(object_list); |
9a298b2a | 4005 | kfree(cliprects); |
673a394b EA |
4006 | |
4007 | return ret; | |
4008 | } | |
4009 | ||
76446cac JB |
4010 | /* |
4011 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
4012 | * list array and passes it to the real function. | |
4013 | */ | |
4014 | int | |
4015 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
4016 | struct drm_file *file_priv) | |
4017 | { | |
4018 | struct drm_i915_gem_execbuffer *args = data; | |
4019 | struct drm_i915_gem_execbuffer2 exec2; | |
4020 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
4021 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4022 | int ret, i; | |
4023 | ||
4024 | #if WATCH_EXEC | |
4025 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4026 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4027 | #endif | |
4028 | ||
4029 | if (args->buffer_count < 1) { | |
4030 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4031 | return -EINVAL; | |
4032 | } | |
4033 | ||
4034 | /* Copy in the exec list from userland */ | |
4035 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4036 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4037 | if (exec_list == NULL || exec2_list == NULL) { | |
4038 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4039 | args->buffer_count); | |
4040 | drm_free_large(exec_list); | |
4041 | drm_free_large(exec2_list); | |
4042 | return -ENOMEM; | |
4043 | } | |
4044 | ret = copy_from_user(exec_list, | |
4045 | (struct drm_i915_relocation_entry __user *) | |
4046 | (uintptr_t) args->buffers_ptr, | |
4047 | sizeof(*exec_list) * args->buffer_count); | |
4048 | if (ret != 0) { | |
4049 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4050 | args->buffer_count, ret); | |
4051 | drm_free_large(exec_list); | |
4052 | drm_free_large(exec2_list); | |
4053 | return -EFAULT; | |
4054 | } | |
4055 | ||
4056 | for (i = 0; i < args->buffer_count; i++) { | |
4057 | exec2_list[i].handle = exec_list[i].handle; | |
4058 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4059 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4060 | exec2_list[i].alignment = exec_list[i].alignment; | |
4061 | exec2_list[i].offset = exec_list[i].offset; | |
4062 | if (!IS_I965G(dev)) | |
4063 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
4064 | else | |
4065 | exec2_list[i].flags = 0; | |
4066 | } | |
4067 | ||
4068 | exec2.buffers_ptr = args->buffers_ptr; | |
4069 | exec2.buffer_count = args->buffer_count; | |
4070 | exec2.batch_start_offset = args->batch_start_offset; | |
4071 | exec2.batch_len = args->batch_len; | |
4072 | exec2.DR1 = args->DR1; | |
4073 | exec2.DR4 = args->DR4; | |
4074 | exec2.num_cliprects = args->num_cliprects; | |
4075 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4076 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4077 | |
4078 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4079 | if (!ret) { | |
4080 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4081 | for (i = 0; i < args->buffer_count; i++) | |
4082 | exec_list[i].offset = exec2_list[i].offset; | |
4083 | /* ... and back out to userspace */ | |
4084 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4085 | (uintptr_t) args->buffers_ptr, | |
4086 | exec_list, | |
4087 | sizeof(*exec_list) * args->buffer_count); | |
4088 | if (ret) { | |
4089 | ret = -EFAULT; | |
4090 | DRM_ERROR("failed to copy %d exec entries " | |
4091 | "back to user (%d)\n", | |
4092 | args->buffer_count, ret); | |
4093 | } | |
76446cac JB |
4094 | } |
4095 | ||
4096 | drm_free_large(exec_list); | |
4097 | drm_free_large(exec2_list); | |
4098 | return ret; | |
4099 | } | |
4100 | ||
4101 | int | |
4102 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4103 | struct drm_file *file_priv) | |
4104 | { | |
4105 | struct drm_i915_gem_execbuffer2 *args = data; | |
4106 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4107 | int ret; | |
4108 | ||
4109 | #if WATCH_EXEC | |
4110 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4111 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4112 | #endif | |
4113 | ||
4114 | if (args->buffer_count < 1) { | |
4115 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4116 | return -EINVAL; | |
4117 | } | |
4118 | ||
4119 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4120 | if (exec2_list == NULL) { | |
4121 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4122 | args->buffer_count); | |
4123 | return -ENOMEM; | |
4124 | } | |
4125 | ret = copy_from_user(exec2_list, | |
4126 | (struct drm_i915_relocation_entry __user *) | |
4127 | (uintptr_t) args->buffers_ptr, | |
4128 | sizeof(*exec2_list) * args->buffer_count); | |
4129 | if (ret != 0) { | |
4130 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4131 | args->buffer_count, ret); | |
4132 | drm_free_large(exec2_list); | |
4133 | return -EFAULT; | |
4134 | } | |
4135 | ||
4136 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4137 | if (!ret) { | |
4138 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4139 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4140 | (uintptr_t) args->buffers_ptr, | |
4141 | exec2_list, | |
4142 | sizeof(*exec2_list) * args->buffer_count); | |
4143 | if (ret) { | |
4144 | ret = -EFAULT; | |
4145 | DRM_ERROR("failed to copy %d exec entries " | |
4146 | "back to user (%d)\n", | |
4147 | args->buffer_count, ret); | |
4148 | } | |
4149 | } | |
4150 | ||
4151 | drm_free_large(exec2_list); | |
4152 | return ret; | |
4153 | } | |
4154 | ||
673a394b EA |
4155 | int |
4156 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
4157 | { | |
4158 | struct drm_device *dev = obj->dev; | |
23010e43 | 4159 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4160 | int ret; |
4161 | ||
778c3544 DV |
4162 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
4163 | ||
673a394b EA |
4164 | i915_verify_inactive(dev, __FILE__, __LINE__); |
4165 | if (obj_priv->gtt_space == NULL) { | |
4166 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 4167 | if (ret) |
673a394b | 4168 | return ret; |
22c344e9 | 4169 | } |
76446cac | 4170 | |
673a394b EA |
4171 | obj_priv->pin_count++; |
4172 | ||
4173 | /* If the object is not active and not pending a flush, | |
4174 | * remove it from the inactive list | |
4175 | */ | |
4176 | if (obj_priv->pin_count == 1) { | |
4177 | atomic_inc(&dev->pin_count); | |
4178 | atomic_add(obj->size, &dev->pin_memory); | |
4179 | if (!obj_priv->active && | |
21d509e3 | 4180 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && |
673a394b EA |
4181 | !list_empty(&obj_priv->list)) |
4182 | list_del_init(&obj_priv->list); | |
4183 | } | |
4184 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4185 | ||
4186 | return 0; | |
4187 | } | |
4188 | ||
4189 | void | |
4190 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4191 | { | |
4192 | struct drm_device *dev = obj->dev; | |
4193 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4194 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4195 | |
4196 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4197 | obj_priv->pin_count--; | |
4198 | BUG_ON(obj_priv->pin_count < 0); | |
4199 | BUG_ON(obj_priv->gtt_space == NULL); | |
4200 | ||
4201 | /* If the object is no longer pinned, and is | |
4202 | * neither active nor being flushed, then stick it on | |
4203 | * the inactive list | |
4204 | */ | |
4205 | if (obj_priv->pin_count == 0) { | |
4206 | if (!obj_priv->active && | |
21d509e3 | 4207 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
673a394b EA |
4208 | list_move_tail(&obj_priv->list, |
4209 | &dev_priv->mm.inactive_list); | |
4210 | atomic_dec(&dev->pin_count); | |
4211 | atomic_sub(obj->size, &dev->pin_memory); | |
4212 | } | |
4213 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4214 | } | |
4215 | ||
4216 | int | |
4217 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4218 | struct drm_file *file_priv) | |
4219 | { | |
4220 | struct drm_i915_gem_pin *args = data; | |
4221 | struct drm_gem_object *obj; | |
4222 | struct drm_i915_gem_object *obj_priv; | |
4223 | int ret; | |
4224 | ||
4225 | mutex_lock(&dev->struct_mutex); | |
4226 | ||
4227 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4228 | if (obj == NULL) { | |
4229 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
4230 | args->handle); | |
4231 | mutex_unlock(&dev->struct_mutex); | |
4232 | return -EBADF; | |
4233 | } | |
23010e43 | 4234 | obj_priv = to_intel_bo(obj); |
673a394b | 4235 | |
bb6baf76 CW |
4236 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4237 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
4238 | drm_gem_object_unreference(obj); |
4239 | mutex_unlock(&dev->struct_mutex); | |
4240 | return -EINVAL; | |
4241 | } | |
4242 | ||
79e53945 JB |
4243 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4244 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4245 | args->handle); | |
96dec61d | 4246 | drm_gem_object_unreference(obj); |
673a394b | 4247 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
4248 | return -EINVAL; |
4249 | } | |
4250 | ||
4251 | obj_priv->user_pin_count++; | |
4252 | obj_priv->pin_filp = file_priv; | |
4253 | if (obj_priv->user_pin_count == 1) { | |
4254 | ret = i915_gem_object_pin(obj, args->alignment); | |
4255 | if (ret != 0) { | |
4256 | drm_gem_object_unreference(obj); | |
4257 | mutex_unlock(&dev->struct_mutex); | |
4258 | return ret; | |
4259 | } | |
673a394b EA |
4260 | } |
4261 | ||
4262 | /* XXX - flush the CPU caches for pinned objects | |
4263 | * as the X server doesn't manage domains yet | |
4264 | */ | |
e47c68e9 | 4265 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
4266 | args->offset = obj_priv->gtt_offset; |
4267 | drm_gem_object_unreference(obj); | |
4268 | mutex_unlock(&dev->struct_mutex); | |
4269 | ||
4270 | return 0; | |
4271 | } | |
4272 | ||
4273 | int | |
4274 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4275 | struct drm_file *file_priv) | |
4276 | { | |
4277 | struct drm_i915_gem_pin *args = data; | |
4278 | struct drm_gem_object *obj; | |
79e53945 | 4279 | struct drm_i915_gem_object *obj_priv; |
673a394b EA |
4280 | |
4281 | mutex_lock(&dev->struct_mutex); | |
4282 | ||
4283 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4284 | if (obj == NULL) { | |
4285 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
4286 | args->handle); | |
4287 | mutex_unlock(&dev->struct_mutex); | |
4288 | return -EBADF; | |
4289 | } | |
4290 | ||
23010e43 | 4291 | obj_priv = to_intel_bo(obj); |
79e53945 JB |
4292 | if (obj_priv->pin_filp != file_priv) { |
4293 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4294 | args->handle); | |
4295 | drm_gem_object_unreference(obj); | |
4296 | mutex_unlock(&dev->struct_mutex); | |
4297 | return -EINVAL; | |
4298 | } | |
4299 | obj_priv->user_pin_count--; | |
4300 | if (obj_priv->user_pin_count == 0) { | |
4301 | obj_priv->pin_filp = NULL; | |
4302 | i915_gem_object_unpin(obj); | |
4303 | } | |
673a394b EA |
4304 | |
4305 | drm_gem_object_unreference(obj); | |
4306 | mutex_unlock(&dev->struct_mutex); | |
4307 | return 0; | |
4308 | } | |
4309 | ||
4310 | int | |
4311 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4312 | struct drm_file *file_priv) | |
4313 | { | |
4314 | struct drm_i915_gem_busy *args = data; | |
4315 | struct drm_gem_object *obj; | |
4316 | struct drm_i915_gem_object *obj_priv; | |
852835f3 | 4317 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 4318 | |
673a394b EA |
4319 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4320 | if (obj == NULL) { | |
4321 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4322 | args->handle); | |
673a394b EA |
4323 | return -EBADF; |
4324 | } | |
4325 | ||
b1ce786c | 4326 | mutex_lock(&dev->struct_mutex); |
f21289b3 EA |
4327 | /* Update the active list for the hardware's current position. |
4328 | * Otherwise this only updates on a delayed timer or when irqs are | |
4329 | * actually unmasked, and our working set ends up being larger than | |
4330 | * required. | |
4331 | */ | |
852835f3 | 4332 | i915_gem_retire_requests(dev, &dev_priv->render_ring); |
f21289b3 | 4333 | |
d1b851fc ZN |
4334 | if (HAS_BSD(dev)) |
4335 | i915_gem_retire_requests(dev, &dev_priv->bsd_ring); | |
4336 | ||
23010e43 | 4337 | obj_priv = to_intel_bo(obj); |
c4de0a5d EA |
4338 | /* Don't count being on the flushing list against the object being |
4339 | * done. Otherwise, a buffer left on the flushing list but not getting | |
4340 | * flushed (because nobody's flushing that domain) won't ever return | |
4341 | * unbusy and get reused by libdrm's bo cache. The other expected | |
4342 | * consumer of this interface, OpenGL's occlusion queries, also specs | |
4343 | * that the objects get unbusy "eventually" without any interference. | |
4344 | */ | |
4345 | args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; | |
673a394b EA |
4346 | |
4347 | drm_gem_object_unreference(obj); | |
4348 | mutex_unlock(&dev->struct_mutex); | |
4349 | return 0; | |
4350 | } | |
4351 | ||
4352 | int | |
4353 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4354 | struct drm_file *file_priv) | |
4355 | { | |
4356 | return i915_gem_ring_throttle(dev, file_priv); | |
4357 | } | |
4358 | ||
3ef94daa CW |
4359 | int |
4360 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4361 | struct drm_file *file_priv) | |
4362 | { | |
4363 | struct drm_i915_gem_madvise *args = data; | |
4364 | struct drm_gem_object *obj; | |
4365 | struct drm_i915_gem_object *obj_priv; | |
4366 | ||
4367 | switch (args->madv) { | |
4368 | case I915_MADV_DONTNEED: | |
4369 | case I915_MADV_WILLNEED: | |
4370 | break; | |
4371 | default: | |
4372 | return -EINVAL; | |
4373 | } | |
4374 | ||
4375 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4376 | if (obj == NULL) { | |
4377 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4378 | args->handle); | |
4379 | return -EBADF; | |
4380 | } | |
4381 | ||
4382 | mutex_lock(&dev->struct_mutex); | |
23010e43 | 4383 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4384 | |
4385 | if (obj_priv->pin_count) { | |
4386 | drm_gem_object_unreference(obj); | |
4387 | mutex_unlock(&dev->struct_mutex); | |
4388 | ||
4389 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4390 | return -EINVAL; | |
4391 | } | |
4392 | ||
bb6baf76 CW |
4393 | if (obj_priv->madv != __I915_MADV_PURGED) |
4394 | obj_priv->madv = args->madv; | |
3ef94daa | 4395 | |
2d7ef395 CW |
4396 | /* if the object is no longer bound, discard its backing storage */ |
4397 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4398 | obj_priv->gtt_space == NULL) | |
4399 | i915_gem_object_truncate(obj); | |
4400 | ||
bb6baf76 CW |
4401 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4402 | ||
3ef94daa CW |
4403 | drm_gem_object_unreference(obj); |
4404 | mutex_unlock(&dev->struct_mutex); | |
4405 | ||
4406 | return 0; | |
4407 | } | |
4408 | ||
ac52bc56 DV |
4409 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4410 | size_t size) | |
4411 | { | |
c397b908 | 4412 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4413 | |
c397b908 DV |
4414 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4415 | if (obj == NULL) | |
4416 | return NULL; | |
673a394b | 4417 | |
c397b908 DV |
4418 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4419 | kfree(obj); | |
4420 | return NULL; | |
4421 | } | |
673a394b | 4422 | |
c397b908 DV |
4423 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4424 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4425 | |
c397b908 | 4426 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4427 | obj->base.driver_private = NULL; |
c397b908 DV |
4428 | obj->fence_reg = I915_FENCE_REG_NONE; |
4429 | INIT_LIST_HEAD(&obj->list); | |
4430 | INIT_LIST_HEAD(&obj->gpu_write_list); | |
c397b908 | 4431 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4432 | |
c397b908 DV |
4433 | trace_i915_gem_object_create(&obj->base); |
4434 | ||
4435 | return &obj->base; | |
4436 | } | |
4437 | ||
4438 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4439 | { | |
4440 | BUG(); | |
de151cf6 | 4441 | |
673a394b EA |
4442 | return 0; |
4443 | } | |
4444 | ||
4445 | void i915_gem_free_object(struct drm_gem_object *obj) | |
4446 | { | |
de151cf6 | 4447 | struct drm_device *dev = obj->dev; |
23010e43 | 4448 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4449 | |
1c5d22f7 CW |
4450 | trace_i915_gem_object_destroy(obj); |
4451 | ||
673a394b EA |
4452 | while (obj_priv->pin_count > 0) |
4453 | i915_gem_object_unpin(obj); | |
4454 | ||
71acb5eb DA |
4455 | if (obj_priv->phys_obj) |
4456 | i915_gem_detach_phys_object(dev, obj); | |
4457 | ||
673a394b EA |
4458 | i915_gem_object_unbind(obj); |
4459 | ||
7e616158 CW |
4460 | if (obj_priv->mmap_offset) |
4461 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4462 | |
c397b908 DV |
4463 | drm_gem_object_release(obj); |
4464 | ||
9a298b2a | 4465 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4466 | kfree(obj_priv->bit_17); |
c397b908 | 4467 | kfree(obj_priv); |
673a394b EA |
4468 | } |
4469 | ||
ab5ee576 | 4470 | /** Unbinds all inactive objects. */ |
673a394b | 4471 | static int |
ab5ee576 | 4472 | i915_gem_evict_from_inactive_list(struct drm_device *dev) |
673a394b | 4473 | { |
ab5ee576 | 4474 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 4475 | |
ab5ee576 CW |
4476 | while (!list_empty(&dev_priv->mm.inactive_list)) { |
4477 | struct drm_gem_object *obj; | |
4478 | int ret; | |
673a394b | 4479 | |
a8089e84 DV |
4480 | obj = &list_first_entry(&dev_priv->mm.inactive_list, |
4481 | struct drm_i915_gem_object, | |
4482 | list)->base; | |
673a394b EA |
4483 | |
4484 | ret = i915_gem_object_unbind(obj); | |
4485 | if (ret != 0) { | |
ab5ee576 | 4486 | DRM_ERROR("Error unbinding object: %d\n", ret); |
673a394b EA |
4487 | return ret; |
4488 | } | |
4489 | } | |
4490 | ||
673a394b EA |
4491 | return 0; |
4492 | } | |
4493 | ||
29105ccc CW |
4494 | int |
4495 | i915_gem_idle(struct drm_device *dev) | |
4496 | { | |
4497 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4498 | int ret; | |
28dfe52a | 4499 | |
29105ccc | 4500 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4501 | |
8187a2b7 | 4502 | if (dev_priv->mm.suspended || |
d1b851fc ZN |
4503 | (dev_priv->render_ring.gem_object == NULL) || |
4504 | (HAS_BSD(dev) && | |
4505 | dev_priv->bsd_ring.gem_object == NULL)) { | |
29105ccc CW |
4506 | mutex_unlock(&dev->struct_mutex); |
4507 | return 0; | |
28dfe52a EA |
4508 | } |
4509 | ||
29105ccc | 4510 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4511 | if (ret) { |
4512 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4513 | return ret; |
6dbe2772 | 4514 | } |
673a394b | 4515 | |
29105ccc CW |
4516 | /* Under UMS, be paranoid and evict. */ |
4517 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
4518 | ret = i915_gem_evict_from_inactive_list(dev); | |
4519 | if (ret) { | |
4520 | mutex_unlock(&dev->struct_mutex); | |
4521 | return ret; | |
4522 | } | |
4523 | } | |
4524 | ||
4525 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4526 | * We need to replace this with a semaphore, or something. | |
4527 | * And not confound mm.suspended! | |
4528 | */ | |
4529 | dev_priv->mm.suspended = 1; | |
4530 | del_timer(&dev_priv->hangcheck_timer); | |
4531 | ||
4532 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4533 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4534 | |
6dbe2772 KP |
4535 | mutex_unlock(&dev->struct_mutex); |
4536 | ||
29105ccc CW |
4537 | /* Cancel the retire work handler, which should be idle now. */ |
4538 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4539 | ||
673a394b EA |
4540 | return 0; |
4541 | } | |
4542 | ||
e552eb70 JB |
4543 | /* |
4544 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4545 | * over cache flushing. | |
4546 | */ | |
8187a2b7 | 4547 | static int |
e552eb70 JB |
4548 | i915_gem_init_pipe_control(struct drm_device *dev) |
4549 | { | |
4550 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4551 | struct drm_gem_object *obj; | |
4552 | struct drm_i915_gem_object *obj_priv; | |
4553 | int ret; | |
4554 | ||
34dc4d44 | 4555 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4556 | if (obj == NULL) { |
4557 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4558 | ret = -ENOMEM; | |
4559 | goto err; | |
4560 | } | |
4561 | obj_priv = to_intel_bo(obj); | |
4562 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4563 | ||
4564 | ret = i915_gem_object_pin(obj, 4096); | |
4565 | if (ret) | |
4566 | goto err_unref; | |
4567 | ||
4568 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4569 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4570 | if (dev_priv->seqno_page == NULL) | |
4571 | goto err_unpin; | |
4572 | ||
4573 | dev_priv->seqno_obj = obj; | |
4574 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4575 | ||
4576 | return 0; | |
4577 | ||
4578 | err_unpin: | |
4579 | i915_gem_object_unpin(obj); | |
4580 | err_unref: | |
4581 | drm_gem_object_unreference(obj); | |
4582 | err: | |
4583 | return ret; | |
4584 | } | |
4585 | ||
8187a2b7 ZN |
4586 | |
4587 | static void | |
e552eb70 JB |
4588 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4589 | { | |
4590 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4591 | struct drm_gem_object *obj; | |
4592 | struct drm_i915_gem_object *obj_priv; | |
4593 | ||
4594 | obj = dev_priv->seqno_obj; | |
4595 | obj_priv = to_intel_bo(obj); | |
4596 | kunmap(obj_priv->pages[0]); | |
4597 | i915_gem_object_unpin(obj); | |
4598 | drm_gem_object_unreference(obj); | |
4599 | dev_priv->seqno_obj = NULL; | |
4600 | ||
4601 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4602 | } |
4603 | ||
8187a2b7 ZN |
4604 | int |
4605 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4606 | { | |
4607 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4608 | int ret; | |
4609 | dev_priv->render_ring = render_ring; | |
4610 | if (!I915_NEED_GFX_HWS(dev)) { | |
4611 | dev_priv->render_ring.status_page.page_addr | |
4612 | = dev_priv->status_page_dmah->vaddr; | |
4613 | memset(dev_priv->render_ring.status_page.page_addr, | |
4614 | 0, PAGE_SIZE); | |
4615 | } | |
4616 | if (HAS_PIPE_CONTROL(dev)) { | |
4617 | ret = i915_gem_init_pipe_control(dev); | |
4618 | if (ret) | |
4619 | return ret; | |
4620 | } | |
4621 | ret = intel_init_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4622 | if (!ret && HAS_BSD(dev)) { |
4623 | dev_priv->bsd_ring = bsd_ring; | |
4624 | ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
4625 | } | |
8187a2b7 ZN |
4626 | return ret; |
4627 | } | |
4628 | ||
4629 | void | |
4630 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4631 | { | |
4632 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4633 | ||
4634 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4635 | if (HAS_BSD(dev)) |
4636 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
8187a2b7 ZN |
4637 | if (HAS_PIPE_CONTROL(dev)) |
4638 | i915_gem_cleanup_pipe_control(dev); | |
4639 | } | |
4640 | ||
673a394b EA |
4641 | int |
4642 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4643 | struct drm_file *file_priv) | |
4644 | { | |
4645 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4646 | int ret; | |
4647 | ||
79e53945 JB |
4648 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4649 | return 0; | |
4650 | ||
ba1234d1 | 4651 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4652 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4653 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4654 | } |
4655 | ||
673a394b | 4656 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4657 | dev_priv->mm.suspended = 0; |
4658 | ||
4659 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4660 | if (ret != 0) { |
4661 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4662 | return ret; |
d816f6ac | 4663 | } |
9bb2d6f9 | 4664 | |
5e118f41 | 4665 | spin_lock(&dev_priv->mm.active_list_lock); |
852835f3 | 4666 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
d1b851fc | 4667 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
5e118f41 CW |
4668 | spin_unlock(&dev_priv->mm.active_list_lock); |
4669 | ||
673a394b EA |
4670 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4671 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4672 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
d1b851fc | 4673 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
673a394b | 4674 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 KH |
4675 | |
4676 | drm_irq_install(dev); | |
4677 | ||
673a394b EA |
4678 | return 0; |
4679 | } | |
4680 | ||
4681 | int | |
4682 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4683 | struct drm_file *file_priv) | |
4684 | { | |
79e53945 JB |
4685 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4686 | return 0; | |
4687 | ||
dbb19d30 | 4688 | drm_irq_uninstall(dev); |
e6890f6f | 4689 | return i915_gem_idle(dev); |
673a394b EA |
4690 | } |
4691 | ||
4692 | void | |
4693 | i915_gem_lastclose(struct drm_device *dev) | |
4694 | { | |
4695 | int ret; | |
673a394b | 4696 | |
e806b495 EA |
4697 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4698 | return; | |
4699 | ||
6dbe2772 KP |
4700 | ret = i915_gem_idle(dev); |
4701 | if (ret) | |
4702 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4703 | } |
4704 | ||
4705 | void | |
4706 | i915_gem_load(struct drm_device *dev) | |
4707 | { | |
b5aa8a0f | 4708 | int i; |
673a394b EA |
4709 | drm_i915_private_t *dev_priv = dev->dev_private; |
4710 | ||
5e118f41 | 4711 | spin_lock_init(&dev_priv->mm.active_list_lock); |
673a394b | 4712 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
99fcb766 | 4713 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
673a394b | 4714 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
a09ba7fa | 4715 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
852835f3 ZN |
4716 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
4717 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); | |
d1b851fc ZN |
4718 | if (HAS_BSD(dev)) { |
4719 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); | |
4720 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); | |
4721 | } | |
007cc8ac DV |
4722 | for (i = 0; i < 16; i++) |
4723 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4724 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4725 | i915_gem_retire_work_handler); | |
31169714 CW |
4726 | spin_lock(&shrink_list_lock); |
4727 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4728 | spin_unlock(&shrink_list_lock); | |
4729 | ||
de151cf6 | 4730 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4731 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4732 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4733 | |
0f973f27 | 4734 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4735 | dev_priv->num_fence_regs = 16; |
4736 | else | |
4737 | dev_priv->num_fence_regs = 8; | |
4738 | ||
b5aa8a0f GH |
4739 | /* Initialize fence registers to zero */ |
4740 | if (IS_I965G(dev)) { | |
4741 | for (i = 0; i < 16; i++) | |
4742 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
4743 | } else { | |
4744 | for (i = 0; i < 8; i++) | |
4745 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4746 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4747 | for (i = 0; i < 8; i++) | |
4748 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
4749 | } | |
673a394b | 4750 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4751 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4752 | } |
71acb5eb DA |
4753 | |
4754 | /* | |
4755 | * Create a physically contiguous memory object for this object | |
4756 | * e.g. for cursor + overlay regs | |
4757 | */ | |
4758 | int i915_gem_init_phys_object(struct drm_device *dev, | |
4759 | int id, int size) | |
4760 | { | |
4761 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4762 | struct drm_i915_gem_phys_object *phys_obj; | |
4763 | int ret; | |
4764 | ||
4765 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4766 | return 0; | |
4767 | ||
9a298b2a | 4768 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4769 | if (!phys_obj) |
4770 | return -ENOMEM; | |
4771 | ||
4772 | phys_obj->id = id; | |
4773 | ||
e6be8d9d | 4774 | phys_obj->handle = drm_pci_alloc(dev, size, 0); |
71acb5eb DA |
4775 | if (!phys_obj->handle) { |
4776 | ret = -ENOMEM; | |
4777 | goto kfree_obj; | |
4778 | } | |
4779 | #ifdef CONFIG_X86 | |
4780 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4781 | #endif | |
4782 | ||
4783 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4784 | ||
4785 | return 0; | |
4786 | kfree_obj: | |
9a298b2a | 4787 | kfree(phys_obj); |
71acb5eb DA |
4788 | return ret; |
4789 | } | |
4790 | ||
4791 | void i915_gem_free_phys_object(struct drm_device *dev, int id) | |
4792 | { | |
4793 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4794 | struct drm_i915_gem_phys_object *phys_obj; | |
4795 | ||
4796 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4797 | return; | |
4798 | ||
4799 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4800 | if (phys_obj->cur_obj) { | |
4801 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4802 | } | |
4803 | ||
4804 | #ifdef CONFIG_X86 | |
4805 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4806 | #endif | |
4807 | drm_pci_free(dev, phys_obj->handle); | |
4808 | kfree(phys_obj); | |
4809 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4810 | } | |
4811 | ||
4812 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4813 | { | |
4814 | int i; | |
4815 | ||
260883c8 | 4816 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4817 | i915_gem_free_phys_object(dev, i); |
4818 | } | |
4819 | ||
4820 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4821 | struct drm_gem_object *obj) | |
4822 | { | |
4823 | struct drm_i915_gem_object *obj_priv; | |
4824 | int i; | |
4825 | int ret; | |
4826 | int page_count; | |
4827 | ||
23010e43 | 4828 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4829 | if (!obj_priv->phys_obj) |
4830 | return; | |
4831 | ||
4bdadb97 | 4832 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4833 | if (ret) |
4834 | goto out; | |
4835 | ||
4836 | page_count = obj->size / PAGE_SIZE; | |
4837 | ||
4838 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4839 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4840 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4841 | ||
4842 | memcpy(dst, src, PAGE_SIZE); | |
4843 | kunmap_atomic(dst, KM_USER0); | |
4844 | } | |
856fa198 | 4845 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4846 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4847 | |
4848 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4849 | out: |
4850 | obj_priv->phys_obj->cur_obj = NULL; | |
4851 | obj_priv->phys_obj = NULL; | |
4852 | } | |
4853 | ||
4854 | int | |
4855 | i915_gem_attach_phys_object(struct drm_device *dev, | |
4856 | struct drm_gem_object *obj, int id) | |
4857 | { | |
4858 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4859 | struct drm_i915_gem_object *obj_priv; | |
4860 | int ret = 0; | |
4861 | int page_count; | |
4862 | int i; | |
4863 | ||
4864 | if (id > I915_MAX_PHYS_OBJECT) | |
4865 | return -EINVAL; | |
4866 | ||
23010e43 | 4867 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4868 | |
4869 | if (obj_priv->phys_obj) { | |
4870 | if (obj_priv->phys_obj->id == id) | |
4871 | return 0; | |
4872 | i915_gem_detach_phys_object(dev, obj); | |
4873 | } | |
4874 | ||
4875 | ||
4876 | /* create a new object */ | |
4877 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4878 | ret = i915_gem_init_phys_object(dev, id, | |
4879 | obj->size); | |
4880 | if (ret) { | |
aeb565df | 4881 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4882 | goto out; |
4883 | } | |
4884 | } | |
4885 | ||
4886 | /* bind to the object */ | |
4887 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4888 | obj_priv->phys_obj->cur_obj = obj; | |
4889 | ||
4bdadb97 | 4890 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4891 | if (ret) { |
4892 | DRM_ERROR("failed to get page list\n"); | |
4893 | goto out; | |
4894 | } | |
4895 | ||
4896 | page_count = obj->size / PAGE_SIZE; | |
4897 | ||
4898 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4899 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4900 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4901 | ||
4902 | memcpy(dst, src, PAGE_SIZE); | |
4903 | kunmap_atomic(src, KM_USER0); | |
4904 | } | |
4905 | ||
d78b47b9 CW |
4906 | i915_gem_object_put_pages(obj); |
4907 | ||
71acb5eb DA |
4908 | return 0; |
4909 | out: | |
4910 | return ret; | |
4911 | } | |
4912 | ||
4913 | static int | |
4914 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4915 | struct drm_i915_gem_pwrite *args, | |
4916 | struct drm_file *file_priv) | |
4917 | { | |
23010e43 | 4918 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4919 | void *obj_addr; |
4920 | int ret; | |
4921 | char __user *user_data; | |
4922 | ||
4923 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4924 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4925 | ||
44d98a61 | 4926 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4927 | ret = copy_from_user(obj_addr, user_data, args->size); |
4928 | if (ret) | |
4929 | return -EFAULT; | |
4930 | ||
4931 | drm_agp_chipset_flush(dev); | |
4932 | return 0; | |
4933 | } | |
b962442e EA |
4934 | |
4935 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) | |
4936 | { | |
4937 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
4938 | ||
4939 | /* Clean up our request list when the client is going away, so that | |
4940 | * later retire_requests won't dereference our soon-to-be-gone | |
4941 | * file_priv. | |
4942 | */ | |
4943 | mutex_lock(&dev->struct_mutex); | |
4944 | while (!list_empty(&i915_file_priv->mm.request_list)) | |
4945 | list_del_init(i915_file_priv->mm.request_list.next); | |
4946 | mutex_unlock(&dev->struct_mutex); | |
4947 | } | |
31169714 | 4948 | |
1637ef41 CW |
4949 | static int |
4950 | i915_gpu_is_active(struct drm_device *dev) | |
4951 | { | |
4952 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4953 | int lists_empty; | |
4954 | ||
4955 | spin_lock(&dev_priv->mm.active_list_lock); | |
4956 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && | |
852835f3 | 4957 | list_empty(&dev_priv->render_ring.active_list); |
d1b851fc ZN |
4958 | if (HAS_BSD(dev)) |
4959 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); | |
1637ef41 CW |
4960 | spin_unlock(&dev_priv->mm.active_list_lock); |
4961 | ||
4962 | return !lists_empty; | |
4963 | } | |
4964 | ||
31169714 CW |
4965 | static int |
4966 | i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask) | |
4967 | { | |
4968 | drm_i915_private_t *dev_priv, *next_dev; | |
4969 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4970 | int cnt = 0; | |
4971 | int would_deadlock = 1; | |
4972 | ||
4973 | /* "fast-path" to count number of available objects */ | |
4974 | if (nr_to_scan == 0) { | |
4975 | spin_lock(&shrink_list_lock); | |
4976 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4977 | struct drm_device *dev = dev_priv->dev; | |
4978 | ||
4979 | if (mutex_trylock(&dev->struct_mutex)) { | |
4980 | list_for_each_entry(obj_priv, | |
4981 | &dev_priv->mm.inactive_list, | |
4982 | list) | |
4983 | cnt++; | |
4984 | mutex_unlock(&dev->struct_mutex); | |
4985 | } | |
4986 | } | |
4987 | spin_unlock(&shrink_list_lock); | |
4988 | ||
4989 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4990 | } | |
4991 | ||
4992 | spin_lock(&shrink_list_lock); | |
4993 | ||
1637ef41 | 4994 | rescan: |
31169714 CW |
4995 | /* first scan for clean buffers */ |
4996 | list_for_each_entry_safe(dev_priv, next_dev, | |
4997 | &shrink_list, mm.shrink_list) { | |
4998 | struct drm_device *dev = dev_priv->dev; | |
4999 | ||
5000 | if (! mutex_trylock(&dev->struct_mutex)) | |
5001 | continue; | |
5002 | ||
5003 | spin_unlock(&shrink_list_lock); | |
852835f3 | 5004 | i915_gem_retire_requests(dev, &dev_priv->render_ring); |
d1b851fc ZN |
5005 | |
5006 | if (HAS_BSD(dev)) | |
5007 | i915_gem_retire_requests(dev, &dev_priv->bsd_ring); | |
31169714 CW |
5008 | |
5009 | list_for_each_entry_safe(obj_priv, next_obj, | |
5010 | &dev_priv->mm.inactive_list, | |
5011 | list) { | |
5012 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
a8089e84 | 5013 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5014 | if (--nr_to_scan <= 0) |
5015 | break; | |
5016 | } | |
5017 | } | |
5018 | ||
5019 | spin_lock(&shrink_list_lock); | |
5020 | mutex_unlock(&dev->struct_mutex); | |
5021 | ||
963b4836 CW |
5022 | would_deadlock = 0; |
5023 | ||
31169714 CW |
5024 | if (nr_to_scan <= 0) |
5025 | break; | |
5026 | } | |
5027 | ||
5028 | /* second pass, evict/count anything still on the inactive list */ | |
5029 | list_for_each_entry_safe(dev_priv, next_dev, | |
5030 | &shrink_list, mm.shrink_list) { | |
5031 | struct drm_device *dev = dev_priv->dev; | |
5032 | ||
5033 | if (! mutex_trylock(&dev->struct_mutex)) | |
5034 | continue; | |
5035 | ||
5036 | spin_unlock(&shrink_list_lock); | |
5037 | ||
5038 | list_for_each_entry_safe(obj_priv, next_obj, | |
5039 | &dev_priv->mm.inactive_list, | |
5040 | list) { | |
5041 | if (nr_to_scan > 0) { | |
a8089e84 | 5042 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5043 | nr_to_scan--; |
5044 | } else | |
5045 | cnt++; | |
5046 | } | |
5047 | ||
5048 | spin_lock(&shrink_list_lock); | |
5049 | mutex_unlock(&dev->struct_mutex); | |
5050 | ||
5051 | would_deadlock = 0; | |
5052 | } | |
5053 | ||
1637ef41 CW |
5054 | if (nr_to_scan) { |
5055 | int active = 0; | |
5056 | ||
5057 | /* | |
5058 | * We are desperate for pages, so as a last resort, wait | |
5059 | * for the GPU to finish and discard whatever we can. | |
5060 | * This has a dramatic impact to reduce the number of | |
5061 | * OOM-killer events whilst running the GPU aggressively. | |
5062 | */ | |
5063 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5064 | struct drm_device *dev = dev_priv->dev; | |
5065 | ||
5066 | if (!mutex_trylock(&dev->struct_mutex)) | |
5067 | continue; | |
5068 | ||
5069 | spin_unlock(&shrink_list_lock); | |
5070 | ||
5071 | if (i915_gpu_is_active(dev)) { | |
5072 | i915_gpu_idle(dev); | |
5073 | active++; | |
5074 | } | |
5075 | ||
5076 | spin_lock(&shrink_list_lock); | |
5077 | mutex_unlock(&dev->struct_mutex); | |
5078 | } | |
5079 | ||
5080 | if (active) | |
5081 | goto rescan; | |
5082 | } | |
5083 | ||
31169714 CW |
5084 | spin_unlock(&shrink_list_lock); |
5085 | ||
5086 | if (would_deadlock) | |
5087 | return -1; | |
5088 | else if (cnt > 0) | |
5089 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5090 | else | |
5091 | return 0; | |
5092 | } | |
5093 | ||
5094 | static struct shrinker shrinker = { | |
5095 | .shrink = i915_gem_shrink, | |
5096 | .seeks = DEFAULT_SEEKS, | |
5097 | }; | |
5098 | ||
5099 | __init void | |
5100 | i915_gem_shrinker_init(void) | |
5101 | { | |
5102 | register_shrinker(&shrinker); | |
5103 | } | |
5104 | ||
5105 | __exit void | |
5106 | i915_gem_shrinker_exit(void) | |
5107 | { | |
5108 | unregister_shrinker(&shrinker); | |
5109 | } |