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[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
673a394b 37
2dafb1e0 38static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 41static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 int write);
43static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
44 uint64_t offset,
45 uint64_t size);
46static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 47static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 48static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment);
de151cf6 50static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 51static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 52static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 53static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
be72615b 56static void i915_gem_free_object_tail(struct drm_gem_object *obj);
673a394b 57
31169714
CW		 58static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
79e53945
JB		 61int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
673a394b
EA		 63{
64 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 65
79e53945
JB		 66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 69 return -EINVAL;
70 }
71
79e53945
JB		 72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
673a394b 74
79e53945
JB		 75 dev->gtt_total = (uint32_t) (end - start);
76
77 return 0;
78}
673a394b 79
79e53945
JB		 80int
81i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
83{
84 struct drm_i915_gem_init *args = data;
85 int ret;
86
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 89 mutex_unlock(&dev->struct_mutex);
90
79e53945 91 return ret;
673a394b
EA		 92}
93
5a125c3c
EA		 94int
95i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
97{
5a125c3c 98 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 99
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
102
103 args->aper_size = dev->gtt_total;
2678d9d6
KP		 104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
5a125c3c
EA		 106
107 return 0;
108}
109
673a394b
EA		 110
111/**
112 * Creates a new mm object and returns a handle to it.
113 */
114int
115i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
117{
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
a1a2d1d3
PP		 120 int ret;
121 u32 handle;
673a394b
EA		 122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
ac52bc56 126 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
86f100b1 131 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 132 if (ret)
133 return ret;
134
135 args->handle = handle;
136
137 return 0;
138}
139
eb01459f
EA		 140static inline int
141fast_shmem_read(struct page **pages,
142 loff_t page_base, int page_offset,
143 char __user *data,
144 int length)
145{
146 char __iomem *vaddr;
2bc43b5c 147 int unwritten;
eb01459f
EA		 148
149 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
150 if (vaddr == NULL)
151 return -ENOMEM;
2bc43b5c 152 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 153 kunmap_atomic(vaddr, KM_USER0);
154
2bc43b5c
FM		 155 if (unwritten)
156 return -EFAULT;
157
158 return 0;
eb01459f
EA		 159}
160
280b713b
EA		 161static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
162{
163 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 165
166 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
167 obj_priv->tiling_mode != I915_TILING_NONE;
168}
169
99a03df5 170static inline void
40123c1f
EA		 171slow_shmem_copy(struct page *dst_page,
172 int dst_offset,
173 struct page *src_page,
174 int src_offset,
175 int length)
176{
177 char *dst_vaddr, *src_vaddr;
178
99a03df5
CW		 179 dst_vaddr = kmap(dst_page);
180 src_vaddr = kmap(src_page);
40123c1f
EA		 181
182 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
183
99a03df5
CW		 184 kunmap(src_page);
185 kunmap(dst_page);
40123c1f
EA		 186}
187
99a03df5 188static inline void
280b713b
EA		 189slow_shmem_bit17_copy(struct page *gpu_page,
190 int gpu_offset,
191 struct page *cpu_page,
192 int cpu_offset,
193 int length,
194 int is_read)
195{
196 char *gpu_vaddr, *cpu_vaddr;
197
198 /* Use the unswizzled path if this page isn't affected. */
199 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
200 if (is_read)
201 return slow_shmem_copy(cpu_page, cpu_offset,
202 gpu_page, gpu_offset, length);
203 else
204 return slow_shmem_copy(gpu_page, gpu_offset,
205 cpu_page, cpu_offset, length);
206 }
207
99a03df5
CW		 208 gpu_vaddr = kmap(gpu_page);
209 cpu_vaddr = kmap(cpu_page);
280b713b
EA		 210
211 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
212 * XORing with the other bits (A9 for Y, A9 and A10 for X)
213 */
214 while (length > 0) {
215 int cacheline_end = ALIGN(gpu_offset + 1, 64);
216 int this_length = min(cacheline_end - gpu_offset, length);
217 int swizzled_gpu_offset = gpu_offset ^ 64;
218
219 if (is_read) {
220 memcpy(cpu_vaddr + cpu_offset,
221 gpu_vaddr + swizzled_gpu_offset,
222 this_length);
223 } else {
224 memcpy(gpu_vaddr + swizzled_gpu_offset,
225 cpu_vaddr + cpu_offset,
226 this_length);
227 }
228 cpu_offset += this_length;
229 gpu_offset += this_length;
230 length -= this_length;
231 }
232
99a03df5
CW		 233 kunmap(cpu_page);
234 kunmap(gpu_page);
280b713b
EA		 235}
236
eb01459f
EA		 237/**
238 * This is the fast shmem pread path, which attempts to copy_from_user directly
239 * from the backing pages of the object to the user's address space. On a
240 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
241 */
242static int
243i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
244 struct drm_i915_gem_pread *args,
245 struct drm_file *file_priv)
246{
23010e43 247 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 248 ssize_t remain;
249 loff_t offset, page_base;
250 char __user *user_data;
251 int page_offset, page_length;
252 int ret;
253
254 user_data = (char __user *) (uintptr_t) args->data_ptr;
255 remain = args->size;
256
257 mutex_lock(&dev->struct_mutex);
258
4bdadb97 259 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 260 if (ret != 0)
261 goto fail_unlock;
262
263 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
264 args->size);
265 if (ret != 0)
266 goto fail_put_pages;
267
23010e43 268 obj_priv = to_intel_bo(obj);
eb01459f
EA		 269 offset = args->offset;
270
271 while (remain > 0) {
272 /* Operation in this page
273 *
274 * page_base = page offset within aperture
275 * page_offset = offset within page
276 * page_length = bytes to copy for this page
277 */
278 page_base = (offset & ~(PAGE_SIZE-1));
279 page_offset = offset & (PAGE_SIZE-1);
280 page_length = remain;
281 if ((page_offset + remain) > PAGE_SIZE)
282 page_length = PAGE_SIZE - page_offset;
283
284 ret = fast_shmem_read(obj_priv->pages,
285 page_base, page_offset,
286 user_data, page_length);
287 if (ret)
288 goto fail_put_pages;
289
290 remain -= page_length;
291 user_data += page_length;
292 offset += page_length;
293 }
294
295fail_put_pages:
296 i915_gem_object_put_pages(obj);
297fail_unlock:
298 mutex_unlock(&dev->struct_mutex);
299
300 return ret;
301}
302
07f73f69
CW		 303static int
304i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
305{
306 int ret;
307
4bdadb97 308 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 309
310 /* If we've insufficient memory to map in the pages, attempt
311 * to make some space by throwing out some old buffers.
312 */
313 if (ret == -ENOMEM) {
314 struct drm_device *dev = obj->dev;
07f73f69
CW		 315
316 ret = i915_gem_evict_something(dev, obj->size);
317 if (ret)
318 return ret;
319
4bdadb97 320 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 321 }
322
323 return ret;
324}
325
eb01459f
EA		 326/**
327 * This is the fallback shmem pread path, which allocates temporary storage
328 * in kernel space to copy_to_user into outside of the struct_mutex, so we
329 * can copy out of the object's backing pages while holding the struct mutex
330 * and not take page faults.
331 */
332static int
333i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
334 struct drm_i915_gem_pread *args,
335 struct drm_file *file_priv)
336{
23010e43 337 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 338 struct mm_struct *mm = current->mm;
339 struct page **user_pages;
340 ssize_t remain;
341 loff_t offset, pinned_pages, i;
342 loff_t first_data_page, last_data_page, num_pages;
343 int shmem_page_index, shmem_page_offset;
344 int data_page_index, data_page_offset;
345 int page_length;
346 int ret;
347 uint64_t data_ptr = args->data_ptr;
280b713b 348 int do_bit17_swizzling;
eb01459f
EA		 349
350 remain = args->size;
351
352 /* Pin the user pages containing the data. We can't fault while
353 * holding the struct mutex, yet we want to hold it while
354 * dereferencing the user data.
355 */
356 first_data_page = data_ptr / PAGE_SIZE;
357 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
358 num_pages = last_data_page - first_data_page + 1;
359
8e7d2b2c 360 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 361 if (user_pages == NULL)
362 return -ENOMEM;
363
364 down_read(&mm->mmap_sem);
365 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 366 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 367 up_read(&mm->mmap_sem);
368 if (pinned_pages < num_pages) {
369 ret = -EFAULT;
370 goto fail_put_user_pages;
371 }
372
280b713b
EA		 373 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
374
eb01459f
EA		 375 mutex_lock(&dev->struct_mutex);
376
07f73f69
CW		 377 ret = i915_gem_object_get_pages_or_evict(obj);
378 if (ret)
eb01459f
EA		 379 goto fail_unlock;
380
381 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
382 args->size);
383 if (ret != 0)
384 goto fail_put_pages;
385
23010e43 386 obj_priv = to_intel_bo(obj);
eb01459f
EA		 387 offset = args->offset;
388
389 while (remain > 0) {
390 /* Operation in this page
391 *
392 * shmem_page_index = page number within shmem file
393 * shmem_page_offset = offset within page in shmem file
394 * data_page_index = page number in get_user_pages return
395 * data_page_offset = offset with data_page_index page.
396 * page_length = bytes to copy for this page
397 */
398 shmem_page_index = offset / PAGE_SIZE;
399 shmem_page_offset = offset & ~PAGE_MASK;
400 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
401 data_page_offset = data_ptr & ~PAGE_MASK;
402
403 page_length = remain;
404 if ((shmem_page_offset + page_length) > PAGE_SIZE)
405 page_length = PAGE_SIZE - shmem_page_offset;
406 if ((data_page_offset + page_length) > PAGE_SIZE)
407 page_length = PAGE_SIZE - data_page_offset;
408
280b713b 409 if (do_bit17_swizzling) {
99a03df5 410 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b 411 shmem_page_offset,
99a03df5
CW		 412 user_pages[data_page_index],
413 data_page_offset,
414 page_length,
415 1);
416 } else {
417 slow_shmem_copy(user_pages[data_page_index],
418 data_page_offset,
419 obj_priv->pages[shmem_page_index],
420 shmem_page_offset,
421 page_length);
280b713b 422 }
eb01459f
EA		 423
424 remain -= page_length;
425 data_ptr += page_length;
426 offset += page_length;
427 }
428
429fail_put_pages:
430 i915_gem_object_put_pages(obj);
431fail_unlock:
432 mutex_unlock(&dev->struct_mutex);
433fail_put_user_pages:
434 for (i = 0; i < pinned_pages; i++) {
435 SetPageDirty(user_pages[i]);
436 page_cache_release(user_pages[i]);
437 }
8e7d2b2c 438 drm_free_large(user_pages);
eb01459f
EA		 439
440 return ret;
441}
442
673a394b
EA		 443/**
444 * Reads data from the object referenced by handle.
445 *
446 * On error, the contents of *data are undefined.
447 */
448int
449i915_gem_pread_ioctl(struct drm_device *dev, void *data,
450 struct drm_file *file_priv)
451{
452 struct drm_i915_gem_pread *args = data;
453 struct drm_gem_object *obj;
454 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 455 int ret;
456
457 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
458 if (obj == NULL)
459 return -EBADF;
23010e43 460 obj_priv = to_intel_bo(obj);
673a394b
EA		 461
462 /* Bounds check source.
463 *
464 * XXX: This could use review for overflow issues...
465 */
466 if (args->offset > obj->size || args->size > obj->size ||
467 args->offset + args->size > obj->size) {
bc9025bd 468 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 469 return -EINVAL;
470 }
471
280b713b 472 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 473 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 474 } else {
475 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
476 if (ret != 0)
477 ret = i915_gem_shmem_pread_slow(dev, obj, args,
478 file_priv);
479 }
673a394b 480
bc9025bd 481 drm_gem_object_unreference_unlocked(obj);
673a394b 482
eb01459f 483 return ret;
673a394b
EA		 484}
485
0839ccb8
KP		 486/* This is the fast write path which cannot handle
487 * page faults in the source data
9b7530cc 488 */
0839ccb8
KP		 489
490static inline int
491fast_user_write(struct io_mapping *mapping,
492 loff_t page_base, int page_offset,
493 char __user *user_data,
494 int length)
9b7530cc 495{
9b7530cc 496 char *vaddr_atomic;
0839ccb8 497 unsigned long unwritten;
9b7530cc 498
0839ccb8
KP		 499 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
500 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
501 user_data, length);
502 io_mapping_unmap_atomic(vaddr_atomic);
503 if (unwritten)
504 return -EFAULT;
505 return 0;
506}
507
508/* Here's the write path which can sleep for
509 * page faults
510 */
511
ab34c226 512static inline void
3de09aa3
EA		 513slow_kernel_write(struct io_mapping *mapping,
514 loff_t gtt_base, int gtt_offset,
515 struct page *user_page, int user_offset,
516 int length)
0839ccb8 517{
ab34c226
CW		 518 char __iomem *dst_vaddr;
519 char *src_vaddr;
0839ccb8 520
ab34c226
CW		 521 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
522 src_vaddr = kmap(user_page);
523
524 memcpy_toio(dst_vaddr + gtt_offset,
525 src_vaddr + user_offset,
526 length);
527
528 kunmap(user_page);
529 io_mapping_unmap(dst_vaddr);
9b7530cc
LT		 530}
531
40123c1f
EA		 532static inline int
533fast_shmem_write(struct page **pages,
534 loff_t page_base, int page_offset,
535 char __user *data,
536 int length)
537{
538 char __iomem *vaddr;
d0088775 539 unsigned long unwritten;
40123c1f
EA		 540
541 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
542 if (vaddr == NULL)
543 return -ENOMEM;
d0088775 544 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 545 kunmap_atomic(vaddr, KM_USER0);
546
d0088775
DA		 547 if (unwritten)
548 return -EFAULT;
40123c1f
EA		 549 return 0;
550}
551
3de09aa3
EA		 552/**
553 * This is the fast pwrite path, where we copy the data directly from the
554 * user into the GTT, uncached.
555 */
673a394b 556static int
3de09aa3
EA		 557i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
558 struct drm_i915_gem_pwrite *args,
559 struct drm_file *file_priv)
673a394b 560{
23010e43 561 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 562 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 563 ssize_t remain;
0839ccb8 564 loff_t offset, page_base;
673a394b 565 char __user *user_data;
0839ccb8
KP		 566 int page_offset, page_length;
567 int ret;
673a394b
EA		 568
569 user_data = (char __user *) (uintptr_t) args->data_ptr;
570 remain = args->size;
571 if (!access_ok(VERIFY_READ, user_data, remain))
572 return -EFAULT;
573
574
575 mutex_lock(&dev->struct_mutex);
576 ret = i915_gem_object_pin(obj, 0);
577 if (ret) {
578 mutex_unlock(&dev->struct_mutex);
579 return ret;
580 }
2ef7eeaa 581 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 582 if (ret)
583 goto fail;
584
23010e43 585 obj_priv = to_intel_bo(obj);
673a394b 586 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 587
588 while (remain > 0) {
589 /* Operation in this page
590 *
0839ccb8
KP		 591 * page_base = page offset within aperture
592 * page_offset = offset within page
593 * page_length = bytes to copy for this page
673a394b 594 */
0839ccb8
KP		 595 page_base = (offset & ~(PAGE_SIZE-1));
596 page_offset = offset & (PAGE_SIZE-1);
597 page_length = remain;
598 if ((page_offset + remain) > PAGE_SIZE)
599 page_length = PAGE_SIZE - page_offset;
600
601 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
602 page_offset, user_data, page_length);
603
604 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 605 * source page isn't available. Return the error and we'll
606 * retry in the slow path.
0839ccb8 607 */
3de09aa3
EA		 608 if (ret)
609 goto fail;
673a394b 610
0839ccb8
KP		 611 remain -= page_length;
612 user_data += page_length;
613 offset += page_length;
673a394b 614 }
673a394b
EA		 615
616fail:
617 i915_gem_object_unpin(obj);
618 mutex_unlock(&dev->struct_mutex);
619
620 return ret;
621}
622
3de09aa3
EA		 623/**
624 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
625 * the memory and maps it using kmap_atomic for copying.
626 *
627 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
628 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
629 */
3043c60c 630static int
3de09aa3
EA		 631i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
632 struct drm_i915_gem_pwrite *args,
633 struct drm_file *file_priv)
673a394b 634{
23010e43 635 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 636 drm_i915_private_t *dev_priv = dev->dev_private;
637 ssize_t remain;
638 loff_t gtt_page_base, offset;
639 loff_t first_data_page, last_data_page, num_pages;
640 loff_t pinned_pages, i;
641 struct page **user_pages;
642 struct mm_struct *mm = current->mm;
643 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 644 int ret;
3de09aa3
EA		 645 uint64_t data_ptr = args->data_ptr;
646
647 remain = args->size;
648
649 /* Pin the user pages containing the data. We can't fault while
650 * holding the struct mutex, and all of the pwrite implementations
651 * want to hold it while dereferencing the user data.
652 */
653 first_data_page = data_ptr / PAGE_SIZE;
654 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
655 num_pages = last_data_page - first_data_page + 1;
656
8e7d2b2c 657 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 658 if (user_pages == NULL)
659 return -ENOMEM;
660
661 down_read(&mm->mmap_sem);
662 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
663 num_pages, 0, 0, user_pages, NULL);
664 up_read(&mm->mmap_sem);
665 if (pinned_pages < num_pages) {
666 ret = -EFAULT;
667 goto out_unpin_pages;
668 }
673a394b
EA		 669
670 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 671 ret = i915_gem_object_pin(obj, 0);
672 if (ret)
673 goto out_unlock;
674
675 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
676 if (ret)
677 goto out_unpin_object;
678
23010e43 679 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 680 offset = obj_priv->gtt_offset + args->offset;
681
682 while (remain > 0) {
683 /* Operation in this page
684 *
685 * gtt_page_base = page offset within aperture
686 * gtt_page_offset = offset within page in aperture
687 * data_page_index = page number in get_user_pages return
688 * data_page_offset = offset with data_page_index page.
689 * page_length = bytes to copy for this page
690 */
691 gtt_page_base = offset & PAGE_MASK;
692 gtt_page_offset = offset & ~PAGE_MASK;
693 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
694 data_page_offset = data_ptr & ~PAGE_MASK;
695
696 page_length = remain;
697 if ((gtt_page_offset + page_length) > PAGE_SIZE)
698 page_length = PAGE_SIZE - gtt_page_offset;
699 if ((data_page_offset + page_length) > PAGE_SIZE)
700 page_length = PAGE_SIZE - data_page_offset;
701
ab34c226
CW		 702 slow_kernel_write(dev_priv->mm.gtt_mapping,
703 gtt_page_base, gtt_page_offset,
704 user_pages[data_page_index],
705 data_page_offset,
706 page_length);
3de09aa3
EA		 707
708 remain -= page_length;
709 offset += page_length;
710 data_ptr += page_length;
711 }
712
713out_unpin_object:
714 i915_gem_object_unpin(obj);
715out_unlock:
716 mutex_unlock(&dev->struct_mutex);
717out_unpin_pages:
718 for (i = 0; i < pinned_pages; i++)
719 page_cache_release(user_pages[i]);
8e7d2b2c 720 drm_free_large(user_pages);
3de09aa3
EA		 721
722 return ret;
723}
724
40123c1f
EA		 725/**
726 * This is the fast shmem pwrite path, which attempts to directly
727 * copy_from_user into the kmapped pages backing the object.
728 */
3043c60c 729static int
40123c1f
EA		 730i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
731 struct drm_i915_gem_pwrite *args,
732 struct drm_file *file_priv)
673a394b 733{
23010e43 734 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 735 ssize_t remain;
736 loff_t offset, page_base;
737 char __user *user_data;
738 int page_offset, page_length;
673a394b 739 int ret;
40123c1f
EA		 740
741 user_data = (char __user *) (uintptr_t) args->data_ptr;
742 remain = args->size;
673a394b
EA		 743
744 mutex_lock(&dev->struct_mutex);
745
4bdadb97 746 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 747 if (ret != 0)
748 goto fail_unlock;
673a394b 749
e47c68e9 750 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 751 if (ret != 0)
752 goto fail_put_pages;
753
23010e43 754 obj_priv = to_intel_bo(obj);
40123c1f
EA		 755 offset = args->offset;
756 obj_priv->dirty = 1;
757
758 while (remain > 0) {
759 /* Operation in this page
760 *
761 * page_base = page offset within aperture
762 * page_offset = offset within page
763 * page_length = bytes to copy for this page
764 */
765 page_base = (offset & ~(PAGE_SIZE-1));
766 page_offset = offset & (PAGE_SIZE-1);
767 page_length = remain;
768 if ((page_offset + remain) > PAGE_SIZE)
769 page_length = PAGE_SIZE - page_offset;
770
771 ret = fast_shmem_write(obj_priv->pages,
772 page_base, page_offset,
773 user_data, page_length);
774 if (ret)
775 goto fail_put_pages;
776
777 remain -= page_length;
778 user_data += page_length;
779 offset += page_length;
780 }
781
782fail_put_pages:
783 i915_gem_object_put_pages(obj);
784fail_unlock:
785 mutex_unlock(&dev->struct_mutex);
786
787 return ret;
788}
789
790/**
791 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
792 * the memory and maps it using kmap_atomic for copying.
793 *
794 * This avoids taking mmap_sem for faulting on the user's address while the
795 * struct_mutex is held.
796 */
797static int
798i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
799 struct drm_i915_gem_pwrite *args,
800 struct drm_file *file_priv)
801{
23010e43 802 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 803 struct mm_struct *mm = current->mm;
804 struct page **user_pages;
805 ssize_t remain;
806 loff_t offset, pinned_pages, i;
807 loff_t first_data_page, last_data_page, num_pages;
808 int shmem_page_index, shmem_page_offset;
809 int data_page_index, data_page_offset;
810 int page_length;
811 int ret;
812 uint64_t data_ptr = args->data_ptr;
280b713b 813 int do_bit17_swizzling;
40123c1f
EA		 814
815 remain = args->size;
816
817 /* Pin the user pages containing the data. We can't fault while
818 * holding the struct mutex, and all of the pwrite implementations
819 * want to hold it while dereferencing the user data.
820 */
821 first_data_page = data_ptr / PAGE_SIZE;
822 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
823 num_pages = last_data_page - first_data_page + 1;
824
8e7d2b2c 825 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 826 if (user_pages == NULL)
827 return -ENOMEM;
828
829 down_read(&mm->mmap_sem);
830 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
831 num_pages, 0, 0, user_pages, NULL);
832 up_read(&mm->mmap_sem);
833 if (pinned_pages < num_pages) {
834 ret = -EFAULT;
835 goto fail_put_user_pages;
673a394b
EA		 836 }
837
280b713b
EA		 838 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
839
40123c1f
EA		 840 mutex_lock(&dev->struct_mutex);
841
07f73f69
CW		 842 ret = i915_gem_object_get_pages_or_evict(obj);
843 if (ret)
40123c1f
EA		 844 goto fail_unlock;
845
846 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
847 if (ret != 0)
848 goto fail_put_pages;
849
23010e43 850 obj_priv = to_intel_bo(obj);
673a394b 851 offset = args->offset;
40123c1f 852 obj_priv->dirty = 1;
673a394b 853
40123c1f
EA		 854 while (remain > 0) {
855 /* Operation in this page
856 *
857 * shmem_page_index = page number within shmem file
858 * shmem_page_offset = offset within page in shmem file
859 * data_page_index = page number in get_user_pages return
860 * data_page_offset = offset with data_page_index page.
861 * page_length = bytes to copy for this page
862 */
863 shmem_page_index = offset / PAGE_SIZE;
864 shmem_page_offset = offset & ~PAGE_MASK;
865 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
866 data_page_offset = data_ptr & ~PAGE_MASK;
867
868 page_length = remain;
869 if ((shmem_page_offset + page_length) > PAGE_SIZE)
870 page_length = PAGE_SIZE - shmem_page_offset;
871 if ((data_page_offset + page_length) > PAGE_SIZE)
872 page_length = PAGE_SIZE - data_page_offset;
873
280b713b 874 if (do_bit17_swizzling) {
99a03df5 875 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b
EA		 876 shmem_page_offset,
877 user_pages[data_page_index],
878 data_page_offset,
99a03df5
CW		 879 page_length,
880 0);
881 } else {
882 slow_shmem_copy(obj_priv->pages[shmem_page_index],
883 shmem_page_offset,
884 user_pages[data_page_index],
885 data_page_offset,
886 page_length);
280b713b 887 }
40123c1f
EA		 888
889 remain -= page_length;
890 data_ptr += page_length;
891 offset += page_length;
673a394b
EA		 892 }
893
40123c1f
EA		 894fail_put_pages:
895 i915_gem_object_put_pages(obj);
896fail_unlock:
673a394b 897 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 898fail_put_user_pages:
899 for (i = 0; i < pinned_pages; i++)
900 page_cache_release(user_pages[i]);
8e7d2b2c 901 drm_free_large(user_pages);
673a394b 902
40123c1f 903 return ret;
673a394b
EA		 904}
905
906/**
907 * Writes data to the object referenced by handle.
908 *
909 * On error, the contents of the buffer that were to be modified are undefined.
910 */
911int
912i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
913 struct drm_file *file_priv)
914{
915 struct drm_i915_gem_pwrite *args = data;
916 struct drm_gem_object *obj;
917 struct drm_i915_gem_object *obj_priv;
918 int ret = 0;
919
920 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
921 if (obj == NULL)
922 return -EBADF;
23010e43 923 obj_priv = to_intel_bo(obj);
673a394b
EA		 924
925 /* Bounds check destination.
926 *
927 * XXX: This could use review for overflow issues...
928 */
929 if (args->offset > obj->size || args->size > obj->size ||
930 args->offset + args->size > obj->size) {
bc9025bd 931 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 932 return -EINVAL;
933 }
934
935 /* We can only do the GTT pwrite on untiled buffers, as otherwise
936 * it would end up going through the fenced access, and we'll get
937 * different detiling behavior between reading and writing.
938 * pread/pwrite currently are reading and writing from the CPU
939 * perspective, requiring manual detiling by the client.
940 */
71acb5eb
DA		 941 if (obj_priv->phys_obj)
942 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
943 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
9b8c4a0b
CW		 944 dev->gtt_total != 0 &&
945 obj->write_domain != I915_GEM_DOMAIN_CPU) {
3de09aa3
EA		 946 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
947 if (ret == -EFAULT) {
948 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
949 file_priv);
950 }
280b713b
EA		 951 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
952 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 953 } else {
954 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
955 if (ret == -EFAULT) {
956 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
957 file_priv);
958 }
959 }
673a394b
EA		 960
961#if WATCH_PWRITE
962 if (ret)
963 DRM_INFO("pwrite failed %d\n", ret);
964#endif
965
bc9025bd 966 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 967
968 return ret;
969}
970
971/**
2ef7eeaa
EA		 972 * Called when user space prepares to use an object with the CPU, either
973 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 974 */
975int
976i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
977 struct drm_file *file_priv)
978{
a09ba7fa 979 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 980 struct drm_i915_gem_set_domain *args = data;
981 struct drm_gem_object *obj;
652c393a 982 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 983 uint32_t read_domains = args->read_domains;
984 uint32_t write_domain = args->write_domain;
673a394b
EA		 985 int ret;
986
987 if (!(dev->driver->driver_features & DRIVER_GEM))
988 return -ENODEV;
989
2ef7eeaa 990 /* Only handle setting domains to types used by the CPU. */
21d509e3 991 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 992 return -EINVAL;
993
21d509e3 994 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 995 return -EINVAL;
996
997 /* Having something in the write domain implies it's in the read
998 * domain, and only that read domain. Enforce that in the request.
999 */
1000 if (write_domain != 0 && read_domains != write_domain)
1001 return -EINVAL;
1002
673a394b
EA		 1003 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1004 if (obj == NULL)
1005 return -EBADF;
23010e43 1006 obj_priv = to_intel_bo(obj);
673a394b
EA		 1007
1008 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1009
1010 intel_mark_busy(dev, obj);
1011
673a394b 1012#if WATCH_BUF
cfd43c02 1013 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1014 obj, obj->size, read_domains, write_domain);
673a394b 1015#endif
2ef7eeaa
EA		 1016 if (read_domains & I915_GEM_DOMAIN_GTT) {
1017 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1018
a09ba7fa
EA		 1019 /* Update the LRU on the fence for the CPU access that's
1020 * about to occur.
1021 */
1022 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 1023 struct drm_i915_fence_reg *reg =
1024 &dev_priv->fence_regs[obj_priv->fence_reg];
1025 list_move_tail(&reg->lru_list,
a09ba7fa
EA		 1026 &dev_priv->mm.fence_list);
1027 }
1028
02354392
EA		 1029 /* Silently promote "you're not bound, there was nothing to do"
1030 * to success, since the client was just asking us to
1031 * make sure everything was done.
1032 */
1033 if (ret == -EINVAL)
1034 ret = 0;
2ef7eeaa 1035 } else {
e47c68e9 1036 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1037 }
1038
673a394b
EA		 1039 drm_gem_object_unreference(obj);
1040 mutex_unlock(&dev->struct_mutex);
1041 return ret;
1042}
1043
1044/**
1045 * Called when user space has done writes to this buffer
1046 */
1047int
1048i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1049 struct drm_file *file_priv)
1050{
1051 struct drm_i915_gem_sw_finish *args = data;
1052 struct drm_gem_object *obj;
1053 struct drm_i915_gem_object *obj_priv;
1054 int ret = 0;
1055
1056 if (!(dev->driver->driver_features & DRIVER_GEM))
1057 return -ENODEV;
1058
1059 mutex_lock(&dev->struct_mutex);
1060 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1061 if (obj == NULL) {
1062 mutex_unlock(&dev->struct_mutex);
1063 return -EBADF;
1064 }
1065
1066#if WATCH_BUF
cfd43c02 1067 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1068 __func__, args->handle, obj, obj->size);
1069#endif
23010e43 1070 obj_priv = to_intel_bo(obj);
673a394b
EA		 1071
1072 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1073 if (obj_priv->pin_count)
1074 i915_gem_object_flush_cpu_write_domain(obj);
1075
673a394b
EA		 1076 drm_gem_object_unreference(obj);
1077 mutex_unlock(&dev->struct_mutex);
1078 return ret;
1079}
1080
1081/**
1082 * Maps the contents of an object, returning the address it is mapped
1083 * into.
1084 *
1085 * While the mapping holds a reference on the contents of the object, it doesn't
1086 * imply a ref on the object itself.
1087 */
1088int
1089i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1090 struct drm_file *file_priv)
1091{
1092 struct drm_i915_gem_mmap *args = data;
1093 struct drm_gem_object *obj;
1094 loff_t offset;
1095 unsigned long addr;
1096
1097 if (!(dev->driver->driver_features & DRIVER_GEM))
1098 return -ENODEV;
1099
1100 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1101 if (obj == NULL)
1102 return -EBADF;
1103
1104 offset = args->offset;
1105
1106 down_write(&current->mm->mmap_sem);
1107 addr = do_mmap(obj->filp, 0, args->size,
1108 PROT_READ | PROT_WRITE, MAP_SHARED,
1109 args->offset);
1110 up_write(&current->mm->mmap_sem);
bc9025bd 1111 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1112 if (IS_ERR((void *)addr))
1113 return addr;
1114
1115 args->addr_ptr = (uint64_t) addr;
1116
1117 return 0;
1118}
1119
de151cf6
JB		 1120/**
1121 * i915_gem_fault - fault a page into the GTT
1122 * vma: VMA in question
1123 * vmf: fault info
1124 *
1125 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1126 * from userspace. The fault handler takes care of binding the object to
1127 * the GTT (if needed), allocating and programming a fence register (again,
1128 * only if needed based on whether the old reg is still valid or the object
1129 * is tiled) and inserting a new PTE into the faulting process.
1130 *
1131 * Note that the faulting process may involve evicting existing objects
1132 * from the GTT and/or fence registers to make room. So performance may
1133 * suffer if the GTT working set is large or there are few fence registers
1134 * left.
1135 */
1136int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1137{
1138 struct drm_gem_object *obj = vma->vm_private_data;
1139 struct drm_device *dev = obj->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 1141 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1142 pgoff_t page_offset;
1143 unsigned long pfn;
1144 int ret = 0;
0f973f27 1145 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1146
1147 /* We don't use vmf->pgoff since that has the fake offset */
1148 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1149 PAGE_SHIFT;
1150
1151 /* Now bind it into the GTT if needed */
1152 mutex_lock(&dev->struct_mutex);
1153 if (!obj_priv->gtt_space) {
e67b8ce1 1154 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1155 if (ret)
1156 goto unlock;
07f4f3e8 1157
14b60391 1158 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1159
1160 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1161 if (ret)
1162 goto unlock;
de151cf6
JB		 1163 }
1164
1165 /* Need a new fence register? */
a09ba7fa 1166 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1167 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1168 if (ret)
1169 goto unlock;
d9ddcb96 1170 }
de151cf6
JB		 1171
1172 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1173 page_offset;
1174
1175 /* Finally, remap it using the new GTT offset */
1176 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1177unlock:
de151cf6
JB		 1178 mutex_unlock(&dev->struct_mutex);
1179
1180 switch (ret) {
c715089f
CW		 1181 case 0:
1182 case -ERESTARTSYS:
1183 return VM_FAULT_NOPAGE;
de151cf6
JB		 1184 case -ENOMEM:
1185 case -EAGAIN:
1186 return VM_FAULT_OOM;
de151cf6 1187 default:
c715089f 1188 return VM_FAULT_SIGBUS;
de151cf6
JB		 1189 }
1190}
1191
1192/**
1193 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1194 * @obj: obj in question
1195 *
1196 * GEM memory mapping works by handing back to userspace a fake mmap offset
1197 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1198 * up the object based on the offset and sets up the various memory mapping
1199 * structures.
1200 *
1201 * This routine allocates and attaches a fake offset for @obj.
1202 */
1203static int
1204i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1205{
1206 struct drm_device *dev = obj->dev;
1207 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1208 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1209 struct drm_map_list *list;
f77d390c 1210 struct drm_local_map *map;
de151cf6
JB		 1211 int ret = 0;
1212
1213 /* Set the object up for mmap'ing */
1214 list = &obj->map_list;
9a298b2a 1215 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1216 if (!list->map)
1217 return -ENOMEM;
1218
1219 map = list->map;
1220 map->type = _DRM_GEM;
1221 map->size = obj->size;
1222 map->handle = obj;
1223
1224 /* Get a DRM GEM mmap offset allocated... */
1225 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1226 obj->size / PAGE_SIZE, 0, 0);
1227 if (!list->file_offset_node) {
1228 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1229 ret = -ENOMEM;
1230 goto out_free_list;
1231 }
1232
1233 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1234 obj->size / PAGE_SIZE, 0);
1235 if (!list->file_offset_node) {
1236 ret = -ENOMEM;
1237 goto out_free_list;
1238 }
1239
1240 list->hash.key = list->file_offset_node->start;
1241 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1242 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1243 ret = -ENOMEM;
de151cf6
JB		 1244 goto out_free_mm;
1245 }
1246
1247 /* By now we should be all set, any drm_mmap request on the offset
1248 * below will get to our mmap & fault handler */
1249 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1250
1251 return 0;
1252
1253out_free_mm:
1254 drm_mm_put_block(list->file_offset_node);
1255out_free_list:
9a298b2a 1256 kfree(list->map);
de151cf6
JB		 1257
1258 return ret;
1259}
1260
901782b2
CW		 1261/**
1262 * i915_gem_release_mmap - remove physical page mappings
1263 * @obj: obj in question
1264 *
af901ca1 1265 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1266 * relinquish ownership of the pages back to the system.
1267 *
1268 * It is vital that we remove the page mapping if we have mapped a tiled
1269 * object through the GTT and then lose the fence register due to
1270 * resource pressure. Similarly if the object has been moved out of the
1271 * aperture, than pages mapped into userspace must be revoked. Removing the
1272 * mapping will then trigger a page fault on the next user access, allowing
1273 * fixup by i915_gem_fault().
1274 */
d05ca301 1275void
901782b2
CW		 1276i915_gem_release_mmap(struct drm_gem_object *obj)
1277{
1278 struct drm_device *dev = obj->dev;
23010e43 1279 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1280
1281 if (dev->dev_mapping)
1282 unmap_mapping_range(dev->dev_mapping,
1283 obj_priv->mmap_offset, obj->size, 1);
1284}
1285
ab00b3e5
JB		 1286static void
1287i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1288{
1289 struct drm_device *dev = obj->dev;
23010e43 1290 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1291 struct drm_gem_mm *mm = dev->mm_private;
1292 struct drm_map_list *list;
1293
1294 list = &obj->map_list;
1295 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1296
1297 if (list->file_offset_node) {
1298 drm_mm_put_block(list->file_offset_node);
1299 list->file_offset_node = NULL;
1300 }
1301
1302 if (list->map) {
9a298b2a 1303 kfree(list->map);
ab00b3e5
JB		 1304 list->map = NULL;
1305 }
1306
1307 obj_priv->mmap_offset = 0;
1308}
1309
de151cf6
JB		 1310/**
1311 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1312 * @obj: object to check
1313 *
1314 * Return the required GTT alignment for an object, taking into account
1315 * potential fence register mapping if needed.
1316 */
1317static uint32_t
1318i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1319{
1320 struct drm_device *dev = obj->dev;
23010e43 1321 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1322 int start, i;
1323
1324 /*
1325 * Minimum alignment is 4k (GTT page size), but might be greater
1326 * if a fence register is needed for the object.
1327 */
1328 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1329 return 4096;
1330
1331 /*
1332 * Previous chips need to be aligned to the size of the smallest
1333 * fence register that can contain the object.
1334 */
1335 if (IS_I9XX(dev))
1336 start = 1024*1024;
1337 else
1338 start = 512*1024;
1339
1340 for (i = start; i < obj->size; i <<= 1)
1341 ;
1342
1343 return i;
1344}
1345
1346/**
1347 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1348 * @dev: DRM device
1349 * @data: GTT mapping ioctl data
1350 * @file_priv: GEM object info
1351 *
1352 * Simply returns the fake offset to userspace so it can mmap it.
1353 * The mmap call will end up in drm_gem_mmap(), which will set things
1354 * up so we can get faults in the handler above.
1355 *
1356 * The fault handler will take care of binding the object into the GTT
1357 * (since it may have been evicted to make room for something), allocating
1358 * a fence register, and mapping the appropriate aperture address into
1359 * userspace.
1360 */
1361int
1362i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1363 struct drm_file *file_priv)
1364{
1365 struct drm_i915_gem_mmap_gtt *args = data;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 struct drm_gem_object *obj;
1368 struct drm_i915_gem_object *obj_priv;
1369 int ret;
1370
1371 if (!(dev->driver->driver_features & DRIVER_GEM))
1372 return -ENODEV;
1373
1374 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1375 if (obj == NULL)
1376 return -EBADF;
1377
1378 mutex_lock(&dev->struct_mutex);
1379
23010e43 1380 obj_priv = to_intel_bo(obj);
de151cf6 1381
ab18282d
CW		 1382 if (obj_priv->madv != I915_MADV_WILLNEED) {
1383 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1384 drm_gem_object_unreference(obj);
1385 mutex_unlock(&dev->struct_mutex);
1386 return -EINVAL;
1387 }
1388
1389
de151cf6
JB		 1390 if (!obj_priv->mmap_offset) {
1391 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1392 if (ret) {
1393 drm_gem_object_unreference(obj);
1394 mutex_unlock(&dev->struct_mutex);
de151cf6 1395 return ret;
13af1062 1396 }
de151cf6
JB		 1397 }
1398
1399 args->offset = obj_priv->mmap_offset;
1400
de151cf6
JB		 1401 /*
1402 * Pull it into the GTT so that we have a page list (makes the
1403 * initial fault faster and any subsequent flushing possible).
1404 */
1405 if (!obj_priv->agp_mem) {
e67b8ce1 1406 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1407 if (ret) {
1408 drm_gem_object_unreference(obj);
1409 mutex_unlock(&dev->struct_mutex);
1410 return ret;
1411 }
14b60391 1412 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1413 }
1414
1415 drm_gem_object_unreference(obj);
1416 mutex_unlock(&dev->struct_mutex);
1417
1418 return 0;
1419}
1420
6911a9b8 1421void
856fa198 1422i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1423{
23010e43 1424 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1425 int page_count = obj->size / PAGE_SIZE;
1426 int i;
1427
856fa198 1428 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1429 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1430
856fa198
EA		 1431 if (--obj_priv->pages_refcount != 0)
1432 return;
673a394b 1433
280b713b
EA		 1434 if (obj_priv->tiling_mode != I915_TILING_NONE)
1435 i915_gem_object_save_bit_17_swizzle(obj);
1436
3ef94daa 1437 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1438 obj_priv->dirty = 0;
3ef94daa
CW		 1439
1440 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1441 if (obj_priv->dirty)
1442 set_page_dirty(obj_priv->pages[i]);
1443
1444 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1445 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1446
1447 page_cache_release(obj_priv->pages[i]);
1448 }
673a394b
EA		 1449 obj_priv->dirty = 0;
1450
8e7d2b2c 1451 drm_free_large(obj_priv->pages);
856fa198 1452 obj_priv->pages = NULL;
673a394b
EA		 1453}
1454
1455static void
852835f3
ZN		 1456i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1457 struct intel_ring_buffer *ring)
673a394b
EA		 1458{
1459 struct drm_device *dev = obj->dev;
1460 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1461 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
852835f3
ZN		 1462 BUG_ON(ring == NULL);
1463 obj_priv->ring = ring;
673a394b
EA		 1464
1465 /* Add a reference if we're newly entering the active list. */
1466 if (!obj_priv->active) {
1467 drm_gem_object_reference(obj);
1468 obj_priv->active = 1;
1469 }
1470 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1471 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1472 list_move_tail(&obj_priv->list, &ring->active_list);
5e118f41 1473 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1474 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1475}
1476
ce44b0ea
EA		 1477static void
1478i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1479{
1480 struct drm_device *dev = obj->dev;
1481 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1482 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1483
1484 BUG_ON(!obj_priv->active);
1485 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1486 obj_priv->last_rendering_seqno = 0;
1487}
673a394b 1488
963b4836
CW		 1489/* Immediately discard the backing storage */
1490static void
1491i915_gem_object_truncate(struct drm_gem_object *obj)
1492{
23010e43 1493 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1494 struct inode *inode;
963b4836 1495
bb6baf76
CW		 1496 inode = obj->filp->f_path.dentry->d_inode;
1497 if (inode->i_op->truncate)
1498 inode->i_op->truncate (inode);
1499
1500 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1501}
1502
1503static inline int
1504i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1505{
1506 return obj_priv->madv == I915_MADV_DONTNEED;
1507}
1508
673a394b
EA		 1509static void
1510i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1511{
1512 struct drm_device *dev = obj->dev;
1513 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1514 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1515
1516 i915_verify_inactive(dev, __FILE__, __LINE__);
1517 if (obj_priv->pin_count != 0)
1518 list_del_init(&obj_priv->list);
1519 else
1520 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1521
99fcb766
DV		 1522 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1523
ce44b0ea 1524 obj_priv->last_rendering_seqno = 0;
852835f3 1525 obj_priv->ring = NULL;
673a394b
EA		 1526 if (obj_priv->active) {
1527 obj_priv->active = 0;
1528 drm_gem_object_unreference(obj);
1529 }
1530 i915_verify_inactive(dev, __FILE__, __LINE__);
1531}
1532
63560396
DV		 1533static void
1534i915_gem_process_flushing_list(struct drm_device *dev,
852835f3
ZN		 1535 uint32_t flush_domains, uint32_t seqno,
1536 struct intel_ring_buffer *ring)
63560396
DV		 1537{
1538 drm_i915_private_t *dev_priv = dev->dev_private;
1539 struct drm_i915_gem_object *obj_priv, *next;
1540
1541 list_for_each_entry_safe(obj_priv, next,
1542 &dev_priv->mm.gpu_write_list,
1543 gpu_write_list) {
a8089e84 1544 struct drm_gem_object *obj = &obj_priv->base;
63560396
DV		 1545
1546 if ((obj->write_domain & flush_domains) ==
852835f3
ZN		 1547 obj->write_domain &&
1548 obj_priv->ring->ring_flag == ring->ring_flag) {
63560396
DV		 1549 uint32_t old_write_domain = obj->write_domain;
1550
1551 obj->write_domain = 0;
1552 list_del_init(&obj_priv->gpu_write_list);
852835f3 1553 i915_gem_object_move_to_active(obj, seqno, ring);
63560396
DV		 1554
1555 /* update the fence lru list */
007cc8ac
DV		 1556 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1557 struct drm_i915_fence_reg *reg =
1558 &dev_priv->fence_regs[obj_priv->fence_reg];
1559 list_move_tail(&reg->lru_list,
63560396 1560 &dev_priv->mm.fence_list);
007cc8ac 1561 }
63560396
DV		 1562
1563 trace_i915_gem_object_change_domain(obj,
1564 obj->read_domains,
1565 old_write_domain);
1566 }
1567 }
1568}
8187a2b7 1569
5a5a0c64 1570uint32_t
b962442e 1571i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
852835f3 1572 uint32_t flush_domains, struct intel_ring_buffer *ring)
673a394b
EA		 1573{
1574 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1575 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1576 struct drm_i915_gem_request *request;
1577 uint32_t seqno;
1578 int was_empty;
673a394b 1579
b962442e
EA		 1580 if (file_priv != NULL)
1581 i915_file_priv = file_priv->driver_priv;
1582
9a298b2a 1583 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1584 if (request == NULL)
1585 return 0;
1586
852835f3 1587 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
673a394b
EA		 1588
1589 request->seqno = seqno;
852835f3 1590 request->ring = ring;
673a394b 1591 request->emitted_jiffies = jiffies;
852835f3
ZN		 1592 was_empty = list_empty(&ring->request_list);
1593 list_add_tail(&request->list, &ring->request_list);
1594
b962442e
EA		 1595 if (i915_file_priv) {
1596 list_add_tail(&request->client_list,
1597 &i915_file_priv->mm.request_list);
1598 } else {
1599 INIT_LIST_HEAD(&request->client_list);
1600 }
673a394b 1601
ce44b0ea
EA		 1602 /* Associate any objects on the flushing list matching the write
1603 * domain we're flushing with our flush.
1604 */
63560396 1605 if (flush_domains != 0)
852835f3 1606 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
ce44b0ea 1607
f65d9421
BG		 1608 if (!dev_priv->mm.suspended) {
1609 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1610 if (was_empty)
1611 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1612 }
673a394b
EA		 1613 return seqno;
1614}
1615
1616/**
1617 * Command execution barrier
1618 *
1619 * Ensures that all commands in the ring are finished
1620 * before signalling the CPU
1621 */
3043c60c 1622static uint32_t
852835f3 1623i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
673a394b 1624{
673a394b 1625 uint32_t flush_domains = 0;
673a394b
EA		 1626
1627 /* The sampler always gets flushed on i965 (sigh) */
1628 if (IS_I965G(dev))
1629 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
852835f3
ZN		 1630
1631 ring->flush(dev, ring,
1632 I915_GEM_DOMAIN_COMMAND, flush_domains);
673a394b
EA		 1633 return flush_domains;
1634}
1635
1636/**
1637 * Moves buffers associated only with the given active seqno from the active
1638 * to inactive list, potentially freeing them.
1639 */
1640static void
1641i915_gem_retire_request(struct drm_device *dev,
1642 struct drm_i915_gem_request *request)
1643{
1644 drm_i915_private_t *dev_priv = dev->dev_private;
1645
1c5d22f7
CW		 1646 trace_i915_gem_request_retire(dev, request->seqno);
1647
673a394b
EA		 1648 /* Move any buffers on the active list that are no longer referenced
1649 * by the ringbuffer to the flushing/inactive lists as appropriate.
1650 */
5e118f41 1651 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1652 while (!list_empty(&request->ring->active_list)) {
673a394b
EA		 1653 struct drm_gem_object *obj;
1654 struct drm_i915_gem_object *obj_priv;
1655
852835f3 1656 obj_priv = list_first_entry(&request->ring->active_list,
673a394b
EA		 1657 struct drm_i915_gem_object,
1658 list);
a8089e84 1659 obj = &obj_priv->base;
673a394b
EA		 1660
1661 /* If the seqno being retired doesn't match the oldest in the
1662 * list, then the oldest in the list must still be newer than
1663 * this seqno.
1664 */
1665 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1666 goto out;
de151cf6 1667
673a394b
EA		 1668#if WATCH_LRU
1669 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1670 __func__, request->seqno, obj);
1671#endif
1672
ce44b0ea
EA		 1673 if (obj->write_domain != 0)
1674 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1675 else {
1676 /* Take a reference on the object so it won't be
1677 * freed while the spinlock is held. The list
1678 * protection for this spinlock is safe when breaking
1679 * the lock like this since the next thing we do
1680 * is just get the head of the list again.
1681 */
1682 drm_gem_object_reference(obj);
673a394b 1683 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1684 spin_unlock(&dev_priv->mm.active_list_lock);
1685 drm_gem_object_unreference(obj);
1686 spin_lock(&dev_priv->mm.active_list_lock);
1687 }
673a394b 1688 }
5e118f41
CW		 1689out:
1690 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1691}
1692
1693/**
1694 * Returns true if seq1 is later than seq2.
1695 */
22be1724 1696bool
673a394b
EA		 1697i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1698{
1699 return (int32_t)(seq1 - seq2) >= 0;
1700}
1701
1702uint32_t
852835f3 1703i915_get_gem_seqno(struct drm_device *dev,
d1b851fc 1704 struct intel_ring_buffer *ring)
673a394b 1705{
852835f3 1706 return ring->get_gem_seqno(dev, ring);
673a394b
EA		 1707}
1708
1709/**
1710 * This function clears the request list as sequence numbers are passed.
1711 */
b09a1fec
CW		 1712static void
1713i915_gem_retire_requests_ring(struct drm_device *dev,
1714 struct intel_ring_buffer *ring)
673a394b
EA		 1715{
1716 drm_i915_private_t *dev_priv = dev->dev_private;
1717 uint32_t seqno;
1718
8187a2b7 1719 if (!ring->status_page.page_addr
852835f3 1720 || list_empty(&ring->request_list))
6c0594a3
KW		 1721 return;
1722
852835f3 1723 seqno = i915_get_gem_seqno(dev, ring);
673a394b 1724
852835f3 1725 while (!list_empty(&ring->request_list)) {
673a394b
EA		 1726 struct drm_i915_gem_request *request;
1727 uint32_t retiring_seqno;
1728
852835f3 1729 request = list_first_entry(&ring->request_list,
673a394b
EA		 1730 struct drm_i915_gem_request,
1731 list);
1732 retiring_seqno = request->seqno;
1733
1734 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1735 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1736 i915_gem_retire_request(dev, request);
1737
1738 list_del(&request->list);
b962442e 1739 list_del(&request->client_list);
9a298b2a 1740 kfree(request);
673a394b
EA		 1741 } else
1742 break;
1743 }
9d34e5db
CW		 1744
1745 if (unlikely (dev_priv->trace_irq_seqno &&
1746 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
8187a2b7
ZN		 1747
1748 ring->user_irq_put(dev, ring);
9d34e5db
CW		 1749 dev_priv->trace_irq_seqno = 0;
1750 }
673a394b
EA		 1751}
1752
b09a1fec
CW		 1753void
1754i915_gem_retire_requests(struct drm_device *dev)
1755{
1756 drm_i915_private_t *dev_priv = dev->dev_private;
1757
be72615b
CW		 1758 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1759 struct drm_i915_gem_object *obj_priv, *tmp;
1760
1761 /* We must be careful that during unbind() we do not
1762 * accidentally infinitely recurse into retire requests.
1763 * Currently:
1764 * retire -> free -> unbind -> wait -> retire_ring
1765 */
1766 list_for_each_entry_safe(obj_priv, tmp,
1767 &dev_priv->mm.deferred_free_list,
1768 list)
1769 i915_gem_free_object_tail(&obj_priv->base);
1770 }
1771
b09a1fec
CW		 1772 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1773 if (HAS_BSD(dev))
1774 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1775}
1776
673a394b
EA		 1777void
1778i915_gem_retire_work_handler(struct work_struct *work)
1779{
1780 drm_i915_private_t *dev_priv;
1781 struct drm_device *dev;
1782
1783 dev_priv = container_of(work, drm_i915_private_t,
1784 mm.retire_work.work);
1785 dev = dev_priv->dev;
1786
1787 mutex_lock(&dev->struct_mutex);
b09a1fec 1788 i915_gem_retire_requests(dev);
d1b851fc 1789
6dbe2772 1790 if (!dev_priv->mm.suspended &&
d1b851fc
ZN		 1791 (!list_empty(&dev_priv->render_ring.request_list) ||
1792 (HAS_BSD(dev) &&
1793 !list_empty(&dev_priv->bsd_ring.request_list))))
9c9fe1f8 1794 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1795 mutex_unlock(&dev->struct_mutex);
1796}
1797
5a5a0c64 1798int
852835f3
ZN		 1799i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1800 int interruptible, struct intel_ring_buffer *ring)
673a394b
EA		 1801{
1802 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1803 u32 ier;
673a394b
EA		 1804 int ret = 0;
1805
1806 BUG_ON(seqno == 0);
1807
ba1234d1 1808 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1809 return -EIO;
1810
852835f3 1811 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
bad720ff 1812 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1813 ier = I915_READ(DEIER) | I915_READ(GTIER);
1814 else
1815 ier = I915_READ(IER);
802c7eb6
JB		 1816 if (!ier) {
1817 DRM_ERROR("something (likely vbetool) disabled "
1818 "interrupts, re-enabling\n");
1819 i915_driver_irq_preinstall(dev);
1820 i915_driver_irq_postinstall(dev);
1821 }
1822
1c5d22f7
CW		 1823 trace_i915_gem_request_wait_begin(dev, seqno);
1824
852835f3 1825 ring->waiting_gem_seqno = seqno;
8187a2b7 1826 ring->user_irq_get(dev, ring);
48764bf4 1827 if (interruptible)
852835f3
ZN		 1828 ret = wait_event_interruptible(ring->irq_queue,
1829 i915_seqno_passed(
1830 ring->get_gem_seqno(dev, ring), seqno)
1831 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1832 else
852835f3
ZN		 1833 wait_event(ring->irq_queue,
1834 i915_seqno_passed(
1835 ring->get_gem_seqno(dev, ring), seqno)
1836 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1837
8187a2b7 1838 ring->user_irq_put(dev, ring);
852835f3 1839 ring->waiting_gem_seqno = 0;
1c5d22f7
CW		 1840
1841 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1842 }
ba1234d1 1843 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1844 ret = -EIO;
1845
1846 if (ret && ret != -ERESTARTSYS)
1847 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
852835f3 1848 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
673a394b
EA		 1849
1850 /* Directly dispatch request retiring. While we have the work queue
1851 * to handle this, the waiter on a request often wants an associated
1852 * buffer to have made it to the inactive list, and we would need
1853 * a separate wait queue to handle that.
1854 */
1855 if (ret == 0)
b09a1fec 1856 i915_gem_retire_requests_ring(dev, ring);
673a394b
EA		 1857
1858 return ret;
1859}
1860
48764bf4
DV		 1861/**
1862 * Waits for a sequence number to be signaled, and cleans up the
1863 * request and object lists appropriately for that event.
1864 */
1865static int
852835f3
ZN		 1866i915_wait_request(struct drm_device *dev, uint32_t seqno,
1867 struct intel_ring_buffer *ring)
48764bf4 1868{
852835f3 1869 return i915_do_wait_request(dev, seqno, 1, ring);
48764bf4
DV		 1870}
1871
8187a2b7
ZN		 1872static void
1873i915_gem_flush(struct drm_device *dev,
1874 uint32_t invalidate_domains,
1875 uint32_t flush_domains)
1876{
1877 drm_i915_private_t *dev_priv = dev->dev_private;
1878 if (flush_domains & I915_GEM_DOMAIN_CPU)
1879 drm_agp_chipset_flush(dev);
1880 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1881 invalidate_domains,
1882 flush_domains);
d1b851fc
ZN		 1883
1884 if (HAS_BSD(dev))
1885 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1886 invalidate_domains,
1887 flush_domains);
8187a2b7
ZN		 1888}
1889
852835f3
ZN		 1890static void
1891i915_gem_flush_ring(struct drm_device *dev,
1892 uint32_t invalidate_domains,
1893 uint32_t flush_domains,
1894 struct intel_ring_buffer *ring)
1895{
1896 if (flush_domains & I915_GEM_DOMAIN_CPU)
1897 drm_agp_chipset_flush(dev);
1898 ring->flush(dev, ring,
1899 invalidate_domains,
1900 flush_domains);
1901}
1902
673a394b
EA		 1903/**
1904 * Ensures that all rendering to the object has completed and the object is
1905 * safe to unbind from the GTT or access from the CPU.
1906 */
1907static int
1908i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1909{
1910 struct drm_device *dev = obj->dev;
23010e43 1911 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1912 int ret;
1913
e47c68e9
EA		 1914 /* This function only exists to support waiting for existing rendering,
1915 * not for emitting required flushes.
673a394b 1916 */
e47c68e9 1917 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1918
1919 /* If there is rendering queued on the buffer being evicted, wait for
1920 * it.
1921 */
1922 if (obj_priv->active) {
1923#if WATCH_BUF
1924 DRM_INFO("%s: object %p wait for seqno %08x\n",
1925 __func__, obj, obj_priv->last_rendering_seqno);
1926#endif
852835f3
ZN		 1927 ret = i915_wait_request(dev,
1928 obj_priv->last_rendering_seqno, obj_priv->ring);
673a394b
EA		 1929 if (ret != 0)
1930 return ret;
1931 }
1932
1933 return 0;
1934}
1935
1936/**
1937 * Unbinds an object from the GTT aperture.
1938 */
0f973f27 1939int
673a394b
EA		 1940i915_gem_object_unbind(struct drm_gem_object *obj)
1941{
1942 struct drm_device *dev = obj->dev;
4a87b8ca 1943 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1944 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1945 int ret = 0;
1946
1947#if WATCH_BUF
1948 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1949 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1950#endif
1951 if (obj_priv->gtt_space == NULL)
1952 return 0;
1953
1954 if (obj_priv->pin_count != 0) {
1955 DRM_ERROR("Attempting to unbind pinned buffer\n");
1956 return -EINVAL;
1957 }
1958
5323fd04
EA		 1959 /* blow away mappings if mapped through GTT */
1960 i915_gem_release_mmap(obj);
1961
673a394b
EA		 1962 /* Move the object to the CPU domain to ensure that
1963 * any possible CPU writes while it's not in the GTT
1964 * are flushed when we go to remap it. This will
1965 * also ensure that all pending GPU writes are finished
1966 * before we unbind.
1967 */
e47c68e9 1968 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
8dc1775d 1969 if (ret == -ERESTARTSYS)
673a394b 1970 return ret;
8dc1775d
CW		 1971 /* Continue on if we fail due to EIO, the GPU is hung so we
1972 * should be safe and we need to cleanup or else we might
1973 * cause memory corruption through use-after-free.
1974 */
673a394b 1975
5323fd04
EA		 1976 BUG_ON(obj_priv->active);
1977
96b47b65
DV		 1978 /* release the fence reg _after_ flushing */
1979 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1980 i915_gem_clear_fence_reg(obj);
1981
673a394b
EA		 1982 if (obj_priv->agp_mem != NULL) {
1983 drm_unbind_agp(obj_priv->agp_mem);
1984 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1985 obj_priv->agp_mem = NULL;
1986 }
1987
856fa198 1988 i915_gem_object_put_pages(obj);
a32808c0 1989 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 1990
1991 if (obj_priv->gtt_space) {
1992 atomic_dec(&dev->gtt_count);
1993 atomic_sub(obj->size, &dev->gtt_memory);
1994
1995 drm_mm_put_block(obj_priv->gtt_space);
1996 obj_priv->gtt_space = NULL;
1997 }
1998
1999 /* Remove ourselves from the LRU list if present. */
4a87b8ca 2000 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 2001 if (!list_empty(&obj_priv->list))
2002 list_del_init(&obj_priv->list);
4a87b8ca 2003 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 2004
963b4836
CW		 2005 if (i915_gem_object_is_purgeable(obj_priv))
2006 i915_gem_object_truncate(obj);
2007
1c5d22f7
CW		 2008 trace_i915_gem_object_unbind(obj);
2009
8dc1775d 2010 return ret;
673a394b
EA		 2011}
2012
07f73f69
CW		 2013static struct drm_gem_object *
2014i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2015{
2016 drm_i915_private_t *dev_priv = dev->dev_private;
2017 struct drm_i915_gem_object *obj_priv;
2018 struct drm_gem_object *best = NULL;
2019 struct drm_gem_object *first = NULL;
2020
2021 /* Try to find the smallest clean object */
2022 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
a8089e84 2023 struct drm_gem_object *obj = &obj_priv->base;
07f73f69 2024 if (obj->size >= min_size) {
963b4836
CW		 2025 if ((!obj_priv->dirty ||
2026 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2027 (!best || obj->size < best->size)) {
2028 best = obj;
2029 if (best->size == min_size)
2030 return best;
2031 }
2032 if (!first)
2033 first = obj;
2034 }
2035 }
2036
2037 return best ? best : first;
2038}
2039
4df2faf4
DV		 2040static int
2041i915_gpu_idle(struct drm_device *dev)
2042{
2043 drm_i915_private_t *dev_priv = dev->dev_private;
2044 bool lists_empty;
d1b851fc 2045 uint32_t seqno1, seqno2;
852835f3 2046 int ret;
4df2faf4
DV		 2047
2048 spin_lock(&dev_priv->mm.active_list_lock);
d1b851fc
ZN		 2049 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2050 list_empty(&dev_priv->render_ring.active_list) &&
2051 (!HAS_BSD(dev) ||
2052 list_empty(&dev_priv->bsd_ring.active_list)));
4df2faf4
DV		 2053 spin_unlock(&dev_priv->mm.active_list_lock);
2054
2055 if (lists_empty)
2056 return 0;
2057
2058 /* Flush everything onto the inactive list. */
2059 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
d1b851fc 2060 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
852835f3 2061 &dev_priv->render_ring);
d1b851fc 2062 if (seqno1 == 0)
4df2faf4 2063 return -ENOMEM;
d1b851fc
ZN		 2064 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2065
2066 if (HAS_BSD(dev)) {
2067 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2068 &dev_priv->bsd_ring);
2069 if (seqno2 == 0)
2070 return -ENOMEM;
2071
2072 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2073 if (ret)
2074 return ret;
2075 }
2076
4df2faf4 2077
852835f3 2078 return ret;
4df2faf4
DV		 2079}
2080
673a394b 2081static int
07f73f69
CW		 2082i915_gem_evict_everything(struct drm_device *dev)
2083{
2084 drm_i915_private_t *dev_priv = dev->dev_private;
07f73f69
CW		 2085 int ret;
2086 bool lists_empty;
2087
07f73f69
CW		 2088 spin_lock(&dev_priv->mm.active_list_lock);
2089 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2090 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2091 list_empty(&dev_priv->render_ring.active_list) &&
2092 (!HAS_BSD(dev)
2093 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2094 spin_unlock(&dev_priv->mm.active_list_lock);
2095
9731129c 2096 if (lists_empty)
07f73f69 2097 return -ENOSPC;
07f73f69
CW		 2098
2099 /* Flush everything (on to the inactive lists) and evict */
4df2faf4 2100 ret = i915_gpu_idle(dev);
07f73f69
CW		 2101 if (ret)
2102 return ret;
2103
99fcb766
DV		 2104 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2105
ab5ee576 2106 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2107 if (ret)
2108 return ret;
2109
2110 spin_lock(&dev_priv->mm.active_list_lock);
2111 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2112 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2113 list_empty(&dev_priv->render_ring.active_list) &&
2114 (!HAS_BSD(dev)
2115 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2116 spin_unlock(&dev_priv->mm.active_list_lock);
2117 BUG_ON(!lists_empty);
2118
2119 return 0;
2120}
2121
673a394b 2122static int
07f73f69 2123i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2124{
2125 drm_i915_private_t *dev_priv = dev->dev_private;
2126 struct drm_gem_object *obj;
07f73f69 2127 int ret;
673a394b 2128
852835f3 2129 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
d1b851fc 2130 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
673a394b 2131 for (;;) {
b09a1fec 2132 i915_gem_retire_requests(dev);
d1b851fc 2133
673a394b
EA		 2134 /* If there's an inactive buffer available now, grab it
2135 * and be done.
2136 */
07f73f69
CW		 2137 obj = i915_gem_find_inactive_object(dev, min_size);
2138 if (obj) {
2139 struct drm_i915_gem_object *obj_priv;
2140
673a394b
EA		 2141#if WATCH_LRU
2142 DRM_INFO("%s: evicting %p\n", __func__, obj);
2143#endif
23010e43 2144 obj_priv = to_intel_bo(obj);
07f73f69 2145 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2146 BUG_ON(obj_priv->active);
2147
2148 /* Wait on the rendering and unbind the buffer. */
07f73f69 2149 return i915_gem_object_unbind(obj);
673a394b
EA		 2150 }
2151
2152 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2153 * things, wait for the next to finish and hopefully leave us
2154 * a buffer to evict.
673a394b 2155 */
852835f3 2156 if (!list_empty(&render_ring->request_list)) {
673a394b
EA		 2157 struct drm_i915_gem_request *request;
2158
852835f3 2159 request = list_first_entry(&render_ring->request_list,
673a394b
EA		 2160 struct drm_i915_gem_request,
2161 list);
2162
852835f3
ZN		 2163 ret = i915_wait_request(dev,
2164 request->seqno, request->ring);
673a394b 2165 if (ret)
07f73f69 2166 return ret;
673a394b 2167
07f73f69 2168 continue;
673a394b
EA		 2169 }
2170
d1b851fc
ZN		 2171 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2172 struct drm_i915_gem_request *request;
2173
2174 request = list_first_entry(&bsd_ring->request_list,
2175 struct drm_i915_gem_request,
2176 list);
2177
2178 ret = i915_wait_request(dev,
2179 request->seqno, request->ring);
2180 if (ret)
2181 return ret;
2182
2183 continue;
2184 }
2185
673a394b
EA		 2186 /* If we didn't have anything on the request list but there
2187 * are buffers awaiting a flush, emit one and try again.
2188 * When we wait on it, those buffers waiting for that flush
2189 * will get moved to inactive.
2190 */
2191 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2192 struct drm_i915_gem_object *obj_priv;
673a394b 2193
9a1e2582
CW		 2194 /* Find an object that we can immediately reuse */
2195 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
a8089e84 2196 obj = &obj_priv->base;
9a1e2582
CW		 2197 if (obj->size >= min_size)
2198 break;
673a394b 2199
9a1e2582
CW		 2200 obj = NULL;
2201 }
673a394b 2202
9a1e2582
CW		 2203 if (obj != NULL) {
2204 uint32_t seqno;
673a394b 2205
852835f3
ZN		 2206 i915_gem_flush_ring(dev,
2207 obj->write_domain,
9a1e2582 2208 obj->write_domain,
852835f3
ZN		 2209 obj_priv->ring);
2210 seqno = i915_add_request(dev, NULL,
2211 obj->write_domain,
2212 obj_priv->ring);
9a1e2582
CW		 2213 if (seqno == 0)
2214 return -ENOMEM;
9a1e2582
CW		 2215 continue;
2216 }
673a394b
EA		 2217 }
2218
07f73f69
CW		 2219 /* If we didn't do any of the above, there's no single buffer
2220 * large enough to swap out for the new one, so just evict
2221 * everything and start again. (This should be rare.)
673a394b 2222 */
9731129c 2223 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2224 return i915_gem_evict_from_inactive_list(dev);
9731129c 2225 else
07f73f69 2226 return i915_gem_evict_everything(dev);
ac94a962 2227 }
ac94a962
KP		 2228}
2229
6911a9b8 2230int
4bdadb97
CW		 2231i915_gem_object_get_pages(struct drm_gem_object *obj,
2232 gfp_t gfpmask)
673a394b 2233{
23010e43 2234 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2235 int page_count, i;
2236 struct address_space *mapping;
2237 struct inode *inode;
2238 struct page *page;
673a394b 2239
778c3544
DV		 2240 BUG_ON(obj_priv->pages_refcount
2241 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2242
856fa198 2243 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2244 return 0;
2245
2246 /* Get the list of pages out of our struct file. They'll be pinned
2247 * at this point until we release them.
2248 */
2249 page_count = obj->size / PAGE_SIZE;
856fa198 2250 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2251 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2252 if (obj_priv->pages == NULL) {
856fa198 2253 obj_priv->pages_refcount--;
673a394b
EA		 2254 return -ENOMEM;
2255 }
2256
2257 inode = obj->filp->f_path.dentry->d_inode;
2258 mapping = inode->i_mapping;
2259 for (i = 0; i < page_count; i++) {
4bdadb97 2260 page = read_cache_page_gfp(mapping, i,
985b823b 2261 GFP_HIGHUSER |
4bdadb97 2262 __GFP_COLD |
cd9f040d 2263 __GFP_RECLAIMABLE |
4bdadb97 2264 gfpmask);
1f2b1013
CW		 2265 if (IS_ERR(page))
2266 goto err_pages;
2267
856fa198 2268 obj_priv->pages[i] = page;
673a394b 2269 }
280b713b
EA		 2270
2271 if (obj_priv->tiling_mode != I915_TILING_NONE)
2272 i915_gem_object_do_bit_17_swizzle(obj);
2273
673a394b 2274 return 0;
1f2b1013
CW		 2275
2276err_pages:
2277 while (i--)
2278 page_cache_release(obj_priv->pages[i]);
2279
2280 drm_free_large(obj_priv->pages);
2281 obj_priv->pages = NULL;
2282 obj_priv->pages_refcount--;
2283 return PTR_ERR(page);
673a394b
EA		 2284}
2285
4e901fdc
EA		 2286static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2287{
2288 struct drm_gem_object *obj = reg->obj;
2289 struct drm_device *dev = obj->dev;
2290 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2291 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2292 int regnum = obj_priv->fence_reg;
2293 uint64_t val;
2294
2295 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2296 0xfffff000) << 32;
2297 val |= obj_priv->gtt_offset & 0xfffff000;
2298 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2299 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2300
2301 if (obj_priv->tiling_mode == I915_TILING_Y)
2302 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2303 val |= I965_FENCE_REG_VALID;
2304
2305 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2306}
2307
de151cf6
JB		 2308static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2309{
2310 struct drm_gem_object *obj = reg->obj;
2311 struct drm_device *dev = obj->dev;
2312 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2313 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2314 int regnum = obj_priv->fence_reg;
2315 uint64_t val;
2316
2317 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2318 0xfffff000) << 32;
2319 val |= obj_priv->gtt_offset & 0xfffff000;
2320 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2321 if (obj_priv->tiling_mode == I915_TILING_Y)
2322 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2323 val |= I965_FENCE_REG_VALID;
2324
2325 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2326}
2327
2328static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2329{
2330 struct drm_gem_object *obj = reg->obj;
2331 struct drm_device *dev = obj->dev;
2332 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2333 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2334 int regnum = obj_priv->fence_reg;
0f973f27 2335 int tile_width;
dc529a4f 2336 uint32_t fence_reg, val;
de151cf6
JB		 2337 uint32_t pitch_val;
2338
2339 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2340 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2341 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2342 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2343 return;
2344 }
2345
0f973f27
JB		 2346 if (obj_priv->tiling_mode == I915_TILING_Y &&
2347 HAS_128_BYTE_Y_TILING(dev))
2348 tile_width = 128;
de151cf6 2349 else
0f973f27
JB		 2350 tile_width = 512;
2351
2352 /* Note: pitch better be a power of two tile widths */
2353 pitch_val = obj_priv->stride / tile_width;
2354 pitch_val = ffs(pitch_val) - 1;
de151cf6 2355
c36a2a6d
DV		 2356 if (obj_priv->tiling_mode == I915_TILING_Y &&
2357 HAS_128_BYTE_Y_TILING(dev))
2358 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2359 else
2360 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2361
de151cf6
JB		 2362 val = obj_priv->gtt_offset;
2363 if (obj_priv->tiling_mode == I915_TILING_Y)
2364 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2365 val |= I915_FENCE_SIZE_BITS(obj->size);
2366 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2367 val |= I830_FENCE_REG_VALID;
2368
dc529a4f
EA		 2369 if (regnum < 8)
2370 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2371 else
2372 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2373 I915_WRITE(fence_reg, val);
de151cf6
JB		 2374}
2375
2376static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2377{
2378 struct drm_gem_object *obj = reg->obj;
2379 struct drm_device *dev = obj->dev;
2380 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2381 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2382 int regnum = obj_priv->fence_reg;
2383 uint32_t val;
2384 uint32_t pitch_val;
8d7773a3 2385 uint32_t fence_size_bits;
de151cf6 2386
8d7773a3 2387 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2388 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2389 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2390 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2391 return;
2392 }
2393
e76a16de
EA		 2394 pitch_val = obj_priv->stride / 128;
2395 pitch_val = ffs(pitch_val) - 1;
2396 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2397
de151cf6
JB		 2398 val = obj_priv->gtt_offset;
2399 if (obj_priv->tiling_mode == I915_TILING_Y)
2400 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2401 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2402 WARN_ON(fence_size_bits & ~0x00000f00);
2403 val |= fence_size_bits;
de151cf6
JB		 2404 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2405 val |= I830_FENCE_REG_VALID;
2406
2407 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2408}
2409
ae3db24a
DV		 2410static int i915_find_fence_reg(struct drm_device *dev)
2411{
2412 struct drm_i915_fence_reg *reg = NULL;
2413 struct drm_i915_gem_object *obj_priv = NULL;
2414 struct drm_i915_private *dev_priv = dev->dev_private;
2415 struct drm_gem_object *obj = NULL;
2416 int i, avail, ret;
2417
2418 /* First try to find a free reg */
2419 avail = 0;
2420 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2421 reg = &dev_priv->fence_regs[i];
2422 if (!reg->obj)
2423 return i;
2424
23010e43 2425 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2426 if (!obj_priv->pin_count)
2427 avail++;
2428 }
2429
2430 if (avail == 0)
2431 return -ENOSPC;
2432
2433 /* None available, try to steal one or wait for a user to finish */
2434 i = I915_FENCE_REG_NONE;
007cc8ac
DV		 2435 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2436 lru_list) {
2437 obj = reg->obj;
2438 obj_priv = to_intel_bo(obj);
ae3db24a
DV		 2439
2440 if (obj_priv->pin_count)
2441 continue;
2442
2443 /* found one! */
2444 i = obj_priv->fence_reg;
2445 break;
2446 }
2447
2448 BUG_ON(i == I915_FENCE_REG_NONE);
2449
2450 /* We only have a reference on obj from the active list. put_fence_reg
2451 * might drop that one, causing a use-after-free in it. So hold a
2452 * private reference to obj like the other callers of put_fence_reg
2453 * (set_tiling ioctl) do. */
2454 drm_gem_object_reference(obj);
2455 ret = i915_gem_object_put_fence_reg(obj);
2456 drm_gem_object_unreference(obj);
2457 if (ret != 0)
2458 return ret;
2459
2460 return i;
2461}
2462
de151cf6
JB		 2463/**
2464 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2465 * @obj: object to map through a fence reg
2466 *
2467 * When mapping objects through the GTT, userspace wants to be able to write
2468 * to them without having to worry about swizzling if the object is tiled.
2469 *
2470 * This function walks the fence regs looking for a free one for @obj,
2471 * stealing one if it can't find any.
2472 *
2473 * It then sets up the reg based on the object's properties: address, pitch
2474 * and tiling format.
2475 */
8c4b8c3f
CW		 2476int
2477i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2478{
2479 struct drm_device *dev = obj->dev;
79e53945 2480 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2481 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2482 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2483 int ret;
de151cf6 2484
a09ba7fa
EA		 2485 /* Just update our place in the LRU if our fence is getting used. */
2486 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 2487 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2488 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa
EA		 2489 return 0;
2490 }
2491
de151cf6
JB		 2492 switch (obj_priv->tiling_mode) {
2493 case I915_TILING_NONE:
2494 WARN(1, "allocating a fence for non-tiled object?\n");
2495 break;
2496 case I915_TILING_X:
0f973f27
JB		 2497 if (!obj_priv->stride)
2498 return -EINVAL;
2499 WARN((obj_priv->stride & (512 - 1)),
2500 "object 0x%08x is X tiled but has non-512B pitch\n",
2501 obj_priv->gtt_offset);
de151cf6
JB		 2502 break;
2503 case I915_TILING_Y:
0f973f27
JB		 2504 if (!obj_priv->stride)
2505 return -EINVAL;
2506 WARN((obj_priv->stride & (128 - 1)),
2507 "object 0x%08x is Y tiled but has non-128B pitch\n",
2508 obj_priv->gtt_offset);
de151cf6
JB		 2509 break;
2510 }
2511
ae3db24a
DV		 2512 ret = i915_find_fence_reg(dev);
2513 if (ret < 0)
2514 return ret;
de151cf6 2515
ae3db24a
DV		 2516 obj_priv->fence_reg = ret;
2517 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
007cc8ac 2518 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa 2519
de151cf6
JB		 2520 reg->obj = obj;
2521
4e901fdc
EA		 2522 if (IS_GEN6(dev))
2523 sandybridge_write_fence_reg(reg);
2524 else if (IS_I965G(dev))
de151cf6
JB		 2525 i965_write_fence_reg(reg);
2526 else if (IS_I9XX(dev))
2527 i915_write_fence_reg(reg);
2528 else
2529 i830_write_fence_reg(reg);
d9ddcb96 2530
ae3db24a
DV		 2531 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2532 obj_priv->tiling_mode);
1c5d22f7 2533
d9ddcb96 2534 return 0;
de151cf6
JB		 2535}
2536
2537/**
2538 * i915_gem_clear_fence_reg - clear out fence register info
2539 * @obj: object to clear
2540 *
2541 * Zeroes out the fence register itself and clears out the associated
2542 * data structures in dev_priv and obj_priv.
2543 */
2544static void
2545i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2546{
2547 struct drm_device *dev = obj->dev;
79e53945 2548 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2549 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
007cc8ac
DV		 2550 struct drm_i915_fence_reg *reg =
2551 &dev_priv->fence_regs[obj_priv->fence_reg];
de151cf6 2552
4e901fdc
EA		 2553 if (IS_GEN6(dev)) {
2554 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2555 (obj_priv->fence_reg * 8), 0);
2556 } else if (IS_I965G(dev)) {
de151cf6 2557 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
4e901fdc 2558 } else {
dc529a4f
EA		 2559 uint32_t fence_reg;
2560
2561 if (obj_priv->fence_reg < 8)
2562 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2563 else
2564 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2565 8) * 4;
2566
2567 I915_WRITE(fence_reg, 0);
2568 }
de151cf6 2569
007cc8ac 2570 reg->obj = NULL;
de151cf6 2571 obj_priv->fence_reg = I915_FENCE_REG_NONE;
007cc8ac 2572 list_del_init(&reg->lru_list);
de151cf6
JB		 2573}
2574
52dc7d32
CW		 2575/**
2576 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2577 * to the buffer to finish, and then resets the fence register.
2578 * @obj: tiled object holding a fence register.
2579 *
2580 * Zeroes out the fence register itself and clears out the associated
2581 * data structures in dev_priv and obj_priv.
2582 */
2583int
2584i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2585{
2586 struct drm_device *dev = obj->dev;
23010e43 2587 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2588
2589 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2590 return 0;
2591
10ae9bd2
DV		 2592 /* If we've changed tiling, GTT-mappings of the object
2593 * need to re-fault to ensure that the correct fence register
2594 * setup is in place.
2595 */
2596 i915_gem_release_mmap(obj);
2597
52dc7d32
CW		 2598 /* On the i915, GPU access to tiled buffers is via a fence,
2599 * therefore we must wait for any outstanding access to complete
2600 * before clearing the fence.
2601 */
2602 if (!IS_I965G(dev)) {
2603 int ret;
2604
2dafb1e0
CW		 2605 ret = i915_gem_object_flush_gpu_write_domain(obj);
2606 if (ret != 0)
2607 return ret;
2608
52dc7d32
CW		 2609 ret = i915_gem_object_wait_rendering(obj);
2610 if (ret != 0)
2611 return ret;
2612 }
2613
4a726612 2614 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2615 i915_gem_clear_fence_reg (obj);
2616
2617 return 0;
2618}
2619
673a394b
EA		 2620/**
2621 * Finds free space in the GTT aperture and binds the object there.
2622 */
2623static int
2624i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2625{
2626 struct drm_device *dev = obj->dev;
2627 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2628 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2629 struct drm_mm_node *free_space;
4bdadb97 2630 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2631 int ret;
673a394b 2632
bb6baf76 2633 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2634 DRM_ERROR("Attempting to bind a purgeable object\n");
2635 return -EINVAL;
2636 }
2637
673a394b 2638 if (alignment == 0)
0f973f27 2639 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2640 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2641 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2642 return -EINVAL;
2643 }
2644
654fc607
CW		 2645 /* If the object is bigger than the entire aperture, reject it early
2646 * before evicting everything in a vain attempt to find space.
2647 */
2648 if (obj->size > dev->gtt_total) {
2649 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2650 return -E2BIG;
2651 }
2652
673a394b
EA		 2653 search_free:
2654 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2655 obj->size, alignment, 0);
2656 if (free_space != NULL) {
2657 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2658 alignment);
db3307a9 2659 if (obj_priv->gtt_space != NULL)
673a394b 2660 obj_priv->gtt_offset = obj_priv->gtt_space->start;
673a394b
EA		 2661 }
2662 if (obj_priv->gtt_space == NULL) {
2663 /* If the gtt is empty and we're still having trouble
2664 * fitting our object in, we're out of memory.
2665 */
2666#if WATCH_LRU
2667 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2668#endif
07f73f69 2669 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2670 if (ret)
673a394b 2671 return ret;
9731129c 2672
673a394b
EA		 2673 goto search_free;
2674 }
2675
2676#if WATCH_BUF
cfd43c02 2677 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2678 obj->size, obj_priv->gtt_offset);
2679#endif
4bdadb97 2680 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2681 if (ret) {
2682 drm_mm_put_block(obj_priv->gtt_space);
2683 obj_priv->gtt_space = NULL;
07f73f69
CW		 2684
2685 if (ret == -ENOMEM) {
2686 /* first try to clear up some space from the GTT */
2687 ret = i915_gem_evict_something(dev, obj->size);
2688 if (ret) {
07f73f69 2689 /* now try to shrink everyone else */
4bdadb97
CW		 2690 if (gfpmask) {
2691 gfpmask = 0;
2692 goto search_free;
07f73f69
CW		 2693 }
2694
2695 return ret;
2696 }
2697
2698 goto search_free;
2699 }
2700
673a394b
EA		 2701 return ret;
2702 }
2703
673a394b
EA		 2704 /* Create an AGP memory structure pointing at our pages, and bind it
2705 * into the GTT.
2706 */
2707 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2708 obj_priv->pages,
07f73f69 2709 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2710 obj_priv->gtt_offset,
2711 obj_priv->agp_type);
673a394b 2712 if (obj_priv->agp_mem == NULL) {
856fa198 2713 i915_gem_object_put_pages(obj);
673a394b
EA		 2714 drm_mm_put_block(obj_priv->gtt_space);
2715 obj_priv->gtt_space = NULL;
07f73f69
CW		 2716
2717 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2718 if (ret)
07f73f69 2719 return ret;
07f73f69
CW		 2720
2721 goto search_free;
673a394b
EA		 2722 }
2723 atomic_inc(&dev->gtt_count);
2724 atomic_add(obj->size, &dev->gtt_memory);
2725
2726 /* Assert that the object is not currently in any GPU domain. As it
2727 * wasn't in the GTT, there shouldn't be any way it could have been in
2728 * a GPU cache
2729 */
21d509e3
CW		 2730 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2731 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2732
1c5d22f7
CW		 2733 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2734
673a394b
EA		 2735 return 0;
2736}
2737
2738void
2739i915_gem_clflush_object(struct drm_gem_object *obj)
2740{
23010e43 2741 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2742
2743 /* If we don't have a page list set up, then we're not pinned
2744 * to GPU, and we can ignore the cache flush because it'll happen
2745 * again at bind time.
2746 */
856fa198 2747 if (obj_priv->pages == NULL)
673a394b
EA		 2748 return;
2749
1c5d22f7 2750 trace_i915_gem_object_clflush(obj);
cfa16a0d 2751
856fa198 2752 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2753}
2754
e47c68e9 2755/** Flushes any GPU write domain for the object if it's dirty. */
2dafb1e0 2756static int
e47c68e9
EA		 2757i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2758{
2759 struct drm_device *dev = obj->dev;
1c5d22f7 2760 uint32_t old_write_domain;
852835f3 2761 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
e47c68e9
EA		 2762
2763 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2dafb1e0 2764 return 0;
e47c68e9
EA		 2765
2766 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2767 old_write_domain = obj->write_domain;
e47c68e9 2768 i915_gem_flush(dev, 0, obj->write_domain);
2dafb1e0
CW		 2769 if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2770 return -ENOMEM;
1c5d22f7
CW		 2771
2772 trace_i915_gem_object_change_domain(obj,
2773 obj->read_domains,
2774 old_write_domain);
2dafb1e0 2775 return 0;
e47c68e9
EA		 2776}
2777
2778/** Flushes the GTT write domain for the object if it's dirty. */
2779static void
2780i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2781{
1c5d22f7
CW		 2782 uint32_t old_write_domain;
2783
e47c68e9
EA		 2784 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2785 return;
2786
2787 /* No actual flushing is required for the GTT write domain. Writes
2788 * to it immediately go to main memory as far as we know, so there's
2789 * no chipset flush. It also doesn't land in render cache.
2790 */
1c5d22f7 2791 old_write_domain = obj->write_domain;
e47c68e9 2792 obj->write_domain = 0;
1c5d22f7
CW		 2793
2794 trace_i915_gem_object_change_domain(obj,
2795 obj->read_domains,
2796 old_write_domain);
e47c68e9
EA		 2797}
2798
2799/** Flushes the CPU write domain for the object if it's dirty. */
2800static void
2801i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2802{
2803 struct drm_device *dev = obj->dev;
1c5d22f7 2804 uint32_t old_write_domain;
e47c68e9
EA		 2805
2806 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2807 return;
2808
2809 i915_gem_clflush_object(obj);
2810 drm_agp_chipset_flush(dev);
1c5d22f7 2811 old_write_domain = obj->write_domain;
e47c68e9 2812 obj->write_domain = 0;
1c5d22f7
CW		 2813
2814 trace_i915_gem_object_change_domain(obj,
2815 obj->read_domains,
2816 old_write_domain);
e47c68e9
EA		 2817}
2818
2dafb1e0 2819int
6b95a207
KH		 2820i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2821{
2dafb1e0
CW		 2822 int ret = 0;
2823
6b95a207
KH		 2824 switch (obj->write_domain) {
2825 case I915_GEM_DOMAIN_GTT:
2826 i915_gem_object_flush_gtt_write_domain(obj);
2827 break;
2828 case I915_GEM_DOMAIN_CPU:
2829 i915_gem_object_flush_cpu_write_domain(obj);
2830 break;
2831 default:
2dafb1e0 2832 ret = i915_gem_object_flush_gpu_write_domain(obj);
6b95a207
KH		 2833 break;
2834 }
2dafb1e0
CW		 2835
2836 return ret;
6b95a207
KH		 2837}
2838
2ef7eeaa
EA		 2839/**
2840 * Moves a single object to the GTT read, and possibly write domain.
2841 *
2842 * This function returns when the move is complete, including waiting on
2843 * flushes to occur.
2844 */
79e53945 2845int
2ef7eeaa
EA		 2846i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2847{
23010e43 2848 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2849 uint32_t old_write_domain, old_read_domains;
e47c68e9 2850 int ret;
2ef7eeaa 2851
02354392
EA		 2852 /* Not valid to be called on unbound objects. */
2853 if (obj_priv->gtt_space == NULL)
2854 return -EINVAL;
2855
2dafb1e0
CW		 2856 ret = i915_gem_object_flush_gpu_write_domain(obj);
2857 if (ret != 0)
2858 return ret;
2859
e47c68e9
EA		 2860 /* Wait on any GPU rendering and flushing to occur. */
2861 ret = i915_gem_object_wait_rendering(obj);
2862 if (ret != 0)
2863 return ret;
2864
1c5d22f7
CW		 2865 old_write_domain = obj->write_domain;
2866 old_read_domains = obj->read_domains;
2867
e47c68e9
EA		 2868 /* If we're writing through the GTT domain, then CPU and GPU caches
2869 * will need to be invalidated at next use.
2ef7eeaa 2870 */
e47c68e9
EA		 2871 if (write)
2872 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2873
e47c68e9 2874 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2875
e47c68e9
EA		 2876 /* It should now be out of any other write domains, and we can update
2877 * the domain values for our changes.
2878 */
2879 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2880 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2881 if (write) {
2882 obj->write_domain = I915_GEM_DOMAIN_GTT;
2883 obj_priv->dirty = 1;
2ef7eeaa
EA		 2884 }
2885
1c5d22f7
CW		 2886 trace_i915_gem_object_change_domain(obj,
2887 old_read_domains,
2888 old_write_domain);
2889
e47c68e9
EA		 2890 return 0;
2891}
2892
b9241ea3
ZW		 2893/*
2894 * Prepare buffer for display plane. Use uninterruptible for possible flush
2895 * wait, as in modesetting process we're not supposed to be interrupted.
2896 */
2897int
2898i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2899{
2900 struct drm_device *dev = obj->dev;
23010e43 2901 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2902 uint32_t old_write_domain, old_read_domains;
2903 int ret;
2904
2905 /* Not valid to be called on unbound objects. */
2906 if (obj_priv->gtt_space == NULL)
2907 return -EINVAL;
2908
2dafb1e0
CW		 2909 ret = i915_gem_object_flush_gpu_write_domain(obj);
2910 if (ret)
2911 return ret;
b9241ea3
ZW		 2912
2913 /* Wait on any GPU rendering and flushing to occur. */
2914 if (obj_priv->active) {
2915#if WATCH_BUF
2916 DRM_INFO("%s: object %p wait for seqno %08x\n",
2917 __func__, obj, obj_priv->last_rendering_seqno);
2918#endif
852835f3
ZN		 2919 ret = i915_do_wait_request(dev,
2920 obj_priv->last_rendering_seqno,
2921 0,
2922 obj_priv->ring);
b9241ea3
ZW		 2923 if (ret != 0)
2924 return ret;
2925 }
2926
b118c1e3
CW		 2927 i915_gem_object_flush_cpu_write_domain(obj);
2928
b9241ea3
ZW		 2929 old_write_domain = obj->write_domain;
2930 old_read_domains = obj->read_domains;
2931
b9241ea3
ZW		 2932 /* It should now be out of any other write domains, and we can update
2933 * the domain values for our changes.
2934 */
2935 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
b118c1e3 2936 obj->read_domains = I915_GEM_DOMAIN_GTT;
b9241ea3
ZW		 2937 obj->write_domain = I915_GEM_DOMAIN_GTT;
2938 obj_priv->dirty = 1;
2939
2940 trace_i915_gem_object_change_domain(obj,
2941 old_read_domains,
2942 old_write_domain);
2943
2944 return 0;
2945}
2946
e47c68e9
EA		 2947/**
2948 * Moves a single object to the CPU read, and possibly write domain.
2949 *
2950 * This function returns when the move is complete, including waiting on
2951 * flushes to occur.
2952 */
2953static int
2954i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2955{
1c5d22f7 2956 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2957 int ret;
2958
2dafb1e0
CW		 2959 ret = i915_gem_object_flush_gpu_write_domain(obj);
2960 if (ret)
2961 return ret;
2962
2ef7eeaa 2963 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2964 ret = i915_gem_object_wait_rendering(obj);
2965 if (ret != 0)
2966 return ret;
2ef7eeaa 2967
e47c68e9 2968 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2969
e47c68e9
EA		 2970 /* If we have a partially-valid cache of the object in the CPU,
2971 * finish invalidating it and free the per-page flags.
2ef7eeaa 2972 */
e47c68e9 2973 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2974
1c5d22f7
CW		 2975 old_write_domain = obj->write_domain;
2976 old_read_domains = obj->read_domains;
2977
e47c68e9
EA		 2978 /* Flush the CPU cache if it's still invalid. */
2979 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2980 i915_gem_clflush_object(obj);
2ef7eeaa 2981
e47c68e9 2982 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2983 }
2984
2985 /* It should now be out of any other write domains, and we can update
2986 * the domain values for our changes.
2987 */
e47c68e9
EA		 2988 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2989
2990 /* If we're writing through the CPU, then the GPU read domains will
2991 * need to be invalidated at next use.
2992 */
2993 if (write) {
2994 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2995 obj->write_domain = I915_GEM_DOMAIN_CPU;
2996 }
2ef7eeaa 2997
1c5d22f7
CW		 2998 trace_i915_gem_object_change_domain(obj,
2999 old_read_domains,
3000 old_write_domain);
3001
2ef7eeaa
EA		 3002 return 0;
3003}
3004
673a394b
EA		 3005/*
3006 * Set the next domain for the specified object. This
3007 * may not actually perform the necessary flushing/invaliding though,
3008 * as that may want to be batched with other set_domain operations
3009 *
3010 * This is (we hope) the only really tricky part of gem. The goal
3011 * is fairly simple -- track which caches hold bits of the object
3012 * and make sure they remain coherent. A few concrete examples may
3013 * help to explain how it works. For shorthand, we use the notation
3014 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3015 * a pair of read and write domain masks.
3016 *
3017 * Case 1: the batch buffer
3018 *
3019 * 1. Allocated
3020 * 2. Written by CPU
3021 * 3. Mapped to GTT
3022 * 4. Read by GPU
3023 * 5. Unmapped from GTT
3024 * 6. Freed
3025 *
3026 * Let's take these a step at a time
3027 *
3028 * 1. Allocated
3029 * Pages allocated from the kernel may still have
3030 * cache contents, so we set them to (CPU, CPU) always.
3031 * 2. Written by CPU (using pwrite)
3032 * The pwrite function calls set_domain (CPU, CPU) and
3033 * this function does nothing (as nothing changes)
3034 * 3. Mapped by GTT
3035 * This function asserts that the object is not
3036 * currently in any GPU-based read or write domains
3037 * 4. Read by GPU
3038 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3039 * As write_domain is zero, this function adds in the
3040 * current read domains (CPU+COMMAND, 0).
3041 * flush_domains is set to CPU.
3042 * invalidate_domains is set to COMMAND
3043 * clflush is run to get data out of the CPU caches
3044 * then i915_dev_set_domain calls i915_gem_flush to
3045 * emit an MI_FLUSH and drm_agp_chipset_flush
3046 * 5. Unmapped from GTT
3047 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3048 * flush_domains and invalidate_domains end up both zero
3049 * so no flushing/invalidating happens
3050 * 6. Freed
3051 * yay, done
3052 *
3053 * Case 2: The shared render buffer
3054 *
3055 * 1. Allocated
3056 * 2. Mapped to GTT
3057 * 3. Read/written by GPU
3058 * 4. set_domain to (CPU,CPU)
3059 * 5. Read/written by CPU
3060 * 6. Read/written by GPU
3061 *
3062 * 1. Allocated
3063 * Same as last example, (CPU, CPU)
3064 * 2. Mapped to GTT
3065 * Nothing changes (assertions find that it is not in the GPU)
3066 * 3. Read/written by GPU
3067 * execbuffer calls set_domain (RENDER, RENDER)
3068 * flush_domains gets CPU
3069 * invalidate_domains gets GPU
3070 * clflush (obj)
3071 * MI_FLUSH and drm_agp_chipset_flush
3072 * 4. set_domain (CPU, CPU)
3073 * flush_domains gets GPU
3074 * invalidate_domains gets CPU
3075 * wait_rendering (obj) to make sure all drawing is complete.
3076 * This will include an MI_FLUSH to get the data from GPU
3077 * to memory
3078 * clflush (obj) to invalidate the CPU cache
3079 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3080 * 5. Read/written by CPU
3081 * cache lines are loaded and dirtied
3082 * 6. Read written by GPU
3083 * Same as last GPU access
3084 *
3085 * Case 3: The constant buffer
3086 *
3087 * 1. Allocated
3088 * 2. Written by CPU
3089 * 3. Read by GPU
3090 * 4. Updated (written) by CPU again
3091 * 5. Read by GPU
3092 *
3093 * 1. Allocated
3094 * (CPU, CPU)
3095 * 2. Written by CPU
3096 * (CPU, CPU)
3097 * 3. Read by GPU
3098 * (CPU+RENDER, 0)
3099 * flush_domains = CPU
3100 * invalidate_domains = RENDER
3101 * clflush (obj)
3102 * MI_FLUSH
3103 * drm_agp_chipset_flush
3104 * 4. Updated (written) by CPU again
3105 * (CPU, CPU)
3106 * flush_domains = 0 (no previous write domain)
3107 * invalidate_domains = 0 (no new read domains)
3108 * 5. Read by GPU
3109 * (CPU+RENDER, 0)
3110 * flush_domains = CPU
3111 * invalidate_domains = RENDER
3112 * clflush (obj)
3113 * MI_FLUSH
3114 * drm_agp_chipset_flush
3115 */
c0d90829 3116static void
8b0e378a 3117i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3118{
3119 struct drm_device *dev = obj->dev;
23010e43 3120 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 3121 uint32_t invalidate_domains = 0;
3122 uint32_t flush_domains = 0;
1c5d22f7 3123 uint32_t old_read_domains;
e47c68e9 3124
8b0e378a
EA		 3125 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3126 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3127
652c393a
JB		 3128 intel_mark_busy(dev, obj);
3129
673a394b
EA		 3130#if WATCH_BUF
3131 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3132 __func__, obj,
8b0e378a
EA		 3133 obj->read_domains, obj->pending_read_domains,
3134 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 3135#endif
3136 /*
3137 * If the object isn't moving to a new write domain,
3138 * let the object stay in multiple read domains
3139 */
8b0e378a
EA		 3140 if (obj->pending_write_domain == 0)
3141 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3142 else
3143 obj_priv->dirty = 1;
3144
3145 /*
3146 * Flush the current write domain if
3147 * the new read domains don't match. Invalidate
3148 * any read domains which differ from the old
3149 * write domain
3150 */
8b0e378a
EA		 3151 if (obj->write_domain &&
3152 obj->write_domain != obj->pending_read_domains) {
673a394b 3153 flush_domains |= obj->write_domain;
8b0e378a
EA		 3154 invalidate_domains |=
3155 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3156 }
3157 /*
3158 * Invalidate any read caches which may have
3159 * stale data. That is, any new read domains.
3160 */
8b0e378a 3161 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3162 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3163#if WATCH_BUF
3164 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3165 __func__, flush_domains, invalidate_domains);
3166#endif
673a394b
EA		 3167 i915_gem_clflush_object(obj);
3168 }
3169
1c5d22f7
CW		 3170 old_read_domains = obj->read_domains;
3171
efbeed96
EA		 3172 /* The actual obj->write_domain will be updated with
3173 * pending_write_domain after we emit the accumulated flush for all
3174 * of our domain changes in execbuffers (which clears objects'
3175 * write_domains). So if we have a current write domain that we
3176 * aren't changing, set pending_write_domain to that.
3177 */
3178 if (flush_domains == 0 && obj->pending_write_domain == 0)
3179 obj->pending_write_domain = obj->write_domain;
8b0e378a 3180 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3181
3182 dev->invalidate_domains |= invalidate_domains;
3183 dev->flush_domains |= flush_domains;
3184#if WATCH_BUF
3185 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3186 __func__,
3187 obj->read_domains, obj->write_domain,
3188 dev->invalidate_domains, dev->flush_domains);
3189#endif
1c5d22f7
CW		 3190
3191 trace_i915_gem_object_change_domain(obj,
3192 old_read_domains,
3193 obj->write_domain);
673a394b
EA		 3194}
3195
3196/**
e47c68e9 3197 * Moves the object from a partially CPU read to a full one.
673a394b 3198 *
e47c68e9
EA		 3199 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3200 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3201 */
e47c68e9
EA		 3202static void
3203i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3204{
23010e43 3205 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3206
e47c68e9
EA		 3207 if (!obj_priv->page_cpu_valid)
3208 return;
3209
3210 /* If we're partially in the CPU read domain, finish moving it in.
3211 */
3212 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3213 int i;
3214
3215 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3216 if (obj_priv->page_cpu_valid[i])
3217 continue;
856fa198 3218 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3219 }
e47c68e9
EA		 3220 }
3221
3222 /* Free the page_cpu_valid mappings which are now stale, whether
3223 * or not we've got I915_GEM_DOMAIN_CPU.
3224 */
9a298b2a 3225 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3226 obj_priv->page_cpu_valid = NULL;
3227}
3228
3229/**
3230 * Set the CPU read domain on a range of the object.
3231 *
3232 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3233 * not entirely valid. The page_cpu_valid member of the object flags which
3234 * pages have been flushed, and will be respected by
3235 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3236 * of the whole object.
3237 *
3238 * This function returns when the move is complete, including waiting on
3239 * flushes to occur.
3240 */
3241static int
3242i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3243 uint64_t offset, uint64_t size)
3244{
23010e43 3245 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3246 uint32_t old_read_domains;
e47c68e9 3247 int i, ret;
673a394b 3248
e47c68e9
EA		 3249 if (offset == 0 && size == obj->size)
3250 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3251
2dafb1e0
CW		 3252 ret = i915_gem_object_flush_gpu_write_domain(obj);
3253 if (ret)
3254 return ret;
3255
e47c68e9 3256 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3257 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3258 if (ret != 0)
6a47baa6 3259 return ret;
e47c68e9
EA		 3260 i915_gem_object_flush_gtt_write_domain(obj);
3261
3262 /* If we're already fully in the CPU read domain, we're done. */
3263 if (obj_priv->page_cpu_valid == NULL &&
3264 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3265 return 0;
673a394b 3266
e47c68e9
EA		 3267 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3268 * newly adding I915_GEM_DOMAIN_CPU
3269 */
673a394b 3270 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3271 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3272 GFP_KERNEL);
e47c68e9
EA		 3273 if (obj_priv->page_cpu_valid == NULL)
3274 return -ENOMEM;
3275 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3276 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3277
3278 /* Flush the cache on any pages that are still invalid from the CPU's
3279 * perspective.
3280 */
e47c68e9
EA		 3281 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3282 i++) {
673a394b
EA		 3283 if (obj_priv->page_cpu_valid[i])
3284 continue;
3285
856fa198 3286 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3287
3288 obj_priv->page_cpu_valid[i] = 1;
3289 }
3290
e47c68e9
EA		 3291 /* It should now be out of any other write domains, and we can update
3292 * the domain values for our changes.
3293 */
3294 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3295
1c5d22f7 3296 old_read_domains = obj->read_domains;
e47c68e9
EA		 3297 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3298
1c5d22f7
CW		 3299 trace_i915_gem_object_change_domain(obj,
3300 old_read_domains,
3301 obj->write_domain);
3302
673a394b
EA		 3303 return 0;
3304}
3305
673a394b
EA		 3306/**
3307 * Pin an object to the GTT and evaluate the relocations landing in it.
3308 */
3309static int
3310i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3311 struct drm_file *file_priv,
76446cac 3312 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3313 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3314{
3315 struct drm_device *dev = obj->dev;
0839ccb8 3316 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3317 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3318 int i, ret;
0839ccb8 3319 void __iomem *reloc_page;
76446cac
JB		 3320 bool need_fence;
3321
3322 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3323 obj_priv->tiling_mode != I915_TILING_NONE;
3324
3325 /* Check fence reg constraints and rebind if necessary */
808b24d6
CW		 3326 if (need_fence &&
3327 !i915_gem_object_fence_offset_ok(obj,
3328 obj_priv->tiling_mode)) {
3329 ret = i915_gem_object_unbind(obj);
3330 if (ret)
3331 return ret;
3332 }
673a394b
EA		 3333
3334 /* Choose the GTT offset for our buffer and put it there. */
3335 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3336 if (ret)
3337 return ret;
3338
76446cac
JB		 3339 /*
3340 * Pre-965 chips need a fence register set up in order to
3341 * properly handle blits to/from tiled surfaces.
3342 */
3343 if (need_fence) {
3344 ret = i915_gem_object_get_fence_reg(obj);
3345 if (ret != 0) {
76446cac
JB		 3346 i915_gem_object_unpin(obj);
3347 return ret;
3348 }
3349 }
3350
673a394b
EA		 3351 entry->offset = obj_priv->gtt_offset;
3352
673a394b
EA		 3353 /* Apply the relocations, using the GTT aperture to avoid cache
3354 * flushing requirements.
3355 */
3356 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3357 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3358 struct drm_gem_object *target_obj;
3359 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3360 uint32_t reloc_val, reloc_offset;
3361 uint32_t __iomem *reloc_entry;
673a394b 3362
673a394b 3363 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3364 reloc->target_handle);
673a394b
EA		 3365 if (target_obj == NULL) {
3366 i915_gem_object_unpin(obj);
3367 return -EBADF;
3368 }
23010e43 3369 target_obj_priv = to_intel_bo(target_obj);
673a394b 3370
8542a0bb
CW		 3371#if WATCH_RELOC
3372 DRM_INFO("%s: obj %p offset %08x target %d "
3373 "read %08x write %08x gtt %08x "
3374 "presumed %08x delta %08x\n",
3375 __func__,
3376 obj,
3377 (int) reloc->offset,
3378 (int) reloc->target_handle,
3379 (int) reloc->read_domains,
3380 (int) reloc->write_domain,
3381 (int) target_obj_priv->gtt_offset,
3382 (int) reloc->presumed_offset,
3383 reloc->delta);
3384#endif
3385
673a394b
EA		 3386 /* The target buffer should have appeared before us in the
3387 * exec_object list, so it should have a GTT space bound by now.
3388 */
3389 if (target_obj_priv->gtt_space == NULL) {
3390 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3391 reloc->target_handle);
673a394b
EA		 3392 drm_gem_object_unreference(target_obj);
3393 i915_gem_object_unpin(obj);
3394 return -EINVAL;
3395 }
3396
8542a0bb 3397 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3398 if (reloc->write_domain & (reloc->write_domain - 1)) {
3399 DRM_ERROR("reloc with multiple write domains: "
3400 "obj %p target %d offset %d "
3401 "read %08x write %08x",
3402 obj, reloc->target_handle,
3403 (int) reloc->offset,
3404 reloc->read_domains,
3405 reloc->write_domain);
3406 return -EINVAL;
3407 }
40a5f0de
EA		 3408 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3409 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3410 DRM_ERROR("reloc with read/write CPU domains: "
3411 "obj %p target %d offset %d "
3412 "read %08x write %08x",
40a5f0de
EA		 3413 obj, reloc->target_handle,
3414 (int) reloc->offset,
3415 reloc->read_domains,
3416 reloc->write_domain);
491152b8
CW		 3417 drm_gem_object_unreference(target_obj);
3418 i915_gem_object_unpin(obj);
e47c68e9
EA		 3419 return -EINVAL;
3420 }
40a5f0de
EA		 3421 if (reloc->write_domain && target_obj->pending_write_domain &&
3422 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3423 DRM_ERROR("Write domain conflict: "
3424 "obj %p target %d offset %d "
3425 "new %08x old %08x\n",
40a5f0de
EA		 3426 obj, reloc->target_handle,
3427 (int) reloc->offset,
3428 reloc->write_domain,
673a394b
EA		 3429 target_obj->pending_write_domain);
3430 drm_gem_object_unreference(target_obj);
3431 i915_gem_object_unpin(obj);
3432 return -EINVAL;
3433 }
3434
40a5f0de
EA		 3435 target_obj->pending_read_domains |= reloc->read_domains;
3436 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3437
3438 /* If the relocation already has the right value in it, no
3439 * more work needs to be done.
3440 */
40a5f0de 3441 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3442 drm_gem_object_unreference(target_obj);
3443 continue;
3444 }
3445
8542a0bb
CW		 3446 /* Check that the relocation address is valid... */
3447 if (reloc->offset > obj->size - 4) {
3448 DRM_ERROR("Relocation beyond object bounds: "
3449 "obj %p target %d offset %d size %d.\n",
3450 obj, reloc->target_handle,
3451 (int) reloc->offset, (int) obj->size);
3452 drm_gem_object_unreference(target_obj);
3453 i915_gem_object_unpin(obj);
3454 return -EINVAL;
3455 }
3456 if (reloc->offset & 3) {
3457 DRM_ERROR("Relocation not 4-byte aligned: "
3458 "obj %p target %d offset %d.\n",
3459 obj, reloc->target_handle,
3460 (int) reloc->offset);
3461 drm_gem_object_unreference(target_obj);
3462 i915_gem_object_unpin(obj);
3463 return -EINVAL;
3464 }
3465
3466 /* and points to somewhere within the target object. */
3467 if (reloc->delta >= target_obj->size) {
3468 DRM_ERROR("Relocation beyond target object bounds: "
3469 "obj %p target %d delta %d size %d.\n",
3470 obj, reloc->target_handle,
3471 (int) reloc->delta, (int) target_obj->size);
3472 drm_gem_object_unreference(target_obj);
3473 i915_gem_object_unpin(obj);
3474 return -EINVAL;
3475 }
3476
2ef7eeaa
EA		 3477 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3478 if (ret != 0) {
3479 drm_gem_object_unreference(target_obj);
3480 i915_gem_object_unpin(obj);
3481 return -EINVAL;
673a394b
EA		 3482 }
3483
3484 /* Map the page containing the relocation we're going to
3485 * perform.
3486 */
40a5f0de 3487 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3488 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3489 (reloc_offset &
3490 ~(PAGE_SIZE - 1)));
3043c60c 3491 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3492 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3493 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3494
3495#if WATCH_BUF
3496 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3497 obj, (unsigned int) reloc->offset,
673a394b
EA		 3498 readl(reloc_entry), reloc_val);
3499#endif
3500 writel(reloc_val, reloc_entry);
0839ccb8 3501 io_mapping_unmap_atomic(reloc_page);
673a394b 3502
40a5f0de
EA		 3503 /* The updated presumed offset for this entry will be
3504 * copied back out to the user.
673a394b 3505 */
40a5f0de 3506 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3507
3508 drm_gem_object_unreference(target_obj);
3509 }
3510
673a394b
EA		 3511#if WATCH_BUF
3512 if (0)
3513 i915_gem_dump_object(obj, 128, __func__, ~0);
3514#endif
3515 return 0;
3516}
3517
673a394b
EA		 3518/* Throttle our rendering by waiting until the ring has completed our requests
3519 * emitted over 20 msec ago.
3520 *
b962442e
EA		 3521 * Note that if we were to use the current jiffies each time around the loop,
3522 * we wouldn't escape the function with any frames outstanding if the time to
3523 * render a frame was over 20ms.
3524 *
673a394b
EA		 3525 * This should get us reasonable parallelism between CPU and GPU but also
3526 * relatively low latency when blocking on a particular request to finish.
3527 */
3528static int
3529i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3530{
3531 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3532 int ret = 0;
b962442e 3533 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3534
3535 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3536 while (!list_empty(&i915_file_priv->mm.request_list)) {
3537 struct drm_i915_gem_request *request;
3538
3539 request = list_first_entry(&i915_file_priv->mm.request_list,
3540 struct drm_i915_gem_request,
3541 client_list);
3542
3543 if (time_after_eq(request->emitted_jiffies, recent_enough))
3544 break;
3545
852835f3 3546 ret = i915_wait_request(dev, request->seqno, request->ring);
b962442e
EA		 3547 if (ret != 0)
3548 break;
3549 }
673a394b 3550 mutex_unlock(&dev->struct_mutex);
b962442e 3551
673a394b
EA		 3552 return ret;
3553}
3554
40a5f0de 3555static int
76446cac 3556i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3557 uint32_t buffer_count,
3558 struct drm_i915_gem_relocation_entry **relocs)
3559{
3560 uint32_t reloc_count = 0, reloc_index = 0, i;
3561 int ret;
3562
3563 *relocs = NULL;
3564 for (i = 0; i < buffer_count; i++) {
3565 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3566 return -EINVAL;
3567 reloc_count += exec_list[i].relocation_count;
3568 }
3569
8e7d2b2c 3570 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3571 if (*relocs == NULL) {
3572 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3573 return -ENOMEM;
76446cac 3574 }
40a5f0de
EA		 3575
3576 for (i = 0; i < buffer_count; i++) {
3577 struct drm_i915_gem_relocation_entry __user *user_relocs;
3578
3579 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3580
3581 ret = copy_from_user(&(*relocs)[reloc_index],
3582 user_relocs,
3583 exec_list[i].relocation_count *
3584 sizeof(**relocs));
3585 if (ret != 0) {
8e7d2b2c 3586 drm_free_large(*relocs);
40a5f0de 3587 *relocs = NULL;
2bc43b5c 3588 return -EFAULT;
40a5f0de
EA		 3589 }
3590
3591 reloc_index += exec_list[i].relocation_count;
3592 }
3593
2bc43b5c 3594 return 0;
40a5f0de
EA		 3595}
3596
3597static int
76446cac 3598i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3599 uint32_t buffer_count,
3600 struct drm_i915_gem_relocation_entry *relocs)
3601{
3602 uint32_t reloc_count = 0, i;
2bc43b5c 3603 int ret = 0;
40a5f0de 3604
93533c29
CW		 3605 if (relocs == NULL)
3606 return 0;
3607
40a5f0de
EA		 3608 for (i = 0; i < buffer_count; i++) {
3609 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3610 int unwritten;
40a5f0de
EA		 3611
3612 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3613
2bc43b5c
FM		 3614 unwritten = copy_to_user(user_relocs,
3615 &relocs[reloc_count],
3616 exec_list[i].relocation_count *
3617 sizeof(*relocs));
3618
3619 if (unwritten) {
3620 ret = -EFAULT;
3621 goto err;
40a5f0de
EA		 3622 }
3623
3624 reloc_count += exec_list[i].relocation_count;
3625 }
3626
2bc43b5c 3627err:
8e7d2b2c 3628 drm_free_large(relocs);
40a5f0de
EA		 3629
3630 return ret;
3631}
3632
83d60795 3633static int
76446cac 3634i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3635 uint64_t exec_offset)
3636{
3637 uint32_t exec_start, exec_len;
3638
3639 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3640 exec_len = (uint32_t) exec->batch_len;
3641
3642 if ((exec_start | exec_len) & 0x7)
3643 return -EINVAL;
3644
3645 if (!exec_start)
3646 return -EINVAL;
3647
3648 return 0;
3649}
3650
6b95a207
KH		 3651static int
3652i915_gem_wait_for_pending_flip(struct drm_device *dev,
3653 struct drm_gem_object **object_list,
3654 int count)
3655{
3656 drm_i915_private_t *dev_priv = dev->dev_private;
3657 struct drm_i915_gem_object *obj_priv;
3658 DEFINE_WAIT(wait);
3659 int i, ret = 0;
3660
3661 for (;;) {
3662 prepare_to_wait(&dev_priv->pending_flip_queue,
3663 &wait, TASK_INTERRUPTIBLE);
3664 for (i = 0; i < count; i++) {
23010e43 3665 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3666 if (atomic_read(&obj_priv->pending_flip) > 0)
3667 break;
3668 }
3669 if (i == count)
3670 break;
3671
3672 if (!signal_pending(current)) {
3673 mutex_unlock(&dev->struct_mutex);
3674 schedule();
3675 mutex_lock(&dev->struct_mutex);
3676 continue;
3677 }
3678 ret = -ERESTARTSYS;
3679 break;
3680 }
3681 finish_wait(&dev_priv->pending_flip_queue, &wait);
3682
3683 return ret;
3684}
3685
43b27f40 3686
673a394b 3687int
76446cac
JB		 3688i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3689 struct drm_file *file_priv,
3690 struct drm_i915_gem_execbuffer2 *args,
3691 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3692{
3693 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3694 struct drm_gem_object **object_list = NULL;
3695 struct drm_gem_object *batch_obj;
b70d11da 3696 struct drm_i915_gem_object *obj_priv;
201361a5 3697 struct drm_clip_rect *cliprects = NULL;
93533c29 3698 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3699 int ret = 0, ret2, i, pinned = 0;
673a394b 3700 uint64_t exec_offset;
40a5f0de 3701 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3702 int pin_tries, flips;
673a394b 3703
852835f3
ZN		 3704 struct intel_ring_buffer *ring = NULL;
3705
673a394b
EA		 3706#if WATCH_EXEC
3707 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3708 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3709#endif
d1b851fc
ZN		 3710 if (args->flags & I915_EXEC_BSD) {
3711 if (!HAS_BSD(dev)) {
3712 DRM_ERROR("execbuf with wrong flag\n");
3713 return -EINVAL;
3714 }
3715 ring = &dev_priv->bsd_ring;
3716 } else {
3717 ring = &dev_priv->render_ring;
3718 }
3719
673a394b 3720
4f481ed2
EA		 3721 if (args->buffer_count < 1) {
3722 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3723 return -EINVAL;
3724 }
c8e0f93a 3725 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3726 if (object_list == NULL) {
3727 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3728 args->buffer_count);
3729 ret = -ENOMEM;
3730 goto pre_mutex_err;
3731 }
673a394b 3732
201361a5 3733 if (args->num_cliprects != 0) {
9a298b2a
EA		 3734 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3735 GFP_KERNEL);
a40e8d31
OA		 3736 if (cliprects == NULL) {
3737 ret = -ENOMEM;
201361a5 3738 goto pre_mutex_err;
a40e8d31 3739 }
201361a5
EA		 3740
3741 ret = copy_from_user(cliprects,
3742 (struct drm_clip_rect __user *)
3743 (uintptr_t) args->cliprects_ptr,
3744 sizeof(*cliprects) * args->num_cliprects);
3745 if (ret != 0) {
3746 DRM_ERROR("copy %d cliprects failed: %d\n",
3747 args->num_cliprects, ret);
3748 goto pre_mutex_err;
3749 }
3750 }
3751
40a5f0de
EA		 3752 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3753 &relocs);
3754 if (ret != 0)
3755 goto pre_mutex_err;
3756
673a394b
EA		 3757 mutex_lock(&dev->struct_mutex);
3758
3759 i915_verify_inactive(dev, __FILE__, __LINE__);
3760
ba1234d1 3761 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3762 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3763 ret = -EIO;
3764 goto pre_mutex_err;
673a394b
EA		 3765 }
3766
3767 if (dev_priv->mm.suspended) {
673a394b 3768 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3769 ret = -EBUSY;
3770 goto pre_mutex_err;
673a394b
EA		 3771 }
3772
ac94a962 3773 /* Look up object handles */
6b95a207 3774 flips = 0;
673a394b
EA		 3775 for (i = 0; i < args->buffer_count; i++) {
3776 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3777 exec_list[i].handle);
3778 if (object_list[i] == NULL) {
3779 DRM_ERROR("Invalid object handle %d at index %d\n",
3780 exec_list[i].handle, i);
0ce907f8
CW		 3781 /* prevent error path from reading uninitialized data */
3782 args->buffer_count = i + 1;
673a394b
EA		 3783 ret = -EBADF;
3784 goto err;
3785 }
b70d11da 3786
23010e43 3787 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3788 if (obj_priv->in_execbuffer) {
3789 DRM_ERROR("Object %p appears more than once in object list\n",
3790 object_list[i]);
0ce907f8
CW		 3791 /* prevent error path from reading uninitialized data */
3792 args->buffer_count = i + 1;
b70d11da
KH		 3793 ret = -EBADF;
3794 goto err;
3795 }
3796 obj_priv->in_execbuffer = true;
6b95a207
KH		 3797 flips += atomic_read(&obj_priv->pending_flip);
3798 }
3799
3800 if (flips > 0) {
3801 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3802 args->buffer_count);
3803 if (ret)
3804 goto err;
ac94a962 3805 }
673a394b 3806
ac94a962
KP		 3807 /* Pin and relocate */
3808 for (pin_tries = 0; ; pin_tries++) {
3809 ret = 0;
40a5f0de
EA		 3810 reloc_index = 0;
3811
ac94a962
KP		 3812 for (i = 0; i < args->buffer_count; i++) {
3813 object_list[i]->pending_read_domains = 0;
3814 object_list[i]->pending_write_domain = 0;
3815 ret = i915_gem_object_pin_and_relocate(object_list[i],
3816 file_priv,
40a5f0de
EA		 3817 &exec_list[i],
3818 &relocs[reloc_index]);
ac94a962
KP		 3819 if (ret)
3820 break;
3821 pinned = i + 1;
40a5f0de 3822 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3823 }
3824 /* success */
3825 if (ret == 0)
3826 break;
3827
3828 /* error other than GTT full, or we've already tried again */
2939e1f5 3829 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3830 if (ret != -ERESTARTSYS) {
3831 unsigned long long total_size = 0;
3d1cc470
CW		 3832 int num_fences = 0;
3833 for (i = 0; i < args->buffer_count; i++) {
43b27f40 3834 obj_priv = to_intel_bo(object_list[i]);
3d1cc470 3835
07f73f69 3836 total_size += object_list[i]->size;
3d1cc470
CW		 3837 num_fences +=
3838 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3839 obj_priv->tiling_mode != I915_TILING_NONE;
3840 }
3841 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
07f73f69 3842 pinned+1, args->buffer_count,
3d1cc470
CW		 3843 total_size, num_fences,
3844 ret);
07f73f69
CW		 3845 DRM_ERROR("%d objects [%d pinned], "
3846 "%d object bytes [%d pinned], "
3847 "%d/%d gtt bytes\n",
3848 atomic_read(&dev->object_count),
3849 atomic_read(&dev->pin_count),
3850 atomic_read(&dev->object_memory),
3851 atomic_read(&dev->pin_memory),
3852 atomic_read(&dev->gtt_memory),
3853 dev->gtt_total);
3854 }
673a394b
EA		 3855 goto err;
3856 }
ac94a962
KP		 3857
3858 /* unpin all of our buffers */
3859 for (i = 0; i < pinned; i++)
3860 i915_gem_object_unpin(object_list[i]);
b1177636 3861 pinned = 0;
ac94a962
KP		 3862
3863 /* evict everyone we can from the aperture */
3864 ret = i915_gem_evict_everything(dev);
07f73f69 3865 if (ret && ret != -ENOSPC)
ac94a962 3866 goto err;
673a394b
EA		 3867 }
3868
3869 /* Set the pending read domains for the batch buffer to COMMAND */
3870 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3871 if (batch_obj->pending_write_domain) {
3872 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3873 ret = -EINVAL;
3874 goto err;
3875 }
3876 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3877
83d60795
CW		 3878 /* Sanity check the batch buffer, prior to moving objects */
3879 exec_offset = exec_list[args->buffer_count - 1].offset;
3880 ret = i915_gem_check_execbuffer (args, exec_offset);
3881 if (ret != 0) {
3882 DRM_ERROR("execbuf with invalid offset/length\n");
3883 goto err;
3884 }
3885
673a394b
EA		 3886 i915_verify_inactive(dev, __FILE__, __LINE__);
3887
646f0f6e
KP		 3888 /* Zero the global flush/invalidate flags. These
3889 * will be modified as new domains are computed
3890 * for each object
3891 */
3892 dev->invalidate_domains = 0;
3893 dev->flush_domains = 0;
3894
673a394b
EA		 3895 for (i = 0; i < args->buffer_count; i++) {
3896 struct drm_gem_object *obj = object_list[i];
673a394b 3897
646f0f6e 3898 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3899 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3900 }
3901
3902 i915_verify_inactive(dev, __FILE__, __LINE__);
3903
646f0f6e
KP		 3904 if (dev->invalidate_domains | dev->flush_domains) {
3905#if WATCH_EXEC
3906 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3907 __func__,
3908 dev->invalidate_domains,
3909 dev->flush_domains);
3910#endif
3911 i915_gem_flush(dev,
3912 dev->invalidate_domains,
3913 dev->flush_domains);
852835f3 3914 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
b962442e 3915 (void)i915_add_request(dev, file_priv,
852835f3
ZN		 3916 dev->flush_domains,
3917 &dev_priv->render_ring);
3918
d1b851fc
ZN		 3919 if (HAS_BSD(dev))
3920 (void)i915_add_request(dev, file_priv,
3921 dev->flush_domains,
3922 &dev_priv->bsd_ring);
852835f3 3923 }
646f0f6e 3924 }
673a394b 3925
efbeed96
EA		 3926 for (i = 0; i < args->buffer_count; i++) {
3927 struct drm_gem_object *obj = object_list[i];
23010e43 3928 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3929 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3930
3931 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3932 if (obj->write_domain)
3933 list_move_tail(&obj_priv->gpu_write_list,
3934 &dev_priv->mm.gpu_write_list);
3935 else
3936 list_del_init(&obj_priv->gpu_write_list);
3937
1c5d22f7
CW		 3938 trace_i915_gem_object_change_domain(obj,
3939 obj->read_domains,
3940 old_write_domain);
efbeed96
EA		 3941 }
3942
673a394b
EA		 3943 i915_verify_inactive(dev, __FILE__, __LINE__);
3944
3945#if WATCH_COHERENCY
3946 for (i = 0; i < args->buffer_count; i++) {
3947 i915_gem_object_check_coherency(object_list[i],
3948 exec_list[i].handle);
3949 }
3950#endif
3951
673a394b 3952#if WATCH_EXEC
6911a9b8 3953 i915_gem_dump_object(batch_obj,
673a394b
EA		 3954 args->batch_len,
3955 __func__,
3956 ~0);
3957#endif
3958
673a394b 3959 /* Exec the batchbuffer */
852835f3
ZN		 3960 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3961 cliprects, exec_offset);
673a394b
EA		 3962 if (ret) {
3963 DRM_ERROR("dispatch failed %d\n", ret);
3964 goto err;
3965 }
3966
3967 /*
3968 * Ensure that the commands in the batch buffer are
3969 * finished before the interrupt fires
3970 */
852835f3 3971 flush_domains = i915_retire_commands(dev, ring);
673a394b
EA		 3972
3973 i915_verify_inactive(dev, __FILE__, __LINE__);
3974
3975 /*
3976 * Get a seqno representing the execution of the current buffer,
3977 * which we can wait on. We would like to mitigate these interrupts,
3978 * likely by only creating seqnos occasionally (so that we have
3979 * *some* interrupts representing completion of buffers that we can
3980 * wait on when trying to clear up gtt space).
3981 */
852835f3 3982 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
673a394b 3983 BUG_ON(seqno == 0);
673a394b
EA		 3984 for (i = 0; i < args->buffer_count; i++) {
3985 struct drm_gem_object *obj = object_list[i];
852835f3 3986 obj_priv = to_intel_bo(obj);
673a394b 3987
852835f3 3988 i915_gem_object_move_to_active(obj, seqno, ring);
673a394b
EA		 3989#if WATCH_LRU
3990 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3991#endif
3992 }
3993#if WATCH_LRU
3994 i915_dump_lru(dev, __func__);
3995#endif
3996
3997 i915_verify_inactive(dev, __FILE__, __LINE__);
3998
673a394b 3999err:
aad87dff
JL		 4000 for (i = 0; i < pinned; i++)
4001 i915_gem_object_unpin(object_list[i]);
4002
b70d11da
KH		 4003 for (i = 0; i < args->buffer_count; i++) {
4004 if (object_list[i]) {
23010e43 4005 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 4006 obj_priv->in_execbuffer = false;
4007 }
aad87dff 4008 drm_gem_object_unreference(object_list[i]);
b70d11da 4009 }
673a394b 4010
673a394b
EA		 4011 mutex_unlock(&dev->struct_mutex);
4012
93533c29 4013pre_mutex_err:
40a5f0de
EA		 4014 /* Copy the updated relocations out regardless of current error
4015 * state. Failure to update the relocs would mean that the next
4016 * time userland calls execbuf, it would do so with presumed offset
4017 * state that didn't match the actual object state.
4018 */
4019 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4020 relocs);
4021 if (ret2 != 0) {
4022 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4023
4024 if (ret == 0)
4025 ret = ret2;
4026 }
4027
8e7d2b2c 4028 drm_free_large(object_list);
9a298b2a 4029 kfree(cliprects);
673a394b
EA		 4030
4031 return ret;
4032}
4033
76446cac
JB		 4034/*
4035 * Legacy execbuffer just creates an exec2 list from the original exec object
4036 * list array and passes it to the real function.
4037 */
4038int
4039i915_gem_execbuffer(struct drm_device *dev, void *data,
4040 struct drm_file *file_priv)
4041{
4042 struct drm_i915_gem_execbuffer *args = data;
4043 struct drm_i915_gem_execbuffer2 exec2;
4044 struct drm_i915_gem_exec_object *exec_list = NULL;
4045 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4046 int ret, i;
4047
4048#if WATCH_EXEC
4049 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4050 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4051#endif
4052
4053 if (args->buffer_count < 1) {
4054 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4055 return -EINVAL;
4056 }
4057
4058 /* Copy in the exec list from userland */
4059 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4060 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4061 if (exec_list == NULL || exec2_list == NULL) {
4062 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4063 args->buffer_count);
4064 drm_free_large(exec_list);
4065 drm_free_large(exec2_list);
4066 return -ENOMEM;
4067 }
4068 ret = copy_from_user(exec_list,
4069 (struct drm_i915_relocation_entry __user *)
4070 (uintptr_t) args->buffers_ptr,
4071 sizeof(*exec_list) * args->buffer_count);
4072 if (ret != 0) {
4073 DRM_ERROR("copy %d exec entries failed %d\n",
4074 args->buffer_count, ret);
4075 drm_free_large(exec_list);
4076 drm_free_large(exec2_list);
4077 return -EFAULT;
4078 }
4079
4080 for (i = 0; i < args->buffer_count; i++) {
4081 exec2_list[i].handle = exec_list[i].handle;
4082 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4083 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4084 exec2_list[i].alignment = exec_list[i].alignment;
4085 exec2_list[i].offset = exec_list[i].offset;
4086 if (!IS_I965G(dev))
4087 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4088 else
4089 exec2_list[i].flags = 0;
4090 }
4091
4092 exec2.buffers_ptr = args->buffers_ptr;
4093 exec2.buffer_count = args->buffer_count;
4094 exec2.batch_start_offset = args->batch_start_offset;
4095 exec2.batch_len = args->batch_len;
4096 exec2.DR1 = args->DR1;
4097 exec2.DR4 = args->DR4;
4098 exec2.num_cliprects = args->num_cliprects;
4099 exec2.cliprects_ptr = args->cliprects_ptr;
852835f3 4100 exec2.flags = I915_EXEC_RENDER;
76446cac
JB		 4101
4102 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4103 if (!ret) {
4104 /* Copy the new buffer offsets back to the user's exec list. */
4105 for (i = 0; i < args->buffer_count; i++)
4106 exec_list[i].offset = exec2_list[i].offset;
4107 /* ... and back out to userspace */
4108 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4109 (uintptr_t) args->buffers_ptr,
4110 exec_list,
4111 sizeof(*exec_list) * args->buffer_count);
4112 if (ret) {
4113 ret = -EFAULT;
4114 DRM_ERROR("failed to copy %d exec entries "
4115 "back to user (%d)\n",
4116 args->buffer_count, ret);
4117 }
76446cac
JB		 4118 }
4119
4120 drm_free_large(exec_list);
4121 drm_free_large(exec2_list);
4122 return ret;
4123}
4124
4125int
4126i915_gem_execbuffer2(struct drm_device *dev, void *data,
4127 struct drm_file *file_priv)
4128{
4129 struct drm_i915_gem_execbuffer2 *args = data;
4130 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4131 int ret;
4132
4133#if WATCH_EXEC
4134 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4135 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4136#endif
4137
4138 if (args->buffer_count < 1) {
4139 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4140 return -EINVAL;
4141 }
4142
4143 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4144 if (exec2_list == NULL) {
4145 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4146 args->buffer_count);
4147 return -ENOMEM;
4148 }
4149 ret = copy_from_user(exec2_list,
4150 (struct drm_i915_relocation_entry __user *)
4151 (uintptr_t) args->buffers_ptr,
4152 sizeof(*exec2_list) * args->buffer_count);
4153 if (ret != 0) {
4154 DRM_ERROR("copy %d exec entries failed %d\n",
4155 args->buffer_count, ret);
4156 drm_free_large(exec2_list);
4157 return -EFAULT;
4158 }
4159
4160 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4161 if (!ret) {
4162 /* Copy the new buffer offsets back to the user's exec list. */
4163 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4164 (uintptr_t) args->buffers_ptr,
4165 exec2_list,
4166 sizeof(*exec2_list) * args->buffer_count);
4167 if (ret) {
4168 ret = -EFAULT;
4169 DRM_ERROR("failed to copy %d exec entries "
4170 "back to user (%d)\n",
4171 args->buffer_count, ret);
4172 }
4173 }
4174
4175 drm_free_large(exec2_list);
4176 return ret;
4177}
4178
673a394b
EA		 4179int
4180i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4181{
4182 struct drm_device *dev = obj->dev;
23010e43 4183 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4184 int ret;
4185
778c3544
DV		 4186 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4187
673a394b 4188 i915_verify_inactive(dev, __FILE__, __LINE__);
ac0c6b5a
CW		 4189
4190 if (obj_priv->gtt_space != NULL) {
4191 if (alignment == 0)
4192 alignment = i915_gem_get_gtt_alignment(obj);
4193 if (obj_priv->gtt_offset & (alignment - 1)) {
4194 ret = i915_gem_object_unbind(obj);
4195 if (ret)
4196 return ret;
4197 }
4198 }
4199
673a394b
EA		 4200 if (obj_priv->gtt_space == NULL) {
4201 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4202 if (ret)
673a394b 4203 return ret;
22c344e9 4204 }
76446cac 4205
673a394b
EA		 4206 obj_priv->pin_count++;
4207
4208 /* If the object is not active and not pending a flush,
4209 * remove it from the inactive list
4210 */
4211 if (obj_priv->pin_count == 1) {
4212 atomic_inc(&dev->pin_count);
4213 atomic_add(obj->size, &dev->pin_memory);
4214 if (!obj_priv->active &&
21d509e3 4215 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 4216 !list_empty(&obj_priv->list))
4217 list_del_init(&obj_priv->list);
4218 }
4219 i915_verify_inactive(dev, __FILE__, __LINE__);
4220
4221 return 0;
4222}
4223
4224void
4225i915_gem_object_unpin(struct drm_gem_object *obj)
4226{
4227 struct drm_device *dev = obj->dev;
4228 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4229 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4230
4231 i915_verify_inactive(dev, __FILE__, __LINE__);
4232 obj_priv->pin_count--;
4233 BUG_ON(obj_priv->pin_count < 0);
4234 BUG_ON(obj_priv->gtt_space == NULL);
4235
4236 /* If the object is no longer pinned, and is
4237 * neither active nor being flushed, then stick it on
4238 * the inactive list
4239 */
4240 if (obj_priv->pin_count == 0) {
4241 if (!obj_priv->active &&
21d509e3 4242 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4243 list_move_tail(&obj_priv->list,
4244 &dev_priv->mm.inactive_list);
4245 atomic_dec(&dev->pin_count);
4246 atomic_sub(obj->size, &dev->pin_memory);
4247 }
4248 i915_verify_inactive(dev, __FILE__, __LINE__);
4249}
4250
4251int
4252i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4253 struct drm_file *file_priv)
4254{
4255 struct drm_i915_gem_pin *args = data;
4256 struct drm_gem_object *obj;
4257 struct drm_i915_gem_object *obj_priv;
4258 int ret;
4259
4260 mutex_lock(&dev->struct_mutex);
4261
4262 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4263 if (obj == NULL) {
4264 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4265 args->handle);
4266 mutex_unlock(&dev->struct_mutex);
4267 return -EBADF;
4268 }
23010e43 4269 obj_priv = to_intel_bo(obj);
673a394b 4270
bb6baf76
CW		 4271 if (obj_priv->madv != I915_MADV_WILLNEED) {
4272 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4273 drm_gem_object_unreference(obj);
4274 mutex_unlock(&dev->struct_mutex);
4275 return -EINVAL;
4276 }
4277
79e53945
JB		 4278 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4279 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4280 args->handle);
96dec61d 4281 drm_gem_object_unreference(obj);
673a394b 4282 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4283 return -EINVAL;
4284 }
4285
4286 obj_priv->user_pin_count++;
4287 obj_priv->pin_filp = file_priv;
4288 if (obj_priv->user_pin_count == 1) {
4289 ret = i915_gem_object_pin(obj, args->alignment);
4290 if (ret != 0) {
4291 drm_gem_object_unreference(obj);
4292 mutex_unlock(&dev->struct_mutex);
4293 return ret;
4294 }
673a394b
EA		 4295 }
4296
4297 /* XXX - flush the CPU caches for pinned objects
4298 * as the X server doesn't manage domains yet
4299 */
e47c68e9 4300 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4301 args->offset = obj_priv->gtt_offset;
4302 drm_gem_object_unreference(obj);
4303 mutex_unlock(&dev->struct_mutex);
4304
4305 return 0;
4306}
4307
4308int
4309i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4310 struct drm_file *file_priv)
4311{
4312 struct drm_i915_gem_pin *args = data;
4313 struct drm_gem_object *obj;
79e53945 4314 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4315
4316 mutex_lock(&dev->struct_mutex);
4317
4318 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4319 if (obj == NULL) {
4320 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4321 args->handle);
4322 mutex_unlock(&dev->struct_mutex);
4323 return -EBADF;
4324 }
4325
23010e43 4326 obj_priv = to_intel_bo(obj);
79e53945
JB		 4327 if (obj_priv->pin_filp != file_priv) {
4328 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4329 args->handle);
4330 drm_gem_object_unreference(obj);
4331 mutex_unlock(&dev->struct_mutex);
4332 return -EINVAL;
4333 }
4334 obj_priv->user_pin_count--;
4335 if (obj_priv->user_pin_count == 0) {
4336 obj_priv->pin_filp = NULL;
4337 i915_gem_object_unpin(obj);
4338 }
673a394b
EA		 4339
4340 drm_gem_object_unreference(obj);
4341 mutex_unlock(&dev->struct_mutex);
4342 return 0;
4343}
4344
4345int
4346i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4347 struct drm_file *file_priv)
4348{
4349 struct drm_i915_gem_busy *args = data;
4350 struct drm_gem_object *obj;
4351 struct drm_i915_gem_object *obj_priv;
4352
673a394b
EA		 4353 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4354 if (obj == NULL) {
4355 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4356 args->handle);
673a394b
EA		 4357 return -EBADF;
4358 }
4359
b1ce786c 4360 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4361 /* Update the active list for the hardware's current position.
4362 * Otherwise this only updates on a delayed timer or when irqs are
4363 * actually unmasked, and our working set ends up being larger than
4364 * required.
4365 */
b09a1fec 4366 i915_gem_retire_requests(dev);
d1b851fc 4367
23010e43 4368 obj_priv = to_intel_bo(obj);
c4de0a5d
EA		 4369 /* Don't count being on the flushing list against the object being
4370 * done. Otherwise, a buffer left on the flushing list but not getting
4371 * flushed (because nobody's flushing that domain) won't ever return
4372 * unbusy and get reused by libdrm's bo cache. The other expected
4373 * consumer of this interface, OpenGL's occlusion queries, also specs
4374 * that the objects get unbusy "eventually" without any interference.
4375 */
4376 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4377
4378 drm_gem_object_unreference(obj);
4379 mutex_unlock(&dev->struct_mutex);
4380 return 0;
4381}
4382
4383int
4384i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4385 struct drm_file *file_priv)
4386{
4387 return i915_gem_ring_throttle(dev, file_priv);
4388}
4389
3ef94daa
CW		 4390int
4391i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4392 struct drm_file *file_priv)
4393{
4394 struct drm_i915_gem_madvise *args = data;
4395 struct drm_gem_object *obj;
4396 struct drm_i915_gem_object *obj_priv;
4397
4398 switch (args->madv) {
4399 case I915_MADV_DONTNEED:
4400 case I915_MADV_WILLNEED:
4401 break;
4402 default:
4403 return -EINVAL;
4404 }
4405
4406 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4407 if (obj == NULL) {
4408 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4409 args->handle);
4410 return -EBADF;
4411 }
4412
4413 mutex_lock(&dev->struct_mutex);
23010e43 4414 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4415
4416 if (obj_priv->pin_count) {
4417 drm_gem_object_unreference(obj);
4418 mutex_unlock(&dev->struct_mutex);
4419
4420 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4421 return -EINVAL;
4422 }
4423
bb6baf76
CW		 4424 if (obj_priv->madv != __I915_MADV_PURGED)
4425 obj_priv->madv = args->madv;
3ef94daa 4426
2d7ef395
CW		 4427 /* if the object is no longer bound, discard its backing storage */
4428 if (i915_gem_object_is_purgeable(obj_priv) &&
4429 obj_priv->gtt_space == NULL)
4430 i915_gem_object_truncate(obj);
4431
bb6baf76
CW		 4432 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4433
3ef94daa
CW		 4434 drm_gem_object_unreference(obj);
4435 mutex_unlock(&dev->struct_mutex);
4436
4437 return 0;
4438}
4439
ac52bc56
DV		 4440struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4441 size_t size)
4442{
c397b908 4443 struct drm_i915_gem_object *obj;
ac52bc56 4444
c397b908
DV		 4445 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4446 if (obj == NULL)
4447 return NULL;
673a394b 4448
c397b908
DV		 4449 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4450 kfree(obj);
4451 return NULL;
4452 }
673a394b 4453
c397b908
DV		 4454 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4455 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4456
c397b908 4457 obj->agp_type = AGP_USER_MEMORY;
62b8b215 4458 obj->base.driver_private = NULL;
c397b908
DV		 4459 obj->fence_reg = I915_FENCE_REG_NONE;
4460 INIT_LIST_HEAD(&obj->list);
4461 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 4462 obj->madv = I915_MADV_WILLNEED;
de151cf6 4463
c397b908
DV		 4464 trace_i915_gem_object_create(&obj->base);
4465
4466 return &obj->base;
4467}
4468
4469int i915_gem_init_object(struct drm_gem_object *obj)
4470{
4471 BUG();
de151cf6 4472
673a394b
EA		 4473 return 0;
4474}
4475
be72615b 4476static void i915_gem_free_object_tail(struct drm_gem_object *obj)
673a394b 4477{
de151cf6 4478 struct drm_device *dev = obj->dev;
be72615b 4479 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4480 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
be72615b 4481 int ret;
673a394b 4482
be72615b
CW		 4483 ret = i915_gem_object_unbind(obj);
4484 if (ret == -ERESTARTSYS) {
4485 list_move(&obj_priv->list,
4486 &dev_priv->mm.deferred_free_list);
4487 return;
4488 }
673a394b 4489
7e616158
CW		 4490 if (obj_priv->mmap_offset)
4491 i915_gem_free_mmap_offset(obj);
de151cf6 4492
c397b908
DV		 4493 drm_gem_object_release(obj);
4494
9a298b2a 4495 kfree(obj_priv->page_cpu_valid);
280b713b 4496 kfree(obj_priv->bit_17);
c397b908 4497 kfree(obj_priv);
673a394b
EA		 4498}
4499
be72615b
CW		 4500void i915_gem_free_object(struct drm_gem_object *obj)
4501{
4502 struct drm_device *dev = obj->dev;
4503 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4504
4505 trace_i915_gem_object_destroy(obj);
4506
4507 while (obj_priv->pin_count > 0)
4508 i915_gem_object_unpin(obj);
4509
4510 if (obj_priv->phys_obj)
4511 i915_gem_detach_phys_object(dev, obj);
4512
4513 i915_gem_free_object_tail(obj);
4514}
4515
ab5ee576 4516/** Unbinds all inactive objects. */
673a394b 4517static int
ab5ee576 4518i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4519{
ab5ee576 4520 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4521
ab5ee576
CW		 4522 while (!list_empty(&dev_priv->mm.inactive_list)) {
4523 struct drm_gem_object *obj;
4524 int ret;
673a394b 4525
a8089e84
DV		 4526 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4527 struct drm_i915_gem_object,
4528 list)->base;
673a394b
EA		 4529
4530 ret = i915_gem_object_unbind(obj);
4531 if (ret != 0) {
ab5ee576 4532 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4533 return ret;
4534 }
4535 }
4536
673a394b
EA		 4537 return 0;
4538}
4539
29105ccc
CW		 4540int
4541i915_gem_idle(struct drm_device *dev)
4542{
4543 drm_i915_private_t *dev_priv = dev->dev_private;
4544 int ret;
28dfe52a 4545
29105ccc 4546 mutex_lock(&dev->struct_mutex);
1c5d22f7 4547
8187a2b7 4548 if (dev_priv->mm.suspended ||
d1b851fc
ZN		 4549 (dev_priv->render_ring.gem_object == NULL) ||
4550 (HAS_BSD(dev) &&
4551 dev_priv->bsd_ring.gem_object == NULL)) {
29105ccc
CW		 4552 mutex_unlock(&dev->struct_mutex);
4553 return 0;
28dfe52a
EA		 4554 }
4555
29105ccc 4556 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4557 if (ret) {
4558 mutex_unlock(&dev->struct_mutex);
673a394b 4559 return ret;
6dbe2772 4560 }
673a394b 4561
29105ccc
CW		 4562 /* Under UMS, be paranoid and evict. */
4563 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4564 ret = i915_gem_evict_from_inactive_list(dev);
4565 if (ret) {
4566 mutex_unlock(&dev->struct_mutex);
4567 return ret;
4568 }
4569 }
4570
4571 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4572 * We need to replace this with a semaphore, or something.
4573 * And not confound mm.suspended!
4574 */
4575 dev_priv->mm.suspended = 1;
4576 del_timer(&dev_priv->hangcheck_timer);
4577
4578 i915_kernel_lost_context(dev);
6dbe2772 4579 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4580
6dbe2772
KP		 4581 mutex_unlock(&dev->struct_mutex);
4582
29105ccc
CW		 4583 /* Cancel the retire work handler, which should be idle now. */
4584 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4585
673a394b
EA		 4586 return 0;
4587}
4588
e552eb70
JB		 4589/*
4590 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4591 * over cache flushing.
4592 */
8187a2b7 4593static int
e552eb70
JB		 4594i915_gem_init_pipe_control(struct drm_device *dev)
4595{
4596 drm_i915_private_t *dev_priv = dev->dev_private;
4597 struct drm_gem_object *obj;
4598 struct drm_i915_gem_object *obj_priv;
4599 int ret;
4600
34dc4d44 4601 obj = i915_gem_alloc_object(dev, 4096);
e552eb70
JB		 4602 if (obj == NULL) {
4603 DRM_ERROR("Failed to allocate seqno page\n");
4604 ret = -ENOMEM;
4605 goto err;
4606 }
4607 obj_priv = to_intel_bo(obj);
4608 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4609
4610 ret = i915_gem_object_pin(obj, 4096);
4611 if (ret)
4612 goto err_unref;
4613
4614 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4615 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4616 if (dev_priv->seqno_page == NULL)
4617 goto err_unpin;
4618
4619 dev_priv->seqno_obj = obj;
4620 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4621
4622 return 0;
4623
4624err_unpin:
4625 i915_gem_object_unpin(obj);
4626err_unref:
4627 drm_gem_object_unreference(obj);
4628err:
4629 return ret;
4630}
4631
8187a2b7
ZN		 4632
4633static void
e552eb70
JB		 4634i915_gem_cleanup_pipe_control(struct drm_device *dev)
4635{
4636 drm_i915_private_t *dev_priv = dev->dev_private;
4637 struct drm_gem_object *obj;
4638 struct drm_i915_gem_object *obj_priv;
4639
4640 obj = dev_priv->seqno_obj;
4641 obj_priv = to_intel_bo(obj);
4642 kunmap(obj_priv->pages[0]);
4643 i915_gem_object_unpin(obj);
4644 drm_gem_object_unreference(obj);
4645 dev_priv->seqno_obj = NULL;
4646
4647 dev_priv->seqno_page = NULL;
673a394b
EA		 4648}
4649
8187a2b7
ZN		 4650int
4651i915_gem_init_ringbuffer(struct drm_device *dev)
4652{
4653 drm_i915_private_t *dev_priv = dev->dev_private;
4654 int ret;
68f95ba9 4655
8187a2b7 4656 dev_priv->render_ring = render_ring;
68f95ba9 4657
8187a2b7
ZN		 4658 if (!I915_NEED_GFX_HWS(dev)) {
4659 dev_priv->render_ring.status_page.page_addr
4660 = dev_priv->status_page_dmah->vaddr;
4661 memset(dev_priv->render_ring.status_page.page_addr,
4662 0, PAGE_SIZE);
4663 }
68f95ba9 4664
8187a2b7
ZN		 4665 if (HAS_PIPE_CONTROL(dev)) {
4666 ret = i915_gem_init_pipe_control(dev);
4667 if (ret)
4668 return ret;
4669 }
68f95ba9 4670
8187a2b7 4671 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
68f95ba9
CW		 4672 if (ret)
4673 goto cleanup_pipe_control;
4674
4675 if (HAS_BSD(dev)) {
d1b851fc
ZN		 4676 dev_priv->bsd_ring = bsd_ring;
4677 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
68f95ba9
CW		 4678 if (ret)
4679 goto cleanup_render_ring;
d1b851fc 4680 }
68f95ba9
CW		 4681
4682 return 0;
4683
4684cleanup_render_ring:
4685 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4686cleanup_pipe_control:
4687 if (HAS_PIPE_CONTROL(dev))
4688 i915_gem_cleanup_pipe_control(dev);
8187a2b7
ZN		 4689 return ret;
4690}
4691
4692void
4693i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4694{
4695 drm_i915_private_t *dev_priv = dev->dev_private;
4696
4697 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 4698 if (HAS_BSD(dev))
4699 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
8187a2b7
ZN		 4700 if (HAS_PIPE_CONTROL(dev))
4701 i915_gem_cleanup_pipe_control(dev);
4702}
4703
673a394b
EA		 4704int
4705i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4706 struct drm_file *file_priv)
4707{
4708 drm_i915_private_t *dev_priv = dev->dev_private;
4709 int ret;
4710
79e53945
JB		 4711 if (drm_core_check_feature(dev, DRIVER_MODESET))
4712 return 0;
4713
ba1234d1 4714 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4715 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4716 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4717 }
4718
673a394b 4719 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4720 dev_priv->mm.suspended = 0;
4721
4722 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4723 if (ret != 0) {
4724 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4725 return ret;
d816f6ac 4726 }
9bb2d6f9 4727
5e118f41 4728 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 4729 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
d1b851fc 4730 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
5e118f41
CW		 4731 spin_unlock(&dev_priv->mm.active_list_lock);
4732
673a394b
EA		 4733 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4734 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
852835f3 4735 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
d1b851fc 4736 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
673a394b 4737 mutex_unlock(&dev->struct_mutex);
dbb19d30 4738
5f35308b
CW		 4739 ret = drm_irq_install(dev);
4740 if (ret)
4741 goto cleanup_ringbuffer;
dbb19d30 4742
673a394b 4743 return 0;
5f35308b
CW		 4744
4745cleanup_ringbuffer:
4746 mutex_lock(&dev->struct_mutex);
4747 i915_gem_cleanup_ringbuffer(dev);
4748 dev_priv->mm.suspended = 1;
4749 mutex_unlock(&dev->struct_mutex);
4750
4751 return ret;
673a394b
EA		 4752}
4753
4754int
4755i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4756 struct drm_file *file_priv)
4757{
79e53945
JB		 4758 if (drm_core_check_feature(dev, DRIVER_MODESET))
4759 return 0;
4760
dbb19d30 4761 drm_irq_uninstall(dev);
e6890f6f 4762 return i915_gem_idle(dev);
673a394b
EA		 4763}
4764
4765void
4766i915_gem_lastclose(struct drm_device *dev)
4767{
4768 int ret;
673a394b 4769
e806b495
EA		 4770 if (drm_core_check_feature(dev, DRIVER_MODESET))
4771 return;
4772
6dbe2772
KP		 4773 ret = i915_gem_idle(dev);
4774 if (ret)
4775 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4776}
4777
4778void
4779i915_gem_load(struct drm_device *dev)
4780{
b5aa8a0f 4781 int i;
673a394b
EA		 4782 drm_i915_private_t *dev_priv = dev->dev_private;
4783
5e118f41 4784 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b 4785 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4786 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b 4787 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
a09ba7fa 4788 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
be72615b 4789 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
852835f3
ZN		 4790 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4791 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
d1b851fc
ZN		 4792 if (HAS_BSD(dev)) {
4793 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4794 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4795 }
007cc8ac
DV		 4796 for (i = 0; i < 16; i++)
4797 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 4798 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4799 i915_gem_retire_work_handler);
31169714
CW		 4800 spin_lock(&shrink_list_lock);
4801 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4802 spin_unlock(&shrink_list_lock);
4803
94400120
DA		 4804 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4805 if (IS_GEN3(dev)) {
4806 u32 tmp = I915_READ(MI_ARB_STATE);
4807 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4808 /* arb state is a masked write, so set bit + bit in mask */
4809 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4810 I915_WRITE(MI_ARB_STATE, tmp);
4811 }
4812 }
4813
de151cf6 4814 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4815 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4816 dev_priv->fence_reg_start = 3;
de151cf6 4817
0f973f27 4818 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4819 dev_priv->num_fence_regs = 16;
4820 else
4821 dev_priv->num_fence_regs = 8;
4822
b5aa8a0f
GH		 4823 /* Initialize fence registers to zero */
4824 if (IS_I965G(dev)) {
4825 for (i = 0; i < 16; i++)
4826 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4827 } else {
4828 for (i = 0; i < 8; i++)
4829 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4830 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4831 for (i = 0; i < 8; i++)
4832 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4833 }
673a394b 4834 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4835 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4836}
71acb5eb
DA		 4837
4838/*
4839 * Create a physically contiguous memory object for this object
4840 * e.g. for cursor + overlay regs
4841 */
4842int i915_gem_init_phys_object(struct drm_device *dev,
4843 int id, int size)
4844{
4845 drm_i915_private_t *dev_priv = dev->dev_private;
4846 struct drm_i915_gem_phys_object *phys_obj;
4847 int ret;
4848
4849 if (dev_priv->mm.phys_objs[id - 1] || !size)
4850 return 0;
4851
9a298b2a 4852 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4853 if (!phys_obj)
4854 return -ENOMEM;
4855
4856 phys_obj->id = id;
4857
e6be8d9d 4858 phys_obj->handle = drm_pci_alloc(dev, size, 0);
71acb5eb
DA		 4859 if (!phys_obj->handle) {
4860 ret = -ENOMEM;
4861 goto kfree_obj;
4862 }
4863#ifdef CONFIG_X86
4864 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4865#endif
4866
4867 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4868
4869 return 0;
4870kfree_obj:
9a298b2a 4871 kfree(phys_obj);
71acb5eb
DA		 4872 return ret;
4873}
4874
4875void i915_gem_free_phys_object(struct drm_device *dev, int id)
4876{
4877 drm_i915_private_t *dev_priv = dev->dev_private;
4878 struct drm_i915_gem_phys_object *phys_obj;
4879
4880 if (!dev_priv->mm.phys_objs[id - 1])
4881 return;
4882
4883 phys_obj = dev_priv->mm.phys_objs[id - 1];
4884 if (phys_obj->cur_obj) {
4885 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4886 }
4887
4888#ifdef CONFIG_X86
4889 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4890#endif
4891 drm_pci_free(dev, phys_obj->handle);
4892 kfree(phys_obj);
4893 dev_priv->mm.phys_objs[id - 1] = NULL;
4894}
4895
4896void i915_gem_free_all_phys_object(struct drm_device *dev)
4897{
4898 int i;
4899
260883c8 4900 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4901 i915_gem_free_phys_object(dev, i);
4902}
4903
4904void i915_gem_detach_phys_object(struct drm_device *dev,
4905 struct drm_gem_object *obj)
4906{
4907 struct drm_i915_gem_object *obj_priv;
4908 int i;
4909 int ret;
4910 int page_count;
4911
23010e43 4912 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4913 if (!obj_priv->phys_obj)
4914 return;
4915
4bdadb97 4916 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4917 if (ret)
4918 goto out;
4919
4920 page_count = obj->size / PAGE_SIZE;
4921
4922 for (i = 0; i < page_count; i++) {
856fa198 4923 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4924 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4925
4926 memcpy(dst, src, PAGE_SIZE);
4927 kunmap_atomic(dst, KM_USER0);
4928 }
856fa198 4929 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4930 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4931
4932 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4933out:
4934 obj_priv->phys_obj->cur_obj = NULL;
4935 obj_priv->phys_obj = NULL;
4936}
4937
4938int
4939i915_gem_attach_phys_object(struct drm_device *dev,
4940 struct drm_gem_object *obj, int id)
4941{
4942 drm_i915_private_t *dev_priv = dev->dev_private;
4943 struct drm_i915_gem_object *obj_priv;
4944 int ret = 0;
4945 int page_count;
4946 int i;
4947
4948 if (id > I915_MAX_PHYS_OBJECT)
4949 return -EINVAL;
4950
23010e43 4951 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4952
4953 if (obj_priv->phys_obj) {
4954 if (obj_priv->phys_obj->id == id)
4955 return 0;
4956 i915_gem_detach_phys_object(dev, obj);
4957 }
4958
4959
4960 /* create a new object */
4961 if (!dev_priv->mm.phys_objs[id - 1]) {
4962 ret = i915_gem_init_phys_object(dev, id,
4963 obj->size);
4964 if (ret) {
aeb565df 4965 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4966 goto out;
4967 }
4968 }
4969
4970 /* bind to the object */
4971 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4972 obj_priv->phys_obj->cur_obj = obj;
4973
4bdadb97 4974 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4975 if (ret) {
4976 DRM_ERROR("failed to get page list\n");
4977 goto out;
4978 }
4979
4980 page_count = obj->size / PAGE_SIZE;
4981
4982 for (i = 0; i < page_count; i++) {
856fa198 4983 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4984 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4985
4986 memcpy(dst, src, PAGE_SIZE);
4987 kunmap_atomic(src, KM_USER0);
4988 }
4989
d78b47b9
CW		 4990 i915_gem_object_put_pages(obj);
4991
71acb5eb
DA		 4992 return 0;
4993out:
4994 return ret;
4995}
4996
4997static int
4998i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4999 struct drm_i915_gem_pwrite *args,
5000 struct drm_file *file_priv)
5001{
23010e43 5002 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 5003 void *obj_addr;
5004 int ret;
5005 char __user *user_data;
5006
5007 user_data = (char __user *) (uintptr_t) args->data_ptr;
5008 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5009
44d98a61 5010 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 5011 ret = copy_from_user(obj_addr, user_data, args->size);
5012 if (ret)
5013 return -EFAULT;
5014
5015 drm_agp_chipset_flush(dev);
5016 return 0;
5017}
b962442e
EA		 5018
5019void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5020{
5021 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5022
5023 /* Clean up our request list when the client is going away, so that
5024 * later retire_requests won't dereference our soon-to-be-gone
5025 * file_priv.
5026 */
5027 mutex_lock(&dev->struct_mutex);
5028 while (!list_empty(&i915_file_priv->mm.request_list))
5029 list_del_init(i915_file_priv->mm.request_list.next);
5030 mutex_unlock(&dev->struct_mutex);
5031}
31169714 5032
1637ef41
CW		 5033static int
5034i915_gpu_is_active(struct drm_device *dev)
5035{
5036 drm_i915_private_t *dev_priv = dev->dev_private;
5037 int lists_empty;
5038
5039 spin_lock(&dev_priv->mm.active_list_lock);
5040 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
852835f3 5041 list_empty(&dev_priv->render_ring.active_list);
d1b851fc
ZN		 5042 if (HAS_BSD(dev))
5043 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
1637ef41
CW		 5044 spin_unlock(&dev_priv->mm.active_list_lock);
5045
5046 return !lists_empty;
5047}
5048
31169714 5049static int
7f8275d0 5050i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
31169714
CW		 5051{
5052 drm_i915_private_t *dev_priv, *next_dev;
5053 struct drm_i915_gem_object *obj_priv, *next_obj;
5054 int cnt = 0;
5055 int would_deadlock = 1;
5056
5057 /* "fast-path" to count number of available objects */
5058 if (nr_to_scan == 0) {
5059 spin_lock(&shrink_list_lock);
5060 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5061 struct drm_device *dev = dev_priv->dev;
5062
5063 if (mutex_trylock(&dev->struct_mutex)) {
5064 list_for_each_entry(obj_priv,
5065 &dev_priv->mm.inactive_list,
5066 list)
5067 cnt++;
5068 mutex_unlock(&dev->struct_mutex);
5069 }
5070 }
5071 spin_unlock(&shrink_list_lock);
5072
5073 return (cnt / 100) * sysctl_vfs_cache_pressure;
5074 }
5075
5076 spin_lock(&shrink_list_lock);
5077
1637ef41 5078rescan:
31169714
CW		 5079 /* first scan for clean buffers */
5080 list_for_each_entry_safe(dev_priv, next_dev,
5081 &shrink_list, mm.shrink_list) {
5082 struct drm_device *dev = dev_priv->dev;
5083
5084 if (! mutex_trylock(&dev->struct_mutex))
5085 continue;
5086
5087 spin_unlock(&shrink_list_lock);
b09a1fec 5088 i915_gem_retire_requests(dev);
31169714
CW		 5089
5090 list_for_each_entry_safe(obj_priv, next_obj,
5091 &dev_priv->mm.inactive_list,
5092 list) {
5093 if (i915_gem_object_is_purgeable(obj_priv)) {
a8089e84 5094 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5095 if (--nr_to_scan <= 0)
5096 break;
5097 }
5098 }
5099
5100 spin_lock(&shrink_list_lock);
5101 mutex_unlock(&dev->struct_mutex);
5102
963b4836
CW		 5103 would_deadlock = 0;
5104
31169714
CW		 5105 if (nr_to_scan <= 0)
5106 break;
5107 }
5108
5109 /* second pass, evict/count anything still on the inactive list */
5110 list_for_each_entry_safe(dev_priv, next_dev,
5111 &shrink_list, mm.shrink_list) {
5112 struct drm_device *dev = dev_priv->dev;
5113
5114 if (! mutex_trylock(&dev->struct_mutex))
5115 continue;
5116
5117 spin_unlock(&shrink_list_lock);
5118
5119 list_for_each_entry_safe(obj_priv, next_obj,
5120 &dev_priv->mm.inactive_list,
5121 list) {
5122 if (nr_to_scan > 0) {
a8089e84 5123 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5124 nr_to_scan--;
5125 } else
5126 cnt++;
5127 }
5128
5129 spin_lock(&shrink_list_lock);
5130 mutex_unlock(&dev->struct_mutex);
5131
5132 would_deadlock = 0;
5133 }
5134
1637ef41
CW		 5135 if (nr_to_scan) {
5136 int active = 0;
5137
5138 /*
5139 * We are desperate for pages, so as a last resort, wait
5140 * for the GPU to finish and discard whatever we can.
5141 * This has a dramatic impact to reduce the number of
5142 * OOM-killer events whilst running the GPU aggressively.
5143 */
5144 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5145 struct drm_device *dev = dev_priv->dev;
5146
5147 if (!mutex_trylock(&dev->struct_mutex))
5148 continue;
5149
5150 spin_unlock(&shrink_list_lock);
5151
5152 if (i915_gpu_is_active(dev)) {
5153 i915_gpu_idle(dev);
5154 active++;
5155 }
5156
5157 spin_lock(&shrink_list_lock);
5158 mutex_unlock(&dev->struct_mutex);
5159 }
5160
5161 if (active)
5162 goto rescan;
5163 }
5164
31169714
CW		 5165 spin_unlock(&shrink_list_lock);
5166
5167 if (would_deadlock)
5168 return -1;
5169 else if (cnt > 0)
5170 return (cnt / 100) * sysctl_vfs_cache_pressure;
5171 else
5172 return 0;
5173}
5174
5175static struct shrinker shrinker = {
5176 .shrink = i915_gem_shrink,
5177 .seeks = DEFAULT_SEEKS,
5178};
5179
5180__init void
5181i915_gem_shrinker_init(void)
5182{
5183 register_shrinker(&shrinker);
5184}
5185
5186__exit void
5187i915_gem_shrinker_exit(void)
5188{
5189 unregister_shrinker(&shrinker);
5190}
Clone of davem's net-next-2.6 tree