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drm/i915: cleanup FBC buffers at unload time
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
673a394b 37
28dfe52a
EA		 38#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39
e47c68e9
EA		 40static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
41static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 43static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 int write);
45static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 uint64_t offset,
47 uint64_t size);
48static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 49static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 50static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 unsigned alignment);
de151cf6 52static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 53static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 54static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 55static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
56 struct drm_i915_gem_pwrite *args,
57 struct drm_file *file_priv);
673a394b 58
31169714
CW		 59static LIST_HEAD(shrink_list);
60static DEFINE_SPINLOCK(shrink_list_lock);
61
79e53945
JB		 62int i915_gem_do_init(struct drm_device *dev, unsigned long start,
63 unsigned long end)
673a394b
EA		 64{
65 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 66
79e53945
JB		 67 if (start >= end ||
68 (start & (PAGE_SIZE - 1)) != 0 ||
69 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 70 return -EINVAL;
71 }
72
79e53945
JB		 73 drm_mm_init(&dev_priv->mm.gtt_space, start,
74 end - start);
673a394b 75
79e53945
JB		 76 dev->gtt_total = (uint32_t) (end - start);
77
78 return 0;
79}
673a394b 80
79e53945
JB		 81int
82i915_gem_init_ioctl(struct drm_device *dev, void *data,
83 struct drm_file *file_priv)
84{
85 struct drm_i915_gem_init *args = data;
86 int ret;
87
88 mutex_lock(&dev->struct_mutex);
89 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 90 mutex_unlock(&dev->struct_mutex);
91
79e53945 92 return ret;
673a394b
EA		 93}
94
5a125c3c
EA		 95int
96i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
97 struct drm_file *file_priv)
98{
5a125c3c 99 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 100
101 if (!(dev->driver->driver_features & DRIVER_GEM))
102 return -ENODEV;
103
104 args->aper_size = dev->gtt_total;
2678d9d6
KP		 105 args->aper_available_size = (args->aper_size -
106 atomic_read(&dev->pin_memory));
5a125c3c
EA		 107
108 return 0;
109}
110
673a394b
EA		 111
112/**
113 * Creates a new mm object and returns a handle to it.
114 */
115int
116i915_gem_create_ioctl(struct drm_device *dev, void *data,
117 struct drm_file *file_priv)
118{
119 struct drm_i915_gem_create *args = data;
120 struct drm_gem_object *obj;
a1a2d1d3
PP		 121 int ret;
122 u32 handle;
673a394b
EA		 123
124 args->size = roundup(args->size, PAGE_SIZE);
125
126 /* Allocate the new object */
127 obj = drm_gem_object_alloc(dev, args->size);
128 if (obj == NULL)
129 return -ENOMEM;
130
131 ret = drm_gem_handle_create(file_priv, obj, &handle);
bc9025bd 132 drm_gem_object_handle_unreference_unlocked(obj);
673a394b
EA		 133
134 if (ret)
135 return ret;
136
137 args->handle = handle;
138
139 return 0;
140}
141
eb01459f
EA		 142static inline int
143fast_shmem_read(struct page **pages,
144 loff_t page_base, int page_offset,
145 char __user *data,
146 int length)
147{
148 char __iomem *vaddr;
2bc43b5c 149 int unwritten;
eb01459f
EA		 150
151 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
152 if (vaddr == NULL)
153 return -ENOMEM;
2bc43b5c 154 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 155 kunmap_atomic(vaddr, KM_USER0);
156
2bc43b5c
FM		 157 if (unwritten)
158 return -EFAULT;
159
160 return 0;
eb01459f
EA		 161}
162
280b713b
EA		 163static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
164{
165 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 166 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 167
168 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
169 obj_priv->tiling_mode != I915_TILING_NONE;
170}
171
40123c1f
EA		 172static inline int
173slow_shmem_copy(struct page *dst_page,
174 int dst_offset,
175 struct page *src_page,
176 int src_offset,
177 int length)
178{
179 char *dst_vaddr, *src_vaddr;
180
181 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
182 if (dst_vaddr == NULL)
183 return -ENOMEM;
184
185 src_vaddr = kmap_atomic(src_page, KM_USER1);
186 if (src_vaddr == NULL) {
187 kunmap_atomic(dst_vaddr, KM_USER0);
188 return -ENOMEM;
189 }
190
191 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
192
193 kunmap_atomic(src_vaddr, KM_USER1);
194 kunmap_atomic(dst_vaddr, KM_USER0);
195
196 return 0;
197}
198
280b713b
EA		 199static inline int
200slow_shmem_bit17_copy(struct page *gpu_page,
201 int gpu_offset,
202 struct page *cpu_page,
203 int cpu_offset,
204 int length,
205 int is_read)
206{
207 char *gpu_vaddr, *cpu_vaddr;
208
209 /* Use the unswizzled path if this page isn't affected. */
210 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
211 if (is_read)
212 return slow_shmem_copy(cpu_page, cpu_offset,
213 gpu_page, gpu_offset, length);
214 else
215 return slow_shmem_copy(gpu_page, gpu_offset,
216 cpu_page, cpu_offset, length);
217 }
218
219 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
220 if (gpu_vaddr == NULL)
221 return -ENOMEM;
222
223 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
224 if (cpu_vaddr == NULL) {
225 kunmap_atomic(gpu_vaddr, KM_USER0);
226 return -ENOMEM;
227 }
228
229 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
230 * XORing with the other bits (A9 for Y, A9 and A10 for X)
231 */
232 while (length > 0) {
233 int cacheline_end = ALIGN(gpu_offset + 1, 64);
234 int this_length = min(cacheline_end - gpu_offset, length);
235 int swizzled_gpu_offset = gpu_offset ^ 64;
236
237 if (is_read) {
238 memcpy(cpu_vaddr + cpu_offset,
239 gpu_vaddr + swizzled_gpu_offset,
240 this_length);
241 } else {
242 memcpy(gpu_vaddr + swizzled_gpu_offset,
243 cpu_vaddr + cpu_offset,
244 this_length);
245 }
246 cpu_offset += this_length;
247 gpu_offset += this_length;
248 length -= this_length;
249 }
250
251 kunmap_atomic(cpu_vaddr, KM_USER1);
252 kunmap_atomic(gpu_vaddr, KM_USER0);
253
254 return 0;
255}
256
eb01459f
EA		 257/**
258 * This is the fast shmem pread path, which attempts to copy_from_user directly
259 * from the backing pages of the object to the user's address space. On a
260 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
261 */
262static int
263i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
264 struct drm_i915_gem_pread *args,
265 struct drm_file *file_priv)
266{
23010e43 267 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 268 ssize_t remain;
269 loff_t offset, page_base;
270 char __user *user_data;
271 int page_offset, page_length;
272 int ret;
273
274 user_data = (char __user *) (uintptr_t) args->data_ptr;
275 remain = args->size;
276
277 mutex_lock(&dev->struct_mutex);
278
4bdadb97 279 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 280 if (ret != 0)
281 goto fail_unlock;
282
283 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
284 args->size);
285 if (ret != 0)
286 goto fail_put_pages;
287
23010e43 288 obj_priv = to_intel_bo(obj);
eb01459f
EA		 289 offset = args->offset;
290
291 while (remain > 0) {
292 /* Operation in this page
293 *
294 * page_base = page offset within aperture
295 * page_offset = offset within page
296 * page_length = bytes to copy for this page
297 */
298 page_base = (offset & ~(PAGE_SIZE-1));
299 page_offset = offset & (PAGE_SIZE-1);
300 page_length = remain;
301 if ((page_offset + remain) > PAGE_SIZE)
302 page_length = PAGE_SIZE - page_offset;
303
304 ret = fast_shmem_read(obj_priv->pages,
305 page_base, page_offset,
306 user_data, page_length);
307 if (ret)
308 goto fail_put_pages;
309
310 remain -= page_length;
311 user_data += page_length;
312 offset += page_length;
313 }
314
315fail_put_pages:
316 i915_gem_object_put_pages(obj);
317fail_unlock:
318 mutex_unlock(&dev->struct_mutex);
319
320 return ret;
321}
322
07f73f69
CW		 323static int
324i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
325{
326 int ret;
327
4bdadb97 328 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 329
330 /* If we've insufficient memory to map in the pages, attempt
331 * to make some space by throwing out some old buffers.
332 */
333 if (ret == -ENOMEM) {
334 struct drm_device *dev = obj->dev;
07f73f69
CW		 335
336 ret = i915_gem_evict_something(dev, obj->size);
337 if (ret)
338 return ret;
339
4bdadb97 340 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 341 }
342
343 return ret;
344}
345
eb01459f
EA		 346/**
347 * This is the fallback shmem pread path, which allocates temporary storage
348 * in kernel space to copy_to_user into outside of the struct_mutex, so we
349 * can copy out of the object's backing pages while holding the struct mutex
350 * and not take page faults.
351 */
352static int
353i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
354 struct drm_i915_gem_pread *args,
355 struct drm_file *file_priv)
356{
23010e43 357 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 358 struct mm_struct *mm = current->mm;
359 struct page **user_pages;
360 ssize_t remain;
361 loff_t offset, pinned_pages, i;
362 loff_t first_data_page, last_data_page, num_pages;
363 int shmem_page_index, shmem_page_offset;
364 int data_page_index, data_page_offset;
365 int page_length;
366 int ret;
367 uint64_t data_ptr = args->data_ptr;
280b713b 368 int do_bit17_swizzling;
eb01459f
EA		 369
370 remain = args->size;
371
372 /* Pin the user pages containing the data. We can't fault while
373 * holding the struct mutex, yet we want to hold it while
374 * dereferencing the user data.
375 */
376 first_data_page = data_ptr / PAGE_SIZE;
377 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
378 num_pages = last_data_page - first_data_page + 1;
379
8e7d2b2c 380 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 381 if (user_pages == NULL)
382 return -ENOMEM;
383
384 down_read(&mm->mmap_sem);
385 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 386 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 387 up_read(&mm->mmap_sem);
388 if (pinned_pages < num_pages) {
389 ret = -EFAULT;
390 goto fail_put_user_pages;
391 }
392
280b713b
EA		 393 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
394
eb01459f
EA		 395 mutex_lock(&dev->struct_mutex);
396
07f73f69
CW		 397 ret = i915_gem_object_get_pages_or_evict(obj);
398 if (ret)
eb01459f
EA		 399 goto fail_unlock;
400
401 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
402 args->size);
403 if (ret != 0)
404 goto fail_put_pages;
405
23010e43 406 obj_priv = to_intel_bo(obj);
eb01459f
EA		 407 offset = args->offset;
408
409 while (remain > 0) {
410 /* Operation in this page
411 *
412 * shmem_page_index = page number within shmem file
413 * shmem_page_offset = offset within page in shmem file
414 * data_page_index = page number in get_user_pages return
415 * data_page_offset = offset with data_page_index page.
416 * page_length = bytes to copy for this page
417 */
418 shmem_page_index = offset / PAGE_SIZE;
419 shmem_page_offset = offset & ~PAGE_MASK;
420 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
421 data_page_offset = data_ptr & ~PAGE_MASK;
422
423 page_length = remain;
424 if ((shmem_page_offset + page_length) > PAGE_SIZE)
425 page_length = PAGE_SIZE - shmem_page_offset;
426 if ((data_page_offset + page_length) > PAGE_SIZE)
427 page_length = PAGE_SIZE - data_page_offset;
428
280b713b
EA		 429 if (do_bit17_swizzling) {
430 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
431 shmem_page_offset,
432 user_pages[data_page_index],
433 data_page_offset,
434 page_length,
435 1);
436 } else {
437 ret = slow_shmem_copy(user_pages[data_page_index],
438 data_page_offset,
439 obj_priv->pages[shmem_page_index],
440 shmem_page_offset,
441 page_length);
442 }
eb01459f
EA		 443 if (ret)
444 goto fail_put_pages;
445
446 remain -= page_length;
447 data_ptr += page_length;
448 offset += page_length;
449 }
450
451fail_put_pages:
452 i915_gem_object_put_pages(obj);
453fail_unlock:
454 mutex_unlock(&dev->struct_mutex);
455fail_put_user_pages:
456 for (i = 0; i < pinned_pages; i++) {
457 SetPageDirty(user_pages[i]);
458 page_cache_release(user_pages[i]);
459 }
8e7d2b2c 460 drm_free_large(user_pages);
eb01459f
EA		 461
462 return ret;
463}
464
673a394b
EA		 465/**
466 * Reads data from the object referenced by handle.
467 *
468 * On error, the contents of *data are undefined.
469 */
470int
471i915_gem_pread_ioctl(struct drm_device *dev, void *data,
472 struct drm_file *file_priv)
473{
474 struct drm_i915_gem_pread *args = data;
475 struct drm_gem_object *obj;
476 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 477 int ret;
478
479 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
480 if (obj == NULL)
481 return -EBADF;
23010e43 482 obj_priv = to_intel_bo(obj);
673a394b
EA		 483
484 /* Bounds check source.
485 *
486 * XXX: This could use review for overflow issues...
487 */
488 if (args->offset > obj->size || args->size > obj->size ||
489 args->offset + args->size > obj->size) {
bc9025bd 490 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 491 return -EINVAL;
492 }
493
280b713b 494 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 495 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 496 } else {
497 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
498 if (ret != 0)
499 ret = i915_gem_shmem_pread_slow(dev, obj, args,
500 file_priv);
501 }
673a394b 502
bc9025bd 503 drm_gem_object_unreference_unlocked(obj);
673a394b 504
eb01459f 505 return ret;
673a394b
EA		 506}
507
0839ccb8
KP		 508/* This is the fast write path which cannot handle
509 * page faults in the source data
9b7530cc 510 */
0839ccb8
KP		 511
512static inline int
513fast_user_write(struct io_mapping *mapping,
514 loff_t page_base, int page_offset,
515 char __user *user_data,
516 int length)
9b7530cc 517{
9b7530cc 518 char *vaddr_atomic;
0839ccb8 519 unsigned long unwritten;
9b7530cc 520
0839ccb8
KP		 521 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
522 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
523 user_data, length);
524 io_mapping_unmap_atomic(vaddr_atomic);
525 if (unwritten)
526 return -EFAULT;
527 return 0;
528}
529
530/* Here's the write path which can sleep for
531 * page faults
532 */
533
534static inline int
3de09aa3
EA		 535slow_kernel_write(struct io_mapping *mapping,
536 loff_t gtt_base, int gtt_offset,
537 struct page *user_page, int user_offset,
538 int length)
0839ccb8 539{
3de09aa3 540 char *src_vaddr, *dst_vaddr;
0839ccb8
KP		 541 unsigned long unwritten;
542
3de09aa3
EA		 543 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
544 src_vaddr = kmap_atomic(user_page, KM_USER1);
545 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
546 src_vaddr + user_offset,
547 length);
548 kunmap_atomic(src_vaddr, KM_USER1);
549 io_mapping_unmap_atomic(dst_vaddr);
0839ccb8
KP		 550 if (unwritten)
551 return -EFAULT;
9b7530cc 552 return 0;
9b7530cc
LT		 553}
554
40123c1f
EA		 555static inline int
556fast_shmem_write(struct page **pages,
557 loff_t page_base, int page_offset,
558 char __user *data,
559 int length)
560{
561 char __iomem *vaddr;
d0088775 562 unsigned long unwritten;
40123c1f
EA		 563
564 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
565 if (vaddr == NULL)
566 return -ENOMEM;
d0088775 567 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 568 kunmap_atomic(vaddr, KM_USER0);
569
d0088775
DA		 570 if (unwritten)
571 return -EFAULT;
40123c1f
EA		 572 return 0;
573}
574
3de09aa3
EA		 575/**
576 * This is the fast pwrite path, where we copy the data directly from the
577 * user into the GTT, uncached.
578 */
673a394b 579static int
3de09aa3
EA		 580i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
581 struct drm_i915_gem_pwrite *args,
582 struct drm_file *file_priv)
673a394b 583{
23010e43 584 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 585 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 586 ssize_t remain;
0839ccb8 587 loff_t offset, page_base;
673a394b 588 char __user *user_data;
0839ccb8
KP		 589 int page_offset, page_length;
590 int ret;
673a394b
EA		 591
592 user_data = (char __user *) (uintptr_t) args->data_ptr;
593 remain = args->size;
594 if (!access_ok(VERIFY_READ, user_data, remain))
595 return -EFAULT;
596
597
598 mutex_lock(&dev->struct_mutex);
599 ret = i915_gem_object_pin(obj, 0);
600 if (ret) {
601 mutex_unlock(&dev->struct_mutex);
602 return ret;
603 }
2ef7eeaa 604 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 605 if (ret)
606 goto fail;
607
23010e43 608 obj_priv = to_intel_bo(obj);
673a394b 609 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 610
611 while (remain > 0) {
612 /* Operation in this page
613 *
0839ccb8
KP		 614 * page_base = page offset within aperture
615 * page_offset = offset within page
616 * page_length = bytes to copy for this page
673a394b 617 */
0839ccb8
KP		 618 page_base = (offset & ~(PAGE_SIZE-1));
619 page_offset = offset & (PAGE_SIZE-1);
620 page_length = remain;
621 if ((page_offset + remain) > PAGE_SIZE)
622 page_length = PAGE_SIZE - page_offset;
623
624 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
625 page_offset, user_data, page_length);
626
627 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
0839ccb8 630 */
3de09aa3
EA		 631 if (ret)
632 goto fail;
673a394b 633
0839ccb8
KP		 634 remain -= page_length;
635 user_data += page_length;
636 offset += page_length;
673a394b 637 }
673a394b
EA		 638
639fail:
640 i915_gem_object_unpin(obj);
641 mutex_unlock(&dev->struct_mutex);
642
643 return ret;
644}
645
3de09aa3
EA		 646/**
647 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
648 * the memory and maps it using kmap_atomic for copying.
649 *
650 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
651 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
652 */
3043c60c 653static int
3de09aa3
EA		 654i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
655 struct drm_i915_gem_pwrite *args,
656 struct drm_file *file_priv)
673a394b 657{
23010e43 658 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 659 drm_i915_private_t *dev_priv = dev->dev_private;
660 ssize_t remain;
661 loff_t gtt_page_base, offset;
662 loff_t first_data_page, last_data_page, num_pages;
663 loff_t pinned_pages, i;
664 struct page **user_pages;
665 struct mm_struct *mm = current->mm;
666 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 667 int ret;
3de09aa3
EA		 668 uint64_t data_ptr = args->data_ptr;
669
670 remain = args->size;
671
672 /* Pin the user pages containing the data. We can't fault while
673 * holding the struct mutex, and all of the pwrite implementations
674 * want to hold it while dereferencing the user data.
675 */
676 first_data_page = data_ptr / PAGE_SIZE;
677 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
678 num_pages = last_data_page - first_data_page + 1;
679
8e7d2b2c 680 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 681 if (user_pages == NULL)
682 return -ENOMEM;
683
684 down_read(&mm->mmap_sem);
685 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
686 num_pages, 0, 0, user_pages, NULL);
687 up_read(&mm->mmap_sem);
688 if (pinned_pages < num_pages) {
689 ret = -EFAULT;
690 goto out_unpin_pages;
691 }
673a394b
EA		 692
693 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 694 ret = i915_gem_object_pin(obj, 0);
695 if (ret)
696 goto out_unlock;
697
698 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
699 if (ret)
700 goto out_unpin_object;
701
23010e43 702 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 703 offset = obj_priv->gtt_offset + args->offset;
704
705 while (remain > 0) {
706 /* Operation in this page
707 *
708 * gtt_page_base = page offset within aperture
709 * gtt_page_offset = offset within page in aperture
710 * data_page_index = page number in get_user_pages return
711 * data_page_offset = offset with data_page_index page.
712 * page_length = bytes to copy for this page
713 */
714 gtt_page_base = offset & PAGE_MASK;
715 gtt_page_offset = offset & ~PAGE_MASK;
716 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
717 data_page_offset = data_ptr & ~PAGE_MASK;
718
719 page_length = remain;
720 if ((gtt_page_offset + page_length) > PAGE_SIZE)
721 page_length = PAGE_SIZE - gtt_page_offset;
722 if ((data_page_offset + page_length) > PAGE_SIZE)
723 page_length = PAGE_SIZE - data_page_offset;
724
725 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
726 gtt_page_base, gtt_page_offset,
727 user_pages[data_page_index],
728 data_page_offset,
729 page_length);
730
731 /* If we get a fault while copying data, then (presumably) our
732 * source page isn't available. Return the error and we'll
733 * retry in the slow path.
734 */
735 if (ret)
736 goto out_unpin_object;
737
738 remain -= page_length;
739 offset += page_length;
740 data_ptr += page_length;
741 }
742
743out_unpin_object:
744 i915_gem_object_unpin(obj);
745out_unlock:
746 mutex_unlock(&dev->struct_mutex);
747out_unpin_pages:
748 for (i = 0; i < pinned_pages; i++)
749 page_cache_release(user_pages[i]);
8e7d2b2c 750 drm_free_large(user_pages);
3de09aa3
EA		 751
752 return ret;
753}
754
40123c1f
EA		 755/**
756 * This is the fast shmem pwrite path, which attempts to directly
757 * copy_from_user into the kmapped pages backing the object.
758 */
3043c60c 759static int
40123c1f
EA		 760i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
761 struct drm_i915_gem_pwrite *args,
762 struct drm_file *file_priv)
673a394b 763{
23010e43 764 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 765 ssize_t remain;
766 loff_t offset, page_base;
767 char __user *user_data;
768 int page_offset, page_length;
673a394b 769 int ret;
40123c1f
EA		 770
771 user_data = (char __user *) (uintptr_t) args->data_ptr;
772 remain = args->size;
673a394b
EA		 773
774 mutex_lock(&dev->struct_mutex);
775
4bdadb97 776 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 777 if (ret != 0)
778 goto fail_unlock;
673a394b 779
e47c68e9 780 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 781 if (ret != 0)
782 goto fail_put_pages;
783
23010e43 784 obj_priv = to_intel_bo(obj);
40123c1f
EA		 785 offset = args->offset;
786 obj_priv->dirty = 1;
787
788 while (remain > 0) {
789 /* Operation in this page
790 *
791 * page_base = page offset within aperture
792 * page_offset = offset within page
793 * page_length = bytes to copy for this page
794 */
795 page_base = (offset & ~(PAGE_SIZE-1));
796 page_offset = offset & (PAGE_SIZE-1);
797 page_length = remain;
798 if ((page_offset + remain) > PAGE_SIZE)
799 page_length = PAGE_SIZE - page_offset;
800
801 ret = fast_shmem_write(obj_priv->pages,
802 page_base, page_offset,
803 user_data, page_length);
804 if (ret)
805 goto fail_put_pages;
806
807 remain -= page_length;
808 user_data += page_length;
809 offset += page_length;
810 }
811
812fail_put_pages:
813 i915_gem_object_put_pages(obj);
814fail_unlock:
815 mutex_unlock(&dev->struct_mutex);
816
817 return ret;
818}
819
820/**
821 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
822 * the memory and maps it using kmap_atomic for copying.
823 *
824 * This avoids taking mmap_sem for faulting on the user's address while the
825 * struct_mutex is held.
826 */
827static int
828i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
829 struct drm_i915_gem_pwrite *args,
830 struct drm_file *file_priv)
831{
23010e43 832 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 833 struct mm_struct *mm = current->mm;
834 struct page **user_pages;
835 ssize_t remain;
836 loff_t offset, pinned_pages, i;
837 loff_t first_data_page, last_data_page, num_pages;
838 int shmem_page_index, shmem_page_offset;
839 int data_page_index, data_page_offset;
840 int page_length;
841 int ret;
842 uint64_t data_ptr = args->data_ptr;
280b713b 843 int do_bit17_swizzling;
40123c1f
EA		 844
845 remain = args->size;
846
847 /* Pin the user pages containing the data. We can't fault while
848 * holding the struct mutex, and all of the pwrite implementations
849 * want to hold it while dereferencing the user data.
850 */
851 first_data_page = data_ptr / PAGE_SIZE;
852 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
853 num_pages = last_data_page - first_data_page + 1;
854
8e7d2b2c 855 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 856 if (user_pages == NULL)
857 return -ENOMEM;
858
859 down_read(&mm->mmap_sem);
860 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
861 num_pages, 0, 0, user_pages, NULL);
862 up_read(&mm->mmap_sem);
863 if (pinned_pages < num_pages) {
864 ret = -EFAULT;
865 goto fail_put_user_pages;
673a394b
EA		 866 }
867
280b713b
EA		 868 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
869
40123c1f
EA		 870 mutex_lock(&dev->struct_mutex);
871
07f73f69
CW		 872 ret = i915_gem_object_get_pages_or_evict(obj);
873 if (ret)
40123c1f
EA		 874 goto fail_unlock;
875
876 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
877 if (ret != 0)
878 goto fail_put_pages;
879
23010e43 880 obj_priv = to_intel_bo(obj);
673a394b 881 offset = args->offset;
40123c1f 882 obj_priv->dirty = 1;
673a394b 883
40123c1f
EA		 884 while (remain > 0) {
885 /* Operation in this page
886 *
887 * shmem_page_index = page number within shmem file
888 * shmem_page_offset = offset within page in shmem file
889 * data_page_index = page number in get_user_pages return
890 * data_page_offset = offset with data_page_index page.
891 * page_length = bytes to copy for this page
892 */
893 shmem_page_index = offset / PAGE_SIZE;
894 shmem_page_offset = offset & ~PAGE_MASK;
895 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
896 data_page_offset = data_ptr & ~PAGE_MASK;
897
898 page_length = remain;
899 if ((shmem_page_offset + page_length) > PAGE_SIZE)
900 page_length = PAGE_SIZE - shmem_page_offset;
901 if ((data_page_offset + page_length) > PAGE_SIZE)
902 page_length = PAGE_SIZE - data_page_offset;
903
280b713b
EA		 904 if (do_bit17_swizzling) {
905 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
906 shmem_page_offset,
907 user_pages[data_page_index],
908 data_page_offset,
909 page_length,
910 0);
911 } else {
912 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
913 shmem_page_offset,
914 user_pages[data_page_index],
915 data_page_offset,
916 page_length);
917 }
40123c1f
EA		 918 if (ret)
919 goto fail_put_pages;
920
921 remain -= page_length;
922 data_ptr += page_length;
923 offset += page_length;
673a394b
EA		 924 }
925
40123c1f
EA		 926fail_put_pages:
927 i915_gem_object_put_pages(obj);
928fail_unlock:
673a394b 929 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 930fail_put_user_pages:
931 for (i = 0; i < pinned_pages; i++)
932 page_cache_release(user_pages[i]);
8e7d2b2c 933 drm_free_large(user_pages);
673a394b 934
40123c1f 935 return ret;
673a394b
EA		 936}
937
938/**
939 * Writes data to the object referenced by handle.
940 *
941 * On error, the contents of the buffer that were to be modified are undefined.
942 */
943int
944i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
945 struct drm_file *file_priv)
946{
947 struct drm_i915_gem_pwrite *args = data;
948 struct drm_gem_object *obj;
949 struct drm_i915_gem_object *obj_priv;
950 int ret = 0;
951
952 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
953 if (obj == NULL)
954 return -EBADF;
23010e43 955 obj_priv = to_intel_bo(obj);
673a394b
EA		 956
957 /* Bounds check destination.
958 *
959 * XXX: This could use review for overflow issues...
960 */
961 if (args->offset > obj->size || args->size > obj->size ||
962 args->offset + args->size > obj->size) {
bc9025bd 963 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 964 return -EINVAL;
965 }
966
967 /* We can only do the GTT pwrite on untiled buffers, as otherwise
968 * it would end up going through the fenced access, and we'll get
969 * different detiling behavior between reading and writing.
970 * pread/pwrite currently are reading and writing from the CPU
971 * perspective, requiring manual detiling by the client.
972 */
71acb5eb
DA		 973 if (obj_priv->phys_obj)
974 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
975 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
3de09aa3
EA		 976 dev->gtt_total != 0) {
977 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
978 if (ret == -EFAULT) {
979 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
980 file_priv);
981 }
280b713b
EA		 982 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
983 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 984 } else {
985 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
986 if (ret == -EFAULT) {
987 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
988 file_priv);
989 }
990 }
673a394b
EA		 991
992#if WATCH_PWRITE
993 if (ret)
994 DRM_INFO("pwrite failed %d\n", ret);
995#endif
996
bc9025bd 997 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 998
999 return ret;
1000}
1001
1002/**
2ef7eeaa
EA		 1003 * Called when user space prepares to use an object with the CPU, either
1004 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1005 */
1006int
1007i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv)
1009{
a09ba7fa 1010 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1011 struct drm_i915_gem_set_domain *args = data;
1012 struct drm_gem_object *obj;
652c393a 1013 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1014 uint32_t read_domains = args->read_domains;
1015 uint32_t write_domain = args->write_domain;
673a394b
EA		 1016 int ret;
1017
1018 if (!(dev->driver->driver_features & DRIVER_GEM))
1019 return -ENODEV;
1020
2ef7eeaa 1021 /* Only handle setting domains to types used by the CPU. */
21d509e3 1022 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1023 return -EINVAL;
1024
21d509e3 1025 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1026 return -EINVAL;
1027
1028 /* Having something in the write domain implies it's in the read
1029 * domain, and only that read domain. Enforce that in the request.
1030 */
1031 if (write_domain != 0 && read_domains != write_domain)
1032 return -EINVAL;
1033
673a394b
EA		 1034 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1035 if (obj == NULL)
1036 return -EBADF;
23010e43 1037 obj_priv = to_intel_bo(obj);
673a394b
EA		 1038
1039 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1040
1041 intel_mark_busy(dev, obj);
1042
673a394b 1043#if WATCH_BUF
cfd43c02 1044 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1045 obj, obj->size, read_domains, write_domain);
673a394b 1046#endif
2ef7eeaa
EA		 1047 if (read_domains & I915_GEM_DOMAIN_GTT) {
1048 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1049
a09ba7fa
EA		 1050 /* Update the LRU on the fence for the CPU access that's
1051 * about to occur.
1052 */
1053 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1054 list_move_tail(&obj_priv->fence_list,
1055 &dev_priv->mm.fence_list);
1056 }
1057
02354392
EA		 1058 /* Silently promote "you're not bound, there was nothing to do"
1059 * to success, since the client was just asking us to
1060 * make sure everything was done.
1061 */
1062 if (ret == -EINVAL)
1063 ret = 0;
2ef7eeaa 1064 } else {
e47c68e9 1065 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1066 }
1067
673a394b
EA		 1068 drm_gem_object_unreference(obj);
1069 mutex_unlock(&dev->struct_mutex);
1070 return ret;
1071}
1072
1073/**
1074 * Called when user space has done writes to this buffer
1075 */
1076int
1077i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv)
1079{
1080 struct drm_i915_gem_sw_finish *args = data;
1081 struct drm_gem_object *obj;
1082 struct drm_i915_gem_object *obj_priv;
1083 int ret = 0;
1084
1085 if (!(dev->driver->driver_features & DRIVER_GEM))
1086 return -ENODEV;
1087
1088 mutex_lock(&dev->struct_mutex);
1089 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1090 if (obj == NULL) {
1091 mutex_unlock(&dev->struct_mutex);
1092 return -EBADF;
1093 }
1094
1095#if WATCH_BUF
cfd43c02 1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1097 __func__, args->handle, obj, obj->size);
1098#endif
23010e43 1099 obj_priv = to_intel_bo(obj);
673a394b
EA		 1100
1101 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1102 if (obj_priv->pin_count)
1103 i915_gem_object_flush_cpu_write_domain(obj);
1104
673a394b
EA		 1105 drm_gem_object_unreference(obj);
1106 mutex_unlock(&dev->struct_mutex);
1107 return ret;
1108}
1109
1110/**
1111 * Maps the contents of an object, returning the address it is mapped
1112 * into.
1113 *
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1116 */
1117int
1118i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv)
1120{
1121 struct drm_i915_gem_mmap *args = data;
1122 struct drm_gem_object *obj;
1123 loff_t offset;
1124 unsigned long addr;
1125
1126 if (!(dev->driver->driver_features & DRIVER_GEM))
1127 return -ENODEV;
1128
1129 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1130 if (obj == NULL)
1131 return -EBADF;
1132
1133 offset = args->offset;
1134
1135 down_write(&current->mm->mmap_sem);
1136 addr = do_mmap(obj->filp, 0, args->size,
1137 PROT_READ | PROT_WRITE, MAP_SHARED,
1138 args->offset);
1139 up_write(&current->mm->mmap_sem);
bc9025bd 1140 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1141 if (IS_ERR((void *)addr))
1142 return addr;
1143
1144 args->addr_ptr = (uint64_t) addr;
1145
1146 return 0;
1147}
1148
de151cf6
JB		 1149/**
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1152 * vmf: fault info
1153 *
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1159 *
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1163 * left.
1164 */
1165int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1166{
1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev;
1169 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1171 pgoff_t page_offset;
1172 unsigned long pfn;
1173 int ret = 0;
0f973f27 1174 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1175
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1178 PAGE_SHIFT;
1179
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev->struct_mutex);
1182 if (!obj_priv->gtt_space) {
e67b8ce1 1183 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1184 if (ret)
1185 goto unlock;
07f4f3e8 1186
14b60391 1187 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1188
1189 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1190 if (ret)
1191 goto unlock;
de151cf6
JB		 1192 }
1193
1194 /* Need a new fence register? */
a09ba7fa 1195 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1196 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1197 if (ret)
1198 goto unlock;
d9ddcb96 1199 }
de151cf6
JB		 1200
1201 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1202 page_offset;
1203
1204 /* Finally, remap it using the new GTT offset */
1205 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1206unlock:
de151cf6
JB		 1207 mutex_unlock(&dev->struct_mutex);
1208
1209 switch (ret) {
c715089f
CW		 1210 case 0:
1211 case -ERESTARTSYS:
1212 return VM_FAULT_NOPAGE;
de151cf6
JB		 1213 case -ENOMEM:
1214 case -EAGAIN:
1215 return VM_FAULT_OOM;
de151cf6 1216 default:
c715089f 1217 return VM_FAULT_SIGBUS;
de151cf6
JB		 1218 }
1219}
1220
1221/**
1222 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1223 * @obj: obj in question
1224 *
1225 * GEM memory mapping works by handing back to userspace a fake mmap offset
1226 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1227 * up the object based on the offset and sets up the various memory mapping
1228 * structures.
1229 *
1230 * This routine allocates and attaches a fake offset for @obj.
1231 */
1232static int
1233i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1234{
1235 struct drm_device *dev = obj->dev;
1236 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1237 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1238 struct drm_map_list *list;
f77d390c 1239 struct drm_local_map *map;
de151cf6
JB		 1240 int ret = 0;
1241
1242 /* Set the object up for mmap'ing */
1243 list = &obj->map_list;
9a298b2a 1244 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1245 if (!list->map)
1246 return -ENOMEM;
1247
1248 map = list->map;
1249 map->type = _DRM_GEM;
1250 map->size = obj->size;
1251 map->handle = obj;
1252
1253 /* Get a DRM GEM mmap offset allocated... */
1254 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1255 obj->size / PAGE_SIZE, 0, 0);
1256 if (!list->file_offset_node) {
1257 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1258 ret = -ENOMEM;
1259 goto out_free_list;
1260 }
1261
1262 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1263 obj->size / PAGE_SIZE, 0);
1264 if (!list->file_offset_node) {
1265 ret = -ENOMEM;
1266 goto out_free_list;
1267 }
1268
1269 list->hash.key = list->file_offset_node->start;
1270 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1271 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1272 ret = -ENOMEM;
de151cf6
JB		 1273 goto out_free_mm;
1274 }
1275
1276 /* By now we should be all set, any drm_mmap request on the offset
1277 * below will get to our mmap & fault handler */
1278 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1279
1280 return 0;
1281
1282out_free_mm:
1283 drm_mm_put_block(list->file_offset_node);
1284out_free_list:
9a298b2a 1285 kfree(list->map);
de151cf6
JB		 1286
1287 return ret;
1288}
1289
901782b2
CW		 1290/**
1291 * i915_gem_release_mmap - remove physical page mappings
1292 * @obj: obj in question
1293 *
af901ca1 1294 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1295 * relinquish ownership of the pages back to the system.
1296 *
1297 * It is vital that we remove the page mapping if we have mapped a tiled
1298 * object through the GTT and then lose the fence register due to
1299 * resource pressure. Similarly if the object has been moved out of the
1300 * aperture, than pages mapped into userspace must be revoked. Removing the
1301 * mapping will then trigger a page fault on the next user access, allowing
1302 * fixup by i915_gem_fault().
1303 */
d05ca301 1304void
901782b2
CW		 1305i915_gem_release_mmap(struct drm_gem_object *obj)
1306{
1307 struct drm_device *dev = obj->dev;
23010e43 1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1309
1310 if (dev->dev_mapping)
1311 unmap_mapping_range(dev->dev_mapping,
1312 obj_priv->mmap_offset, obj->size, 1);
1313}
1314
ab00b3e5
JB		 1315static void
1316i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1317{
1318 struct drm_device *dev = obj->dev;
23010e43 1319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1320 struct drm_gem_mm *mm = dev->mm_private;
1321 struct drm_map_list *list;
1322
1323 list = &obj->map_list;
1324 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1325
1326 if (list->file_offset_node) {
1327 drm_mm_put_block(list->file_offset_node);
1328 list->file_offset_node = NULL;
1329 }
1330
1331 if (list->map) {
9a298b2a 1332 kfree(list->map);
ab00b3e5
JB		 1333 list->map = NULL;
1334 }
1335
1336 obj_priv->mmap_offset = 0;
1337}
1338
de151cf6
JB		 1339/**
1340 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1341 * @obj: object to check
1342 *
1343 * Return the required GTT alignment for an object, taking into account
1344 * potential fence register mapping if needed.
1345 */
1346static uint32_t
1347i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1348{
1349 struct drm_device *dev = obj->dev;
23010e43 1350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1351 int start, i;
1352
1353 /*
1354 * Minimum alignment is 4k (GTT page size), but might be greater
1355 * if a fence register is needed for the object.
1356 */
1357 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1358 return 4096;
1359
1360 /*
1361 * Previous chips need to be aligned to the size of the smallest
1362 * fence register that can contain the object.
1363 */
1364 if (IS_I9XX(dev))
1365 start = 1024*1024;
1366 else
1367 start = 512*1024;
1368
1369 for (i = start; i < obj->size; i <<= 1)
1370 ;
1371
1372 return i;
1373}
1374
1375/**
1376 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1377 * @dev: DRM device
1378 * @data: GTT mapping ioctl data
1379 * @file_priv: GEM object info
1380 *
1381 * Simply returns the fake offset to userspace so it can mmap it.
1382 * The mmap call will end up in drm_gem_mmap(), which will set things
1383 * up so we can get faults in the handler above.
1384 *
1385 * The fault handler will take care of binding the object into the GTT
1386 * (since it may have been evicted to make room for something), allocating
1387 * a fence register, and mapping the appropriate aperture address into
1388 * userspace.
1389 */
1390int
1391i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *file_priv)
1393{
1394 struct drm_i915_gem_mmap_gtt *args = data;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_gem_object *obj;
1397 struct drm_i915_gem_object *obj_priv;
1398 int ret;
1399
1400 if (!(dev->driver->driver_features & DRIVER_GEM))
1401 return -ENODEV;
1402
1403 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1404 if (obj == NULL)
1405 return -EBADF;
1406
1407 mutex_lock(&dev->struct_mutex);
1408
23010e43 1409 obj_priv = to_intel_bo(obj);
de151cf6 1410
ab18282d
CW		 1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1415 return -EINVAL;
1416 }
1417
1418
de151cf6
JB		 1419 if (!obj_priv->mmap_offset) {
1420 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1421 if (ret) {
1422 drm_gem_object_unreference(obj);
1423 mutex_unlock(&dev->struct_mutex);
de151cf6 1424 return ret;
13af1062 1425 }
de151cf6
JB		 1426 }
1427
1428 args->offset = obj_priv->mmap_offset;
1429
de151cf6
JB		 1430 /*
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1433 */
1434 if (!obj_priv->agp_mem) {
e67b8ce1 1435 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1436 if (ret) {
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1439 return ret;
1440 }
14b60391 1441 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1442 }
1443
1444 drm_gem_object_unreference(obj);
1445 mutex_unlock(&dev->struct_mutex);
1446
1447 return 0;
1448}
1449
6911a9b8 1450void
856fa198 1451i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1452{
23010e43 1453 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1454 int page_count = obj->size / PAGE_SIZE;
1455 int i;
1456
856fa198 1457 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1458 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1459
856fa198
EA		 1460 if (--obj_priv->pages_refcount != 0)
1461 return;
673a394b 1462
280b713b
EA		 1463 if (obj_priv->tiling_mode != I915_TILING_NONE)
1464 i915_gem_object_save_bit_17_swizzle(obj);
1465
3ef94daa 1466 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1467 obj_priv->dirty = 0;
3ef94daa
CW		 1468
1469 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1470 if (obj_priv->dirty)
1471 set_page_dirty(obj_priv->pages[i]);
1472
1473 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1474 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1475
1476 page_cache_release(obj_priv->pages[i]);
1477 }
673a394b
EA		 1478 obj_priv->dirty = 0;
1479
8e7d2b2c 1480 drm_free_large(obj_priv->pages);
856fa198 1481 obj_priv->pages = NULL;
673a394b
EA		 1482}
1483
1484static void
ce44b0ea 1485i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
673a394b
EA		 1486{
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1490
1491 /* Add a reference if we're newly entering the active list. */
1492 if (!obj_priv->active) {
1493 drm_gem_object_reference(obj);
1494 obj_priv->active = 1;
1495 }
1496 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1497 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1498 list_move_tail(&obj_priv->list,
1499 &dev_priv->mm.active_list);
5e118f41 1500 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1501 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1502}
1503
ce44b0ea
EA		 1504static void
1505i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1506{
1507 struct drm_device *dev = obj->dev;
1508 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1510
1511 BUG_ON(!obj_priv->active);
1512 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1513 obj_priv->last_rendering_seqno = 0;
1514}
673a394b 1515
963b4836
CW		 1516/* Immediately discard the backing storage */
1517static void
1518i915_gem_object_truncate(struct drm_gem_object *obj)
1519{
23010e43 1520 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1521 struct inode *inode;
963b4836 1522
bb6baf76
CW		 1523 inode = obj->filp->f_path.dentry->d_inode;
1524 if (inode->i_op->truncate)
1525 inode->i_op->truncate (inode);
1526
1527 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1528}
1529
1530static inline int
1531i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1532{
1533 return obj_priv->madv == I915_MADV_DONTNEED;
1534}
1535
673a394b
EA		 1536static void
1537i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1538{
1539 struct drm_device *dev = obj->dev;
1540 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1541 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1542
1543 i915_verify_inactive(dev, __FILE__, __LINE__);
1544 if (obj_priv->pin_count != 0)
1545 list_del_init(&obj_priv->list);
1546 else
1547 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1548
99fcb766
DV		 1549 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1550
ce44b0ea 1551 obj_priv->last_rendering_seqno = 0;
673a394b
EA		 1552 if (obj_priv->active) {
1553 obj_priv->active = 0;
1554 drm_gem_object_unreference(obj);
1555 }
1556 i915_verify_inactive(dev, __FILE__, __LINE__);
1557}
1558
63560396
DV		 1559static void
1560i915_gem_process_flushing_list(struct drm_device *dev,
1561 uint32_t flush_domains, uint32_t seqno)
1562{
1563 drm_i915_private_t *dev_priv = dev->dev_private;
1564 struct drm_i915_gem_object *obj_priv, *next;
1565
1566 list_for_each_entry_safe(obj_priv, next,
1567 &dev_priv->mm.gpu_write_list,
1568 gpu_write_list) {
1569 struct drm_gem_object *obj = obj_priv->obj;
1570
1571 if ((obj->write_domain & flush_domains) ==
1572 obj->write_domain) {
1573 uint32_t old_write_domain = obj->write_domain;
1574
1575 obj->write_domain = 0;
1576 list_del_init(&obj_priv->gpu_write_list);
1577 i915_gem_object_move_to_active(obj, seqno);
1578
1579 /* update the fence lru list */
1580 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1581 list_move_tail(&obj_priv->fence_list,
1582 &dev_priv->mm.fence_list);
1583
1584 trace_i915_gem_object_change_domain(obj,
1585 obj->read_domains,
1586 old_write_domain);
1587 }
1588 }
1589}
1590
673a394b
EA		 1591/**
1592 * Creates a new sequence number, emitting a write of it to the status page
1593 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1594 *
1595 * Must be called with struct_lock held.
1596 *
1597 * Returned sequence numbers are nonzero on success.
1598 */
5a5a0c64 1599uint32_t
b962442e
EA		 1600i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1601 uint32_t flush_domains)
673a394b
EA		 1602{
1603 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1604 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1605 struct drm_i915_gem_request *request;
1606 uint32_t seqno;
1607 int was_empty;
1608 RING_LOCALS;
1609
b962442e
EA		 1610 if (file_priv != NULL)
1611 i915_file_priv = file_priv->driver_priv;
1612
9a298b2a 1613 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1614 if (request == NULL)
1615 return 0;
1616
1617 /* Grab the seqno we're going to make this request be, and bump the
1618 * next (skipping 0 so it can be the reserved no-seqno value).
1619 */
1620 seqno = dev_priv->mm.next_gem_seqno;
1621 dev_priv->mm.next_gem_seqno++;
1622 if (dev_priv->mm.next_gem_seqno == 0)
1623 dev_priv->mm.next_gem_seqno++;
1624
1625 BEGIN_LP_RING(4);
1626 OUT_RING(MI_STORE_DWORD_INDEX);
1627 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1628 OUT_RING(seqno);
1629
1630 OUT_RING(MI_USER_INTERRUPT);
1631 ADVANCE_LP_RING();
1632
44d98a61 1633 DRM_DEBUG_DRIVER("%d\n", seqno);
673a394b
EA		 1634
1635 request->seqno = seqno;
1636 request->emitted_jiffies = jiffies;
673a394b
EA		 1637 was_empty = list_empty(&dev_priv->mm.request_list);
1638 list_add_tail(&request->list, &dev_priv->mm.request_list);
b962442e
EA		 1639 if (i915_file_priv) {
1640 list_add_tail(&request->client_list,
1641 &i915_file_priv->mm.request_list);
1642 } else {
1643 INIT_LIST_HEAD(&request->client_list);
1644 }
673a394b 1645
ce44b0ea
EA		 1646 /* Associate any objects on the flushing list matching the write
1647 * domain we're flushing with our flush.
1648 */
63560396
DV		 1649 if (flush_domains != 0)
1650 i915_gem_process_flushing_list(dev, flush_domains, seqno);
ce44b0ea 1651
f65d9421
BG		 1652 if (!dev_priv->mm.suspended) {
1653 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1654 if (was_empty)
1655 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1656 }
673a394b
EA		 1657 return seqno;
1658}
1659
1660/**
1661 * Command execution barrier
1662 *
1663 * Ensures that all commands in the ring are finished
1664 * before signalling the CPU
1665 */
3043c60c 1666static uint32_t
673a394b
EA		 1667i915_retire_commands(struct drm_device *dev)
1668{
1669 drm_i915_private_t *dev_priv = dev->dev_private;
1670 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1671 uint32_t flush_domains = 0;
1672 RING_LOCALS;
1673
1674 /* The sampler always gets flushed on i965 (sigh) */
1675 if (IS_I965G(dev))
1676 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1677 BEGIN_LP_RING(2);
1678 OUT_RING(cmd);
1679 OUT_RING(0); /* noop */
1680 ADVANCE_LP_RING();
1681 return flush_domains;
1682}
1683
1684/**
1685 * Moves buffers associated only with the given active seqno from the active
1686 * to inactive list, potentially freeing them.
1687 */
1688static void
1689i915_gem_retire_request(struct drm_device *dev,
1690 struct drm_i915_gem_request *request)
1691{
1692 drm_i915_private_t *dev_priv = dev->dev_private;
1693
1c5d22f7
CW		 1694 trace_i915_gem_request_retire(dev, request->seqno);
1695
673a394b
EA		 1696 /* Move any buffers on the active list that are no longer referenced
1697 * by the ringbuffer to the flushing/inactive lists as appropriate.
1698 */
5e118f41 1699 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1700 while (!list_empty(&dev_priv->mm.active_list)) {
1701 struct drm_gem_object *obj;
1702 struct drm_i915_gem_object *obj_priv;
1703
1704 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1705 struct drm_i915_gem_object,
1706 list);
1707 obj = obj_priv->obj;
1708
1709 /* If the seqno being retired doesn't match the oldest in the
1710 * list, then the oldest in the list must still be newer than
1711 * this seqno.
1712 */
1713 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1714 goto out;
de151cf6 1715
673a394b
EA		 1716#if WATCH_LRU
1717 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1718 __func__, request->seqno, obj);
1719#endif
1720
ce44b0ea
EA		 1721 if (obj->write_domain != 0)
1722 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1723 else {
1724 /* Take a reference on the object so it won't be
1725 * freed while the spinlock is held. The list
1726 * protection for this spinlock is safe when breaking
1727 * the lock like this since the next thing we do
1728 * is just get the head of the list again.
1729 */
1730 drm_gem_object_reference(obj);
673a394b 1731 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1732 spin_unlock(&dev_priv->mm.active_list_lock);
1733 drm_gem_object_unreference(obj);
1734 spin_lock(&dev_priv->mm.active_list_lock);
1735 }
673a394b 1736 }
5e118f41
CW		 1737out:
1738 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1739}
1740
1741/**
1742 * Returns true if seq1 is later than seq2.
1743 */
22be1724 1744bool
673a394b
EA		 1745i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1746{
1747 return (int32_t)(seq1 - seq2) >= 0;
1748}
1749
1750uint32_t
1751i915_get_gem_seqno(struct drm_device *dev)
1752{
1753 drm_i915_private_t *dev_priv = dev->dev_private;
1754
1755 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1756}
1757
1758/**
1759 * This function clears the request list as sequence numbers are passed.
1760 */
1761void
1762i915_gem_retire_requests(struct drm_device *dev)
1763{
1764 drm_i915_private_t *dev_priv = dev->dev_private;
1765 uint32_t seqno;
1766
9d34e5db 1767 if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list))
6c0594a3
KW		 1768 return;
1769
673a394b
EA		 1770 seqno = i915_get_gem_seqno(dev);
1771
1772 while (!list_empty(&dev_priv->mm.request_list)) {
1773 struct drm_i915_gem_request *request;
1774 uint32_t retiring_seqno;
1775
1776 request = list_first_entry(&dev_priv->mm.request_list,
1777 struct drm_i915_gem_request,
1778 list);
1779 retiring_seqno = request->seqno;
1780
1781 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1782 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1783 i915_gem_retire_request(dev, request);
1784
1785 list_del(&request->list);
b962442e 1786 list_del(&request->client_list);
9a298b2a 1787 kfree(request);
673a394b
EA		 1788 } else
1789 break;
1790 }
9d34e5db
CW		 1791
1792 if (unlikely (dev_priv->trace_irq_seqno &&
1793 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1794 i915_user_irq_put(dev);
1795 dev_priv->trace_irq_seqno = 0;
1796 }
673a394b
EA		 1797}
1798
1799void
1800i915_gem_retire_work_handler(struct work_struct *work)
1801{
1802 drm_i915_private_t *dev_priv;
1803 struct drm_device *dev;
1804
1805 dev_priv = container_of(work, drm_i915_private_t,
1806 mm.retire_work.work);
1807 dev = dev_priv->dev;
1808
1809 mutex_lock(&dev->struct_mutex);
1810 i915_gem_retire_requests(dev);
6dbe2772
KP		 1811 if (!dev_priv->mm.suspended &&
1812 !list_empty(&dev_priv->mm.request_list))
9c9fe1f8 1813 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1814 mutex_unlock(&dev->struct_mutex);
1815}
1816
5a5a0c64 1817int
48764bf4 1818i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
673a394b
EA		 1819{
1820 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1821 u32 ier;
673a394b
EA		 1822 int ret = 0;
1823
1824 BUG_ON(seqno == 0);
1825
ba1234d1 1826 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1827 return -EIO;
1828
673a394b 1829 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
bad720ff 1830 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1831 ier = I915_READ(DEIER) | I915_READ(GTIER);
1832 else
1833 ier = I915_READ(IER);
802c7eb6
JB		 1834 if (!ier) {
1835 DRM_ERROR("something (likely vbetool) disabled "
1836 "interrupts, re-enabling\n");
1837 i915_driver_irq_preinstall(dev);
1838 i915_driver_irq_postinstall(dev);
1839 }
1840
1c5d22f7
CW		 1841 trace_i915_gem_request_wait_begin(dev, seqno);
1842
673a394b
EA		 1843 dev_priv->mm.waiting_gem_seqno = seqno;
1844 i915_user_irq_get(dev);
48764bf4
DV		 1845 if (interruptible)
1846 ret = wait_event_interruptible(dev_priv->irq_queue,
1847 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1848 atomic_read(&dev_priv->mm.wedged));
1849 else
1850 wait_event(dev_priv->irq_queue,
1851 i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
1852 atomic_read(&dev_priv->mm.wedged));
1853
673a394b
EA		 1854 i915_user_irq_put(dev);
1855 dev_priv->mm.waiting_gem_seqno = 0;
1c5d22f7
CW		 1856
1857 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1858 }
ba1234d1 1859 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1860 ret = -EIO;
1861
1862 if (ret && ret != -ERESTARTSYS)
1863 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1864 __func__, ret, seqno, i915_get_gem_seqno(dev));
1865
1866 /* Directly dispatch request retiring. While we have the work queue
1867 * to handle this, the waiter on a request often wants an associated
1868 * buffer to have made it to the inactive list, and we would need
1869 * a separate wait queue to handle that.
1870 */
1871 if (ret == 0)
1872 i915_gem_retire_requests(dev);
1873
1874 return ret;
1875}
1876
48764bf4
DV		 1877/**
1878 * Waits for a sequence number to be signaled, and cleans up the
1879 * request and object lists appropriately for that event.
1880 */
1881static int
1882i915_wait_request(struct drm_device *dev, uint32_t seqno)
1883{
1884 return i915_do_wait_request(dev, seqno, 1);
1885}
1886
673a394b
EA		 1887static void
1888i915_gem_flush(struct drm_device *dev,
1889 uint32_t invalidate_domains,
1890 uint32_t flush_domains)
1891{
1892 drm_i915_private_t *dev_priv = dev->dev_private;
1893 uint32_t cmd;
1894 RING_LOCALS;
1895
1896#if WATCH_EXEC
1897 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1898 invalidate_domains, flush_domains);
1899#endif
1c5d22f7
CW		 1900 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1901 invalidate_domains, flush_domains);
673a394b
EA		 1902
1903 if (flush_domains & I915_GEM_DOMAIN_CPU)
1904 drm_agp_chipset_flush(dev);
1905
21d509e3 1906 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
673a394b
EA		 1907 /*
1908 * read/write caches:
1909 *
1910 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1911 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1912 * also flushed at 2d versus 3d pipeline switches.
1913 *
1914 * read-only caches:
1915 *
1916 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1917 * MI_READ_FLUSH is set, and is always flushed on 965.
1918 *
1919 * I915_GEM_DOMAIN_COMMAND may not exist?
1920 *
1921 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1922 * invalidated when MI_EXE_FLUSH is set.
1923 *
1924 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1925 * invalidated with every MI_FLUSH.
1926 *
1927 * TLBs:
1928 *
1929 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1930 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1931 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1932 * are flushed at any MI_FLUSH.
1933 */
1934
1935 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1936 if ((invalidate_domains|flush_domains) &
1937 I915_GEM_DOMAIN_RENDER)
1938 cmd &= ~MI_NO_WRITE_FLUSH;
1939 if (!IS_I965G(dev)) {
1940 /*
1941 * On the 965, the sampler cache always gets flushed
1942 * and this bit is reserved.
1943 */
1944 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1945 cmd |= MI_READ_FLUSH;
1946 }
1947 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1948 cmd |= MI_EXE_FLUSH;
1949
1950#if WATCH_EXEC
1951 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1952#endif
1953 BEGIN_LP_RING(2);
1954 OUT_RING(cmd);
48764bf4 1955 OUT_RING(MI_NOOP);
673a394b
EA		 1956 ADVANCE_LP_RING();
1957 }
1958}
1959
1960/**
1961 * Ensures that all rendering to the object has completed and the object is
1962 * safe to unbind from the GTT or access from the CPU.
1963 */
1964static int
1965i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1966{
1967 struct drm_device *dev = obj->dev;
23010e43 1968 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1969 int ret;
1970
e47c68e9
EA		 1971 /* This function only exists to support waiting for existing rendering,
1972 * not for emitting required flushes.
673a394b 1973 */
e47c68e9 1974 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1975
1976 /* If there is rendering queued on the buffer being evicted, wait for
1977 * it.
1978 */
1979 if (obj_priv->active) {
1980#if WATCH_BUF
1981 DRM_INFO("%s: object %p wait for seqno %08x\n",
1982 __func__, obj, obj_priv->last_rendering_seqno);
1983#endif
1984 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1985 if (ret != 0)
1986 return ret;
1987 }
1988
1989 return 0;
1990}
1991
1992/**
1993 * Unbinds an object from the GTT aperture.
1994 */
0f973f27 1995int
673a394b
EA		 1996i915_gem_object_unbind(struct drm_gem_object *obj)
1997{
1998 struct drm_device *dev = obj->dev;
4a87b8ca 1999 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2000 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2001 int ret = 0;
2002
2003#if WATCH_BUF
2004 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
2005 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2006#endif
2007 if (obj_priv->gtt_space == NULL)
2008 return 0;
2009
2010 if (obj_priv->pin_count != 0) {
2011 DRM_ERROR("Attempting to unbind pinned buffer\n");
2012 return -EINVAL;
2013 }
2014
5323fd04
EA		 2015 /* blow away mappings if mapped through GTT */
2016 i915_gem_release_mmap(obj);
2017
673a394b
EA		 2018 /* Move the object to the CPU domain to ensure that
2019 * any possible CPU writes while it's not in the GTT
2020 * are flushed when we go to remap it. This will
2021 * also ensure that all pending GPU writes are finished
2022 * before we unbind.
2023 */
e47c68e9 2024 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 2025 if (ret) {
e47c68e9
EA		 2026 if (ret != -ERESTARTSYS)
2027 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 2028 return ret;
2029 }
2030
5323fd04
EA		 2031 BUG_ON(obj_priv->active);
2032
96b47b65
DV		 2033 /* release the fence reg _after_ flushing */
2034 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2035 i915_gem_clear_fence_reg(obj);
2036
673a394b
EA		 2037 if (obj_priv->agp_mem != NULL) {
2038 drm_unbind_agp(obj_priv->agp_mem);
2039 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2040 obj_priv->agp_mem = NULL;
2041 }
2042
856fa198 2043 i915_gem_object_put_pages(obj);
a32808c0 2044 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 2045
2046 if (obj_priv->gtt_space) {
2047 atomic_dec(&dev->gtt_count);
2048 atomic_sub(obj->size, &dev->gtt_memory);
2049
2050 drm_mm_put_block(obj_priv->gtt_space);
2051 obj_priv->gtt_space = NULL;
2052 }
2053
2054 /* Remove ourselves from the LRU list if present. */
4a87b8ca 2055 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 2056 if (!list_empty(&obj_priv->list))
2057 list_del_init(&obj_priv->list);
4a87b8ca 2058 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 2059
963b4836
CW		 2060 if (i915_gem_object_is_purgeable(obj_priv))
2061 i915_gem_object_truncate(obj);
2062
1c5d22f7
CW		 2063 trace_i915_gem_object_unbind(obj);
2064
673a394b
EA		 2065 return 0;
2066}
2067
07f73f69
CW		 2068static struct drm_gem_object *
2069i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2070{
2071 drm_i915_private_t *dev_priv = dev->dev_private;
2072 struct drm_i915_gem_object *obj_priv;
2073 struct drm_gem_object *best = NULL;
2074 struct drm_gem_object *first = NULL;
2075
2076 /* Try to find the smallest clean object */
2077 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2078 struct drm_gem_object *obj = obj_priv->obj;
2079 if (obj->size >= min_size) {
963b4836
CW		 2080 if ((!obj_priv->dirty ||
2081 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2082 (!best || obj->size < best->size)) {
2083 best = obj;
2084 if (best->size == min_size)
2085 return best;
2086 }
2087 if (!first)
2088 first = obj;
2089 }
2090 }
2091
2092 return best ? best : first;
2093}
2094
4df2faf4
DV		 2095static int
2096i915_gpu_idle(struct drm_device *dev)
2097{
2098 drm_i915_private_t *dev_priv = dev->dev_private;
2099 bool lists_empty;
2100 uint32_t seqno;
2101
2102 spin_lock(&dev_priv->mm.active_list_lock);
2103 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
2104 list_empty(&dev_priv->mm.active_list);
2105 spin_unlock(&dev_priv->mm.active_list_lock);
2106
2107 if (lists_empty)
2108 return 0;
2109
2110 /* Flush everything onto the inactive list. */
2111 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2112 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2113 if (seqno == 0)
2114 return -ENOMEM;
2115
2116 return i915_wait_request(dev, seqno);
2117}
2118
673a394b 2119static int
07f73f69
CW		 2120i915_gem_evict_everything(struct drm_device *dev)
2121{
2122 drm_i915_private_t *dev_priv = dev->dev_private;
07f73f69
CW		 2123 int ret;
2124 bool lists_empty;
2125
07f73f69
CW		 2126 spin_lock(&dev_priv->mm.active_list_lock);
2127 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2128 list_empty(&dev_priv->mm.flushing_list) &&
2129 list_empty(&dev_priv->mm.active_list));
2130 spin_unlock(&dev_priv->mm.active_list_lock);
2131
9731129c 2132 if (lists_empty)
07f73f69 2133 return -ENOSPC;
07f73f69
CW		 2134
2135 /* Flush everything (on to the inactive lists) and evict */
4df2faf4 2136 ret = i915_gpu_idle(dev);
07f73f69
CW		 2137 if (ret)
2138 return ret;
2139
99fcb766
DV		 2140 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2141
ab5ee576 2142 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2143 if (ret)
2144 return ret;
2145
2146 spin_lock(&dev_priv->mm.active_list_lock);
2147 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2148 list_empty(&dev_priv->mm.flushing_list) &&
2149 list_empty(&dev_priv->mm.active_list));
2150 spin_unlock(&dev_priv->mm.active_list_lock);
2151 BUG_ON(!lists_empty);
2152
2153 return 0;
2154}
2155
673a394b 2156static int
07f73f69 2157i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2158{
2159 drm_i915_private_t *dev_priv = dev->dev_private;
2160 struct drm_gem_object *obj;
07f73f69 2161 int ret;
673a394b
EA		 2162
2163 for (;;) {
07f73f69
CW		 2164 i915_gem_retire_requests(dev);
2165
673a394b
EA		 2166 /* If there's an inactive buffer available now, grab it
2167 * and be done.
2168 */
07f73f69
CW		 2169 obj = i915_gem_find_inactive_object(dev, min_size);
2170 if (obj) {
2171 struct drm_i915_gem_object *obj_priv;
2172
673a394b
EA		 2173#if WATCH_LRU
2174 DRM_INFO("%s: evicting %p\n", __func__, obj);
2175#endif
23010e43 2176 obj_priv = to_intel_bo(obj);
07f73f69 2177 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2178 BUG_ON(obj_priv->active);
2179
2180 /* Wait on the rendering and unbind the buffer. */
07f73f69 2181 return i915_gem_object_unbind(obj);
673a394b
EA		 2182 }
2183
2184 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2185 * things, wait for the next to finish and hopefully leave us
2186 * a buffer to evict.
673a394b
EA		 2187 */
2188 if (!list_empty(&dev_priv->mm.request_list)) {
2189 struct drm_i915_gem_request *request;
2190
2191 request = list_first_entry(&dev_priv->mm.request_list,
2192 struct drm_i915_gem_request,
2193 list);
2194
2195 ret = i915_wait_request(dev, request->seqno);
2196 if (ret)
07f73f69 2197 return ret;
673a394b 2198
07f73f69 2199 continue;
673a394b
EA		 2200 }
2201
2202 /* If we didn't have anything on the request list but there
2203 * are buffers awaiting a flush, emit one and try again.
2204 * When we wait on it, those buffers waiting for that flush
2205 * will get moved to inactive.
2206 */
2207 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2208 struct drm_i915_gem_object *obj_priv;
673a394b 2209
9a1e2582
CW		 2210 /* Find an object that we can immediately reuse */
2211 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2212 obj = obj_priv->obj;
2213 if (obj->size >= min_size)
2214 break;
673a394b 2215
9a1e2582
CW		 2216 obj = NULL;
2217 }
673a394b 2218
9a1e2582
CW		 2219 if (obj != NULL) {
2220 uint32_t seqno;
673a394b 2221
9a1e2582
CW		 2222 i915_gem_flush(dev,
2223 obj->write_domain,
2224 obj->write_domain);
2225 seqno = i915_add_request(dev, NULL, obj->write_domain);
2226 if (seqno == 0)
2227 return -ENOMEM;
9a1e2582
CW		 2228 continue;
2229 }
673a394b
EA		 2230 }
2231
07f73f69
CW		 2232 /* If we didn't do any of the above, there's no single buffer
2233 * large enough to swap out for the new one, so just evict
2234 * everything and start again. (This should be rare.)
673a394b 2235 */
9731129c 2236 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2237 return i915_gem_evict_from_inactive_list(dev);
9731129c 2238 else
07f73f69 2239 return i915_gem_evict_everything(dev);
ac94a962 2240 }
ac94a962
KP		 2241}
2242
6911a9b8 2243int
4bdadb97
CW		 2244i915_gem_object_get_pages(struct drm_gem_object *obj,
2245 gfp_t gfpmask)
673a394b 2246{
23010e43 2247 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2248 int page_count, i;
2249 struct address_space *mapping;
2250 struct inode *inode;
2251 struct page *page;
673a394b 2252
856fa198 2253 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2254 return 0;
2255
2256 /* Get the list of pages out of our struct file. They'll be pinned
2257 * at this point until we release them.
2258 */
2259 page_count = obj->size / PAGE_SIZE;
856fa198 2260 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2261 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2262 if (obj_priv->pages == NULL) {
856fa198 2263 obj_priv->pages_refcount--;
673a394b
EA		 2264 return -ENOMEM;
2265 }
2266
2267 inode = obj->filp->f_path.dentry->d_inode;
2268 mapping = inode->i_mapping;
2269 for (i = 0; i < page_count; i++) {
4bdadb97
CW		 2270 page = read_cache_page_gfp(mapping, i,
2271 mapping_gfp_mask (mapping) |
2272 __GFP_COLD |
2273 gfpmask);
1f2b1013
CW		 2274 if (IS_ERR(page))
2275 goto err_pages;
2276
856fa198 2277 obj_priv->pages[i] = page;
673a394b 2278 }
280b713b
EA		 2279
2280 if (obj_priv->tiling_mode != I915_TILING_NONE)
2281 i915_gem_object_do_bit_17_swizzle(obj);
2282
673a394b 2283 return 0;
1f2b1013
CW		 2284
2285err_pages:
2286 while (i--)
2287 page_cache_release(obj_priv->pages[i]);
2288
2289 drm_free_large(obj_priv->pages);
2290 obj_priv->pages = NULL;
2291 obj_priv->pages_refcount--;
2292 return PTR_ERR(page);
673a394b
EA		 2293}
2294
4e901fdc
EA		 2295static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2296{
2297 struct drm_gem_object *obj = reg->obj;
2298 struct drm_device *dev = obj->dev;
2299 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2300 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2301 int regnum = obj_priv->fence_reg;
2302 uint64_t val;
2303
2304 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2305 0xfffff000) << 32;
2306 val |= obj_priv->gtt_offset & 0xfffff000;
2307 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2308 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2309
2310 if (obj_priv->tiling_mode == I915_TILING_Y)
2311 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2312 val |= I965_FENCE_REG_VALID;
2313
2314 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2315}
2316
de151cf6
JB		 2317static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2318{
2319 struct drm_gem_object *obj = reg->obj;
2320 struct drm_device *dev = obj->dev;
2321 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2322 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2323 int regnum = obj_priv->fence_reg;
2324 uint64_t val;
2325
2326 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2327 0xfffff000) << 32;
2328 val |= obj_priv->gtt_offset & 0xfffff000;
2329 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2330 if (obj_priv->tiling_mode == I915_TILING_Y)
2331 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2332 val |= I965_FENCE_REG_VALID;
2333
2334 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2335}
2336
2337static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2338{
2339 struct drm_gem_object *obj = reg->obj;
2340 struct drm_device *dev = obj->dev;
2341 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2342 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2343 int regnum = obj_priv->fence_reg;
0f973f27 2344 int tile_width;
dc529a4f 2345 uint32_t fence_reg, val;
de151cf6
JB		 2346 uint32_t pitch_val;
2347
2348 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2349 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2350 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2351 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2352 return;
2353 }
2354
0f973f27
JB		 2355 if (obj_priv->tiling_mode == I915_TILING_Y &&
2356 HAS_128_BYTE_Y_TILING(dev))
2357 tile_width = 128;
de151cf6 2358 else
0f973f27
JB		 2359 tile_width = 512;
2360
2361 /* Note: pitch better be a power of two tile widths */
2362 pitch_val = obj_priv->stride / tile_width;
2363 pitch_val = ffs(pitch_val) - 1;
de151cf6 2364
c36a2a6d
DV		 2365 if (obj_priv->tiling_mode == I915_TILING_Y &&
2366 HAS_128_BYTE_Y_TILING(dev))
2367 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2368 else
2369 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2370
de151cf6
JB		 2371 val = obj_priv->gtt_offset;
2372 if (obj_priv->tiling_mode == I915_TILING_Y)
2373 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2374 val |= I915_FENCE_SIZE_BITS(obj->size);
2375 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2376 val |= I830_FENCE_REG_VALID;
2377
dc529a4f
EA		 2378 if (regnum < 8)
2379 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2380 else
2381 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2382 I915_WRITE(fence_reg, val);
de151cf6
JB		 2383}
2384
2385static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2386{
2387 struct drm_gem_object *obj = reg->obj;
2388 struct drm_device *dev = obj->dev;
2389 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2390 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2391 int regnum = obj_priv->fence_reg;
2392 uint32_t val;
2393 uint32_t pitch_val;
8d7773a3 2394 uint32_t fence_size_bits;
de151cf6 2395
8d7773a3 2396 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2397 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2398 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2399 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2400 return;
2401 }
2402
e76a16de
EA		 2403 pitch_val = obj_priv->stride / 128;
2404 pitch_val = ffs(pitch_val) - 1;
2405 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2406
de151cf6
JB		 2407 val = obj_priv->gtt_offset;
2408 if (obj_priv->tiling_mode == I915_TILING_Y)
2409 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2410 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2411 WARN_ON(fence_size_bits & ~0x00000f00);
2412 val |= fence_size_bits;
de151cf6
JB		 2413 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2414 val |= I830_FENCE_REG_VALID;
2415
2416 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2417}
2418
ae3db24a
DV		 2419static int i915_find_fence_reg(struct drm_device *dev)
2420{
2421 struct drm_i915_fence_reg *reg = NULL;
2422 struct drm_i915_gem_object *obj_priv = NULL;
2423 struct drm_i915_private *dev_priv = dev->dev_private;
2424 struct drm_gem_object *obj = NULL;
2425 int i, avail, ret;
2426
2427 /* First try to find a free reg */
2428 avail = 0;
2429 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2430 reg = &dev_priv->fence_regs[i];
2431 if (!reg->obj)
2432 return i;
2433
23010e43 2434 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2435 if (!obj_priv->pin_count)
2436 avail++;
2437 }
2438
2439 if (avail == 0)
2440 return -ENOSPC;
2441
2442 /* None available, try to steal one or wait for a user to finish */
2443 i = I915_FENCE_REG_NONE;
2444 list_for_each_entry(obj_priv, &dev_priv->mm.fence_list,
2445 fence_list) {
2446 obj = obj_priv->obj;
2447
2448 if (obj_priv->pin_count)
2449 continue;
2450
2451 /* found one! */
2452 i = obj_priv->fence_reg;
2453 break;
2454 }
2455
2456 BUG_ON(i == I915_FENCE_REG_NONE);
2457
2458 /* We only have a reference on obj from the active list. put_fence_reg
2459 * might drop that one, causing a use-after-free in it. So hold a
2460 * private reference to obj like the other callers of put_fence_reg
2461 * (set_tiling ioctl) do. */
2462 drm_gem_object_reference(obj);
2463 ret = i915_gem_object_put_fence_reg(obj);
2464 drm_gem_object_unreference(obj);
2465 if (ret != 0)
2466 return ret;
2467
2468 return i;
2469}
2470
de151cf6
JB		 2471/**
2472 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2473 * @obj: object to map through a fence reg
2474 *
2475 * When mapping objects through the GTT, userspace wants to be able to write
2476 * to them without having to worry about swizzling if the object is tiled.
2477 *
2478 * This function walks the fence regs looking for a free one for @obj,
2479 * stealing one if it can't find any.
2480 *
2481 * It then sets up the reg based on the object's properties: address, pitch
2482 * and tiling format.
2483 */
8c4b8c3f
CW		 2484int
2485i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2486{
2487 struct drm_device *dev = obj->dev;
79e53945 2488 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2490 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2491 int ret;
de151cf6 2492
a09ba7fa
EA		 2493 /* Just update our place in the LRU if our fence is getting used. */
2494 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2495 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2496 return 0;
2497 }
2498
de151cf6
JB		 2499 switch (obj_priv->tiling_mode) {
2500 case I915_TILING_NONE:
2501 WARN(1, "allocating a fence for non-tiled object?\n");
2502 break;
2503 case I915_TILING_X:
0f973f27
JB		 2504 if (!obj_priv->stride)
2505 return -EINVAL;
2506 WARN((obj_priv->stride & (512 - 1)),
2507 "object 0x%08x is X tiled but has non-512B pitch\n",
2508 obj_priv->gtt_offset);
de151cf6
JB		 2509 break;
2510 case I915_TILING_Y:
0f973f27
JB		 2511 if (!obj_priv->stride)
2512 return -EINVAL;
2513 WARN((obj_priv->stride & (128 - 1)),
2514 "object 0x%08x is Y tiled but has non-128B pitch\n",
2515 obj_priv->gtt_offset);
de151cf6
JB		 2516 break;
2517 }
2518
ae3db24a
DV		 2519 ret = i915_find_fence_reg(dev);
2520 if (ret < 0)
2521 return ret;
de151cf6 2522
ae3db24a
DV		 2523 obj_priv->fence_reg = ret;
2524 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
a09ba7fa
EA		 2525 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2526
de151cf6
JB		 2527 reg->obj = obj;
2528
4e901fdc
EA		 2529 if (IS_GEN6(dev))
2530 sandybridge_write_fence_reg(reg);
2531 else if (IS_I965G(dev))
de151cf6
JB		 2532 i965_write_fence_reg(reg);
2533 else if (IS_I9XX(dev))
2534 i915_write_fence_reg(reg);
2535 else
2536 i830_write_fence_reg(reg);
d9ddcb96 2537
ae3db24a
DV		 2538 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2539 obj_priv->tiling_mode);
1c5d22f7 2540
d9ddcb96 2541 return 0;
de151cf6
JB		 2542}
2543
2544/**
2545 * i915_gem_clear_fence_reg - clear out fence register info
2546 * @obj: object to clear
2547 *
2548 * Zeroes out the fence register itself and clears out the associated
2549 * data structures in dev_priv and obj_priv.
2550 */
2551static void
2552i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2553{
2554 struct drm_device *dev = obj->dev;
79e53945 2555 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2556 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2557
4e901fdc
EA		 2558 if (IS_GEN6(dev)) {
2559 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2560 (obj_priv->fence_reg * 8), 0);
2561 } else if (IS_I965G(dev)) {
de151cf6 2562 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
4e901fdc 2563 } else {
dc529a4f
EA		 2564 uint32_t fence_reg;
2565
2566 if (obj_priv->fence_reg < 8)
2567 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2568 else
2569 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2570 8) * 4;
2571
2572 I915_WRITE(fence_reg, 0);
2573 }
de151cf6
JB		 2574
2575 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2576 obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2577 list_del_init(&obj_priv->fence_list);
de151cf6
JB		 2578}
2579
52dc7d32
CW		 2580/**
2581 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2582 * to the buffer to finish, and then resets the fence register.
2583 * @obj: tiled object holding a fence register.
2584 *
2585 * Zeroes out the fence register itself and clears out the associated
2586 * data structures in dev_priv and obj_priv.
2587 */
2588int
2589i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2590{
2591 struct drm_device *dev = obj->dev;
23010e43 2592 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2593
2594 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2595 return 0;
2596
10ae9bd2
DV		 2597 /* If we've changed tiling, GTT-mappings of the object
2598 * need to re-fault to ensure that the correct fence register
2599 * setup is in place.
2600 */
2601 i915_gem_release_mmap(obj);
2602
52dc7d32
CW		 2603 /* On the i915, GPU access to tiled buffers is via a fence,
2604 * therefore we must wait for any outstanding access to complete
2605 * before clearing the fence.
2606 */
2607 if (!IS_I965G(dev)) {
2608 int ret;
2609
2610 i915_gem_object_flush_gpu_write_domain(obj);
52dc7d32
CW		 2611 ret = i915_gem_object_wait_rendering(obj);
2612 if (ret != 0)
2613 return ret;
2614 }
2615
4a726612 2616 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2617 i915_gem_clear_fence_reg (obj);
2618
2619 return 0;
2620}
2621
673a394b
EA		 2622/**
2623 * Finds free space in the GTT aperture and binds the object there.
2624 */
2625static int
2626i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2627{
2628 struct drm_device *dev = obj->dev;
2629 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2630 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2631 struct drm_mm_node *free_space;
4bdadb97 2632 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2633 int ret;
673a394b 2634
bb6baf76 2635 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2636 DRM_ERROR("Attempting to bind a purgeable object\n");
2637 return -EINVAL;
2638 }
2639
673a394b 2640 if (alignment == 0)
0f973f27 2641 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2642 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2643 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2644 return -EINVAL;
2645 }
2646
2647 search_free:
2648 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2649 obj->size, alignment, 0);
2650 if (free_space != NULL) {
2651 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2652 alignment);
2653 if (obj_priv->gtt_space != NULL) {
2654 obj_priv->gtt_space->private = obj;
2655 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2656 }
2657 }
2658 if (obj_priv->gtt_space == NULL) {
2659 /* If the gtt is empty and we're still having trouble
2660 * fitting our object in, we're out of memory.
2661 */
2662#if WATCH_LRU
2663 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2664#endif
07f73f69 2665 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2666 if (ret)
673a394b 2667 return ret;
9731129c 2668
673a394b
EA		 2669 goto search_free;
2670 }
2671
2672#if WATCH_BUF
cfd43c02 2673 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2674 obj->size, obj_priv->gtt_offset);
2675#endif
4bdadb97 2676 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2677 if (ret) {
2678 drm_mm_put_block(obj_priv->gtt_space);
2679 obj_priv->gtt_space = NULL;
07f73f69
CW		 2680
2681 if (ret == -ENOMEM) {
2682 /* first try to clear up some space from the GTT */
2683 ret = i915_gem_evict_something(dev, obj->size);
2684 if (ret) {
07f73f69 2685 /* now try to shrink everyone else */
4bdadb97
CW		 2686 if (gfpmask) {
2687 gfpmask = 0;
2688 goto search_free;
07f73f69
CW		 2689 }
2690
2691 return ret;
2692 }
2693
2694 goto search_free;
2695 }
2696
673a394b
EA		 2697 return ret;
2698 }
2699
673a394b
EA		 2700 /* Create an AGP memory structure pointing at our pages, and bind it
2701 * into the GTT.
2702 */
2703 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2704 obj_priv->pages,
07f73f69 2705 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2706 obj_priv->gtt_offset,
2707 obj_priv->agp_type);
673a394b 2708 if (obj_priv->agp_mem == NULL) {
856fa198 2709 i915_gem_object_put_pages(obj);
673a394b
EA		 2710 drm_mm_put_block(obj_priv->gtt_space);
2711 obj_priv->gtt_space = NULL;
07f73f69
CW		 2712
2713 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2714 if (ret)
07f73f69 2715 return ret;
07f73f69
CW		 2716
2717 goto search_free;
673a394b
EA		 2718 }
2719 atomic_inc(&dev->gtt_count);
2720 atomic_add(obj->size, &dev->gtt_memory);
2721
2722 /* Assert that the object is not currently in any GPU domain. As it
2723 * wasn't in the GTT, there shouldn't be any way it could have been in
2724 * a GPU cache
2725 */
21d509e3
CW		 2726 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2727 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2728
1c5d22f7
CW		 2729 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2730
673a394b
EA		 2731 return 0;
2732}
2733
2734void
2735i915_gem_clflush_object(struct drm_gem_object *obj)
2736{
23010e43 2737 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2738
2739 /* If we don't have a page list set up, then we're not pinned
2740 * to GPU, and we can ignore the cache flush because it'll happen
2741 * again at bind time.
2742 */
856fa198 2743 if (obj_priv->pages == NULL)
673a394b
EA		 2744 return;
2745
1c5d22f7 2746 trace_i915_gem_object_clflush(obj);
cfa16a0d 2747
856fa198 2748 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2749}
2750
e47c68e9
EA		 2751/** Flushes any GPU write domain for the object if it's dirty. */
2752static void
2753i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2754{
2755 struct drm_device *dev = obj->dev;
1c5d22f7 2756 uint32_t old_write_domain;
e47c68e9
EA		 2757
2758 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2759 return;
2760
2761 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2762 old_write_domain = obj->write_domain;
e47c68e9 2763 i915_gem_flush(dev, 0, obj->write_domain);
922a2efc 2764 (void) i915_add_request(dev, NULL, obj->write_domain);
99fcb766 2765 BUG_ON(obj->write_domain);
1c5d22f7
CW		 2766
2767 trace_i915_gem_object_change_domain(obj,
2768 obj->read_domains,
2769 old_write_domain);
e47c68e9
EA		 2770}
2771
2772/** Flushes the GTT write domain for the object if it's dirty. */
2773static void
2774i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2775{
1c5d22f7
CW		 2776 uint32_t old_write_domain;
2777
e47c68e9
EA		 2778 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2779 return;
2780
2781 /* No actual flushing is required for the GTT write domain. Writes
2782 * to it immediately go to main memory as far as we know, so there's
2783 * no chipset flush. It also doesn't land in render cache.
2784 */
1c5d22f7 2785 old_write_domain = obj->write_domain;
e47c68e9 2786 obj->write_domain = 0;
1c5d22f7
CW		 2787
2788 trace_i915_gem_object_change_domain(obj,
2789 obj->read_domains,
2790 old_write_domain);
e47c68e9
EA		 2791}
2792
2793/** Flushes the CPU write domain for the object if it's dirty. */
2794static void
2795i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2796{
2797 struct drm_device *dev = obj->dev;
1c5d22f7 2798 uint32_t old_write_domain;
e47c68e9
EA		 2799
2800 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2801 return;
2802
2803 i915_gem_clflush_object(obj);
2804 drm_agp_chipset_flush(dev);
1c5d22f7 2805 old_write_domain = obj->write_domain;
e47c68e9 2806 obj->write_domain = 0;
1c5d22f7
CW		 2807
2808 trace_i915_gem_object_change_domain(obj,
2809 obj->read_domains,
2810 old_write_domain);
e47c68e9
EA		 2811}
2812
6b95a207
KH		 2813void
2814i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2815{
2816 switch (obj->write_domain) {
2817 case I915_GEM_DOMAIN_GTT:
2818 i915_gem_object_flush_gtt_write_domain(obj);
2819 break;
2820 case I915_GEM_DOMAIN_CPU:
2821 i915_gem_object_flush_cpu_write_domain(obj);
2822 break;
2823 default:
2824 i915_gem_object_flush_gpu_write_domain(obj);
2825 break;
2826 }
2827}
2828
2ef7eeaa
EA		 2829/**
2830 * Moves a single object to the GTT read, and possibly write domain.
2831 *
2832 * This function returns when the move is complete, including waiting on
2833 * flushes to occur.
2834 */
79e53945 2835int
2ef7eeaa
EA		 2836i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2837{
23010e43 2838 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2839 uint32_t old_write_domain, old_read_domains;
e47c68e9 2840 int ret;
2ef7eeaa 2841
02354392
EA		 2842 /* Not valid to be called on unbound objects. */
2843 if (obj_priv->gtt_space == NULL)
2844 return -EINVAL;
2845
e47c68e9
EA		 2846 i915_gem_object_flush_gpu_write_domain(obj);
2847 /* Wait on any GPU rendering and flushing to occur. */
2848 ret = i915_gem_object_wait_rendering(obj);
2849 if (ret != 0)
2850 return ret;
2851
1c5d22f7
CW		 2852 old_write_domain = obj->write_domain;
2853 old_read_domains = obj->read_domains;
2854
e47c68e9
EA		 2855 /* If we're writing through the GTT domain, then CPU and GPU caches
2856 * will need to be invalidated at next use.
2ef7eeaa 2857 */
e47c68e9
EA		 2858 if (write)
2859 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2860
e47c68e9 2861 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2862
e47c68e9
EA		 2863 /* It should now be out of any other write domains, and we can update
2864 * the domain values for our changes.
2865 */
2866 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2867 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2868 if (write) {
2869 obj->write_domain = I915_GEM_DOMAIN_GTT;
2870 obj_priv->dirty = 1;
2ef7eeaa
EA		 2871 }
2872
1c5d22f7
CW		 2873 trace_i915_gem_object_change_domain(obj,
2874 old_read_domains,
2875 old_write_domain);
2876
e47c68e9
EA		 2877 return 0;
2878}
2879
b9241ea3
ZW		 2880/*
2881 * Prepare buffer for display plane. Use uninterruptible for possible flush
2882 * wait, as in modesetting process we're not supposed to be interrupted.
2883 */
2884int
2885i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2886{
2887 struct drm_device *dev = obj->dev;
23010e43 2888 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2889 uint32_t old_write_domain, old_read_domains;
2890 int ret;
2891
2892 /* Not valid to be called on unbound objects. */
2893 if (obj_priv->gtt_space == NULL)
2894 return -EINVAL;
2895
2896 i915_gem_object_flush_gpu_write_domain(obj);
2897
2898 /* Wait on any GPU rendering and flushing to occur. */
2899 if (obj_priv->active) {
2900#if WATCH_BUF
2901 DRM_INFO("%s: object %p wait for seqno %08x\n",
2902 __func__, obj, obj_priv->last_rendering_seqno);
2903#endif
2904 ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
2905 if (ret != 0)
2906 return ret;
2907 }
2908
2909 old_write_domain = obj->write_domain;
2910 old_read_domains = obj->read_domains;
2911
2912 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2913
2914 i915_gem_object_flush_cpu_write_domain(obj);
2915
2916 /* It should now be out of any other write domains, and we can update
2917 * the domain values for our changes.
2918 */
2919 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2920 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2921 obj->write_domain = I915_GEM_DOMAIN_GTT;
2922 obj_priv->dirty = 1;
2923
2924 trace_i915_gem_object_change_domain(obj,
2925 old_read_domains,
2926 old_write_domain);
2927
2928 return 0;
2929}
2930
e47c68e9
EA		 2931/**
2932 * Moves a single object to the CPU read, and possibly write domain.
2933 *
2934 * This function returns when the move is complete, including waiting on
2935 * flushes to occur.
2936 */
2937static int
2938i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2939{
1c5d22f7 2940 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2941 int ret;
2942
2943 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2944 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2945 ret = i915_gem_object_wait_rendering(obj);
2946 if (ret != 0)
2947 return ret;
2ef7eeaa 2948
e47c68e9 2949 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2950
e47c68e9
EA		 2951 /* If we have a partially-valid cache of the object in the CPU,
2952 * finish invalidating it and free the per-page flags.
2ef7eeaa 2953 */
e47c68e9 2954 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2955
1c5d22f7
CW		 2956 old_write_domain = obj->write_domain;
2957 old_read_domains = obj->read_domains;
2958
e47c68e9
EA		 2959 /* Flush the CPU cache if it's still invalid. */
2960 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2961 i915_gem_clflush_object(obj);
2ef7eeaa 2962
e47c68e9 2963 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2964 }
2965
2966 /* It should now be out of any other write domains, and we can update
2967 * the domain values for our changes.
2968 */
e47c68e9
EA		 2969 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2970
2971 /* If we're writing through the CPU, then the GPU read domains will
2972 * need to be invalidated at next use.
2973 */
2974 if (write) {
2975 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2976 obj->write_domain = I915_GEM_DOMAIN_CPU;
2977 }
2ef7eeaa 2978
1c5d22f7
CW		 2979 trace_i915_gem_object_change_domain(obj,
2980 old_read_domains,
2981 old_write_domain);
2982
2ef7eeaa
EA		 2983 return 0;
2984}
2985
673a394b
EA		 2986/*
2987 * Set the next domain for the specified object. This
2988 * may not actually perform the necessary flushing/invaliding though,
2989 * as that may want to be batched with other set_domain operations
2990 *
2991 * This is (we hope) the only really tricky part of gem. The goal
2992 * is fairly simple -- track which caches hold bits of the object
2993 * and make sure they remain coherent. A few concrete examples may
2994 * help to explain how it works. For shorthand, we use the notation
2995 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2996 * a pair of read and write domain masks.
2997 *
2998 * Case 1: the batch buffer
2999 *
3000 * 1. Allocated
3001 * 2. Written by CPU
3002 * 3. Mapped to GTT
3003 * 4. Read by GPU
3004 * 5. Unmapped from GTT
3005 * 6. Freed
3006 *
3007 * Let's take these a step at a time
3008 *
3009 * 1. Allocated
3010 * Pages allocated from the kernel may still have
3011 * cache contents, so we set them to (CPU, CPU) always.
3012 * 2. Written by CPU (using pwrite)
3013 * The pwrite function calls set_domain (CPU, CPU) and
3014 * this function does nothing (as nothing changes)
3015 * 3. Mapped by GTT
3016 * This function asserts that the object is not
3017 * currently in any GPU-based read or write domains
3018 * 4. Read by GPU
3019 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3020 * As write_domain is zero, this function adds in the
3021 * current read domains (CPU+COMMAND, 0).
3022 * flush_domains is set to CPU.
3023 * invalidate_domains is set to COMMAND
3024 * clflush is run to get data out of the CPU caches
3025 * then i915_dev_set_domain calls i915_gem_flush to
3026 * emit an MI_FLUSH and drm_agp_chipset_flush
3027 * 5. Unmapped from GTT
3028 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3029 * flush_domains and invalidate_domains end up both zero
3030 * so no flushing/invalidating happens
3031 * 6. Freed
3032 * yay, done
3033 *
3034 * Case 2: The shared render buffer
3035 *
3036 * 1. Allocated
3037 * 2. Mapped to GTT
3038 * 3. Read/written by GPU
3039 * 4. set_domain to (CPU,CPU)
3040 * 5. Read/written by CPU
3041 * 6. Read/written by GPU
3042 *
3043 * 1. Allocated
3044 * Same as last example, (CPU, CPU)
3045 * 2. Mapped to GTT
3046 * Nothing changes (assertions find that it is not in the GPU)
3047 * 3. Read/written by GPU
3048 * execbuffer calls set_domain (RENDER, RENDER)
3049 * flush_domains gets CPU
3050 * invalidate_domains gets GPU
3051 * clflush (obj)
3052 * MI_FLUSH and drm_agp_chipset_flush
3053 * 4. set_domain (CPU, CPU)
3054 * flush_domains gets GPU
3055 * invalidate_domains gets CPU
3056 * wait_rendering (obj) to make sure all drawing is complete.
3057 * This will include an MI_FLUSH to get the data from GPU
3058 * to memory
3059 * clflush (obj) to invalidate the CPU cache
3060 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3061 * 5. Read/written by CPU
3062 * cache lines are loaded and dirtied
3063 * 6. Read written by GPU
3064 * Same as last GPU access
3065 *
3066 * Case 3: The constant buffer
3067 *
3068 * 1. Allocated
3069 * 2. Written by CPU
3070 * 3. Read by GPU
3071 * 4. Updated (written) by CPU again
3072 * 5. Read by GPU
3073 *
3074 * 1. Allocated
3075 * (CPU, CPU)
3076 * 2. Written by CPU
3077 * (CPU, CPU)
3078 * 3. Read by GPU
3079 * (CPU+RENDER, 0)
3080 * flush_domains = CPU
3081 * invalidate_domains = RENDER
3082 * clflush (obj)
3083 * MI_FLUSH
3084 * drm_agp_chipset_flush
3085 * 4. Updated (written) by CPU again
3086 * (CPU, CPU)
3087 * flush_domains = 0 (no previous write domain)
3088 * invalidate_domains = 0 (no new read domains)
3089 * 5. Read by GPU
3090 * (CPU+RENDER, 0)
3091 * flush_domains = CPU
3092 * invalidate_domains = RENDER
3093 * clflush (obj)
3094 * MI_FLUSH
3095 * drm_agp_chipset_flush
3096 */
c0d90829 3097static void
8b0e378a 3098i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3099{
3100 struct drm_device *dev = obj->dev;
23010e43 3101 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 3102 uint32_t invalidate_domains = 0;
3103 uint32_t flush_domains = 0;
1c5d22f7 3104 uint32_t old_read_domains;
e47c68e9 3105
8b0e378a
EA		 3106 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3107 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3108
652c393a
JB		 3109 intel_mark_busy(dev, obj);
3110
673a394b
EA		 3111#if WATCH_BUF
3112 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3113 __func__, obj,
8b0e378a
EA		 3114 obj->read_domains, obj->pending_read_domains,
3115 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 3116#endif
3117 /*
3118 * If the object isn't moving to a new write domain,
3119 * let the object stay in multiple read domains
3120 */
8b0e378a
EA		 3121 if (obj->pending_write_domain == 0)
3122 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3123 else
3124 obj_priv->dirty = 1;
3125
3126 /*
3127 * Flush the current write domain if
3128 * the new read domains don't match. Invalidate
3129 * any read domains which differ from the old
3130 * write domain
3131 */
8b0e378a
EA		 3132 if (obj->write_domain &&
3133 obj->write_domain != obj->pending_read_domains) {
673a394b 3134 flush_domains |= obj->write_domain;
8b0e378a
EA		 3135 invalidate_domains |=
3136 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3137 }
3138 /*
3139 * Invalidate any read caches which may have
3140 * stale data. That is, any new read domains.
3141 */
8b0e378a 3142 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3143 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3144#if WATCH_BUF
3145 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3146 __func__, flush_domains, invalidate_domains);
3147#endif
673a394b
EA		 3148 i915_gem_clflush_object(obj);
3149 }
3150
1c5d22f7
CW		 3151 old_read_domains = obj->read_domains;
3152
efbeed96
EA		 3153 /* The actual obj->write_domain will be updated with
3154 * pending_write_domain after we emit the accumulated flush for all
3155 * of our domain changes in execbuffers (which clears objects'
3156 * write_domains). So if we have a current write domain that we
3157 * aren't changing, set pending_write_domain to that.
3158 */
3159 if (flush_domains == 0 && obj->pending_write_domain == 0)
3160 obj->pending_write_domain = obj->write_domain;
8b0e378a 3161 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3162
3163 dev->invalidate_domains |= invalidate_domains;
3164 dev->flush_domains |= flush_domains;
3165#if WATCH_BUF
3166 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3167 __func__,
3168 obj->read_domains, obj->write_domain,
3169 dev->invalidate_domains, dev->flush_domains);
3170#endif
1c5d22f7
CW		 3171
3172 trace_i915_gem_object_change_domain(obj,
3173 old_read_domains,
3174 obj->write_domain);
673a394b
EA		 3175}
3176
3177/**
e47c68e9 3178 * Moves the object from a partially CPU read to a full one.
673a394b 3179 *
e47c68e9
EA		 3180 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3181 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3182 */
e47c68e9
EA		 3183static void
3184i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3185{
23010e43 3186 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3187
e47c68e9
EA		 3188 if (!obj_priv->page_cpu_valid)
3189 return;
3190
3191 /* If we're partially in the CPU read domain, finish moving it in.
3192 */
3193 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3194 int i;
3195
3196 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3197 if (obj_priv->page_cpu_valid[i])
3198 continue;
856fa198 3199 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3200 }
e47c68e9
EA		 3201 }
3202
3203 /* Free the page_cpu_valid mappings which are now stale, whether
3204 * or not we've got I915_GEM_DOMAIN_CPU.
3205 */
9a298b2a 3206 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3207 obj_priv->page_cpu_valid = NULL;
3208}
3209
3210/**
3211 * Set the CPU read domain on a range of the object.
3212 *
3213 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3214 * not entirely valid. The page_cpu_valid member of the object flags which
3215 * pages have been flushed, and will be respected by
3216 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3217 * of the whole object.
3218 *
3219 * This function returns when the move is complete, including waiting on
3220 * flushes to occur.
3221 */
3222static int
3223i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3224 uint64_t offset, uint64_t size)
3225{
23010e43 3226 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3227 uint32_t old_read_domains;
e47c68e9 3228 int i, ret;
673a394b 3229
e47c68e9
EA		 3230 if (offset == 0 && size == obj->size)
3231 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3232
e47c68e9
EA		 3233 i915_gem_object_flush_gpu_write_domain(obj);
3234 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3235 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3236 if (ret != 0)
6a47baa6 3237 return ret;
e47c68e9
EA		 3238 i915_gem_object_flush_gtt_write_domain(obj);
3239
3240 /* If we're already fully in the CPU read domain, we're done. */
3241 if (obj_priv->page_cpu_valid == NULL &&
3242 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3243 return 0;
673a394b 3244
e47c68e9
EA		 3245 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3246 * newly adding I915_GEM_DOMAIN_CPU
3247 */
673a394b 3248 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3249 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3250 GFP_KERNEL);
e47c68e9
EA		 3251 if (obj_priv->page_cpu_valid == NULL)
3252 return -ENOMEM;
3253 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3254 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3255
3256 /* Flush the cache on any pages that are still invalid from the CPU's
3257 * perspective.
3258 */
e47c68e9
EA		 3259 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3260 i++) {
673a394b
EA		 3261 if (obj_priv->page_cpu_valid[i])
3262 continue;
3263
856fa198 3264 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3265
3266 obj_priv->page_cpu_valid[i] = 1;
3267 }
3268
e47c68e9
EA		 3269 /* It should now be out of any other write domains, and we can update
3270 * the domain values for our changes.
3271 */
3272 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3273
1c5d22f7 3274 old_read_domains = obj->read_domains;
e47c68e9
EA		 3275 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3276
1c5d22f7
CW		 3277 trace_i915_gem_object_change_domain(obj,
3278 old_read_domains,
3279 obj->write_domain);
3280
673a394b
EA		 3281 return 0;
3282}
3283
673a394b
EA		 3284/**
3285 * Pin an object to the GTT and evaluate the relocations landing in it.
3286 */
3287static int
3288i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3289 struct drm_file *file_priv,
76446cac 3290 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3291 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3292{
3293 struct drm_device *dev = obj->dev;
0839ccb8 3294 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3295 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3296 int i, ret;
0839ccb8 3297 void __iomem *reloc_page;
76446cac
JB		 3298 bool need_fence;
3299
3300 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3301 obj_priv->tiling_mode != I915_TILING_NONE;
3302
3303 /* Check fence reg constraints and rebind if necessary */
f590d279
OA		 3304 if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3305 obj_priv->tiling_mode))
76446cac 3306 i915_gem_object_unbind(obj);
673a394b
EA		 3307
3308 /* Choose the GTT offset for our buffer and put it there. */
3309 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3310 if (ret)
3311 return ret;
3312
76446cac
JB		 3313 /*
3314 * Pre-965 chips need a fence register set up in order to
3315 * properly handle blits to/from tiled surfaces.
3316 */
3317 if (need_fence) {
3318 ret = i915_gem_object_get_fence_reg(obj);
3319 if (ret != 0) {
3320 if (ret != -EBUSY && ret != -ERESTARTSYS)
3321 DRM_ERROR("Failure to install fence: %d\n",
3322 ret);
3323 i915_gem_object_unpin(obj);
3324 return ret;
3325 }
3326 }
3327
673a394b
EA		 3328 entry->offset = obj_priv->gtt_offset;
3329
673a394b
EA		 3330 /* Apply the relocations, using the GTT aperture to avoid cache
3331 * flushing requirements.
3332 */
3333 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3334 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3335 struct drm_gem_object *target_obj;
3336 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3337 uint32_t reloc_val, reloc_offset;
3338 uint32_t __iomem *reloc_entry;
673a394b 3339
673a394b 3340 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3341 reloc->target_handle);
673a394b
EA		 3342 if (target_obj == NULL) {
3343 i915_gem_object_unpin(obj);
3344 return -EBADF;
3345 }
23010e43 3346 target_obj_priv = to_intel_bo(target_obj);
673a394b 3347
8542a0bb
CW		 3348#if WATCH_RELOC
3349 DRM_INFO("%s: obj %p offset %08x target %d "
3350 "read %08x write %08x gtt %08x "
3351 "presumed %08x delta %08x\n",
3352 __func__,
3353 obj,
3354 (int) reloc->offset,
3355 (int) reloc->target_handle,
3356 (int) reloc->read_domains,
3357 (int) reloc->write_domain,
3358 (int) target_obj_priv->gtt_offset,
3359 (int) reloc->presumed_offset,
3360 reloc->delta);
3361#endif
3362
673a394b
EA		 3363 /* The target buffer should have appeared before us in the
3364 * exec_object list, so it should have a GTT space bound by now.
3365 */
3366 if (target_obj_priv->gtt_space == NULL) {
3367 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3368 reloc->target_handle);
673a394b
EA		 3369 drm_gem_object_unreference(target_obj);
3370 i915_gem_object_unpin(obj);
3371 return -EINVAL;
3372 }
3373
8542a0bb 3374 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3375 if (reloc->write_domain & (reloc->write_domain - 1)) {
3376 DRM_ERROR("reloc with multiple write domains: "
3377 "obj %p target %d offset %d "
3378 "read %08x write %08x",
3379 obj, reloc->target_handle,
3380 (int) reloc->offset,
3381 reloc->read_domains,
3382 reloc->write_domain);
3383 return -EINVAL;
3384 }
40a5f0de
EA		 3385 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3386 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3387 DRM_ERROR("reloc with read/write CPU domains: "
3388 "obj %p target %d offset %d "
3389 "read %08x write %08x",
40a5f0de
EA		 3390 obj, reloc->target_handle,
3391 (int) reloc->offset,
3392 reloc->read_domains,
3393 reloc->write_domain);
491152b8
CW		 3394 drm_gem_object_unreference(target_obj);
3395 i915_gem_object_unpin(obj);
e47c68e9
EA		 3396 return -EINVAL;
3397 }
40a5f0de
EA		 3398 if (reloc->write_domain && target_obj->pending_write_domain &&
3399 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3400 DRM_ERROR("Write domain conflict: "
3401 "obj %p target %d offset %d "
3402 "new %08x old %08x\n",
40a5f0de
EA		 3403 obj, reloc->target_handle,
3404 (int) reloc->offset,
3405 reloc->write_domain,
673a394b
EA		 3406 target_obj->pending_write_domain);
3407 drm_gem_object_unreference(target_obj);
3408 i915_gem_object_unpin(obj);
3409 return -EINVAL;
3410 }
3411
40a5f0de
EA		 3412 target_obj->pending_read_domains |= reloc->read_domains;
3413 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3414
3415 /* If the relocation already has the right value in it, no
3416 * more work needs to be done.
3417 */
40a5f0de 3418 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3419 drm_gem_object_unreference(target_obj);
3420 continue;
3421 }
3422
8542a0bb
CW		 3423 /* Check that the relocation address is valid... */
3424 if (reloc->offset > obj->size - 4) {
3425 DRM_ERROR("Relocation beyond object bounds: "
3426 "obj %p target %d offset %d size %d.\n",
3427 obj, reloc->target_handle,
3428 (int) reloc->offset, (int) obj->size);
3429 drm_gem_object_unreference(target_obj);
3430 i915_gem_object_unpin(obj);
3431 return -EINVAL;
3432 }
3433 if (reloc->offset & 3) {
3434 DRM_ERROR("Relocation not 4-byte aligned: "
3435 "obj %p target %d offset %d.\n",
3436 obj, reloc->target_handle,
3437 (int) reloc->offset);
3438 drm_gem_object_unreference(target_obj);
3439 i915_gem_object_unpin(obj);
3440 return -EINVAL;
3441 }
3442
3443 /* and points to somewhere within the target object. */
3444 if (reloc->delta >= target_obj->size) {
3445 DRM_ERROR("Relocation beyond target object bounds: "
3446 "obj %p target %d delta %d size %d.\n",
3447 obj, reloc->target_handle,
3448 (int) reloc->delta, (int) target_obj->size);
3449 drm_gem_object_unreference(target_obj);
3450 i915_gem_object_unpin(obj);
3451 return -EINVAL;
3452 }
3453
2ef7eeaa
EA		 3454 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3455 if (ret != 0) {
3456 drm_gem_object_unreference(target_obj);
3457 i915_gem_object_unpin(obj);
3458 return -EINVAL;
673a394b
EA		 3459 }
3460
3461 /* Map the page containing the relocation we're going to
3462 * perform.
3463 */
40a5f0de 3464 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3465 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3466 (reloc_offset &
3467 ~(PAGE_SIZE - 1)));
3043c60c 3468 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3469 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3470 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3471
3472#if WATCH_BUF
3473 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3474 obj, (unsigned int) reloc->offset,
673a394b
EA		 3475 readl(reloc_entry), reloc_val);
3476#endif
3477 writel(reloc_val, reloc_entry);
0839ccb8 3478 io_mapping_unmap_atomic(reloc_page);
673a394b 3479
40a5f0de
EA		 3480 /* The updated presumed offset for this entry will be
3481 * copied back out to the user.
673a394b 3482 */
40a5f0de 3483 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3484
3485 drm_gem_object_unreference(target_obj);
3486 }
3487
673a394b
EA		 3488#if WATCH_BUF
3489 if (0)
3490 i915_gem_dump_object(obj, 128, __func__, ~0);
3491#endif
3492 return 0;
3493}
3494
3495/** Dispatch a batchbuffer to the ring
3496 */
3497static int
3498i915_dispatch_gem_execbuffer(struct drm_device *dev,
76446cac 3499 struct drm_i915_gem_execbuffer2 *exec,
201361a5 3500 struct drm_clip_rect *cliprects,
673a394b
EA		 3501 uint64_t exec_offset)
3502{
3503 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3504 int nbox = exec->num_cliprects;
3505 int i = 0, count;
83d60795 3506 uint32_t exec_start, exec_len;
673a394b
EA		 3507 RING_LOCALS;
3508
3509 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3510 exec_len = (uint32_t) exec->batch_len;
3511
8f0dc5bf 3512 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
1c5d22f7 3513
673a394b
EA		 3514 count = nbox ? nbox : 1;
3515
3516 for (i = 0; i < count; i++) {
3517 if (i < nbox) {
201361a5 3518 int ret = i915_emit_box(dev, cliprects, i,
673a394b
EA		 3519 exec->DR1, exec->DR4);
3520 if (ret)
3521 return ret;
3522 }
3523
3524 if (IS_I830(dev) || IS_845G(dev)) {
3525 BEGIN_LP_RING(4);
3526 OUT_RING(MI_BATCH_BUFFER);
3527 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3528 OUT_RING(exec_start + exec_len - 4);
3529 OUT_RING(0);
3530 ADVANCE_LP_RING();
3531 } else {
3532 BEGIN_LP_RING(2);
3533 if (IS_I965G(dev)) {
3534 OUT_RING(MI_BATCH_BUFFER_START |
3535 (2 << 6) |
3536 MI_BATCH_NON_SECURE_I965);
3537 OUT_RING(exec_start);
3538 } else {
3539 OUT_RING(MI_BATCH_BUFFER_START |
3540 (2 << 6));
3541 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3542 }
3543 ADVANCE_LP_RING();
3544 }
3545 }
3546
3547 /* XXX breadcrumb */
3548 return 0;
3549}
3550
3551/* Throttle our rendering by waiting until the ring has completed our requests
3552 * emitted over 20 msec ago.
3553 *
b962442e
EA		 3554 * Note that if we were to use the current jiffies each time around the loop,
3555 * we wouldn't escape the function with any frames outstanding if the time to
3556 * render a frame was over 20ms.
3557 *
673a394b
EA		 3558 * This should get us reasonable parallelism between CPU and GPU but also
3559 * relatively low latency when blocking on a particular request to finish.
3560 */
3561static int
3562i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3563{
3564 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3565 int ret = 0;
b962442e 3566 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3567
3568 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3569 while (!list_empty(&i915_file_priv->mm.request_list)) {
3570 struct drm_i915_gem_request *request;
3571
3572 request = list_first_entry(&i915_file_priv->mm.request_list,
3573 struct drm_i915_gem_request,
3574 client_list);
3575
3576 if (time_after_eq(request->emitted_jiffies, recent_enough))
3577 break;
3578
3579 ret = i915_wait_request(dev, request->seqno);
3580 if (ret != 0)
3581 break;
3582 }
673a394b 3583 mutex_unlock(&dev->struct_mutex);
b962442e 3584
673a394b
EA		 3585 return ret;
3586}
3587
40a5f0de 3588static int
76446cac 3589i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3590 uint32_t buffer_count,
3591 struct drm_i915_gem_relocation_entry **relocs)
3592{
3593 uint32_t reloc_count = 0, reloc_index = 0, i;
3594 int ret;
3595
3596 *relocs = NULL;
3597 for (i = 0; i < buffer_count; i++) {
3598 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3599 return -EINVAL;
3600 reloc_count += exec_list[i].relocation_count;
3601 }
3602
8e7d2b2c 3603 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3604 if (*relocs == NULL) {
3605 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3606 return -ENOMEM;
76446cac 3607 }
40a5f0de
EA		 3608
3609 for (i = 0; i < buffer_count; i++) {
3610 struct drm_i915_gem_relocation_entry __user *user_relocs;
3611
3612 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3613
3614 ret = copy_from_user(&(*relocs)[reloc_index],
3615 user_relocs,
3616 exec_list[i].relocation_count *
3617 sizeof(**relocs));
3618 if (ret != 0) {
8e7d2b2c 3619 drm_free_large(*relocs);
40a5f0de 3620 *relocs = NULL;
2bc43b5c 3621 return -EFAULT;
40a5f0de
EA		 3622 }
3623
3624 reloc_index += exec_list[i].relocation_count;
3625 }
3626
2bc43b5c 3627 return 0;
40a5f0de
EA		 3628}
3629
3630static int
76446cac 3631i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3632 uint32_t buffer_count,
3633 struct drm_i915_gem_relocation_entry *relocs)
3634{
3635 uint32_t reloc_count = 0, i;
2bc43b5c 3636 int ret = 0;
40a5f0de 3637
93533c29
CW		 3638 if (relocs == NULL)
3639 return 0;
3640
40a5f0de
EA		 3641 for (i = 0; i < buffer_count; i++) {
3642 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3643 int unwritten;
40a5f0de
EA		 3644
3645 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3646
2bc43b5c
FM		 3647 unwritten = copy_to_user(user_relocs,
3648 &relocs[reloc_count],
3649 exec_list[i].relocation_count *
3650 sizeof(*relocs));
3651
3652 if (unwritten) {
3653 ret = -EFAULT;
3654 goto err;
40a5f0de
EA		 3655 }
3656
3657 reloc_count += exec_list[i].relocation_count;
3658 }
3659
2bc43b5c 3660err:
8e7d2b2c 3661 drm_free_large(relocs);
40a5f0de
EA		 3662
3663 return ret;
3664}
3665
83d60795 3666static int
76446cac 3667i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3668 uint64_t exec_offset)
3669{
3670 uint32_t exec_start, exec_len;
3671
3672 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3673 exec_len = (uint32_t) exec->batch_len;
3674
3675 if ((exec_start | exec_len) & 0x7)
3676 return -EINVAL;
3677
3678 if (!exec_start)
3679 return -EINVAL;
3680
3681 return 0;
3682}
3683
6b95a207
KH		 3684static int
3685i915_gem_wait_for_pending_flip(struct drm_device *dev,
3686 struct drm_gem_object **object_list,
3687 int count)
3688{
3689 drm_i915_private_t *dev_priv = dev->dev_private;
3690 struct drm_i915_gem_object *obj_priv;
3691 DEFINE_WAIT(wait);
3692 int i, ret = 0;
3693
3694 for (;;) {
3695 prepare_to_wait(&dev_priv->pending_flip_queue,
3696 &wait, TASK_INTERRUPTIBLE);
3697 for (i = 0; i < count; i++) {
23010e43 3698 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3699 if (atomic_read(&obj_priv->pending_flip) > 0)
3700 break;
3701 }
3702 if (i == count)
3703 break;
3704
3705 if (!signal_pending(current)) {
3706 mutex_unlock(&dev->struct_mutex);
3707 schedule();
3708 mutex_lock(&dev->struct_mutex);
3709 continue;
3710 }
3711 ret = -ERESTARTSYS;
3712 break;
3713 }
3714 finish_wait(&dev_priv->pending_flip_queue, &wait);
3715
3716 return ret;
3717}
3718
673a394b 3719int
76446cac
JB		 3720i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3721 struct drm_file *file_priv,
3722 struct drm_i915_gem_execbuffer2 *args,
3723 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3724{
3725 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3726 struct drm_gem_object **object_list = NULL;
3727 struct drm_gem_object *batch_obj;
b70d11da 3728 struct drm_i915_gem_object *obj_priv;
201361a5 3729 struct drm_clip_rect *cliprects = NULL;
93533c29 3730 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3731 int ret = 0, ret2, i, pinned = 0;
673a394b 3732 uint64_t exec_offset;
40a5f0de 3733 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3734 int pin_tries, flips;
673a394b
EA		 3735
3736#if WATCH_EXEC
3737 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3738 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3739#endif
3740
4f481ed2
EA		 3741 if (args->buffer_count < 1) {
3742 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3743 return -EINVAL;
3744 }
c8e0f93a 3745 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3746 if (object_list == NULL) {
3747 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3748 args->buffer_count);
3749 ret = -ENOMEM;
3750 goto pre_mutex_err;
3751 }
673a394b 3752
201361a5 3753 if (args->num_cliprects != 0) {
9a298b2a
EA		 3754 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3755 GFP_KERNEL);
a40e8d31
OA		 3756 if (cliprects == NULL) {
3757 ret = -ENOMEM;
201361a5 3758 goto pre_mutex_err;
a40e8d31 3759 }
201361a5
EA		 3760
3761 ret = copy_from_user(cliprects,
3762 (struct drm_clip_rect __user *)
3763 (uintptr_t) args->cliprects_ptr,
3764 sizeof(*cliprects) * args->num_cliprects);
3765 if (ret != 0) {
3766 DRM_ERROR("copy %d cliprects failed: %d\n",
3767 args->num_cliprects, ret);
3768 goto pre_mutex_err;
3769 }
3770 }
3771
40a5f0de
EA		 3772 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3773 &relocs);
3774 if (ret != 0)
3775 goto pre_mutex_err;
3776
673a394b
EA		 3777 mutex_lock(&dev->struct_mutex);
3778
3779 i915_verify_inactive(dev, __FILE__, __LINE__);
3780
ba1234d1 3781 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3782 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3783 ret = -EIO;
3784 goto pre_mutex_err;
673a394b
EA		 3785 }
3786
3787 if (dev_priv->mm.suspended) {
673a394b 3788 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3789 ret = -EBUSY;
3790 goto pre_mutex_err;
673a394b
EA		 3791 }
3792
ac94a962 3793 /* Look up object handles */
6b95a207 3794 flips = 0;
673a394b
EA		 3795 for (i = 0; i < args->buffer_count; i++) {
3796 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3797 exec_list[i].handle);
3798 if (object_list[i] == NULL) {
3799 DRM_ERROR("Invalid object handle %d at index %d\n",
3800 exec_list[i].handle, i);
0ce907f8
CW		 3801 /* prevent error path from reading uninitialized data */
3802 args->buffer_count = i + 1;
673a394b
EA		 3803 ret = -EBADF;
3804 goto err;
3805 }
b70d11da 3806
23010e43 3807 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3808 if (obj_priv->in_execbuffer) {
3809 DRM_ERROR("Object %p appears more than once in object list\n",
3810 object_list[i]);
0ce907f8
CW		 3811 /* prevent error path from reading uninitialized data */
3812 args->buffer_count = i + 1;
b70d11da
KH		 3813 ret = -EBADF;
3814 goto err;
3815 }
3816 obj_priv->in_execbuffer = true;
6b95a207
KH		 3817 flips += atomic_read(&obj_priv->pending_flip);
3818 }
3819
3820 if (flips > 0) {
3821 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3822 args->buffer_count);
3823 if (ret)
3824 goto err;
ac94a962 3825 }
673a394b 3826
ac94a962
KP		 3827 /* Pin and relocate */
3828 for (pin_tries = 0; ; pin_tries++) {
3829 ret = 0;
40a5f0de
EA		 3830 reloc_index = 0;
3831
ac94a962
KP		 3832 for (i = 0; i < args->buffer_count; i++) {
3833 object_list[i]->pending_read_domains = 0;
3834 object_list[i]->pending_write_domain = 0;
3835 ret = i915_gem_object_pin_and_relocate(object_list[i],
3836 file_priv,
40a5f0de
EA		 3837 &exec_list[i],
3838 &relocs[reloc_index]);
ac94a962
KP		 3839 if (ret)
3840 break;
3841 pinned = i + 1;
40a5f0de 3842 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3843 }
3844 /* success */
3845 if (ret == 0)
3846 break;
3847
3848 /* error other than GTT full, or we've already tried again */
2939e1f5 3849 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3850 if (ret != -ERESTARTSYS) {
3851 unsigned long long total_size = 0;
3852 for (i = 0; i < args->buffer_count; i++)
3853 total_size += object_list[i]->size;
3854 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3855 pinned+1, args->buffer_count,
3856 total_size, ret);
3857 DRM_ERROR("%d objects [%d pinned], "
3858 "%d object bytes [%d pinned], "
3859 "%d/%d gtt bytes\n",
3860 atomic_read(&dev->object_count),
3861 atomic_read(&dev->pin_count),
3862 atomic_read(&dev->object_memory),
3863 atomic_read(&dev->pin_memory),
3864 atomic_read(&dev->gtt_memory),
3865 dev->gtt_total);
3866 }
673a394b
EA		 3867 goto err;
3868 }
ac94a962
KP		 3869
3870 /* unpin all of our buffers */
3871 for (i = 0; i < pinned; i++)
3872 i915_gem_object_unpin(object_list[i]);
b1177636 3873 pinned = 0;
ac94a962
KP		 3874
3875 /* evict everyone we can from the aperture */
3876 ret = i915_gem_evict_everything(dev);
07f73f69 3877 if (ret && ret != -ENOSPC)
ac94a962 3878 goto err;
673a394b
EA		 3879 }
3880
3881 /* Set the pending read domains for the batch buffer to COMMAND */
3882 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3883 if (batch_obj->pending_write_domain) {
3884 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3885 ret = -EINVAL;
3886 goto err;
3887 }
3888 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3889
83d60795
CW		 3890 /* Sanity check the batch buffer, prior to moving objects */
3891 exec_offset = exec_list[args->buffer_count - 1].offset;
3892 ret = i915_gem_check_execbuffer (args, exec_offset);
3893 if (ret != 0) {
3894 DRM_ERROR("execbuf with invalid offset/length\n");
3895 goto err;
3896 }
3897
673a394b
EA		 3898 i915_verify_inactive(dev, __FILE__, __LINE__);
3899
646f0f6e
KP		 3900 /* Zero the global flush/invalidate flags. These
3901 * will be modified as new domains are computed
3902 * for each object
3903 */
3904 dev->invalidate_domains = 0;
3905 dev->flush_domains = 0;
3906
673a394b
EA		 3907 for (i = 0; i < args->buffer_count; i++) {
3908 struct drm_gem_object *obj = object_list[i];
673a394b 3909
646f0f6e 3910 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3911 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3912 }
3913
3914 i915_verify_inactive(dev, __FILE__, __LINE__);
3915
646f0f6e
KP		 3916 if (dev->invalidate_domains | dev->flush_domains) {
3917#if WATCH_EXEC
3918 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3919 __func__,
3920 dev->invalidate_domains,
3921 dev->flush_domains);
3922#endif
3923 i915_gem_flush(dev,
3924 dev->invalidate_domains,
3925 dev->flush_domains);
99fcb766 3926 if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
b962442e
EA		 3927 (void)i915_add_request(dev, file_priv,
3928 dev->flush_domains);
646f0f6e 3929 }
673a394b 3930
efbeed96
EA		 3931 for (i = 0; i < args->buffer_count; i++) {
3932 struct drm_gem_object *obj = object_list[i];
23010e43 3933 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3934 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3935
3936 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3937 if (obj->write_domain)
3938 list_move_tail(&obj_priv->gpu_write_list,
3939 &dev_priv->mm.gpu_write_list);
3940 else
3941 list_del_init(&obj_priv->gpu_write_list);
3942
1c5d22f7
CW		 3943 trace_i915_gem_object_change_domain(obj,
3944 obj->read_domains,
3945 old_write_domain);
efbeed96
EA		 3946 }
3947
673a394b
EA		 3948 i915_verify_inactive(dev, __FILE__, __LINE__);
3949
3950#if WATCH_COHERENCY
3951 for (i = 0; i < args->buffer_count; i++) {
3952 i915_gem_object_check_coherency(object_list[i],
3953 exec_list[i].handle);
3954 }
3955#endif
3956
673a394b 3957#if WATCH_EXEC
6911a9b8 3958 i915_gem_dump_object(batch_obj,
673a394b
EA		 3959 args->batch_len,
3960 __func__,
3961 ~0);
3962#endif
3963
673a394b 3964 /* Exec the batchbuffer */
201361a5 3965 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
673a394b
EA		 3966 if (ret) {
3967 DRM_ERROR("dispatch failed %d\n", ret);
3968 goto err;
3969 }
3970
3971 /*
3972 * Ensure that the commands in the batch buffer are
3973 * finished before the interrupt fires
3974 */
3975 flush_domains = i915_retire_commands(dev);
3976
3977 i915_verify_inactive(dev, __FILE__, __LINE__);
3978
3979 /*
3980 * Get a seqno representing the execution of the current buffer,
3981 * which we can wait on. We would like to mitigate these interrupts,
3982 * likely by only creating seqnos occasionally (so that we have
3983 * *some* interrupts representing completion of buffers that we can
3984 * wait on when trying to clear up gtt space).
3985 */
b962442e 3986 seqno = i915_add_request(dev, file_priv, flush_domains);
673a394b 3987 BUG_ON(seqno == 0);
673a394b
EA		 3988 for (i = 0; i < args->buffer_count; i++) {
3989 struct drm_gem_object *obj = object_list[i];
673a394b 3990
ce44b0ea 3991 i915_gem_object_move_to_active(obj, seqno);
673a394b
EA		 3992#if WATCH_LRU
3993 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3994#endif
3995 }
3996#if WATCH_LRU
3997 i915_dump_lru(dev, __func__);
3998#endif
3999
4000 i915_verify_inactive(dev, __FILE__, __LINE__);
4001
673a394b 4002err:
aad87dff
JL		 4003 for (i = 0; i < pinned; i++)
4004 i915_gem_object_unpin(object_list[i]);
4005
b70d11da
KH		 4006 for (i = 0; i < args->buffer_count; i++) {
4007 if (object_list[i]) {
23010e43 4008 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 4009 obj_priv->in_execbuffer = false;
4010 }
aad87dff 4011 drm_gem_object_unreference(object_list[i]);
b70d11da 4012 }
673a394b 4013
673a394b
EA		 4014 mutex_unlock(&dev->struct_mutex);
4015
93533c29 4016pre_mutex_err:
40a5f0de
EA		 4017 /* Copy the updated relocations out regardless of current error
4018 * state. Failure to update the relocs would mean that the next
4019 * time userland calls execbuf, it would do so with presumed offset
4020 * state that didn't match the actual object state.
4021 */
4022 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4023 relocs);
4024 if (ret2 != 0) {
4025 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4026
4027 if (ret == 0)
4028 ret = ret2;
4029 }
4030
8e7d2b2c 4031 drm_free_large(object_list);
9a298b2a 4032 kfree(cliprects);
673a394b
EA		 4033
4034 return ret;
4035}
4036
76446cac
JB		 4037/*
4038 * Legacy execbuffer just creates an exec2 list from the original exec object
4039 * list array and passes it to the real function.
4040 */
4041int
4042i915_gem_execbuffer(struct drm_device *dev, void *data,
4043 struct drm_file *file_priv)
4044{
4045 struct drm_i915_gem_execbuffer *args = data;
4046 struct drm_i915_gem_execbuffer2 exec2;
4047 struct drm_i915_gem_exec_object *exec_list = NULL;
4048 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4049 int ret, i;
4050
4051#if WATCH_EXEC
4052 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4053 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4054#endif
4055
4056 if (args->buffer_count < 1) {
4057 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4058 return -EINVAL;
4059 }
4060
4061 /* Copy in the exec list from userland */
4062 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4063 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4064 if (exec_list == NULL || exec2_list == NULL) {
4065 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4066 args->buffer_count);
4067 drm_free_large(exec_list);
4068 drm_free_large(exec2_list);
4069 return -ENOMEM;
4070 }
4071 ret = copy_from_user(exec_list,
4072 (struct drm_i915_relocation_entry __user *)
4073 (uintptr_t) args->buffers_ptr,
4074 sizeof(*exec_list) * args->buffer_count);
4075 if (ret != 0) {
4076 DRM_ERROR("copy %d exec entries failed %d\n",
4077 args->buffer_count, ret);
4078 drm_free_large(exec_list);
4079 drm_free_large(exec2_list);
4080 return -EFAULT;
4081 }
4082
4083 for (i = 0; i < args->buffer_count; i++) {
4084 exec2_list[i].handle = exec_list[i].handle;
4085 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4086 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4087 exec2_list[i].alignment = exec_list[i].alignment;
4088 exec2_list[i].offset = exec_list[i].offset;
4089 if (!IS_I965G(dev))
4090 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4091 else
4092 exec2_list[i].flags = 0;
4093 }
4094
4095 exec2.buffers_ptr = args->buffers_ptr;
4096 exec2.buffer_count = args->buffer_count;
4097 exec2.batch_start_offset = args->batch_start_offset;
4098 exec2.batch_len = args->batch_len;
4099 exec2.DR1 = args->DR1;
4100 exec2.DR4 = args->DR4;
4101 exec2.num_cliprects = args->num_cliprects;
4102 exec2.cliprects_ptr = args->cliprects_ptr;
4103 exec2.flags = 0;
4104
4105 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4106 if (!ret) {
4107 /* Copy the new buffer offsets back to the user's exec list. */
4108 for (i = 0; i < args->buffer_count; i++)
4109 exec_list[i].offset = exec2_list[i].offset;
4110 /* ... and back out to userspace */
4111 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4112 (uintptr_t) args->buffers_ptr,
4113 exec_list,
4114 sizeof(*exec_list) * args->buffer_count);
4115 if (ret) {
4116 ret = -EFAULT;
4117 DRM_ERROR("failed to copy %d exec entries "
4118 "back to user (%d)\n",
4119 args->buffer_count, ret);
4120 }
76446cac
JB		 4121 }
4122
4123 drm_free_large(exec_list);
4124 drm_free_large(exec2_list);
4125 return ret;
4126}
4127
4128int
4129i915_gem_execbuffer2(struct drm_device *dev, void *data,
4130 struct drm_file *file_priv)
4131{
4132 struct drm_i915_gem_execbuffer2 *args = data;
4133 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4134 int ret;
4135
4136#if WATCH_EXEC
4137 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4138 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4139#endif
4140
4141 if (args->buffer_count < 1) {
4142 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4143 return -EINVAL;
4144 }
4145
4146 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4147 if (exec2_list == NULL) {
4148 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4149 args->buffer_count);
4150 return -ENOMEM;
4151 }
4152 ret = copy_from_user(exec2_list,
4153 (struct drm_i915_relocation_entry __user *)
4154 (uintptr_t) args->buffers_ptr,
4155 sizeof(*exec2_list) * args->buffer_count);
4156 if (ret != 0) {
4157 DRM_ERROR("copy %d exec entries failed %d\n",
4158 args->buffer_count, ret);
4159 drm_free_large(exec2_list);
4160 return -EFAULT;
4161 }
4162
4163 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4164 if (!ret) {
4165 /* Copy the new buffer offsets back to the user's exec list. */
4166 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4167 (uintptr_t) args->buffers_ptr,
4168 exec2_list,
4169 sizeof(*exec2_list) * args->buffer_count);
4170 if (ret) {
4171 ret = -EFAULT;
4172 DRM_ERROR("failed to copy %d exec entries "
4173 "back to user (%d)\n",
4174 args->buffer_count, ret);
4175 }
4176 }
4177
4178 drm_free_large(exec2_list);
4179 return ret;
4180}
4181
673a394b
EA		 4182int
4183i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4184{
4185 struct drm_device *dev = obj->dev;
23010e43 4186 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4187 int ret;
4188
4189 i915_verify_inactive(dev, __FILE__, __LINE__);
4190 if (obj_priv->gtt_space == NULL) {
4191 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4192 if (ret)
673a394b 4193 return ret;
22c344e9 4194 }
76446cac 4195
673a394b
EA		 4196 obj_priv->pin_count++;
4197
4198 /* If the object is not active and not pending a flush,
4199 * remove it from the inactive list
4200 */
4201 if (obj_priv->pin_count == 1) {
4202 atomic_inc(&dev->pin_count);
4203 atomic_add(obj->size, &dev->pin_memory);
4204 if (!obj_priv->active &&
21d509e3 4205 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 4206 !list_empty(&obj_priv->list))
4207 list_del_init(&obj_priv->list);
4208 }
4209 i915_verify_inactive(dev, __FILE__, __LINE__);
4210
4211 return 0;
4212}
4213
4214void
4215i915_gem_object_unpin(struct drm_gem_object *obj)
4216{
4217 struct drm_device *dev = obj->dev;
4218 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4219 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4220
4221 i915_verify_inactive(dev, __FILE__, __LINE__);
4222 obj_priv->pin_count--;
4223 BUG_ON(obj_priv->pin_count < 0);
4224 BUG_ON(obj_priv->gtt_space == NULL);
4225
4226 /* If the object is no longer pinned, and is
4227 * neither active nor being flushed, then stick it on
4228 * the inactive list
4229 */
4230 if (obj_priv->pin_count == 0) {
4231 if (!obj_priv->active &&
21d509e3 4232 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4233 list_move_tail(&obj_priv->list,
4234 &dev_priv->mm.inactive_list);
4235 atomic_dec(&dev->pin_count);
4236 atomic_sub(obj->size, &dev->pin_memory);
4237 }
4238 i915_verify_inactive(dev, __FILE__, __LINE__);
4239}
4240
4241int
4242i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4243 struct drm_file *file_priv)
4244{
4245 struct drm_i915_gem_pin *args = data;
4246 struct drm_gem_object *obj;
4247 struct drm_i915_gem_object *obj_priv;
4248 int ret;
4249
4250 mutex_lock(&dev->struct_mutex);
4251
4252 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4253 if (obj == NULL) {
4254 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4255 args->handle);
4256 mutex_unlock(&dev->struct_mutex);
4257 return -EBADF;
4258 }
23010e43 4259 obj_priv = to_intel_bo(obj);
673a394b 4260
bb6baf76
CW		 4261 if (obj_priv->madv != I915_MADV_WILLNEED) {
4262 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4263 drm_gem_object_unreference(obj);
4264 mutex_unlock(&dev->struct_mutex);
4265 return -EINVAL;
4266 }
4267
79e53945
JB		 4268 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4269 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4270 args->handle);
96dec61d 4271 drm_gem_object_unreference(obj);
673a394b 4272 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4273 return -EINVAL;
4274 }
4275
4276 obj_priv->user_pin_count++;
4277 obj_priv->pin_filp = file_priv;
4278 if (obj_priv->user_pin_count == 1) {
4279 ret = i915_gem_object_pin(obj, args->alignment);
4280 if (ret != 0) {
4281 drm_gem_object_unreference(obj);
4282 mutex_unlock(&dev->struct_mutex);
4283 return ret;
4284 }
673a394b
EA		 4285 }
4286
4287 /* XXX - flush the CPU caches for pinned objects
4288 * as the X server doesn't manage domains yet
4289 */
e47c68e9 4290 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4291 args->offset = obj_priv->gtt_offset;
4292 drm_gem_object_unreference(obj);
4293 mutex_unlock(&dev->struct_mutex);
4294
4295 return 0;
4296}
4297
4298int
4299i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4300 struct drm_file *file_priv)
4301{
4302 struct drm_i915_gem_pin *args = data;
4303 struct drm_gem_object *obj;
79e53945 4304 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4305
4306 mutex_lock(&dev->struct_mutex);
4307
4308 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4309 if (obj == NULL) {
4310 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4311 args->handle);
4312 mutex_unlock(&dev->struct_mutex);
4313 return -EBADF;
4314 }
4315
23010e43 4316 obj_priv = to_intel_bo(obj);
79e53945
JB		 4317 if (obj_priv->pin_filp != file_priv) {
4318 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4319 args->handle);
4320 drm_gem_object_unreference(obj);
4321 mutex_unlock(&dev->struct_mutex);
4322 return -EINVAL;
4323 }
4324 obj_priv->user_pin_count--;
4325 if (obj_priv->user_pin_count == 0) {
4326 obj_priv->pin_filp = NULL;
4327 i915_gem_object_unpin(obj);
4328 }
673a394b
EA		 4329
4330 drm_gem_object_unreference(obj);
4331 mutex_unlock(&dev->struct_mutex);
4332 return 0;
4333}
4334
4335int
4336i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4337 struct drm_file *file_priv)
4338{
4339 struct drm_i915_gem_busy *args = data;
4340 struct drm_gem_object *obj;
4341 struct drm_i915_gem_object *obj_priv;
4342
673a394b
EA		 4343 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4344 if (obj == NULL) {
4345 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4346 args->handle);
673a394b
EA		 4347 return -EBADF;
4348 }
4349
b1ce786c 4350 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4351 /* Update the active list for the hardware's current position.
4352 * Otherwise this only updates on a delayed timer or when irqs are
4353 * actually unmasked, and our working set ends up being larger than
4354 * required.
4355 */
4356 i915_gem_retire_requests(dev);
4357
23010e43 4358 obj_priv = to_intel_bo(obj);
c4de0a5d
EA		 4359 /* Don't count being on the flushing list against the object being
4360 * done. Otherwise, a buffer left on the flushing list but not getting
4361 * flushed (because nobody's flushing that domain) won't ever return
4362 * unbusy and get reused by libdrm's bo cache. The other expected
4363 * consumer of this interface, OpenGL's occlusion queries, also specs
4364 * that the objects get unbusy "eventually" without any interference.
4365 */
4366 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4367
4368 drm_gem_object_unreference(obj);
4369 mutex_unlock(&dev->struct_mutex);
4370 return 0;
4371}
4372
4373int
4374i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4375 struct drm_file *file_priv)
4376{
4377 return i915_gem_ring_throttle(dev, file_priv);
4378}
4379
3ef94daa
CW		 4380int
4381i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4382 struct drm_file *file_priv)
4383{
4384 struct drm_i915_gem_madvise *args = data;
4385 struct drm_gem_object *obj;
4386 struct drm_i915_gem_object *obj_priv;
4387
4388 switch (args->madv) {
4389 case I915_MADV_DONTNEED:
4390 case I915_MADV_WILLNEED:
4391 break;
4392 default:
4393 return -EINVAL;
4394 }
4395
4396 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4397 if (obj == NULL) {
4398 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4399 args->handle);
4400 return -EBADF;
4401 }
4402
4403 mutex_lock(&dev->struct_mutex);
23010e43 4404 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4405
4406 if (obj_priv->pin_count) {
4407 drm_gem_object_unreference(obj);
4408 mutex_unlock(&dev->struct_mutex);
4409
4410 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4411 return -EINVAL;
4412 }
4413
bb6baf76
CW		 4414 if (obj_priv->madv != __I915_MADV_PURGED)
4415 obj_priv->madv = args->madv;
3ef94daa 4416
2d7ef395
CW		 4417 /* if the object is no longer bound, discard its backing storage */
4418 if (i915_gem_object_is_purgeable(obj_priv) &&
4419 obj_priv->gtt_space == NULL)
4420 i915_gem_object_truncate(obj);
4421
bb6baf76
CW		 4422 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4423
3ef94daa
CW		 4424 drm_gem_object_unreference(obj);
4425 mutex_unlock(&dev->struct_mutex);
4426
4427 return 0;
4428}
4429
673a394b
EA		 4430int i915_gem_init_object(struct drm_gem_object *obj)
4431{
4432 struct drm_i915_gem_object *obj_priv;
4433
9a298b2a 4434 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
673a394b
EA		 4435 if (obj_priv == NULL)
4436 return -ENOMEM;
4437
4438 /*
4439 * We've just allocated pages from the kernel,
4440 * so they've just been written by the CPU with
4441 * zeros. They'll need to be clflushed before we
4442 * use them with the GPU.
4443 */
4444 obj->write_domain = I915_GEM_DOMAIN_CPU;
4445 obj->read_domains = I915_GEM_DOMAIN_CPU;
4446
ba1eb1d8
KP		 4447 obj_priv->agp_type = AGP_USER_MEMORY;
4448
673a394b
EA		 4449 obj->driver_private = obj_priv;
4450 obj_priv->obj = obj;
de151cf6 4451 obj_priv->fence_reg = I915_FENCE_REG_NONE;
673a394b 4452 INIT_LIST_HEAD(&obj_priv->list);
99fcb766 4453 INIT_LIST_HEAD(&obj_priv->gpu_write_list);
a09ba7fa 4454 INIT_LIST_HEAD(&obj_priv->fence_list);
3ef94daa 4455 obj_priv->madv = I915_MADV_WILLNEED;
de151cf6 4456
1c5d22f7 4457 trace_i915_gem_object_create(obj);
de151cf6 4458
673a394b
EA		 4459 return 0;
4460}
4461
4462void i915_gem_free_object(struct drm_gem_object *obj)
4463{
de151cf6 4464 struct drm_device *dev = obj->dev;
23010e43 4465 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 4466
1c5d22f7
CW		 4467 trace_i915_gem_object_destroy(obj);
4468
673a394b
EA		 4469 while (obj_priv->pin_count > 0)
4470 i915_gem_object_unpin(obj);
4471
71acb5eb
DA		 4472 if (obj_priv->phys_obj)
4473 i915_gem_detach_phys_object(dev, obj);
4474
673a394b
EA		 4475 i915_gem_object_unbind(obj);
4476
7e616158
CW		 4477 if (obj_priv->mmap_offset)
4478 i915_gem_free_mmap_offset(obj);
de151cf6 4479
9a298b2a 4480 kfree(obj_priv->page_cpu_valid);
280b713b 4481 kfree(obj_priv->bit_17);
9a298b2a 4482 kfree(obj->driver_private);
673a394b
EA		 4483}
4484
ab5ee576 4485/** Unbinds all inactive objects. */
673a394b 4486static int
ab5ee576 4487i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4488{
ab5ee576 4489 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4490
ab5ee576
CW		 4491 while (!list_empty(&dev_priv->mm.inactive_list)) {
4492 struct drm_gem_object *obj;
4493 int ret;
673a394b 4494
ab5ee576
CW		 4495 obj = list_first_entry(&dev_priv->mm.inactive_list,
4496 struct drm_i915_gem_object,
4497 list)->obj;
673a394b
EA		 4498
4499 ret = i915_gem_object_unbind(obj);
4500 if (ret != 0) {
ab5ee576 4501 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4502 return ret;
4503 }
4504 }
4505
673a394b
EA		 4506 return 0;
4507}
4508
29105ccc
CW		 4509int
4510i915_gem_idle(struct drm_device *dev)
4511{
4512 drm_i915_private_t *dev_priv = dev->dev_private;
4513 int ret;
28dfe52a 4514
29105ccc 4515 mutex_lock(&dev->struct_mutex);
1c5d22f7 4516
29105ccc
CW		 4517 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4518 mutex_unlock(&dev->struct_mutex);
4519 return 0;
28dfe52a
EA		 4520 }
4521
29105ccc 4522 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4523 if (ret) {
4524 mutex_unlock(&dev->struct_mutex);
673a394b 4525 return ret;
6dbe2772 4526 }
673a394b 4527
29105ccc
CW		 4528 /* Under UMS, be paranoid and evict. */
4529 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4530 ret = i915_gem_evict_from_inactive_list(dev);
4531 if (ret) {
4532 mutex_unlock(&dev->struct_mutex);
4533 return ret;
4534 }
4535 }
4536
4537 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4538 * We need to replace this with a semaphore, or something.
4539 * And not confound mm.suspended!
4540 */
4541 dev_priv->mm.suspended = 1;
4542 del_timer(&dev_priv->hangcheck_timer);
4543
4544 i915_kernel_lost_context(dev);
6dbe2772 4545 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4546
6dbe2772
KP		 4547 mutex_unlock(&dev->struct_mutex);
4548
29105ccc
CW		 4549 /* Cancel the retire work handler, which should be idle now. */
4550 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4551
673a394b
EA		 4552 return 0;
4553}
4554
4555static int
4556i915_gem_init_hws(struct drm_device *dev)
4557{
4558 drm_i915_private_t *dev_priv = dev->dev_private;
4559 struct drm_gem_object *obj;
4560 struct drm_i915_gem_object *obj_priv;
4561 int ret;
4562
4563 /* If we need a physical address for the status page, it's already
4564 * initialized at driver load time.
4565 */
4566 if (!I915_NEED_GFX_HWS(dev))
4567 return 0;
4568
4569 obj = drm_gem_object_alloc(dev, 4096);
4570 if (obj == NULL) {
4571 DRM_ERROR("Failed to allocate status page\n");
4572 return -ENOMEM;
4573 }
23010e43 4574 obj_priv = to_intel_bo(obj);
ba1eb1d8 4575 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
673a394b
EA		 4576
4577 ret = i915_gem_object_pin(obj, 4096);
4578 if (ret != 0) {
4579 drm_gem_object_unreference(obj);
4580 return ret;
4581 }
4582
4583 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
673a394b 4584
856fa198 4585 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
ba1eb1d8 4586 if (dev_priv->hw_status_page == NULL) {
673a394b
EA		 4587 DRM_ERROR("Failed to map status page.\n");
4588 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3eb2ee77 4589 i915_gem_object_unpin(obj);
673a394b
EA		 4590 drm_gem_object_unreference(obj);
4591 return -EINVAL;
4592 }
4593 dev_priv->hws_obj = obj;
673a394b 4594 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
f6e450a6
EA		 4595 if (IS_GEN6(dev)) {
4596 I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
4597 I915_READ(HWS_PGA_GEN6); /* posting read */
4598 } else {
4599 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4600 I915_READ(HWS_PGA); /* posting read */
4601 }
44d98a61 4602 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
673a394b
EA		 4603
4604 return 0;
4605}
4606
85a7bb98
CW		 4607static void
4608i915_gem_cleanup_hws(struct drm_device *dev)
4609{
4610 drm_i915_private_t *dev_priv = dev->dev_private;
bab2d1f6
CW		 4611 struct drm_gem_object *obj;
4612 struct drm_i915_gem_object *obj_priv;
85a7bb98
CW		 4613
4614 if (dev_priv->hws_obj == NULL)
4615 return;
4616
bab2d1f6 4617 obj = dev_priv->hws_obj;
23010e43 4618 obj_priv = to_intel_bo(obj);
bab2d1f6 4619
856fa198 4620 kunmap(obj_priv->pages[0]);
85a7bb98
CW		 4621 i915_gem_object_unpin(obj);
4622 drm_gem_object_unreference(obj);
4623 dev_priv->hws_obj = NULL;
bab2d1f6 4624
85a7bb98
CW		 4625 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4626 dev_priv->hw_status_page = NULL;
4627
4628 /* Write high address into HWS_PGA when disabling. */
4629 I915_WRITE(HWS_PGA, 0x1ffff000);
4630}
4631
79e53945 4632int
673a394b
EA		 4633i915_gem_init_ringbuffer(struct drm_device *dev)
4634{
4635 drm_i915_private_t *dev_priv = dev->dev_private;
4636 struct drm_gem_object *obj;
4637 struct drm_i915_gem_object *obj_priv;
79e53945 4638 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
673a394b 4639 int ret;
50aa253d 4640 u32 head;
673a394b
EA		 4641
4642 ret = i915_gem_init_hws(dev);
4643 if (ret != 0)
4644 return ret;
4645
4646 obj = drm_gem_object_alloc(dev, 128 * 1024);
4647 if (obj == NULL) {
4648 DRM_ERROR("Failed to allocate ringbuffer\n");
85a7bb98 4649 i915_gem_cleanup_hws(dev);
673a394b
EA		 4650 return -ENOMEM;
4651 }
23010e43 4652 obj_priv = to_intel_bo(obj);
673a394b
EA		 4653
4654 ret = i915_gem_object_pin(obj, 4096);
4655 if (ret != 0) {
4656 drm_gem_object_unreference(obj);
85a7bb98 4657 i915_gem_cleanup_hws(dev);
673a394b
EA		 4658 return ret;
4659 }
4660
4661 /* Set up the kernel mapping for the ring. */
79e53945 4662 ring->Size = obj->size;
673a394b 4663
79e53945
JB		 4664 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4665 ring->map.size = obj->size;
4666 ring->map.type = 0;
4667 ring->map.flags = 0;
4668 ring->map.mtrr = 0;
673a394b 4669
79e53945
JB		 4670 drm_core_ioremap_wc(&ring->map, dev);
4671 if (ring->map.handle == NULL) {
673a394b
EA		 4672 DRM_ERROR("Failed to map ringbuffer.\n");
4673 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
47ed185a 4674 i915_gem_object_unpin(obj);
673a394b 4675 drm_gem_object_unreference(obj);
85a7bb98 4676 i915_gem_cleanup_hws(dev);
673a394b
EA		 4677 return -EINVAL;
4678 }
79e53945
JB		 4679 ring->ring_obj = obj;
4680 ring->virtual_start = ring->map.handle;
673a394b
EA		 4681
4682 /* Stop the ring if it's running. */
4683 I915_WRITE(PRB0_CTL, 0);
673a394b 4684 I915_WRITE(PRB0_TAIL, 0);
50aa253d 4685 I915_WRITE(PRB0_HEAD, 0);
673a394b
EA		 4686
4687 /* Initialize the ring. */
4688 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
50aa253d
KP		 4689 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4690
4691 /* G45 ring initialization fails to reset head to zero */
4692 if (head != 0) {
4693 DRM_ERROR("Ring head not reset to zero "
4694 "ctl %08x head %08x tail %08x start %08x\n",
4695 I915_READ(PRB0_CTL),
4696 I915_READ(PRB0_HEAD),
4697 I915_READ(PRB0_TAIL),
4698 I915_READ(PRB0_START));
4699 I915_WRITE(PRB0_HEAD, 0);
4700
4701 DRM_ERROR("Ring head forced to zero "
4702 "ctl %08x head %08x tail %08x start %08x\n",
4703 I915_READ(PRB0_CTL),
4704 I915_READ(PRB0_HEAD),
4705 I915_READ(PRB0_TAIL),
4706 I915_READ(PRB0_START));
4707 }
4708
673a394b
EA		 4709 I915_WRITE(PRB0_CTL,
4710 ((obj->size - 4096) & RING_NR_PAGES) |
4711 RING_NO_REPORT |
4712 RING_VALID);
4713
50aa253d
KP		 4714 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4715
4716 /* If the head is still not zero, the ring is dead */
4717 if (head != 0) {
4718 DRM_ERROR("Ring initialization failed "
4719 "ctl %08x head %08x tail %08x start %08x\n",
4720 I915_READ(PRB0_CTL),
4721 I915_READ(PRB0_HEAD),
4722 I915_READ(PRB0_TAIL),
4723 I915_READ(PRB0_START));
4724 return -EIO;
4725 }
4726
673a394b 4727 /* Update our cache of the ring state */
79e53945
JB		 4728 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4729 i915_kernel_lost_context(dev);
4730 else {
4731 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4732 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4733 ring->space = ring->head - (ring->tail + 8);
4734 if (ring->space < 0)
4735 ring->space += ring->Size;
4736 }
673a394b 4737
71cf39b1
EA		 4738 if (IS_I9XX(dev) && !IS_GEN3(dev)) {
4739 I915_WRITE(MI_MODE,
4740 (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
4741 }
4742
673a394b
EA		 4743 return 0;
4744}
4745
79e53945 4746void
673a394b
EA		 4747i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4748{
4749 drm_i915_private_t *dev_priv = dev->dev_private;
4750
4751 if (dev_priv->ring.ring_obj == NULL)
4752 return;
4753
4754 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4755
4756 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4757 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4758 dev_priv->ring.ring_obj = NULL;
4759 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4760
85a7bb98 4761 i915_gem_cleanup_hws(dev);
673a394b
EA		 4762}
4763
4764int
4765i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4766 struct drm_file *file_priv)
4767{
4768 drm_i915_private_t *dev_priv = dev->dev_private;
4769 int ret;
4770
79e53945
JB		 4771 if (drm_core_check_feature(dev, DRIVER_MODESET))
4772 return 0;
4773
ba1234d1 4774 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4775 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4776 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4777 }
4778
673a394b 4779 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4780 dev_priv->mm.suspended = 0;
4781
4782 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4783 if (ret != 0) {
4784 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4785 return ret;
d816f6ac 4786 }
9bb2d6f9 4787
5e118f41 4788 spin_lock(&dev_priv->mm.active_list_lock);
673a394b 4789 BUG_ON(!list_empty(&dev_priv->mm.active_list));
5e118f41
CW		 4790 spin_unlock(&dev_priv->mm.active_list_lock);
4791
673a394b
EA		 4792 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4793 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4794 BUG_ON(!list_empty(&dev_priv->mm.request_list));
673a394b 4795 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4796
4797 drm_irq_install(dev);
4798
673a394b
EA		 4799 return 0;
4800}
4801
4802int
4803i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4804 struct drm_file *file_priv)
4805{
79e53945
JB		 4806 if (drm_core_check_feature(dev, DRIVER_MODESET))
4807 return 0;
4808
dbb19d30 4809 drm_irq_uninstall(dev);
e6890f6f 4810 return i915_gem_idle(dev);
673a394b
EA		 4811}
4812
4813void
4814i915_gem_lastclose(struct drm_device *dev)
4815{
4816 int ret;
673a394b 4817
e806b495
EA		 4818 if (drm_core_check_feature(dev, DRIVER_MODESET))
4819 return;
4820
6dbe2772
KP		 4821 ret = i915_gem_idle(dev);
4822 if (ret)
4823 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4824}
4825
4826void
4827i915_gem_load(struct drm_device *dev)
4828{
b5aa8a0f 4829 int i;
673a394b
EA		 4830 drm_i915_private_t *dev_priv = dev->dev_private;
4831
5e118f41 4832 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b
EA		 4833 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4834 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4835 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b
EA		 4836 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4837 INIT_LIST_HEAD(&dev_priv->mm.request_list);
a09ba7fa 4838 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
673a394b
EA		 4839 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4840 i915_gem_retire_work_handler);
4841 dev_priv->mm.next_gem_seqno = 1;
4842
31169714
CW		 4843 spin_lock(&shrink_list_lock);
4844 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4845 spin_unlock(&shrink_list_lock);
4846
de151cf6 4847 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4848 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4849 dev_priv->fence_reg_start = 3;
de151cf6 4850
0f973f27 4851 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4852 dev_priv->num_fence_regs = 16;
4853 else
4854 dev_priv->num_fence_regs = 8;
4855
b5aa8a0f
GH		 4856 /* Initialize fence registers to zero */
4857 if (IS_I965G(dev)) {
4858 for (i = 0; i < 16; i++)
4859 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4860 } else {
4861 for (i = 0; i < 8; i++)
4862 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4863 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4864 for (i = 0; i < 8; i++)
4865 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4866 }
673a394b 4867 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4868 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4869}
71acb5eb
DA		 4870
4871/*
4872 * Create a physically contiguous memory object for this object
4873 * e.g. for cursor + overlay regs
4874 */
4875int i915_gem_init_phys_object(struct drm_device *dev,
4876 int id, int size)
4877{
4878 drm_i915_private_t *dev_priv = dev->dev_private;
4879 struct drm_i915_gem_phys_object *phys_obj;
4880 int ret;
4881
4882 if (dev_priv->mm.phys_objs[id - 1] || !size)
4883 return 0;
4884
9a298b2a 4885 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4886 if (!phys_obj)
4887 return -ENOMEM;
4888
4889 phys_obj->id = id;
4890
e6be8d9d 4891 phys_obj->handle = drm_pci_alloc(dev, size, 0);
71acb5eb
DA		 4892 if (!phys_obj->handle) {
4893 ret = -ENOMEM;
4894 goto kfree_obj;
4895 }
4896#ifdef CONFIG_X86
4897 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4898#endif
4899
4900 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4901
4902 return 0;
4903kfree_obj:
9a298b2a 4904 kfree(phys_obj);
71acb5eb
DA		 4905 return ret;
4906}
4907
4908void i915_gem_free_phys_object(struct drm_device *dev, int id)
4909{
4910 drm_i915_private_t *dev_priv = dev->dev_private;
4911 struct drm_i915_gem_phys_object *phys_obj;
4912
4913 if (!dev_priv->mm.phys_objs[id - 1])
4914 return;
4915
4916 phys_obj = dev_priv->mm.phys_objs[id - 1];
4917 if (phys_obj->cur_obj) {
4918 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4919 }
4920
4921#ifdef CONFIG_X86
4922 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4923#endif
4924 drm_pci_free(dev, phys_obj->handle);
4925 kfree(phys_obj);
4926 dev_priv->mm.phys_objs[id - 1] = NULL;
4927}
4928
4929void i915_gem_free_all_phys_object(struct drm_device *dev)
4930{
4931 int i;
4932
260883c8 4933 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4934 i915_gem_free_phys_object(dev, i);
4935}
4936
4937void i915_gem_detach_phys_object(struct drm_device *dev,
4938 struct drm_gem_object *obj)
4939{
4940 struct drm_i915_gem_object *obj_priv;
4941 int i;
4942 int ret;
4943 int page_count;
4944
23010e43 4945 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4946 if (!obj_priv->phys_obj)
4947 return;
4948
4bdadb97 4949 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4950 if (ret)
4951 goto out;
4952
4953 page_count = obj->size / PAGE_SIZE;
4954
4955 for (i = 0; i < page_count; i++) {
856fa198 4956 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4957 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4958
4959 memcpy(dst, src, PAGE_SIZE);
4960 kunmap_atomic(dst, KM_USER0);
4961 }
856fa198 4962 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4963 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4964
4965 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4966out:
4967 obj_priv->phys_obj->cur_obj = NULL;
4968 obj_priv->phys_obj = NULL;
4969}
4970
4971int
4972i915_gem_attach_phys_object(struct drm_device *dev,
4973 struct drm_gem_object *obj, int id)
4974{
4975 drm_i915_private_t *dev_priv = dev->dev_private;
4976 struct drm_i915_gem_object *obj_priv;
4977 int ret = 0;
4978 int page_count;
4979 int i;
4980
4981 if (id > I915_MAX_PHYS_OBJECT)
4982 return -EINVAL;
4983
23010e43 4984 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4985
4986 if (obj_priv->phys_obj) {
4987 if (obj_priv->phys_obj->id == id)
4988 return 0;
4989 i915_gem_detach_phys_object(dev, obj);
4990 }
4991
4992
4993 /* create a new object */
4994 if (!dev_priv->mm.phys_objs[id - 1]) {
4995 ret = i915_gem_init_phys_object(dev, id,
4996 obj->size);
4997 if (ret) {
aeb565df 4998 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4999 goto out;
5000 }
5001 }
5002
5003 /* bind to the object */
5004 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
5005 obj_priv->phys_obj->cur_obj = obj;
5006
4bdadb97 5007 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 5008 if (ret) {
5009 DRM_ERROR("failed to get page list\n");
5010 goto out;
5011 }
5012
5013 page_count = obj->size / PAGE_SIZE;
5014
5015 for (i = 0; i < page_count; i++) {
856fa198 5016 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 5017 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
5018
5019 memcpy(dst, src, PAGE_SIZE);
5020 kunmap_atomic(src, KM_USER0);
5021 }
5022
d78b47b9
CW		 5023 i915_gem_object_put_pages(obj);
5024
71acb5eb
DA		 5025 return 0;
5026out:
5027 return ret;
5028}
5029
5030static int
5031i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
5032 struct drm_i915_gem_pwrite *args,
5033 struct drm_file *file_priv)
5034{
23010e43 5035 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 5036 void *obj_addr;
5037 int ret;
5038 char __user *user_data;
5039
5040 user_data = (char __user *) (uintptr_t) args->data_ptr;
5041 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5042
44d98a61 5043 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 5044 ret = copy_from_user(obj_addr, user_data, args->size);
5045 if (ret)
5046 return -EFAULT;
5047
5048 drm_agp_chipset_flush(dev);
5049 return 0;
5050}
b962442e
EA		 5051
5052void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5053{
5054 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5055
5056 /* Clean up our request list when the client is going away, so that
5057 * later retire_requests won't dereference our soon-to-be-gone
5058 * file_priv.
5059 */
5060 mutex_lock(&dev->struct_mutex);
5061 while (!list_empty(&i915_file_priv->mm.request_list))
5062 list_del_init(i915_file_priv->mm.request_list.next);
5063 mutex_unlock(&dev->struct_mutex);
5064}
31169714 5065
31169714
CW		 5066static int
5067i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
5068{
5069 drm_i915_private_t *dev_priv, *next_dev;
5070 struct drm_i915_gem_object *obj_priv, *next_obj;
5071 int cnt = 0;
5072 int would_deadlock = 1;
5073
5074 /* "fast-path" to count number of available objects */
5075 if (nr_to_scan == 0) {
5076 spin_lock(&shrink_list_lock);
5077 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5078 struct drm_device *dev = dev_priv->dev;
5079
5080 if (mutex_trylock(&dev->struct_mutex)) {
5081 list_for_each_entry(obj_priv,
5082 &dev_priv->mm.inactive_list,
5083 list)
5084 cnt++;
5085 mutex_unlock(&dev->struct_mutex);
5086 }
5087 }
5088 spin_unlock(&shrink_list_lock);
5089
5090 return (cnt / 100) * sysctl_vfs_cache_pressure;
5091 }
5092
5093 spin_lock(&shrink_list_lock);
5094
5095 /* first scan for clean buffers */
5096 list_for_each_entry_safe(dev_priv, next_dev,
5097 &shrink_list, mm.shrink_list) {
5098 struct drm_device *dev = dev_priv->dev;
5099
5100 if (! mutex_trylock(&dev->struct_mutex))
5101 continue;
5102
5103 spin_unlock(&shrink_list_lock);
5104
5105 i915_gem_retire_requests(dev);
5106
5107 list_for_each_entry_safe(obj_priv, next_obj,
5108 &dev_priv->mm.inactive_list,
5109 list) {
5110 if (i915_gem_object_is_purgeable(obj_priv)) {
963b4836 5111 i915_gem_object_unbind(obj_priv->obj);
31169714
CW		 5112 if (--nr_to_scan <= 0)
5113 break;
5114 }
5115 }
5116
5117 spin_lock(&shrink_list_lock);
5118 mutex_unlock(&dev->struct_mutex);
5119
963b4836
CW		 5120 would_deadlock = 0;
5121
31169714
CW		 5122 if (nr_to_scan <= 0)
5123 break;
5124 }
5125
5126 /* second pass, evict/count anything still on the inactive list */
5127 list_for_each_entry_safe(dev_priv, next_dev,
5128 &shrink_list, mm.shrink_list) {
5129 struct drm_device *dev = dev_priv->dev;
5130
5131 if (! mutex_trylock(&dev->struct_mutex))
5132 continue;
5133
5134 spin_unlock(&shrink_list_lock);
5135
5136 list_for_each_entry_safe(obj_priv, next_obj,
5137 &dev_priv->mm.inactive_list,
5138 list) {
5139 if (nr_to_scan > 0) {
963b4836 5140 i915_gem_object_unbind(obj_priv->obj);
31169714
CW		 5141 nr_to_scan--;
5142 } else
5143 cnt++;
5144 }
5145
5146 spin_lock(&shrink_list_lock);
5147 mutex_unlock(&dev->struct_mutex);
5148
5149 would_deadlock = 0;
5150 }
5151
5152 spin_unlock(&shrink_list_lock);
5153
5154 if (would_deadlock)
5155 return -1;
5156 else if (cnt > 0)
5157 return (cnt / 100) * sysctl_vfs_cache_pressure;
5158 else
5159 return 0;
5160}
5161
5162static struct shrinker shrinker = {
5163 .shrink = i915_gem_shrink,
5164 .seeks = DEFAULT_SEEKS,
5165};
5166
5167__init void
5168i915_gem_shrinker_init(void)
5169{
5170 register_shrinker(&shrinker);
5171}
5172
5173__exit void
5174i915_gem_shrinker_exit(void)
5175{
5176 unregister_shrinker(&shrinker);
5177}
Clone of davem's net-next-2.6 tree