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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
0839ccb8 | 34 | #include <linux/io-mapping.h> |
585fb111 | 35 | |
1da177e4 LT |
36 | /* General customization: |
37 | */ | |
38 | ||
39 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
40 | ||
41 | #define DRIVER_NAME "i915" | |
42 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 43 | #define DRIVER_DATE "20080730" |
1da177e4 | 44 | |
317c35d1 JB |
45 | enum pipe { |
46 | PIPE_A = 0, | |
47 | PIPE_B, | |
48 | }; | |
49 | ||
52440211 KP |
50 | #define I915_NUM_PIPE 2 |
51 | ||
1da177e4 LT |
52 | /* Interface history: |
53 | * | |
54 | * 1.1: Original. | |
0d6aa60b DA |
55 | * 1.2: Add Power Management |
56 | * 1.3: Add vblank support | |
de227f5f | 57 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 58 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
59 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
60 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
61 | */ |
62 | #define DRIVER_MAJOR 1 | |
2228ed67 | 63 | #define DRIVER_MINOR 6 |
1da177e4 LT |
64 | #define DRIVER_PATCHLEVEL 0 |
65 | ||
673a394b EA |
66 | #define WATCH_COHERENCY 0 |
67 | #define WATCH_BUF 0 | |
68 | #define WATCH_EXEC 0 | |
69 | #define WATCH_LRU 0 | |
70 | #define WATCH_RELOC 0 | |
71 | #define WATCH_INACTIVE 0 | |
72 | #define WATCH_PWRITE 0 | |
73 | ||
1da177e4 LT |
74 | typedef struct _drm_i915_ring_buffer { |
75 | int tail_mask; | |
1da177e4 LT |
76 | unsigned long Size; |
77 | u8 *virtual_start; | |
78 | int head; | |
79 | int tail; | |
80 | int space; | |
81 | drm_local_map_t map; | |
673a394b | 82 | struct drm_gem_object *ring_obj; |
1da177e4 LT |
83 | } drm_i915_ring_buffer_t; |
84 | ||
85 | struct mem_block { | |
86 | struct mem_block *next; | |
87 | struct mem_block *prev; | |
88 | int start; | |
89 | int size; | |
6c340eac | 90 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
91 | }; |
92 | ||
0a3e67a4 JB |
93 | struct opregion_header; |
94 | struct opregion_acpi; | |
95 | struct opregion_swsci; | |
96 | struct opregion_asle; | |
97 | ||
8ee1c3db MG |
98 | struct intel_opregion { |
99 | struct opregion_header *header; | |
100 | struct opregion_acpi *acpi; | |
101 | struct opregion_swsci *swsci; | |
102 | struct opregion_asle *asle; | |
103 | int enabled; | |
104 | }; | |
105 | ||
1da177e4 | 106 | typedef struct drm_i915_private { |
673a394b EA |
107 | struct drm_device *dev; |
108 | ||
3043c60c | 109 | void __iomem *regs; |
1da177e4 | 110 | drm_local_map_t *sarea; |
1da177e4 LT |
111 | |
112 | drm_i915_sarea_t *sarea_priv; | |
113 | drm_i915_ring_buffer_t ring; | |
114 | ||
9c8da5eb | 115 | drm_dma_handle_t *status_page_dmah; |
1da177e4 | 116 | void *hw_status_page; |
1da177e4 | 117 | dma_addr_t dma_status_page; |
0a3e67a4 | 118 | uint32_t counter; |
dc7a9319 WZ |
119 | unsigned int status_gfx_addr; |
120 | drm_local_map_t hws_map; | |
673a394b | 121 | struct drm_gem_object *hws_obj; |
1da177e4 | 122 | |
a6b54f3f | 123 | unsigned int cpp; |
1da177e4 LT |
124 | int back_offset; |
125 | int front_offset; | |
126 | int current_page; | |
127 | int page_flipping; | |
1da177e4 LT |
128 | |
129 | wait_queue_head_t irq_queue; | |
130 | atomic_t irq_received; | |
ed4cb414 EA |
131 | /** Protects user_irq_refcount and irq_mask_reg */ |
132 | spinlock_t user_irq_lock; | |
133 | /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ | |
134 | int user_irq_refcount; | |
135 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
136 | u32 irq_mask_reg; | |
7c463586 | 137 | u32 pipestat[2]; |
1da177e4 LT |
138 | |
139 | int tex_lru_log_granularity; | |
140 | int allow_batchbuffer; | |
141 | struct mem_block *agp_heap; | |
0d6aa60b | 142 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 143 | int vblank_pipe; |
a6b54f3f | 144 | |
8ee1c3db MG |
145 | struct intel_opregion opregion; |
146 | ||
ba8bbcf6 JB |
147 | /* Register state */ |
148 | u8 saveLBB; | |
149 | u32 saveDSPACNTR; | |
150 | u32 saveDSPBCNTR; | |
e948e994 | 151 | u32 saveDSPARB; |
881ee988 | 152 | u32 saveRENDERSTANDBY; |
ba8bbcf6 JB |
153 | u32 savePIPEACONF; |
154 | u32 savePIPEBCONF; | |
155 | u32 savePIPEASRC; | |
156 | u32 savePIPEBSRC; | |
157 | u32 saveFPA0; | |
158 | u32 saveFPA1; | |
159 | u32 saveDPLL_A; | |
160 | u32 saveDPLL_A_MD; | |
161 | u32 saveHTOTAL_A; | |
162 | u32 saveHBLANK_A; | |
163 | u32 saveHSYNC_A; | |
164 | u32 saveVTOTAL_A; | |
165 | u32 saveVBLANK_A; | |
166 | u32 saveVSYNC_A; | |
167 | u32 saveBCLRPAT_A; | |
0da3ea12 | 168 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
169 | u32 saveDSPASTRIDE; |
170 | u32 saveDSPASIZE; | |
171 | u32 saveDSPAPOS; | |
585fb111 | 172 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
173 | u32 saveDSPASURF; |
174 | u32 saveDSPATILEOFF; | |
175 | u32 savePFIT_PGM_RATIOS; | |
176 | u32 saveBLC_PWM_CTL; | |
177 | u32 saveBLC_PWM_CTL2; | |
178 | u32 saveFPB0; | |
179 | u32 saveFPB1; | |
180 | u32 saveDPLL_B; | |
181 | u32 saveDPLL_B_MD; | |
182 | u32 saveHTOTAL_B; | |
183 | u32 saveHBLANK_B; | |
184 | u32 saveHSYNC_B; | |
185 | u32 saveVTOTAL_B; | |
186 | u32 saveVBLANK_B; | |
187 | u32 saveVSYNC_B; | |
188 | u32 saveBCLRPAT_B; | |
0da3ea12 | 189 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
190 | u32 saveDSPBSTRIDE; |
191 | u32 saveDSPBSIZE; | |
192 | u32 saveDSPBPOS; | |
585fb111 | 193 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
194 | u32 saveDSPBSURF; |
195 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
196 | u32 saveVGA0; |
197 | u32 saveVGA1; | |
198 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
199 | u32 saveVGACNTRL; |
200 | u32 saveADPA; | |
201 | u32 saveLVDS; | |
585fb111 JB |
202 | u32 savePP_ON_DELAYS; |
203 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
204 | u32 saveDVOA; |
205 | u32 saveDVOB; | |
206 | u32 saveDVOC; | |
207 | u32 savePP_ON; | |
208 | u32 savePP_OFF; | |
209 | u32 savePP_CONTROL; | |
585fb111 | 210 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
211 | u32 savePFIT_CONTROL; |
212 | u32 save_palette_a[256]; | |
213 | u32 save_palette_b[256]; | |
214 | u32 saveFBC_CFB_BASE; | |
215 | u32 saveFBC_LL_BASE; | |
216 | u32 saveFBC_CONTROL; | |
217 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
218 | u32 saveIER; |
219 | u32 saveIIR; | |
220 | u32 saveIMR; | |
1f84e550 | 221 | u32 saveCACHE_MODE_0; |
e948e994 | 222 | u32 saveD_STATE; |
585fb111 | 223 | u32 saveCG_2D_DIS; |
1f84e550 | 224 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
225 | u32 saveSWF0[16]; |
226 | u32 saveSWF1[16]; | |
227 | u32 saveSWF2[3]; | |
228 | u8 saveMSR; | |
229 | u8 saveSR[8]; | |
123f794f | 230 | u8 saveGR[25]; |
ba8bbcf6 | 231 | u8 saveAR_INDEX; |
a59e122a | 232 | u8 saveAR[21]; |
ba8bbcf6 JB |
233 | u8 saveDACMASK; |
234 | u8 saveDACDATA[256*3]; /* 256 3-byte colors */ | |
a59e122a | 235 | u8 saveCR[37]; |
673a394b EA |
236 | |
237 | struct { | |
238 | struct drm_mm gtt_space; | |
239 | ||
0839ccb8 KP |
240 | struct io_mapping *gtt_mapping; |
241 | ||
673a394b EA |
242 | /** |
243 | * List of objects currently involved in rendering from the | |
244 | * ringbuffer. | |
245 | * | |
246 | * A reference is held on the buffer while on this list. | |
247 | */ | |
248 | struct list_head active_list; | |
249 | ||
250 | /** | |
251 | * List of objects which are not in the ringbuffer but which | |
252 | * still have a write_domain which needs to be flushed before | |
253 | * unbinding. | |
254 | * | |
255 | * A reference is held on the buffer while on this list. | |
256 | */ | |
257 | struct list_head flushing_list; | |
258 | ||
259 | /** | |
260 | * LRU list of objects which are not in the ringbuffer and | |
261 | * are ready to unbind, but are still in the GTT. | |
262 | * | |
263 | * A reference is not held on the buffer while on this list, | |
264 | * as merely being GTT-bound shouldn't prevent its being | |
265 | * freed, and we'll pull it off the list in the free path. | |
266 | */ | |
267 | struct list_head inactive_list; | |
268 | ||
269 | /** | |
270 | * List of breadcrumbs associated with GPU requests currently | |
271 | * outstanding. | |
272 | */ | |
273 | struct list_head request_list; | |
274 | ||
275 | /** | |
276 | * We leave the user IRQ off as much as possible, | |
277 | * but this means that requests will finish and never | |
278 | * be retired once the system goes idle. Set a timer to | |
279 | * fire periodically while the ring is running. When it | |
280 | * fires, go retire requests. | |
281 | */ | |
282 | struct delayed_work retire_work; | |
283 | ||
284 | uint32_t next_gem_seqno; | |
285 | ||
286 | /** | |
287 | * Waiting sequence number, if any | |
288 | */ | |
289 | uint32_t waiting_gem_seqno; | |
290 | ||
291 | /** | |
292 | * Last seq seen at irq time | |
293 | */ | |
294 | uint32_t irq_gem_seqno; | |
295 | ||
296 | /** | |
297 | * Flag if the X Server, and thus DRM, is not currently in | |
298 | * control of the device. | |
299 | * | |
300 | * This is set between LeaveVT and EnterVT. It needs to be | |
301 | * replaced with a semaphore. It also needs to be | |
302 | * transitioned away from for kernel modesetting. | |
303 | */ | |
304 | int suspended; | |
305 | ||
306 | /** | |
307 | * Flag if the hardware appears to be wedged. | |
308 | * | |
309 | * This is set when attempts to idle the device timeout. | |
310 | * It prevents command submission from occuring and makes | |
311 | * every pending request fail | |
312 | */ | |
313 | int wedged; | |
314 | ||
315 | /** Bit 6 swizzling required for X tiling */ | |
316 | uint32_t bit_6_swizzle_x; | |
317 | /** Bit 6 swizzling required for Y tiling */ | |
318 | uint32_t bit_6_swizzle_y; | |
319 | } mm; | |
1da177e4 LT |
320 | } drm_i915_private_t; |
321 | ||
673a394b EA |
322 | /** driver private structure attached to each drm_gem_object */ |
323 | struct drm_i915_gem_object { | |
324 | struct drm_gem_object *obj; | |
325 | ||
326 | /** Current space allocated to this object in the GTT, if any. */ | |
327 | struct drm_mm_node *gtt_space; | |
328 | ||
329 | /** This object's place on the active/flushing/inactive lists */ | |
330 | struct list_head list; | |
331 | ||
332 | /** | |
333 | * This is set if the object is on the active or flushing lists | |
334 | * (has pending rendering), and is not set if it's on inactive (ready | |
335 | * to be unbound). | |
336 | */ | |
337 | int active; | |
338 | ||
339 | /** | |
340 | * This is set if the object has been written to since last bound | |
341 | * to the GTT | |
342 | */ | |
343 | int dirty; | |
344 | ||
345 | /** AGP memory structure for our GTT binding. */ | |
346 | DRM_AGP_MEM *agp_mem; | |
347 | ||
348 | struct page **page_list; | |
349 | ||
350 | /** | |
351 | * Current offset of the object in GTT space. | |
352 | * | |
353 | * This is the same as gtt_space->start | |
354 | */ | |
355 | uint32_t gtt_offset; | |
356 | ||
357 | /** Boolean whether this object has a valid gtt offset. */ | |
358 | int gtt_bound; | |
359 | ||
360 | /** How many users have pinned this object in GTT space */ | |
361 | int pin_count; | |
362 | ||
363 | /** Breadcrumb of last rendering to the buffer. */ | |
364 | uint32_t last_rendering_seqno; | |
365 | ||
366 | /** Current tiling mode for the object. */ | |
367 | uint32_t tiling_mode; | |
368 | ||
ba1eb1d8 KP |
369 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
370 | uint32_t agp_type; | |
371 | ||
673a394b EA |
372 | /** |
373 | * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when | |
374 | * GEM_DOMAIN_CPU is not in the object's read domain. | |
375 | */ | |
376 | uint8_t *page_cpu_valid; | |
377 | }; | |
378 | ||
379 | /** | |
380 | * Request queue structure. | |
381 | * | |
382 | * The request queue allows us to note sequence numbers that have been emitted | |
383 | * and may be associated with active buffers to be retired. | |
384 | * | |
385 | * By keeping this list, we can avoid having to do questionable | |
386 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
387 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
388 | */ | |
389 | struct drm_i915_gem_request { | |
390 | /** GEM sequence number associated with this request. */ | |
391 | uint32_t seqno; | |
392 | ||
393 | /** Time at which this request was emitted, in jiffies. */ | |
394 | unsigned long emitted_jiffies; | |
395 | ||
396 | /** Cache domains that were flushed at the start of the request. */ | |
397 | uint32_t flush_domains; | |
398 | ||
399 | struct list_head list; | |
400 | }; | |
401 | ||
402 | struct drm_i915_file_private { | |
403 | struct { | |
404 | uint32_t last_gem_seqno; | |
405 | uint32_t last_gem_throttle_seqno; | |
406 | } mm; | |
407 | }; | |
408 | ||
c153f45f | 409 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
410 | extern int i915_max_ioctl; |
411 | ||
1da177e4 | 412 | /* i915_dma.c */ |
84b1fd10 | 413 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 414 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 415 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 416 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 417 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
418 | extern void i915_driver_preclose(struct drm_device *dev, |
419 | struct drm_file *file_priv); | |
673a394b EA |
420 | extern void i915_driver_postclose(struct drm_device *dev, |
421 | struct drm_file *file_priv); | |
84b1fd10 | 422 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
423 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
424 | unsigned long arg); | |
673a394b EA |
425 | extern int i915_emit_box(struct drm_device *dev, |
426 | struct drm_clip_rect __user *boxes, | |
427 | int i, int DR1, int DR4); | |
af6061af | 428 | |
1da177e4 | 429 | /* i915_irq.c */ |
c153f45f EA |
430 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
431 | struct drm_file *file_priv); | |
432 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
433 | struct drm_file *file_priv); | |
673a394b EA |
434 | void i915_user_irq_get(struct drm_device *dev); |
435 | void i915_user_irq_put(struct drm_device *dev); | |
1da177e4 LT |
436 | |
437 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 438 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 439 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 440 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
441 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
442 | struct drm_file *file_priv); | |
443 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
444 | struct drm_file *file_priv); | |
0a3e67a4 JB |
445 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
446 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
447 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
c153f45f EA |
448 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
449 | struct drm_file *file_priv); | |
8ee1c3db | 450 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
1da177e4 | 451 | |
7c463586 KP |
452 | void |
453 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
454 | ||
455 | void | |
456 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
457 | ||
458 | ||
1da177e4 | 459 | /* i915_mem.c */ |
c153f45f EA |
460 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
461 | struct drm_file *file_priv); | |
462 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
463 | struct drm_file *file_priv); | |
464 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
465 | struct drm_file *file_priv); | |
466 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
467 | struct drm_file *file_priv); | |
1da177e4 | 468 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 469 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 470 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
471 | /* i915_gem.c */ |
472 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
473 | struct drm_file *file_priv); | |
474 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
475 | struct drm_file *file_priv); | |
476 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
477 | struct drm_file *file_priv); | |
478 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
479 | struct drm_file *file_priv); | |
480 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
481 | struct drm_file *file_priv); | |
482 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
483 | struct drm_file *file_priv); | |
484 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
485 | struct drm_file *file_priv); | |
486 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
487 | struct drm_file *file_priv); | |
488 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
489 | struct drm_file *file_priv); | |
490 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
491 | struct drm_file *file_priv); | |
492 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
493 | struct drm_file *file_priv); | |
494 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
495 | struct drm_file *file_priv); | |
496 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
497 | struct drm_file *file_priv); | |
498 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
499 | struct drm_file *file_priv); | |
500 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
501 | struct drm_file *file_priv); | |
502 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
503 | struct drm_file *file_priv); | |
5a125c3c EA |
504 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
505 | struct drm_file *file_priv); | |
673a394b EA |
506 | void i915_gem_load(struct drm_device *dev); |
507 | int i915_gem_proc_init(struct drm_minor *minor); | |
508 | void i915_gem_proc_cleanup(struct drm_minor *minor); | |
509 | int i915_gem_init_object(struct drm_gem_object *obj); | |
510 | void i915_gem_free_object(struct drm_gem_object *obj); | |
511 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); | |
512 | void i915_gem_object_unpin(struct drm_gem_object *obj); | |
513 | void i915_gem_lastclose(struct drm_device *dev); | |
514 | uint32_t i915_get_gem_seqno(struct drm_device *dev); | |
515 | void i915_gem_retire_requests(struct drm_device *dev); | |
516 | void i915_gem_retire_work_handler(struct work_struct *work); | |
517 | void i915_gem_clflush_object(struct drm_gem_object *obj); | |
518 | ||
519 | /* i915_gem_tiling.c */ | |
520 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
521 | ||
522 | /* i915_gem_debug.c */ | |
523 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
524 | const char *where, uint32_t mark); | |
525 | #if WATCH_INACTIVE | |
526 | void i915_verify_inactive(struct drm_device *dev, char *file, int line); | |
527 | #else | |
528 | #define i915_verify_inactive(dev, file, line) | |
529 | #endif | |
530 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
531 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
532 | const char *where, uint32_t mark); | |
533 | void i915_dump_lru(struct drm_device *dev, const char *where); | |
1da177e4 | 534 | |
317c35d1 JB |
535 | /* i915_suspend.c */ |
536 | extern int i915_save_state(struct drm_device *dev); | |
537 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
538 | |
539 | /* i915_suspend.c */ | |
540 | extern int i915_save_state(struct drm_device *dev); | |
541 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 542 | |
65e082c9 | 543 | #ifdef CONFIG_ACPI |
8ee1c3db MG |
544 | /* i915_opregion.c */ |
545 | extern int intel_opregion_init(struct drm_device *dev); | |
546 | extern void intel_opregion_free(struct drm_device *dev); | |
547 | extern void opregion_asle_intr(struct drm_device *dev); | |
548 | extern void opregion_enable_asle(struct drm_device *dev); | |
65e082c9 LB |
549 | #else |
550 | static inline int intel_opregion_init(struct drm_device *dev) { return 0; } | |
551 | static inline void intel_opregion_free(struct drm_device *dev) { return; } | |
552 | static inline void opregion_asle_intr(struct drm_device *dev) { return; } | |
553 | static inline void opregion_enable_asle(struct drm_device *dev) { return; } | |
554 | #endif | |
8ee1c3db | 555 | |
546b0974 EA |
556 | /** |
557 | * Lock test for when it's just for synchronization of ring access. | |
558 | * | |
559 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
560 | * has access to the ring. | |
561 | */ | |
562 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
563 | if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ | |
564 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ | |
565 | } while (0) | |
566 | ||
3043c60c EA |
567 | #define I915_READ(reg) readl(dev_priv->regs + (reg)) |
568 | #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) | |
569 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) | |
570 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) | |
571 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) | |
572 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) | |
1da177e4 LT |
573 | |
574 | #define I915_VERBOSE 0 | |
575 | ||
576 | #define RING_LOCALS unsigned int outring, ringmask, outcount; \ | |
577 | volatile char *virt; | |
578 | ||
579 | #define BEGIN_LP_RING(n) do { \ | |
580 | if (I915_VERBOSE) \ | |
3e684eae MN |
581 | DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ |
582 | if (dev_priv->ring.space < (n)*4) \ | |
bf9d8929 | 583 | i915_wait_ring(dev, (n)*4, __func__); \ |
1da177e4 LT |
584 | outcount = 0; \ |
585 | outring = dev_priv->ring.tail; \ | |
586 | ringmask = dev_priv->ring.tail_mask; \ | |
587 | virt = dev_priv->ring.virtual_start; \ | |
588 | } while (0) | |
589 | ||
590 | #define OUT_RING(n) do { \ | |
591 | if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ | |
c29b669c | 592 | *(volatile unsigned int *)(virt + outring) = (n); \ |
1da177e4 LT |
593 | outcount++; \ |
594 | outring += 4; \ | |
595 | outring &= ringmask; \ | |
596 | } while (0) | |
597 | ||
598 | #define ADVANCE_LP_RING() do { \ | |
599 | if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ | |
600 | dev_priv->ring.tail = outring; \ | |
601 | dev_priv->ring.space -= outcount * 4; \ | |
585fb111 | 602 | I915_WRITE(PRB0_TAIL, outring); \ |
1da177e4 LT |
603 | } while(0) |
604 | ||
ba8bbcf6 | 605 | /** |
585fb111 JB |
606 | * Reads a dword out of the status page, which is written to from the command |
607 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
608 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 609 | * |
585fb111 | 610 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
611 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
612 | * 0x04: ring 0 head pointer | |
613 | * 0x05: ring 1 head pointer (915-class) | |
614 | * 0x06: ring 2 head pointer (915-class) | |
615 | * 0x10-0x1b: Context status DWords (GM45) | |
616 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 617 | * |
0cdad7e8 | 618 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 619 | */ |
585fb111 | 620 | #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) |
0baf823a | 621 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 622 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 623 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 624 | |
585fb111 | 625 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
ba8bbcf6 JB |
626 | |
627 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
628 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
629 | #define IS_I85X(dev) ((dev)->pci_device == 0x3582) | |
630 | #define IS_I855(dev) ((dev)->pci_device == 0x3582) | |
631 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
632 | ||
4d1f7888 | 633 | #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) |
ba8bbcf6 JB |
634 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
635 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
3bf48468 JB |
636 | #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ |
637 | (dev)->pci_device == 0x27AE) | |
ba8bbcf6 JB |
638 | #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ |
639 | (dev)->pci_device == 0x2982 || \ | |
640 | (dev)->pci_device == 0x2992 || \ | |
641 | (dev)->pci_device == 0x29A2 || \ | |
642 | (dev)->pci_device == 0x2A02 || \ | |
5f5f9d4c | 643 | (dev)->pci_device == 0x2A12 || \ |
d3adbc0c ZW |
644 | (dev)->pci_device == 0x2A42 || \ |
645 | (dev)->pci_device == 0x2E02 || \ | |
646 | (dev)->pci_device == 0x2E12 || \ | |
647 | (dev)->pci_device == 0x2E22) | |
ba8bbcf6 JB |
648 | |
649 | #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) | |
650 | ||
b9bfdfe6 | 651 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) |
5f5f9d4c | 652 | |
d3adbc0c ZW |
653 | #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ |
654 | (dev)->pci_device == 0x2E12 || \ | |
655 | (dev)->pci_device == 0x2E22) | |
656 | ||
ba8bbcf6 JB |
657 | #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ |
658 | (dev)->pci_device == 0x29B2 || \ | |
659 | (dev)->pci_device == 0x29D2) | |
660 | ||
661 | #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ | |
662 | IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) | |
663 | ||
664 | #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ | |
b9bfdfe6 | 665 | IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) |
ba8bbcf6 | 666 | |
b9bfdfe6 | 667 | #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) |
b39d50e5 | 668 | |
ba8bbcf6 | 669 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 670 | |
1da177e4 | 671 | #endif |