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drm/i915: enable memory self refresh on 9xx
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT
1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
1da177e4
LT
31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
35
79e53945 36#include <linux/console.h>
354ff967 37#include "drm_crtc_helper.h"
79e53945 38
d6073d77 39static int i915_modeset = -1;
79e53945
JB
40module_param_named(modeset, i915_modeset, int, 0400);
41
42unsigned int i915_fbpercrtc = 0;
43module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 44
652c393a
JB
45unsigned int i915_powersave = 1;
46module_param_named(powersave, i915_powersave, int, 0400);
47
33814341
JB
48unsigned int i915_lvds_downclock = 0;
49module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
50
112b715e
KH
51static struct drm_driver driver;
52
cfdf1fa2 53#define INTEL_VGA_DEVICE(id, info) { \
49ae35f2
KH
54 .class = PCI_CLASS_DISPLAY_VGA << 8, \
55 .class_mask = 0xffff00, \
56 .vendor = 0x8086, \
57 .device = id, \
58 .subvendor = PCI_ANY_ID, \
59 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH
60 .driver_data = (unsigned long) info }
61
62const static struct intel_device_info intel_i830_info = {
b295d1b6 63 .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
64};
65
66const static struct intel_device_info intel_845g_info = {
67 .is_i8xx = 1,
68};
69
70const static struct intel_device_info intel_i85x_info = {
b295d1b6 71 .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
72};
73
74const static struct intel_device_info intel_i865g_info = {
75 .is_i8xx = 1,
76};
77
78const static struct intel_device_info intel_i915g_info = {
b295d1b6 79 .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
80};
81const static struct intel_device_info intel_i915gm_info = {
82 .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
b295d1b6 83 .cursor_needs_physical = 1,
cfdf1fa2
KH
84};
85const static struct intel_device_info intel_i945g_info = {
b295d1b6 86 .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
87};
88const static struct intel_device_info intel_i945gm_info = {
89 .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
b295d1b6 90 .has_hotplug = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
91};
92
93const static struct intel_device_info intel_i965g_info = {
94 .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
95};
96
97const static struct intel_device_info intel_i965gm_info = {
98 .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
99 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
100 .has_hotplug = 1,
101};
102
103const static struct intel_device_info intel_g33_info = {
104 .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
105 .has_hotplug = 1,
106};
107
108const static struct intel_device_info intel_g45_info = {
109 .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
110 .has_pipe_cxsr = 1,
111 .has_hotplug = 1,
112};
113
114const static struct intel_device_info intel_gm45_info = {
115 .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
116 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
117 .has_pipe_cxsr = 1,
118 .has_hotplug = 1,
119};
120
121const static struct intel_device_info intel_pineview_info = {
122 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
8a6c77d6 123 .need_gfx_hws = 1,
cfdf1fa2
KH
124 .has_hotplug = 1,
125};
126
127const static struct intel_device_info intel_ironlake_d_info = {
128 .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
129 .has_pipe_cxsr = 1,
130 .has_hotplug = 1,
131};
132
133const static struct intel_device_info intel_ironlake_m_info = {
134 .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
135 .need_gfx_hws = 1, .has_rc6 = 1,
136 .has_hotplug = 1,
137};
138
139const static struct pci_device_id pciidlist[] = {
140 INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
141 INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
142 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
143 INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
144 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
145 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
146 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
147 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
148 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
149 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
150 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
151 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
152 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
153 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
154 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
155 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
156 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
157 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
158 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
159 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
160 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
161 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
162 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
163 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
164 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
165 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
166 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
167 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
168 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
169 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
49ae35f2 170 {0, 0, 0}
1da177e4
LT
171};
172
79e53945
JB
173#if defined(CONFIG_DRM_I915_KMS)
174MODULE_DEVICE_TABLE(pci, pciidlist);
175#endif
176
84b79f8d 177static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 178{
ba8bbcf6 179 pci_save_state(dev->pdev);
ba8bbcf6 180
5669fcac 181 /* If KMS is active, we do the leavevt stuff here */
226485e9 182 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW
183 int error = i915_gem_idle(dev);
184 if (error) {
226485e9 185 dev_err(&dev->pdev->dev,
84b79f8d
RW
186 "GEM idle failed, resume might fail\n");
187 return error;
188 }
226485e9 189 drm_irq_uninstall(dev);
5669fcac
JB
190 }
191
9e06dd39
JB
192 i915_save_state(dev);
193
84b79f8d
RW
194 return 0;
195}
196
197static void i915_drm_suspend(struct drm_device *dev)
198{
199 struct drm_i915_private *dev_priv = dev->dev_private;
200
3b1c1c11 201 intel_opregion_free(dev, 1);
8ee1c3db 202
84b79f8d
RW
203 /* Modeset on resume, not lid events */
204 dev_priv->modeset_on_lid = 0;
205}
206
207static int i915_suspend(struct drm_device *dev, pm_message_t state)
208{
209 int error;
210
211 if (!dev || !dev->dev_private) {
212 DRM_ERROR("dev: %p\n", dev);
213 DRM_ERROR("DRM not initialized, aborting suspend.\n");
214 return -ENODEV;
215 }
216
217 if (state.event == PM_EVENT_PRETHAW)
218 return 0;
219
220 error = i915_drm_freeze(dev);
221 if (error)
222 return error;
223
224 i915_drm_suspend(dev);
225
b932ccb5
DA
226 if (state.event == PM_EVENT_SUSPEND) {
227 /* Shut down the device */
228 pci_disable_device(dev->pdev);
229 pci_set_power_state(dev->pdev, PCI_D3hot);
230 }
ba8bbcf6
JB
231
232 return 0;
233}
234
84b79f8d 235static int i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 236{
5669fcac 237 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 238 int error = 0;
8ee1c3db 239
5669fcac
JB
240 /* KMS EnterVT equivalent */
241 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
242 mutex_lock(&dev->struct_mutex);
243 dev_priv->mm.suspended = 0;
244
84b79f8d 245 error = i915_gem_init_ringbuffer(dev);
5669fcac 246 mutex_unlock(&dev->struct_mutex);
226485e9
JB
247
248 drm_irq_install(dev);
84b79f8d 249
354ff967
ZY
250 /* Resume the modeset for every activated CRTC */
251 drm_helper_resume_force_mode(dev);
252 }
5669fcac 253
c9354c85 254 dev_priv->modeset_on_lid = 0;
06891e27 255
84b79f8d
RW
256 return error;
257}
258
259static int i915_resume(struct drm_device *dev)
260{
261 if (pci_enable_device(dev->pdev))
262 return -EIO;
263
264 pci_set_master(dev->pdev);
265
266 i915_restore_state(dev);
267
268 intel_opregion_init(dev, 1);
269
270 return i915_drm_thaw(dev);
ba8bbcf6
JB
271}
272
11ed50ec
BG
273/**
274 * i965_reset - reset chip after a hang
275 * @dev: drm device to reset
276 * @flags: reset domains
277 *
278 * Reset the chip. Useful if a hang is detected. Returns zero on successful
279 * reset or otherwise an error code.
280 *
281 * Procedure is fairly simple:
282 * - reset the chip using the reset reg
283 * - re-init context state
284 * - re-init hardware status page
285 * - re-init ring buffer
286 * - re-init interrupt state
287 * - re-init display
288 */
289int i965_reset(struct drm_device *dev, u8 flags)
290{
291 drm_i915_private_t *dev_priv = dev->dev_private;
292 unsigned long timeout;
293 u8 gdrst;
294 /*
295 * We really should only reset the display subsystem if we actually
296 * need to
297 */
298 bool need_display = true;
299
300 mutex_lock(&dev->struct_mutex);
301
302 /*
303 * Clear request list
304 */
305 i915_gem_retire_requests(dev);
306
307 if (need_display)
308 i915_save_display(dev);
309
310 if (IS_I965G(dev) || IS_G4X(dev)) {
311 /*
312 * Set the domains we want to reset, then the reset bit (bit 0).
313 * Clear the reset bit after a while and wait for hardware status
314 * bit (bit 1) to be set
315 */
316 pci_read_config_byte(dev->pdev, GDRST, &gdrst);
317 pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
318 udelay(50);
319 pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
320
321 /* ...we don't want to loop forever though, 500ms should be plenty */
322 timeout = jiffies + msecs_to_jiffies(500);
323 do {
324 udelay(100);
325 pci_read_config_byte(dev->pdev, GDRST, &gdrst);
326 } while ((gdrst & 0x1) && time_after(timeout, jiffies));
327
328 if (gdrst & 0x1) {
329 WARN(true, "i915: Failed to reset chip\n");
330 mutex_unlock(&dev->struct_mutex);
331 return -EIO;
332 }
333 } else {
334 DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
335 return -ENODEV;
336 }
337
338 /* Ok, now get things going again... */
339
340 /*
341 * Everything depends on having the GTT running, so we need to start
342 * there. Fortunately we don't need to do this unless we reset the
343 * chip at a PCI level.
344 *
345 * Next we need to restore the context, but we don't use those
346 * yet either...
347 *
348 * Ring buffer needs to be re-initialized in the KMS case, or if X
349 * was running at the time of the reset (i.e. we weren't VT
350 * switched away).
351 */
352 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
353 !dev_priv->mm.suspended) {
354 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
355 struct drm_gem_object *obj = ring->ring_obj;
356 struct drm_i915_gem_object *obj_priv = obj->driver_private;
357 dev_priv->mm.suspended = 0;
358
359 /* Stop the ring if it's running. */
360 I915_WRITE(PRB0_CTL, 0);
361 I915_WRITE(PRB0_TAIL, 0);
362 I915_WRITE(PRB0_HEAD, 0);
363
364 /* Initialize the ring. */
365 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
366 I915_WRITE(PRB0_CTL,
367 ((obj->size - 4096) & RING_NR_PAGES) |
368 RING_NO_REPORT |
369 RING_VALID);
370 if (!drm_core_check_feature(dev, DRIVER_MODESET))
371 i915_kernel_lost_context(dev);
372 else {
373 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
374 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
375 ring->space = ring->head - (ring->tail + 8);
376 if (ring->space < 0)
377 ring->space += ring->Size;
378 }
379
380 mutex_unlock(&dev->struct_mutex);
381 drm_irq_uninstall(dev);
382 drm_irq_install(dev);
383 mutex_lock(&dev->struct_mutex);
384 }
385
386 /*
387 * Display needs restore too...
388 */
389 if (need_display)
390 i915_restore_display(dev);
391
392 mutex_unlock(&dev->struct_mutex);
393 return 0;
394}
395
396
112b715e
KH
397static int __devinit
398i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
399{
400 return drm_get_dev(pdev, ent, &driver);
401}
402
403static void
404i915_pci_remove(struct pci_dev *pdev)
405{
406 struct drm_device *dev = pci_get_drvdata(pdev);
407
408 drm_put_dev(dev);
409}
410
84b79f8d 411static int i915_pm_suspend(struct device *dev)
112b715e 412{
84b79f8d
RW
413 struct pci_dev *pdev = to_pci_dev(dev);
414 struct drm_device *drm_dev = pci_get_drvdata(pdev);
415 int error;
112b715e 416
84b79f8d
RW
417 if (!drm_dev || !drm_dev->dev_private) {
418 dev_err(dev, "DRM not initialized, aborting suspend.\n");
419 return -ENODEV;
420 }
112b715e 421
84b79f8d
RW
422 error = i915_drm_freeze(drm_dev);
423 if (error)
424 return error;
112b715e 425
84b79f8d 426 i915_drm_suspend(drm_dev);
112b715e 427
84b79f8d
RW
428 pci_disable_device(pdev);
429 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 430
84b79f8d 431 return 0;
cbda12d7
ZW
432}
433
84b79f8d 434static int i915_pm_resume(struct device *dev)
cbda12d7 435{
84b79f8d
RW
436 struct pci_dev *pdev = to_pci_dev(dev);
437 struct drm_device *drm_dev = pci_get_drvdata(pdev);
438
439 return i915_resume(drm_dev);
cbda12d7
ZW
440}
441
84b79f8d 442static int i915_pm_freeze(struct device *dev)
cbda12d7 443{
84b79f8d
RW
444 struct pci_dev *pdev = to_pci_dev(dev);
445 struct drm_device *drm_dev = pci_get_drvdata(pdev);
446
447 if (!drm_dev || !drm_dev->dev_private) {
448 dev_err(dev, "DRM not initialized, aborting suspend.\n");
449 return -ENODEV;
450 }
451
452 return i915_drm_freeze(drm_dev);
cbda12d7
ZW
453}
454
84b79f8d 455static int i915_pm_thaw(struct device *dev)
cbda12d7 456{
84b79f8d
RW
457 struct pci_dev *pdev = to_pci_dev(dev);
458 struct drm_device *drm_dev = pci_get_drvdata(pdev);
459
460 return i915_drm_thaw(drm_dev);
cbda12d7
ZW
461}
462
84b79f8d 463static int i915_pm_poweroff(struct device *dev)
cbda12d7 464{
84b79f8d
RW
465 struct pci_dev *pdev = to_pci_dev(dev);
466 struct drm_device *drm_dev = pci_get_drvdata(pdev);
467 int error;
468
469 error = i915_drm_freeze(drm_dev);
470 if (!error)
471 i915_drm_suspend(drm_dev);
472
473 return error;
cbda12d7
ZW
474}
475
476const struct dev_pm_ops i915_pm_ops = {
477 .suspend = i915_pm_suspend,
478 .resume = i915_pm_resume,
479 .freeze = i915_pm_freeze,
480 .thaw = i915_pm_thaw,
481 .poweroff = i915_pm_poweroff,
84b79f8d 482 .restore = i915_pm_resume,
cbda12d7
ZW
483};
484
de151cf6
JB
485static struct vm_operations_struct i915_gem_vm_ops = {
486 .fault = i915_gem_fault,
ab00b3e5
JB
487 .open = drm_gem_vm_open,
488 .close = drm_gem_vm_close,
de151cf6
JB
489};
490
1da177e4 491static struct drm_driver driver = {
792d2b9a
DA
492 /* don't use mtrr's here, the Xserver or user space app should
493 * deal with them for intel hardware.
494 */
673a394b
EA
495 .driver_features =
496 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
497 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
22eae947 498 .load = i915_driver_load,
ba8bbcf6 499 .unload = i915_driver_unload,
673a394b 500 .open = i915_driver_open,
22eae947
DA
501 .lastclose = i915_driver_lastclose,
502 .preclose = i915_driver_preclose,
673a394b 503 .postclose = i915_driver_postclose,
d8e29209
RW
504
505 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
506 .suspend = i915_suspend,
507 .resume = i915_resume,
508
cda17380 509 .device_is_agp = i915_driver_device_is_agp,
0a3e67a4
JB
510 .enable_vblank = i915_enable_vblank,
511 .disable_vblank = i915_disable_vblank,
1da177e4
LT
512 .irq_preinstall = i915_driver_irq_preinstall,
513 .irq_postinstall = i915_driver_irq_postinstall,
514 .irq_uninstall = i915_driver_irq_uninstall,
515 .irq_handler = i915_driver_irq_handler,
516 .reclaim_buffers = drm_core_reclaim_buffers,
517 .get_map_ofs = drm_core_get_map_ofs,
518 .get_reg_ofs = drm_core_get_reg_ofs,
7c1c2871
DA
519 .master_create = i915_master_create,
520 .master_destroy = i915_master_destroy,
955b12de 521#if defined(CONFIG_DEBUG_FS)
27c202ad
BG
522 .debugfs_init = i915_debugfs_init,
523 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 524#endif
673a394b
EA
525 .gem_init_object = i915_gem_init_object,
526 .gem_free_object = i915_gem_free_object,
de151cf6 527 .gem_vm_ops = &i915_gem_vm_ops,
1da177e4
LT
528 .ioctls = i915_ioctls,
529 .fops = {
b5e89ed5
DA
530 .owner = THIS_MODULE,
531 .open = drm_open,
532 .release = drm_release,
ed8b6704 533 .unlocked_ioctl = drm_ioctl,
de151cf6 534 .mmap = drm_gem_mmap,
b5e89ed5
DA
535 .poll = drm_poll,
536 .fasync = drm_fasync,
c9a9c5e0 537 .read = drm_read,
8ca7c1df 538#ifdef CONFIG_COMPAT
b5e89ed5 539 .compat_ioctl = i915_compat_ioctl,
8ca7c1df 540#endif
22eae947
DA
541 },
542
1da177e4 543 .pci_driver = {
22eae947
DA
544 .name = DRIVER_NAME,
545 .id_table = pciidlist,
112b715e
KH
546 .probe = i915_pci_probe,
547 .remove = i915_pci_remove,
cbda12d7 548 .driver.pm = &i915_pm_ops,
22eae947 549 },
bc5f4523 550
22eae947
DA
551 .name = DRIVER_NAME,
552 .desc = DRIVER_DESC,
553 .date = DRIVER_DATE,
554 .major = DRIVER_MAJOR,
555 .minor = DRIVER_MINOR,
556 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT
557};
558
559static int __init i915_init(void)
560{
561 driver.num_ioctls = i915_max_ioctl;
79e53945 562
31169714
CW
563 i915_gem_shrinker_init();
564
79e53945
JB
565 /*
566 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
567 * explicitly disabled with the module pararmeter.
568 *
569 * Otherwise, just follow the parameter (defaulting to off).
570 *
571 * Allow optional vga_text_mode_force boot option to override
572 * the default behavior.
573 */
574#if defined(CONFIG_DRM_I915_KMS)
575 if (i915_modeset != 0)
576 driver.driver_features |= DRIVER_MODESET;
577#endif
578 if (i915_modeset == 1)
579 driver.driver_features |= DRIVER_MODESET;
580
581#ifdef CONFIG_VGA_CONSOLE
582 if (vgacon_text_force() && i915_modeset == -1)
583 driver.driver_features &= ~DRIVER_MODESET;
584#endif
585
1da177e4
LT
586 return drm_init(&driver);
587}
588
589static void __exit i915_exit(void)
590{
31169714 591 i915_gem_shrinker_exit();
1da177e4
LT
592 drm_exit(&driver);
593}
594
595module_init(i915_init);
596module_exit(i915_exit);
597
b5e89ed5
DA
598MODULE_AUTHOR(DRIVER_AUTHOR);
599MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 600MODULE_LICENSE("GPL and additional rights");