]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/i915/i915_drv.c
Merge branch 'master' of git://dev.medozas.de/linux
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT
1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
1da177e4
LT
31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
35
79e53945 36#include <linux/console.h>
354ff967 37#include "drm_crtc_helper.h"
79e53945 38
d6073d77 39static int i915_modeset = -1;
79e53945
JB
40module_param_named(modeset, i915_modeset, int, 0400);
41
42unsigned int i915_fbpercrtc = 0;
43module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 44
652c393a
JB
45unsigned int i915_powersave = 1;
46module_param_named(powersave, i915_powersave, int, 0400);
47
33814341
JB
48unsigned int i915_lvds_downclock = 0;
49module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
50
112b715e 51static struct drm_driver driver;
1f7a6e37 52extern int intel_agp_enabled;
112b715e 53
cfdf1fa2 54#define INTEL_VGA_DEVICE(id, info) { \
49ae35f2
KH
55 .class = PCI_CLASS_DISPLAY_VGA << 8, \
56 .class_mask = 0xffff00, \
57 .vendor = 0x8086, \
58 .device = id, \
59 .subvendor = PCI_ANY_ID, \
60 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH
61 .driver_data = (unsigned long) info }
62
63const static struct intel_device_info intel_i830_info = {
b295d1b6 64 .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
65};
66
67const static struct intel_device_info intel_845g_info = {
68 .is_i8xx = 1,
69};
70
71const static struct intel_device_info intel_i85x_info = {
b295d1b6 72 .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
73};
74
75const static struct intel_device_info intel_i865g_info = {
76 .is_i8xx = 1,
77};
78
79const static struct intel_device_info intel_i915g_info = {
b295d1b6 80 .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
81};
82const static struct intel_device_info intel_i915gm_info = {
8d06a1e1 83 .is_i9xx = 1, .is_mobile = 1,
b295d1b6 84 .cursor_needs_physical = 1,
cfdf1fa2
KH
85};
86const static struct intel_device_info intel_i945g_info = {
b295d1b6 87 .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
88};
89const static struct intel_device_info intel_i945gm_info = {
8d06a1e1 90 .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
b295d1b6 91 .has_hotplug = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
92};
93
94const static struct intel_device_info intel_i965g_info = {
95 .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
96};
97
98const static struct intel_device_info intel_i965gm_info = {
99 .is_i965g = 1, .is_mobile = 1, .is_i965gm = 1, .is_i9xx = 1,
100 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
101 .has_hotplug = 1,
102};
103
104const static struct intel_device_info intel_g33_info = {
105 .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
106 .has_hotplug = 1,
107};
108
109const static struct intel_device_info intel_g45_info = {
110 .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
111 .has_pipe_cxsr = 1,
112 .has_hotplug = 1,
113};
114
115const static struct intel_device_info intel_gm45_info = {
116 .is_i965g = 1, .is_mobile = 1, .is_g4x = 1, .is_i9xx = 1,
117 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
118 .has_pipe_cxsr = 1,
119 .has_hotplug = 1,
120};
121
122const static struct intel_device_info intel_pineview_info = {
123 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
8a6c77d6 124 .need_gfx_hws = 1,
cfdf1fa2
KH
125 .has_hotplug = 1,
126};
127
128const static struct intel_device_info intel_ironlake_d_info = {
129 .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
130 .has_pipe_cxsr = 1,
131 .has_hotplug = 1,
132};
133
134const static struct intel_device_info intel_ironlake_m_info = {
135 .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
136 .need_gfx_hws = 1, .has_rc6 = 1,
137 .has_hotplug = 1,
138};
139
f6e450a6
EA
140const static struct intel_device_info intel_sandybridge_d_info = {
141 .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
59f2d0fc 142 .has_hotplug = 1, .is_gen6 = 1,
f6e450a6
EA
143};
144
a13e4093 145const static struct intel_device_info intel_sandybridge_m_info = {
faa7bde6 146 .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1,
59f2d0fc 147 .has_hotplug = 1, .is_gen6 = 1,
a13e4093
EA
148};
149
cfdf1fa2
KH
150const static struct pci_device_id pciidlist[] = {
151 INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
152 INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
153 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
154 INTEL_VGA_DEVICE(0x35e8, &intel_i85x_info),
155 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
156 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
157 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
158 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
159 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
160 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
161 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
162 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
163 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
164 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
165 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
166 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
167 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
168 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
169 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
170 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
171 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
172 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
173 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
174 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
175 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
176 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
177 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
178 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
179 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
180 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
f6e450a6 181 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
a13e4093 182 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
49ae35f2 183 {0, 0, 0}
1da177e4
LT
184};
185
79e53945
JB
186#if defined(CONFIG_DRM_I915_KMS)
187MODULE_DEVICE_TABLE(pci, pciidlist);
188#endif
189
84b79f8d 190static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 191{
61caf87c
RW
192 struct drm_i915_private *dev_priv = dev->dev_private;
193
ba8bbcf6 194 pci_save_state(dev->pdev);
ba8bbcf6 195
5669fcac 196 /* If KMS is active, we do the leavevt stuff here */
226485e9 197 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW
198 int error = i915_gem_idle(dev);
199 if (error) {
226485e9 200 dev_err(&dev->pdev->dev,
84b79f8d
RW
201 "GEM idle failed, resume might fail\n");
202 return error;
203 }
226485e9 204 drm_irq_uninstall(dev);
5669fcac
JB
205 }
206
9e06dd39
JB
207 i915_save_state(dev);
208
3b1c1c11 209 intel_opregion_free(dev, 1);
8ee1c3db 210
84b79f8d
RW
211 /* Modeset on resume, not lid events */
212 dev_priv->modeset_on_lid = 0;
61caf87c
RW
213
214 return 0;
84b79f8d
RW
215}
216
6a9ee8af 217int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW
218{
219 int error;
220
221 if (!dev || !dev->dev_private) {
222 DRM_ERROR("dev: %p\n", dev);
223 DRM_ERROR("DRM not initialized, aborting suspend.\n");
224 return -ENODEV;
225 }
226
227 if (state.event == PM_EVENT_PRETHAW)
228 return 0;
229
230 error = i915_drm_freeze(dev);
231 if (error)
232 return error;
233
b932ccb5
DA
234 if (state.event == PM_EVENT_SUSPEND) {
235 /* Shut down the device */
236 pci_disable_device(dev->pdev);
237 pci_set_power_state(dev->pdev, PCI_D3hot);
238 }
ba8bbcf6
JB
239
240 return 0;
241}
242
84b79f8d 243static int i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 244{
5669fcac 245 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 246 int error = 0;
8ee1c3db 247
61caf87c
RW
248 i915_restore_state(dev);
249
250 intel_opregion_init(dev, 1);
251
5669fcac
JB
252 /* KMS EnterVT equivalent */
253 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
254 mutex_lock(&dev->struct_mutex);
255 dev_priv->mm.suspended = 0;
256
84b79f8d 257 error = i915_gem_init_ringbuffer(dev);
5669fcac 258 mutex_unlock(&dev->struct_mutex);
226485e9
JB
259
260 drm_irq_install(dev);
84b79f8d 261
354ff967
ZY
262 /* Resume the modeset for every activated CRTC */
263 drm_helper_resume_force_mode(dev);
264 }
5669fcac 265
c9354c85 266 dev_priv->modeset_on_lid = 0;
06891e27 267
84b79f8d
RW
268 return error;
269}
270
6a9ee8af 271int i915_resume(struct drm_device *dev)
84b79f8d
RW
272{
273 if (pci_enable_device(dev->pdev))
274 return -EIO;
275
276 pci_set_master(dev->pdev);
277
84b79f8d 278 return i915_drm_thaw(dev);
ba8bbcf6
JB
279}
280
11ed50ec
BG
281/**
282 * i965_reset - reset chip after a hang
283 * @dev: drm device to reset
284 * @flags: reset domains
285 *
286 * Reset the chip. Useful if a hang is detected. Returns zero on successful
287 * reset or otherwise an error code.
288 *
289 * Procedure is fairly simple:
290 * - reset the chip using the reset reg
291 * - re-init context state
292 * - re-init hardware status page
293 * - re-init ring buffer
294 * - re-init interrupt state
295 * - re-init display
296 */
297int i965_reset(struct drm_device *dev, u8 flags)
298{
299 drm_i915_private_t *dev_priv = dev->dev_private;
300 unsigned long timeout;
301 u8 gdrst;
302 /*
303 * We really should only reset the display subsystem if we actually
304 * need to
305 */
306 bool need_display = true;
307
308 mutex_lock(&dev->struct_mutex);
309
310 /*
311 * Clear request list
312 */
313 i915_gem_retire_requests(dev);
314
315 if (need_display)
316 i915_save_display(dev);
317
318 if (IS_I965G(dev) || IS_G4X(dev)) {
319 /*
320 * Set the domains we want to reset, then the reset bit (bit 0).
321 * Clear the reset bit after a while and wait for hardware status
322 * bit (bit 1) to be set
323 */
324 pci_read_config_byte(dev->pdev, GDRST, &gdrst);
325 pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
326 udelay(50);
327 pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
328
329 /* ...we don't want to loop forever though, 500ms should be plenty */
330 timeout = jiffies + msecs_to_jiffies(500);
331 do {
332 udelay(100);
333 pci_read_config_byte(dev->pdev, GDRST, &gdrst);
334 } while ((gdrst & 0x1) && time_after(timeout, jiffies));
335
336 if (gdrst & 0x1) {
337 WARN(true, "i915: Failed to reset chip\n");
338 mutex_unlock(&dev->struct_mutex);
339 return -EIO;
340 }
341 } else {
342 DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
343 return -ENODEV;
344 }
345
346 /* Ok, now get things going again... */
347
348 /*
349 * Everything depends on having the GTT running, so we need to start
350 * there. Fortunately we don't need to do this unless we reset the
351 * chip at a PCI level.
352 *
353 * Next we need to restore the context, but we don't use those
354 * yet either...
355 *
356 * Ring buffer needs to be re-initialized in the KMS case, or if X
357 * was running at the time of the reset (i.e. we weren't VT
358 * switched away).
359 */
360 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
361 !dev_priv->mm.suspended) {
362 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
363 struct drm_gem_object *obj = ring->ring_obj;
23010e43 364 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
11ed50ec
BG
365 dev_priv->mm.suspended = 0;
366
367 /* Stop the ring if it's running. */
368 I915_WRITE(PRB0_CTL, 0);
369 I915_WRITE(PRB0_TAIL, 0);
370 I915_WRITE(PRB0_HEAD, 0);
371
372 /* Initialize the ring. */
373 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
374 I915_WRITE(PRB0_CTL,
375 ((obj->size - 4096) & RING_NR_PAGES) |
376 RING_NO_REPORT |
377 RING_VALID);
378 if (!drm_core_check_feature(dev, DRIVER_MODESET))
379 i915_kernel_lost_context(dev);
380 else {
381 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
382 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
383 ring->space = ring->head - (ring->tail + 8);
384 if (ring->space < 0)
385 ring->space += ring->Size;
386 }
387
388 mutex_unlock(&dev->struct_mutex);
389 drm_irq_uninstall(dev);
390 drm_irq_install(dev);
391 mutex_lock(&dev->struct_mutex);
392 }
393
394 /*
395 * Display needs restore too...
396 */
397 if (need_display)
398 i915_restore_display(dev);
399
400 mutex_unlock(&dev->struct_mutex);
401 return 0;
402}
403
404
112b715e
KH
405static int __devinit
406i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
407{
408 return drm_get_dev(pdev, ent, &driver);
409}
410
411static void
412i915_pci_remove(struct pci_dev *pdev)
413{
414 struct drm_device *dev = pci_get_drvdata(pdev);
415
416 drm_put_dev(dev);
417}
418
84b79f8d 419static int i915_pm_suspend(struct device *dev)
112b715e 420{
84b79f8d
RW
421 struct pci_dev *pdev = to_pci_dev(dev);
422 struct drm_device *drm_dev = pci_get_drvdata(pdev);
423 int error;
112b715e 424
84b79f8d
RW
425 if (!drm_dev || !drm_dev->dev_private) {
426 dev_err(dev, "DRM not initialized, aborting suspend.\n");
427 return -ENODEV;
428 }
112b715e 429
84b79f8d
RW
430 error = i915_drm_freeze(drm_dev);
431 if (error)
432 return error;
112b715e 433
84b79f8d
RW
434 pci_disable_device(pdev);
435 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 436
84b79f8d 437 return 0;
cbda12d7
ZW
438}
439
84b79f8d 440static int i915_pm_resume(struct device *dev)
cbda12d7 441{
84b79f8d
RW
442 struct pci_dev *pdev = to_pci_dev(dev);
443 struct drm_device *drm_dev = pci_get_drvdata(pdev);
444
445 return i915_resume(drm_dev);
cbda12d7
ZW
446}
447
84b79f8d 448static int i915_pm_freeze(struct device *dev)
cbda12d7 449{
84b79f8d
RW
450 struct pci_dev *pdev = to_pci_dev(dev);
451 struct drm_device *drm_dev = pci_get_drvdata(pdev);
452
453 if (!drm_dev || !drm_dev->dev_private) {
454 dev_err(dev, "DRM not initialized, aborting suspend.\n");
455 return -ENODEV;
456 }
457
458 return i915_drm_freeze(drm_dev);
cbda12d7
ZW
459}
460
84b79f8d 461static int i915_pm_thaw(struct device *dev)
cbda12d7 462{
84b79f8d
RW
463 struct pci_dev *pdev = to_pci_dev(dev);
464 struct drm_device *drm_dev = pci_get_drvdata(pdev);
465
466 return i915_drm_thaw(drm_dev);
cbda12d7
ZW
467}
468
84b79f8d 469static int i915_pm_poweroff(struct device *dev)
cbda12d7 470{
84b79f8d
RW
471 struct pci_dev *pdev = to_pci_dev(dev);
472 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 473
61caf87c 474 return i915_drm_freeze(drm_dev);
cbda12d7
ZW
475}
476
477const struct dev_pm_ops i915_pm_ops = {
478 .suspend = i915_pm_suspend,
479 .resume = i915_pm_resume,
480 .freeze = i915_pm_freeze,
481 .thaw = i915_pm_thaw,
482 .poweroff = i915_pm_poweroff,
84b79f8d 483 .restore = i915_pm_resume,
cbda12d7
ZW
484};
485
de151cf6
JB
486static struct vm_operations_struct i915_gem_vm_ops = {
487 .fault = i915_gem_fault,
ab00b3e5
JB
488 .open = drm_gem_vm_open,
489 .close = drm_gem_vm_close,
de151cf6
JB
490};
491
1da177e4 492static struct drm_driver driver = {
792d2b9a
DA
493 /* don't use mtrr's here, the Xserver or user space app should
494 * deal with them for intel hardware.
495 */
673a394b
EA
496 .driver_features =
497 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
498 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
22eae947 499 .load = i915_driver_load,
ba8bbcf6 500 .unload = i915_driver_unload,
673a394b 501 .open = i915_driver_open,
22eae947
DA
502 .lastclose = i915_driver_lastclose,
503 .preclose = i915_driver_preclose,
673a394b 504 .postclose = i915_driver_postclose,
d8e29209
RW
505
506 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
507 .suspend = i915_suspend,
508 .resume = i915_resume,
509
cda17380 510 .device_is_agp = i915_driver_device_is_agp,
0a3e67a4
JB
511 .enable_vblank = i915_enable_vblank,
512 .disable_vblank = i915_disable_vblank,
1da177e4
LT
513 .irq_preinstall = i915_driver_irq_preinstall,
514 .irq_postinstall = i915_driver_irq_postinstall,
515 .irq_uninstall = i915_driver_irq_uninstall,
516 .irq_handler = i915_driver_irq_handler,
517 .reclaim_buffers = drm_core_reclaim_buffers,
518 .get_map_ofs = drm_core_get_map_ofs,
519 .get_reg_ofs = drm_core_get_reg_ofs,
7c1c2871
DA
520 .master_create = i915_master_create,
521 .master_destroy = i915_master_destroy,
955b12de 522#if defined(CONFIG_DEBUG_FS)
27c202ad
BG
523 .debugfs_init = i915_debugfs_init,
524 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 525#endif
673a394b
EA
526 .gem_init_object = i915_gem_init_object,
527 .gem_free_object = i915_gem_free_object,
de151cf6 528 .gem_vm_ops = &i915_gem_vm_ops,
1da177e4
LT
529 .ioctls = i915_ioctls,
530 .fops = {
b5e89ed5
DA
531 .owner = THIS_MODULE,
532 .open = drm_open,
533 .release = drm_release,
ed8b6704 534 .unlocked_ioctl = drm_ioctl,
de151cf6 535 .mmap = drm_gem_mmap,
b5e89ed5
DA
536 .poll = drm_poll,
537 .fasync = drm_fasync,
c9a9c5e0 538 .read = drm_read,
8ca7c1df 539#ifdef CONFIG_COMPAT
b5e89ed5 540 .compat_ioctl = i915_compat_ioctl,
8ca7c1df 541#endif
22eae947
DA
542 },
543
1da177e4 544 .pci_driver = {
22eae947
DA
545 .name = DRIVER_NAME,
546 .id_table = pciidlist,
112b715e
KH
547 .probe = i915_pci_probe,
548 .remove = i915_pci_remove,
cbda12d7 549 .driver.pm = &i915_pm_ops,
22eae947 550 },
bc5f4523 551
22eae947
DA
552 .name = DRIVER_NAME,
553 .desc = DRIVER_DESC,
554 .date = DRIVER_DATE,
555 .major = DRIVER_MAJOR,
556 .minor = DRIVER_MINOR,
557 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT
558};
559
560static int __init i915_init(void)
561{
1f7a6e37
ZW
562 if (!intel_agp_enabled) {
563 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
564 return -ENODEV;
565 }
566
1da177e4 567 driver.num_ioctls = i915_max_ioctl;
79e53945 568
31169714
CW
569 i915_gem_shrinker_init();
570
79e53945
JB
571 /*
572 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
573 * explicitly disabled with the module pararmeter.
574 *
575 * Otherwise, just follow the parameter (defaulting to off).
576 *
577 * Allow optional vga_text_mode_force boot option to override
578 * the default behavior.
579 */
580#if defined(CONFIG_DRM_I915_KMS)
581 if (i915_modeset != 0)
582 driver.driver_features |= DRIVER_MODESET;
583#endif
584 if (i915_modeset == 1)
585 driver.driver_features |= DRIVER_MODESET;
586
587#ifdef CONFIG_VGA_CONSOLE
588 if (vgacon_text_force() && i915_modeset == -1)
589 driver.driver_features &= ~DRIVER_MODESET;
590#endif
591
f97108d1
JB
592 if (!(driver.driver_features & DRIVER_MODESET)) {
593 driver.suspend = i915_suspend;
594 driver.resume = i915_resume;
595 }
596
1da177e4
LT
597 return drm_init(&driver);
598}
599
600static void __exit i915_exit(void)
601{
31169714 602 i915_gem_shrinker_exit();
1da177e4
LT
603 drm_exit(&driver);
604}
605
606module_init(i915_init);
607module_exit(i915_exit);
608
b5e89ed5
DA
609MODULE_AUTHOR(DRIVER_AUTHOR);
610MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 611MODULE_LICENSE("GPL and additional rights");