[net-next-2.6.git] / drivers / gpio / timbgpio.c

/*
 * timbgpio.c timberdale FPGA GPIO driver
 * Copyright (c) 2009 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Timberdale FPGA GPIO
 */

#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/timb_gpio.h>
#include <linux/interrupt.h>
#include <linux/slab.h>

#define DRIVER_NAME "timb-gpio"

#define TGPIOVAL	0x00
#define TGPIODIR	0x04
#define TGPIO_IER	0x08
#define TGPIO_ISR	0x0c
#define TGPIO_IPR	0x10
#define TGPIO_ICR	0x14
#define TGPIO_FLR	0x18
#define TGPIO_LVR	0x1c
#define TGPIO_VER	0x20
#define TGPIO_BFLR	0x24

struct timbgpio {
	void __iomem		*membase;
	spinlock_t		lock; /* mutual exclusion */
	struct gpio_chip	gpio;
	int			irq_base;
};

static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	unsigned offset, bool enabled)
{
	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
	u32 reg;

	spin_lock(&tgpio->lock);
	reg = ioread32(tgpio->membase + offset);

	if (enabled)
		reg |= (1 << index);
	else
		reg &= ~(1 << index);

	iowrite32(reg, tgpio->membase + offset);
	spin_unlock(&tgpio->lock);

	return 0;
}

static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
}

static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
	u32 value;

	value = ioread32(tgpio->membase + TGPIOVAL);
	return (value & (1 << nr)) ? 1 : 0;
}

static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
						unsigned nr, int val)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
}

static void timbgpio_gpio_set(struct gpio_chip *gpio,
				unsigned nr, int val)
{
	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
}

static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);

	if (tgpio->irq_base <= 0)
		return -EINVAL;

	return tgpio->irq_base + offset;
}

/*
 * GPIO IRQ
 */
static void timbgpio_irq_disable(unsigned irq)
{
	struct timbgpio *tgpio = get_irq_chip_data(irq);
	int offset = irq - tgpio->irq_base;

	timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
}

static void timbgpio_irq_enable(unsigned irq)
{
	struct timbgpio *tgpio = get_irq_chip_data(irq);
	int offset = irq - tgpio->irq_base;

	timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
}

static int timbgpio_irq_type(unsigned irq, unsigned trigger)
{
	struct timbgpio *tgpio = get_irq_chip_data(irq);
	int offset = irq - tgpio->irq_base;
	unsigned long flags;
	u32 lvr, flr, bflr = 0;
	u32 ver;
	int ret = 0;

	if (offset < 0 || offset > tgpio->gpio.ngpio)
		return -EINVAL;

	ver = ioread32(tgpio->membase + TGPIO_VER);

	spin_lock_irqsave(&tgpio->lock, flags);

	lvr = ioread32(tgpio->membase + TGPIO_LVR);
	flr = ioread32(tgpio->membase + TGPIO_FLR);
	if (ver > 2)
		bflr = ioread32(tgpio->membase + TGPIO_BFLR);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		bflr &= ~(1 << offset);
		flr &= ~(1 << offset);
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			lvr |= 1 << offset;
		else
			lvr &= ~(1 << offset);
	}

	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		if (ver < 3) {
			ret = -EINVAL;
			goto out;
		}
		else {
			flr |= 1 << offset;
			bflr |= 1 << offset;
		}
	} else {
		bflr &= ~(1 << offset);
		flr |= 1 << offset;
		if (trigger & IRQ_TYPE_EDGE_FALLING)
			lvr &= ~(1 << offset);
		else
			lvr |= 1 << offset;
	}

	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
	iowrite32(flr, tgpio->membase + TGPIO_FLR);
	if (ver > 2)
		iowrite32(bflr, tgpio->membase + TGPIO_BFLR);

	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);

out:
	spin_unlock_irqrestore(&tgpio->lock, flags);
	return ret;
}

static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
{
	struct timbgpio *tgpio = get_irq_data(irq);
	unsigned long ipr;
	int offset;

	desc->chip->ack(irq);
	ipr = ioread32(tgpio->membase + TGPIO_IPR);
	iowrite32(ipr, tgpio->membase + TGPIO_ICR);

	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
		generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
}

static struct irq_chip timbgpio_irqchip = {
	.name		= "GPIO",
	.enable		= timbgpio_irq_enable,
	.disable	= timbgpio_irq_disable,
	.set_type	= timbgpio_irq_type,
};

static int __devinit timbgpio_probe(struct platform_device *pdev)
{
	int err, i;
	struct gpio_chip *gc;
	struct timbgpio *tgpio;
	struct resource *iomem;
	struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
	int irq = platform_get_irq(pdev, 0);

	if (!pdata || pdata->nr_pins > 32) {
		err = -EINVAL;
		goto err_mem;
	}

	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iomem) {
		err = -EINVAL;
		goto err_mem;
	}

	tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
	if (!tgpio) {
		err = -EINVAL;
		goto err_mem;
	}
	tgpio->irq_base = pdata->irq_base;

	spin_lock_init(&tgpio->lock);

	if (!request_mem_region(iomem->start, resource_size(iomem),
		DRIVER_NAME)) {
		err = -EBUSY;
		goto err_request;
	}

	tgpio->membase = ioremap(iomem->start, resource_size(iomem));
	if (!tgpio->membase) {
		err = -ENOMEM;
		goto err_ioremap;
	}

	gc = &tgpio->gpio;

	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->dev = &pdev->dev;
	gc->direction_input = timbgpio_gpio_direction_input;
	gc->get = timbgpio_gpio_get;
	gc->direction_output = timbgpio_gpio_direction_output;
	gc->set = timbgpio_gpio_set;
	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	gc->dbg_show = NULL;
	gc->base = pdata->gpio_base;
	gc->ngpio = pdata->nr_pins;
	gc->can_sleep = 0;

	err = gpiochip_add(gc);
	if (err)
		goto err_chipadd;

	platform_set_drvdata(pdev, tgpio);

	/* make sure to disable interrupts */
	iowrite32(0x0, tgpio->membase + TGPIO_IER);

	if (irq < 0 || tgpio->irq_base <= 0)
		return 0;

	for (i = 0; i < pdata->nr_pins; i++) {
		set_irq_chip_and_handler_name(tgpio->irq_base + i,
			&timbgpio_irqchip, handle_simple_irq, "mux");
		set_irq_chip_data(tgpio->irq_base + i, tgpio);
#ifdef CONFIG_ARM
		set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
#endif
	}

	set_irq_data(irq, tgpio);
	set_irq_chained_handler(irq, timbgpio_irq);

	return 0;

err_chipadd:
	iounmap(tgpio->membase);
err_ioremap:
	release_mem_region(iomem->start, resource_size(iomem));
err_request:
	kfree(tgpio);
err_mem:
	printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);

	return err;
}

static int __devexit timbgpio_remove(struct platform_device *pdev)
{
	int err;
	struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
	struct timbgpio *tgpio = platform_get_drvdata(pdev);
	struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	int irq = platform_get_irq(pdev, 0);

	if (irq >= 0 && tgpio->irq_base > 0) {
		int i;
		for (i = 0; i < pdata->nr_pins; i++) {
			set_irq_chip(tgpio->irq_base + i, NULL);
			set_irq_chip_data(tgpio->irq_base + i, NULL);
		}

		set_irq_handler(irq, NULL);
		set_irq_data(irq, NULL);
	}

	err = gpiochip_remove(&tgpio->gpio);
	if (err)
		printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");

	iounmap(tgpio->membase);
	release_mem_region(iomem->start, resource_size(iomem));
	kfree(tgpio);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver timbgpio_platform_driver = {
	.driver = {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
	},
	.probe		= timbgpio_probe,
	.remove		= timbgpio_remove,
};

/*--------------------------------------------------------------------------*/

static int __init timbgpio_init(void)
{
	return platform_driver_register(&timbgpio_platform_driver);
}

static void __exit timbgpio_exit(void)
{
	platform_driver_unregister(&timbgpio_platform_driver);
}

module_init(timbgpio_init);
module_exit(timbgpio_exit);

MODULE_DESCRIPTION("Timberdale GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mocean Laboratories");
MODULE_ALIAS("platform:"DRIVER_NAME);
Commit	Line	Data
35570ac6 RR	1	/*
	2	* timbgpio.c timberdale FPGA GPIO driver
	3	* Copyright (c) 2009 Intel Corporation
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*/
	18
	19	/* Supports:
	20	* Timberdale FPGA GPIO
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/gpio.h>
	25	#include <linux/platform_device.h>
e3cb91ce	26	#include <linux/irq.h>
35570ac6 RR	27	#include <linux/io.h>
	28	#include <linux/timb_gpio.h>
	29	#include <linux/interrupt.h>
5a0e3ad6	30	#include <linux/slab.h>
35570ac6 RR	31
	32	#define DRIVER_NAME "timb-gpio"
	33
	34	#define TGPIOVAL 0x00
	35	#define TGPIODIR 0x04
	36	#define TGPIO_IER 0x08
	37	#define TGPIO_ISR 0x0c
	38	#define TGPIO_IPR 0x10
	39	#define TGPIO_ICR 0x14
	40	#define TGPIO_FLR 0x18
	41	#define TGPIO_LVR 0x1c
8c35c89a RR	42	#define TGPIO_VER 0x20
8c35c89a RR	43	#define TGPIO_BFLR 0x24
35570ac6 RR	44
	45	struct timbgpio {
	46	void __iomem *membase;
	47	spinlock_t lock; /* mutual exclusion */
	48	struct gpio_chip gpio;
	49	int irq_base;
	50	};
	51
	52	static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	53	unsigned offset, bool enabled)
	54	{
	55	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
	56	u32 reg;
	57
	58	spin_lock(&tgpio->lock);
	59	reg = ioread32(tgpio->membase + offset);
	60
	61	if (enabled)
	62	reg \|= (1 << index);
	63	else
	64	reg &= ~(1 << index);
	65
	66	iowrite32(reg, tgpio->membase + offset);
	67	spin_unlock(&tgpio->lock);
	68
	69	return 0;
	70	}
	71
	72	static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	73	{
	74	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
	75	}
	76
	77	static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
	78	{
	79	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
	80	u32 value;
	81
	82	value = ioread32(tgpio->membase + TGPIOVAL);
	83	return (value & (1 << nr)) ? 1 : 0;
	84	}
	85
	86	static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
	87	unsigned nr, int val)
	88	{
	89	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
	90	}
	91
	92	static void timbgpio_gpio_set(struct gpio_chip *gpio,
	93	unsigned nr, int val)
	94	{
	95	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
	96	}
	97
	98	static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	99	{
	100	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
	101
	102	if (tgpio->irq_base <= 0)
	103	return -EINVAL;
	104
	105	return tgpio->irq_base + offset;
	106	}
	107
108	/*
109	* GPIO IRQ
110	*/
111	static void timbgpio_irq_disable(unsigned irq)
112	{
113	struct timbgpio *tgpio = get_irq_chip_data(irq);
114	int offset = irq - tgpio->irq_base;
115
116	timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
117	}
118
119	static void timbgpio_irq_enable(unsigned irq)
120	{
121	struct timbgpio *tgpio = get_irq_chip_data(irq);
122	int offset = irq - tgpio->irq_base;
123
124	timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
125	}
126
127	static int timbgpio_irq_type(unsigned irq, unsigned trigger)
128	{
129	struct timbgpio *tgpio = get_irq_chip_data(irq);
130	int offset = irq - tgpio->irq_base;
131	unsigned long flags;
8c35c89a RR	132	u32 lvr, flr, bflr = 0;
8c35c89a RR	133	u32 ver;
2a481800	134	int ret = 0;
35570ac6 RR	135
	136	if (offset < 0 \|\| offset > tgpio->gpio.ngpio)
	137	return -EINVAL;
	138
8c35c89a RR	139	ver = ioread32(tgpio->membase + TGPIO_VER);
8c35c89a RR	140
35570ac6 RR	141	spin_lock_irqsave(&tgpio->lock, flags);
	142
	143	lvr = ioread32(tgpio->membase + TGPIO_LVR);
	144	flr = ioread32(tgpio->membase + TGPIO_FLR);
8c35c89a RR	145	if (ver > 2)
8c35c89a RR	146	bflr = ioread32(tgpio->membase + TGPIO_BFLR);
35570ac6 RR	147
35570ac6 RR	148	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
8c35c89a	149	bflr &= ~(1 << offset);
35570ac6 RR	150	flr &= ~(1 << offset);
	151	if (trigger & IRQ_TYPE_LEVEL_HIGH)
	152	lvr \|= 1 << offset;
	153	else
	154	lvr &= ~(1 << offset);
	155	}
	156
8c35c89a	157	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
2a481800 JL	158	if (ver < 3) {
	159	ret = -EINVAL;
	160	goto out;
	161	}
8c35c89a RR	162	else {
	163	flr \|= 1 << offset;
	164	bflr \|= 1 << offset;
	165	}
	166	} else {
	167	bflr &= ~(1 << offset);
35570ac6	168	flr \|= 1 << offset;
35570ac6	169	if (trigger & IRQ_TYPE_EDGE_FALLING)
35570ac6	170	lvr &= ~(1 << offset);
8c35c89a RR	171	else
8c35c89a RR	172	lvr \|= 1 << offset;
35570ac6 RR	173	}
	174
	175	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
	176	iowrite32(flr, tgpio->membase + TGPIO_FLR);
8c35c89a RR	177	if (ver > 2)
	178	iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
	179
35570ac6	180	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
35570ac6	181
2a481800 JL	182	out:
	183	spin_unlock_irqrestore(&tgpio->lock, flags);
	184	return ret;
35570ac6 RR	185	}
	186
	187	static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
	188	{
	189	struct timbgpio *tgpio = get_irq_data(irq);
	190	unsigned long ipr;
	191	int offset;
	192
	193	desc->chip->ack(irq);
	194	ipr = ioread32(tgpio->membase + TGPIO_IPR);
	195	iowrite32(ipr, tgpio->membase + TGPIO_ICR);
	196
984b3f57	197	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
35570ac6 RR	198	generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
	199	}
	200
	201	static struct irq_chip timbgpio_irqchip = {
	202	.name = "GPIO",
	203	.enable = timbgpio_irq_enable,
	204	.disable = timbgpio_irq_disable,
	205	.set_type = timbgpio_irq_type,
	206	};
	207
	208	static int __devinit timbgpio_probe(struct platform_device *pdev)
	209	{
	210	int err, i;
	211	struct gpio_chip *gc;
	212	struct timbgpio *tgpio;
	213	struct resource *iomem;
	214	struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
	215	int irq = platform_get_irq(pdev, 0);
	216
	217	if (!pdata \|\| pdata->nr_pins > 32) {
	218	err = -EINVAL;
	219	goto err_mem;
	220	}
	221
	222	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	223	if (!iomem) {
	224	err = -EINVAL;
	225	goto err_mem;
	226	}
	227
	228	tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
	229	if (!tgpio) {
	230	err = -EINVAL;
	231	goto err_mem;
	232	}
	233	tgpio->irq_base = pdata->irq_base;
	234
	235	spin_lock_init(&tgpio->lock);
	236
	237	if (!request_mem_region(iomem->start, resource_size(iomem),
	238	DRIVER_NAME)) {
	239	err = -EBUSY;
	240	goto err_request;
	241	}
	242
	243	tgpio->membase = ioremap(iomem->start, resource_size(iomem));
	244	if (!tgpio->membase) {
	245	err = -ENOMEM;
	246	goto err_ioremap;
	247	}
	248
	249	gc = &tgpio->gpio;
	250
	251	gc->label = dev_name(&pdev->dev);
	252	gc->owner = THIS_MODULE;
	253	gc->dev = &pdev->dev;
	254	gc->direction_input = timbgpio_gpio_direction_input;
	255	gc->get = timbgpio_gpio_get;
	256	gc->direction_output = timbgpio_gpio_direction_output;
	257	gc->set = timbgpio_gpio_set;
	258	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	259	gc->dbg_show = NULL;
	260	gc->base = pdata->gpio_base;
	261	gc->ngpio = pdata->nr_pins;
262	gc->can_sleep = 0;
263
264	err = gpiochip_add(gc);
265	if (err)
266	goto err_chipadd;
267
268	platform_set_drvdata(pdev, tgpio);
269
270	/* make sure to disable interrupts */
271	iowrite32(0x0, tgpio->membase + TGPIO_IER);
272
273	if (irq < 0 \|\| tgpio->irq_base <= 0)
274	return 0;
275
276	for (i = 0; i < pdata->nr_pins; i++) {
277	set_irq_chip_and_handler_name(tgpio->irq_base + i,
278	&timbgpio_irqchip, handle_simple_irq, "mux");
279	set_irq_chip_data(tgpio->irq_base + i, tgpio);
280	#ifdef CONFIG_ARM
281	set_irq_flags(tgpio->irq_base + i, IRQF_VALID \| IRQF_PROBE);
282	#endif
283	}
284
285	set_irq_data(irq, tgpio);
286	set_irq_chained_handler(irq, timbgpio_irq);
287
288	return 0;
289
290	err_chipadd:
291	iounmap(tgpio->membase);
292	err_ioremap:
293	release_mem_region(iomem->start, resource_size(iomem));
294	err_request:
295	kfree(tgpio);
296	err_mem:
297	printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
298
299	return err;
300	}
301
302	static int __devexit timbgpio_remove(struct platform_device *pdev)
303	{
304	int err;
305	struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
306	struct timbgpio *tgpio = platform_get_drvdata(pdev);
307	struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
308	int irq = platform_get_irq(pdev, 0);
309
310	if (irq >= 0 && tgpio->irq_base > 0) {
311	int i;
312	for (i = 0; i < pdata->nr_pins; i++) {
313	set_irq_chip(tgpio->irq_base + i, NULL);
314	set_irq_chip_data(tgpio->irq_base + i, NULL);
315	}
316
317	set_irq_handler(irq, NULL);
318	set_irq_data(irq, NULL);
319	}
320
321	err = gpiochip_remove(&tgpio->gpio);
322	if (err)
323	printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
324
325	iounmap(tgpio->membase);
326	release_mem_region(iomem->start, resource_size(iomem));
327	kfree(tgpio);
328
329	platform_set_drvdata(pdev, NULL);
330
331	return 0;
332	}
333
334	static struct platform_driver timbgpio_platform_driver = {
335	.driver = {
336	.name = DRIVER_NAME,
337	.owner = THIS_MODULE,
338	},
339	.probe = timbgpio_probe,
340	.remove = timbgpio_remove,
341	};
342
343	/--------------------------------------------------------------------------/
344
345	static int __init timbgpio_init(void)
346	{
347	return platform_driver_register(&timbgpio_platform_driver);
348	}
349
350	static void __exit timbgpio_exit(void)
351	{
352	platform_driver_unregister(&timbgpio_platform_driver);
353	}
354
355	module_init(timbgpio_init);
356	module_exit(timbgpio_exit);
357
358	MODULE_DESCRIPTION("Timberdale GPIO driver");
359	MODULE_LICENSE("GPL v2");
360	MODULE_AUTHOR("Mocean Laboratories");
361	MODULE_ALIAS("platform:"DRIVER_NAME);
362