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Commit | Line | Data |
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c781c06d KH |
1 | /* |
2 | * Driver for OHCI 1394 controllers | |
ed568912 | 3 | * |
ed568912 KH |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
e524f616 | 21 | #include <linux/compiler.h> |
ed568912 | 22 | #include <linux/delay.h> |
e8ca9702 | 23 | #include <linux/device.h> |
cf3e72fd | 24 | #include <linux/dma-mapping.h> |
77c9a5da | 25 | #include <linux/firewire.h> |
e8ca9702 | 26 | #include <linux/firewire-constants.h> |
c26f0234 | 27 | #include <linux/gfp.h> |
a7fb60db SR |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
e8ca9702 | 30 | #include <linux/io.h> |
a7fb60db | 31 | #include <linux/kernel.h> |
e8ca9702 | 32 | #include <linux/list.h> |
faa2fb4e | 33 | #include <linux/mm.h> |
a7fb60db | 34 | #include <linux/module.h> |
ad3c0fe8 | 35 | #include <linux/moduleparam.h> |
a7fb60db | 36 | #include <linux/pci.h> |
fc383796 | 37 | #include <linux/pci_ids.h> |
c26f0234 | 38 | #include <linux/spinlock.h> |
e8ca9702 | 39 | #include <linux/string.h> |
cf3e72fd | 40 | |
e8ca9702 | 41 | #include <asm/byteorder.h> |
c26f0234 | 42 | #include <asm/page.h> |
ee71c2f9 | 43 | #include <asm/system.h> |
ed568912 | 44 | |
ea8d006b SR |
45 | #ifdef CONFIG_PPC_PMAC |
46 | #include <asm/pmac_feature.h> | |
47 | #endif | |
48 | ||
77c9a5da SR |
49 | #include "core.h" |
50 | #include "ohci.h" | |
ed568912 | 51 | |
a77754a7 KH |
52 | #define DESCRIPTOR_OUTPUT_MORE 0 |
53 | #define DESCRIPTOR_OUTPUT_LAST (1 << 12) | |
54 | #define DESCRIPTOR_INPUT_MORE (2 << 12) | |
55 | #define DESCRIPTOR_INPUT_LAST (3 << 12) | |
56 | #define DESCRIPTOR_STATUS (1 << 11) | |
57 | #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) | |
58 | #define DESCRIPTOR_PING (1 << 7) | |
59 | #define DESCRIPTOR_YY (1 << 6) | |
60 | #define DESCRIPTOR_NO_IRQ (0 << 4) | |
61 | #define DESCRIPTOR_IRQ_ERROR (1 << 4) | |
62 | #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) | |
63 | #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) | |
64 | #define DESCRIPTOR_WAIT (3 << 0) | |
ed568912 KH |
65 | |
66 | struct descriptor { | |
67 | __le16 req_count; | |
68 | __le16 control; | |
69 | __le32 data_address; | |
70 | __le32 branch_address; | |
71 | __le16 res_count; | |
72 | __le16 transfer_status; | |
73 | } __attribute__((aligned(16))); | |
74 | ||
a77754a7 KH |
75 | #define CONTROL_SET(regs) (regs) |
76 | #define CONTROL_CLEAR(regs) ((regs) + 4) | |
77 | #define COMMAND_PTR(regs) ((regs) + 12) | |
78 | #define CONTEXT_MATCH(regs) ((regs) + 16) | |
72e318e0 | 79 | |
32b46093 | 80 | struct ar_buffer { |
ed568912 | 81 | struct descriptor descriptor; |
32b46093 KH |
82 | struct ar_buffer *next; |
83 | __le32 data[0]; | |
84 | }; | |
ed568912 | 85 | |
32b46093 KH |
86 | struct ar_context { |
87 | struct fw_ohci *ohci; | |
88 | struct ar_buffer *current_buffer; | |
89 | struct ar_buffer *last_buffer; | |
90 | void *pointer; | |
72e318e0 | 91 | u32 regs; |
ed568912 KH |
92 | struct tasklet_struct tasklet; |
93 | }; | |
94 | ||
30200739 KH |
95 | struct context; |
96 | ||
97 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
98 | struct descriptor *d, | |
99 | struct descriptor *last); | |
fe5ca634 DM |
100 | |
101 | /* | |
102 | * A buffer that contains a block of DMA-able coherent memory used for | |
103 | * storing a portion of a DMA descriptor program. | |
104 | */ | |
105 | struct descriptor_buffer { | |
106 | struct list_head list; | |
107 | dma_addr_t buffer_bus; | |
108 | size_t buffer_size; | |
109 | size_t used; | |
110 | struct descriptor buffer[0]; | |
111 | }; | |
112 | ||
30200739 | 113 | struct context { |
373b2edd | 114 | struct fw_ohci *ohci; |
30200739 | 115 | u32 regs; |
fe5ca634 | 116 | int total_allocation; |
373b2edd | 117 | |
fe5ca634 DM |
118 | /* |
119 | * List of page-sized buffers for storing DMA descriptors. | |
120 | * Head of list contains buffers in use and tail of list contains | |
121 | * free buffers. | |
122 | */ | |
123 | struct list_head buffer_list; | |
124 | ||
125 | /* | |
126 | * Pointer to a buffer inside buffer_list that contains the tail | |
127 | * end of the current DMA program. | |
128 | */ | |
129 | struct descriptor_buffer *buffer_tail; | |
130 | ||
131 | /* | |
132 | * The descriptor containing the branch address of the first | |
133 | * descriptor that has not yet been filled by the device. | |
134 | */ | |
135 | struct descriptor *last; | |
136 | ||
137 | /* | |
138 | * The last descriptor in the DMA program. It contains the branch | |
139 | * address that must be updated upon appending a new descriptor. | |
140 | */ | |
141 | struct descriptor *prev; | |
30200739 KH |
142 | |
143 | descriptor_callback_t callback; | |
144 | ||
373b2edd | 145 | struct tasklet_struct tasklet; |
30200739 | 146 | }; |
30200739 | 147 | |
a77754a7 KH |
148 | #define IT_HEADER_SY(v) ((v) << 0) |
149 | #define IT_HEADER_TCODE(v) ((v) << 4) | |
150 | #define IT_HEADER_CHANNEL(v) ((v) << 8) | |
151 | #define IT_HEADER_TAG(v) ((v) << 14) | |
152 | #define IT_HEADER_SPEED(v) ((v) << 16) | |
153 | #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) | |
ed568912 KH |
154 | |
155 | struct iso_context { | |
156 | struct fw_iso_context base; | |
30200739 | 157 | struct context context; |
0642b657 | 158 | int excess_bytes; |
9b32d5f3 KH |
159 | void *header; |
160 | size_t header_length; | |
ed568912 KH |
161 | }; |
162 | ||
163 | #define CONFIG_ROM_SIZE 1024 | |
164 | ||
165 | struct fw_ohci { | |
166 | struct fw_card card; | |
167 | ||
168 | __iomem char *registers; | |
e636fe25 | 169 | int node_id; |
ed568912 | 170 | int generation; |
e09770db | 171 | int request_generation; /* for timestamping incoming requests */ |
4a635593 | 172 | unsigned quirks; |
ed568912 | 173 | |
c781c06d KH |
174 | /* |
175 | * Spinlock for accessing fw_ohci data. Never call out of | |
176 | * this driver with this lock held. | |
177 | */ | |
ed568912 | 178 | spinlock_t lock; |
ed568912 KH |
179 | |
180 | struct ar_context ar_request_ctx; | |
181 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
182 | struct context at_request_ctx; |
183 | struct context at_response_ctx; | |
ed568912 KH |
184 | |
185 | u32 it_context_mask; | |
186 | struct iso_context *it_context_list; | |
4817ed24 | 187 | u64 ir_context_channels; |
ed568912 KH |
188 | u32 ir_context_mask; |
189 | struct iso_context *ir_context_list; | |
ecb1cf9c SR |
190 | |
191 | __be32 *config_rom; | |
192 | dma_addr_t config_rom_bus; | |
193 | __be32 *next_config_rom; | |
194 | dma_addr_t next_config_rom_bus; | |
195 | __be32 next_header; | |
196 | ||
197 | __le32 *self_id_cpu; | |
198 | dma_addr_t self_id_bus; | |
199 | struct tasklet_struct bus_reset_tasklet; | |
200 | ||
201 | u32 self_id_buffer[512]; | |
ed568912 KH |
202 | }; |
203 | ||
95688e97 | 204 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
205 | { |
206 | return container_of(card, struct fw_ohci, card); | |
207 | } | |
208 | ||
295e3feb KH |
209 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
210 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
211 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
212 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
213 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
214 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
215 | |
216 | #define CONTEXT_RUN 0x8000 | |
217 | #define CONTEXT_WAKE 0x1000 | |
218 | #define CONTEXT_DEAD 0x0800 | |
219 | #define CONTEXT_ACTIVE 0x0400 | |
220 | ||
8b7b6afa | 221 | #define OHCI1394_MAX_AT_REQ_RETRIES 0xf |
ed568912 KH |
222 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 |
223 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
224 | ||
ed568912 KH |
225 | #define OHCI1394_REGISTER_SIZE 0x800 |
226 | #define OHCI_LOOP_COUNT 500 | |
227 | #define OHCI1394_PCI_HCI_Control 0x40 | |
228 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 229 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 230 | #define OHCI_VERSION_1_1 0x010010 |
0edeefd9 | 231 | |
ed568912 KH |
232 | static char ohci_driver_name[] = KBUILD_MODNAME; |
233 | ||
8301b91b CL |
234 | #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 |
235 | ||
4a635593 SR |
236 | #define QUIRK_CYCLE_TIMER 1 |
237 | #define QUIRK_RESET_PACKET 2 | |
238 | #define QUIRK_BE_HEADERS 4 | |
925e7a65 | 239 | #define QUIRK_NO_1394A 8 |
4a635593 SR |
240 | |
241 | /* In case of multiple matches in ohci_quirks[], only the first one is used. */ | |
242 | static const struct { | |
243 | unsigned short vendor, device, flags; | |
244 | } ohci_quirks[] = { | |
8301b91b | 245 | {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER | |
925e7a65 CL |
246 | QUIRK_RESET_PACKET | |
247 | QUIRK_NO_1394A}, | |
4a635593 SR |
248 | {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET}, |
249 | {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, | |
250 | {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, | |
251 | {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, | |
252 | {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS}, | |
253 | }; | |
254 | ||
3e9cc2f3 SR |
255 | /* This overrides anything that was found in ohci_quirks[]. */ |
256 | static int param_quirks; | |
257 | module_param_named(quirks, param_quirks, int, 0644); | |
258 | MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" | |
259 | ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) | |
260 | ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) | |
261 | ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS) | |
925e7a65 | 262 | ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) |
3e9cc2f3 SR |
263 | ")"); |
264 | ||
ad3c0fe8 SR |
265 | #ifdef CONFIG_FIREWIRE_OHCI_DEBUG |
266 | ||
a007bb85 | 267 | #define OHCI_PARAM_DEBUG_AT_AR 1 |
ad3c0fe8 | 268 | #define OHCI_PARAM_DEBUG_SELFIDS 2 |
a007bb85 SR |
269 | #define OHCI_PARAM_DEBUG_IRQS 4 |
270 | #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ | |
ad3c0fe8 SR |
271 | |
272 | static int param_debug; | |
273 | module_param_named(debug, param_debug, int, 0644); | |
274 | MODULE_PARM_DESC(debug, "Verbose logging (default = 0" | |
ad3c0fe8 | 275 | ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) |
a007bb85 SR |
276 | ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) |
277 | ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) | |
278 | ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) | |
ad3c0fe8 SR |
279 | ", or a combination, or all = -1)"); |
280 | ||
281 | static void log_irqs(u32 evt) | |
282 | { | |
a007bb85 SR |
283 | if (likely(!(param_debug & |
284 | (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) | |
285 | return; | |
286 | ||
287 | if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && | |
288 | !(evt & OHCI1394_busReset)) | |
ad3c0fe8 SR |
289 | return; |
290 | ||
168cf9af | 291 | fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, |
161b96e7 SR |
292 | evt & OHCI1394_selfIDComplete ? " selfID" : "", |
293 | evt & OHCI1394_RQPkt ? " AR_req" : "", | |
294 | evt & OHCI1394_RSPkt ? " AR_resp" : "", | |
295 | evt & OHCI1394_reqTxComplete ? " AT_req" : "", | |
296 | evt & OHCI1394_respTxComplete ? " AT_resp" : "", | |
297 | evt & OHCI1394_isochRx ? " IR" : "", | |
298 | evt & OHCI1394_isochTx ? " IT" : "", | |
299 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", | |
300 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", | |
5ed1f321 | 301 | evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", |
161b96e7 SR |
302 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", |
303 | evt & OHCI1394_busReset ? " busReset" : "", | |
304 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | | |
305 | OHCI1394_RSPkt | OHCI1394_reqTxComplete | | |
306 | OHCI1394_respTxComplete | OHCI1394_isochRx | | |
307 | OHCI1394_isochTx | OHCI1394_postedWriteErr | | |
168cf9af | 308 | OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent | |
161b96e7 | 309 | OHCI1394_regAccessFail | OHCI1394_busReset) |
ad3c0fe8 SR |
310 | ? " ?" : ""); |
311 | } | |
312 | ||
313 | static const char *speed[] = { | |
314 | [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", | |
315 | }; | |
316 | static const char *power[] = { | |
317 | [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", | |
318 | [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", | |
319 | }; | |
320 | static const char port[] = { '.', '-', 'p', 'c', }; | |
321 | ||
322 | static char _p(u32 *s, int shift) | |
323 | { | |
324 | return port[*s >> shift & 3]; | |
325 | } | |
326 | ||
08ddb2f4 | 327 | static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) |
ad3c0fe8 SR |
328 | { |
329 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) | |
330 | return; | |
331 | ||
161b96e7 SR |
332 | fw_notify("%d selfIDs, generation %d, local node ID %04x\n", |
333 | self_id_count, generation, node_id); | |
ad3c0fe8 SR |
334 | |
335 | for (; self_id_count--; ++s) | |
336 | if ((*s & 1 << 23) == 0) | |
161b96e7 SR |
337 | fw_notify("selfID 0: %08x, phy %d [%c%c%c] " |
338 | "%s gc=%d %s %s%s%s\n", | |
339 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), | |
340 | speed[*s >> 14 & 3], *s >> 16 & 63, | |
341 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", | |
342 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); | |
ad3c0fe8 | 343 | else |
161b96e7 SR |
344 | fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", |
345 | *s, *s >> 24 & 63, | |
346 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), | |
347 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); | |
ad3c0fe8 SR |
348 | } |
349 | ||
350 | static const char *evts[] = { | |
351 | [0x00] = "evt_no_status", [0x01] = "-reserved-", | |
352 | [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", | |
353 | [0x04] = "evt_underrun", [0x05] = "evt_overrun", | |
354 | [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", | |
355 | [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", | |
356 | [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", | |
357 | [0x0c] = "-reserved-", [0x0d] = "-reserved-", | |
358 | [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", | |
359 | [0x10] = "-reserved-", [0x11] = "ack_complete", | |
360 | [0x12] = "ack_pending ", [0x13] = "-reserved-", | |
361 | [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", | |
362 | [0x16] = "ack_busy_B", [0x17] = "-reserved-", | |
363 | [0x18] = "-reserved-", [0x19] = "-reserved-", | |
364 | [0x1a] = "-reserved-", [0x1b] = "ack_tardy", | |
365 | [0x1c] = "-reserved-", [0x1d] = "ack_data_error", | |
366 | [0x1e] = "ack_type_error", [0x1f] = "-reserved-", | |
367 | [0x20] = "pending/cancelled", | |
368 | }; | |
369 | static const char *tcodes[] = { | |
370 | [0x0] = "QW req", [0x1] = "BW req", | |
371 | [0x2] = "W resp", [0x3] = "-reserved-", | |
372 | [0x4] = "QR req", [0x5] = "BR req", | |
373 | [0x6] = "QR resp", [0x7] = "BR resp", | |
374 | [0x8] = "cycle start", [0x9] = "Lk req", | |
375 | [0xa] = "async stream packet", [0xb] = "Lk resp", | |
376 | [0xc] = "-reserved-", [0xd] = "-reserved-", | |
377 | [0xe] = "link internal", [0xf] = "-reserved-", | |
378 | }; | |
379 | static const char *phys[] = { | |
380 | [0x0] = "phy config packet", [0x1] = "link-on packet", | |
381 | [0x2] = "self-id packet", [0x3] = "-reserved-", | |
382 | }; | |
383 | ||
384 | static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |
385 | { | |
386 | int tcode = header[0] >> 4 & 0xf; | |
387 | char specific[12]; | |
388 | ||
389 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) | |
390 | return; | |
391 | ||
392 | if (unlikely(evt >= ARRAY_SIZE(evts))) | |
393 | evt = 0x1f; | |
394 | ||
08ddb2f4 | 395 | if (evt == OHCI1394_evt_bus_reset) { |
161b96e7 SR |
396 | fw_notify("A%c evt_bus_reset, generation %d\n", |
397 | dir, (header[2] >> 16) & 0xff); | |
08ddb2f4 SR |
398 | return; |
399 | } | |
400 | ||
ad3c0fe8 | 401 | if (header[0] == ~header[1]) { |
161b96e7 SR |
402 | fw_notify("A%c %s, %s, %08x\n", |
403 | dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]); | |
ad3c0fe8 SR |
404 | return; |
405 | } | |
406 | ||
407 | switch (tcode) { | |
408 | case 0x0: case 0x6: case 0x8: | |
409 | snprintf(specific, sizeof(specific), " = %08x", | |
410 | be32_to_cpu((__force __be32)header[3])); | |
411 | break; | |
412 | case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: | |
413 | snprintf(specific, sizeof(specific), " %x,%x", | |
414 | header[3] >> 16, header[3] & 0xffff); | |
415 | break; | |
416 | default: | |
417 | specific[0] = '\0'; | |
418 | } | |
419 | ||
420 | switch (tcode) { | |
421 | case 0xe: case 0xa: | |
161b96e7 | 422 | fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); |
ad3c0fe8 SR |
423 | break; |
424 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: | |
161b96e7 SR |
425 | fw_notify("A%c spd %x tl %02x, " |
426 | "%04x -> %04x, %s, " | |
427 | "%s, %04x%08x%s\n", | |
428 | dir, speed, header[0] >> 10 & 0x3f, | |
429 | header[1] >> 16, header[0] >> 16, evts[evt], | |
430 | tcodes[tcode], header[1] & 0xffff, header[2], specific); | |
ad3c0fe8 SR |
431 | break; |
432 | default: | |
161b96e7 SR |
433 | fw_notify("A%c spd %x tl %02x, " |
434 | "%04x -> %04x, %s, " | |
435 | "%s%s\n", | |
436 | dir, speed, header[0] >> 10 & 0x3f, | |
437 | header[1] >> 16, header[0] >> 16, evts[evt], | |
438 | tcodes[tcode], specific); | |
ad3c0fe8 SR |
439 | } |
440 | } | |
441 | ||
442 | #else | |
443 | ||
444 | #define log_irqs(evt) | |
08ddb2f4 | 445 | #define log_selfids(node_id, generation, self_id_count, sid) |
ad3c0fe8 SR |
446 | #define log_ar_at_event(dir, speed, header, evt) |
447 | ||
448 | #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ | |
449 | ||
95688e97 | 450 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
451 | { |
452 | writel(data, ohci->registers + offset); | |
453 | } | |
454 | ||
95688e97 | 455 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
456 | { |
457 | return readl(ohci->registers + offset); | |
458 | } | |
459 | ||
95688e97 | 460 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
461 | { |
462 | /* Do a dummy read to flush writes. */ | |
463 | reg_read(ohci, OHCI1394_Version); | |
464 | } | |
465 | ||
35d999b1 | 466 | static int read_phy_reg(struct fw_ohci *ohci, int addr) |
ed568912 | 467 | { |
4a96b4fc | 468 | u32 val; |
35d999b1 | 469 | int i; |
ed568912 KH |
470 | |
471 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
35d999b1 SR |
472 | for (i = 0; i < 10; i++) { |
473 | val = reg_read(ohci, OHCI1394_PhyControl); | |
474 | if (val & OHCI1394_PhyControl_ReadDone) | |
475 | return OHCI1394_PhyControl_ReadData(val); | |
476 | ||
477 | msleep(1); | |
ed568912 | 478 | } |
35d999b1 | 479 | fw_error("failed to read phy reg\n"); |
ed568912 | 480 | |
35d999b1 SR |
481 | return -EBUSY; |
482 | } | |
4a96b4fc | 483 | |
35d999b1 SR |
484 | static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) |
485 | { | |
486 | int i; | |
487 | ||
488 | reg_write(ohci, OHCI1394_PhyControl, | |
489 | OHCI1394_PhyControl_Write(addr, val)); | |
490 | for (i = 0; i < 100; i++) { | |
491 | val = reg_read(ohci, OHCI1394_PhyControl); | |
492 | if (!(val & OHCI1394_PhyControl_WritePending)) | |
493 | return 0; | |
494 | ||
495 | msleep(1); | |
496 | } | |
497 | fw_error("failed to write phy reg\n"); | |
498 | ||
499 | return -EBUSY; | |
4a96b4fc CL |
500 | } |
501 | ||
502 | static int ohci_update_phy_reg(struct fw_card *card, int addr, | |
503 | int clear_bits, int set_bits) | |
504 | { | |
505 | struct fw_ohci *ohci = fw_ohci(card); | |
35d999b1 | 506 | int ret; |
4a96b4fc | 507 | |
35d999b1 SR |
508 | ret = read_phy_reg(ohci, addr); |
509 | if (ret < 0) | |
510 | return ret; | |
4a96b4fc | 511 | |
e7014dad CL |
512 | /* |
513 | * The interrupt status bits are cleared by writing a one bit. | |
514 | * Avoid clearing them unless explicitly requested in set_bits. | |
515 | */ | |
516 | if (addr == 5) | |
517 | clear_bits |= PHY_INT_STATUS_BITS; | |
518 | ||
35d999b1 | 519 | return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); |
ed568912 KH |
520 | } |
521 | ||
35d999b1 | 522 | static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) |
925e7a65 | 523 | { |
35d999b1 | 524 | int ret; |
925e7a65 | 525 | |
35d999b1 SR |
526 | ret = ohci_update_phy_reg(&ohci->card, 7, PHY_PAGE_SELECT, page << 5); |
527 | if (ret < 0) | |
528 | return ret; | |
925e7a65 | 529 | |
35d999b1 | 530 | return read_phy_reg(ohci, addr); |
925e7a65 CL |
531 | } |
532 | ||
32b46093 | 533 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 534 | { |
32b46093 KH |
535 | struct device *dev = ctx->ohci->card.device; |
536 | struct ar_buffer *ab; | |
f5101d58 | 537 | dma_addr_t uninitialized_var(ab_bus); |
32b46093 KH |
538 | size_t offset; |
539 | ||
bde1709a | 540 | ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC); |
32b46093 KH |
541 | if (ab == NULL) |
542 | return -ENOMEM; | |
543 | ||
a55709ba | 544 | ab->next = NULL; |
2d826cc5 | 545 | memset(&ab->descriptor, 0, sizeof(ab->descriptor)); |
a77754a7 KH |
546 | ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | |
547 | DESCRIPTOR_STATUS | | |
548 | DESCRIPTOR_BRANCH_ALWAYS); | |
32b46093 KH |
549 | offset = offsetof(struct ar_buffer, data); |
550 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
551 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
552 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
553 | ab->descriptor.branch_address = 0; | |
554 | ||
ec839e43 | 555 | ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); |
32b46093 KH |
556 | ctx->last_buffer->next = ab; |
557 | ctx->last_buffer = ab; | |
558 | ||
a77754a7 | 559 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
ed568912 | 560 | flush_writes(ctx->ohci); |
32b46093 KH |
561 | |
562 | return 0; | |
ed568912 KH |
563 | } |
564 | ||
a55709ba JF |
565 | static void ar_context_release(struct ar_context *ctx) |
566 | { | |
567 | struct ar_buffer *ab, *ab_next; | |
568 | size_t offset; | |
569 | dma_addr_t ab_bus; | |
570 | ||
571 | for (ab = ctx->current_buffer; ab; ab = ab_next) { | |
572 | ab_next = ab->next; | |
573 | offset = offsetof(struct ar_buffer, data); | |
574 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; | |
575 | dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
576 | ab, ab_bus); | |
577 | } | |
578 | } | |
579 | ||
11bf20ad SR |
580 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
581 | #define cond_le32_to_cpu(v) \ | |
4a635593 | 582 | (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) |
11bf20ad SR |
583 | #else |
584 | #define cond_le32_to_cpu(v) le32_to_cpu(v) | |
585 | #endif | |
586 | ||
32b46093 | 587 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 588 | { |
ed568912 | 589 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
590 | struct fw_packet p; |
591 | u32 status, length, tcode; | |
43286568 | 592 | int evt; |
2639a6fb | 593 | |
11bf20ad SR |
594 | p.header[0] = cond_le32_to_cpu(buffer[0]); |
595 | p.header[1] = cond_le32_to_cpu(buffer[1]); | |
596 | p.header[2] = cond_le32_to_cpu(buffer[2]); | |
2639a6fb KH |
597 | |
598 | tcode = (p.header[0] >> 4) & 0x0f; | |
599 | switch (tcode) { | |
600 | case TCODE_WRITE_QUADLET_REQUEST: | |
601 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 602 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 603 | p.header_length = 16; |
32b46093 | 604 | p.payload_length = 0; |
2639a6fb KH |
605 | break; |
606 | ||
2639a6fb | 607 | case TCODE_READ_BLOCK_REQUEST : |
11bf20ad | 608 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
32b46093 KH |
609 | p.header_length = 16; |
610 | p.payload_length = 0; | |
611 | break; | |
612 | ||
613 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
614 | case TCODE_READ_BLOCK_RESPONSE: |
615 | case TCODE_LOCK_REQUEST: | |
616 | case TCODE_LOCK_RESPONSE: | |
11bf20ad | 617 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
2639a6fb | 618 | p.header_length = 16; |
32b46093 | 619 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
620 | break; |
621 | ||
622 | case TCODE_WRITE_RESPONSE: | |
623 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 624 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 625 | p.header_length = 12; |
32b46093 | 626 | p.payload_length = 0; |
2639a6fb | 627 | break; |
ccff9629 SR |
628 | |
629 | default: | |
630 | /* FIXME: Stop context, discard everything, and restart? */ | |
631 | p.header_length = 0; | |
632 | p.payload_length = 0; | |
2639a6fb | 633 | } |
ed568912 | 634 | |
32b46093 KH |
635 | p.payload = (void *) buffer + p.header_length; |
636 | ||
637 | /* FIXME: What to do about evt_* errors? */ | |
638 | length = (p.header_length + p.payload_length + 3) / 4; | |
11bf20ad | 639 | status = cond_le32_to_cpu(buffer[length]); |
43286568 | 640 | evt = (status >> 16) & 0x1f; |
32b46093 | 641 | |
43286568 | 642 | p.ack = evt - 16; |
32b46093 KH |
643 | p.speed = (status >> 21) & 0x7; |
644 | p.timestamp = status & 0xffff; | |
645 | p.generation = ohci->request_generation; | |
ed568912 | 646 | |
43286568 | 647 | log_ar_at_event('R', p.speed, p.header, evt); |
ad3c0fe8 | 648 | |
c781c06d KH |
649 | /* |
650 | * The OHCI bus reset handler synthesizes a phy packet with | |
ed568912 KH |
651 | * the new generation number when a bus reset happens (see |
652 | * section 8.4.2.3). This helps us determine when a request | |
653 | * was received and make sure we send the response in the same | |
654 | * generation. We only need this for requests; for responses | |
655 | * we use the unique tlabel for finding the matching | |
c781c06d | 656 | * request. |
d34316a4 SR |
657 | * |
658 | * Alas some chips sometimes emit bus reset packets with a | |
659 | * wrong generation. We set the correct generation for these | |
660 | * at a slightly incorrect time (in bus_reset_tasklet). | |
c781c06d | 661 | */ |
d34316a4 | 662 | if (evt == OHCI1394_evt_bus_reset) { |
4a635593 | 663 | if (!(ohci->quirks & QUIRK_RESET_PACKET)) |
d34316a4 SR |
664 | ohci->request_generation = (p.header[2] >> 16) & 0xff; |
665 | } else if (ctx == &ohci->ar_request_ctx) { | |
2639a6fb | 666 | fw_core_handle_request(&ohci->card, &p); |
d34316a4 | 667 | } else { |
2639a6fb | 668 | fw_core_handle_response(&ohci->card, &p); |
d34316a4 | 669 | } |
ed568912 | 670 | |
32b46093 KH |
671 | return buffer + length + 1; |
672 | } | |
ed568912 | 673 | |
32b46093 KH |
674 | static void ar_context_tasklet(unsigned long data) |
675 | { | |
676 | struct ar_context *ctx = (struct ar_context *)data; | |
677 | struct fw_ohci *ohci = ctx->ohci; | |
678 | struct ar_buffer *ab; | |
679 | struct descriptor *d; | |
680 | void *buffer, *end; | |
681 | ||
682 | ab = ctx->current_buffer; | |
683 | d = &ab->descriptor; | |
684 | ||
685 | if (d->res_count == 0) { | |
686 | size_t size, rest, offset; | |
6b84236d JW |
687 | dma_addr_t start_bus; |
688 | void *start; | |
32b46093 | 689 | |
c781c06d KH |
690 | /* |
691 | * This descriptor is finished and we may have a | |
32b46093 | 692 | * packet split across this and the next buffer. We |
c781c06d KH |
693 | * reuse the page for reassembling the split packet. |
694 | */ | |
32b46093 KH |
695 | |
696 | offset = offsetof(struct ar_buffer, data); | |
6b84236d JW |
697 | start = buffer = ab; |
698 | start_bus = le32_to_cpu(ab->descriptor.data_address) - offset; | |
32b46093 | 699 | |
32b46093 KH |
700 | ab = ab->next; |
701 | d = &ab->descriptor; | |
702 | size = buffer + PAGE_SIZE - ctx->pointer; | |
703 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
704 | memmove(buffer, ctx->pointer, size); | |
705 | memcpy(buffer + size, ab->data, rest); | |
706 | ctx->current_buffer = ab; | |
707 | ctx->pointer = (void *) ab->data + rest; | |
708 | end = buffer + size + rest; | |
709 | ||
710 | while (buffer < end) | |
711 | buffer = handle_ar_packet(ctx, buffer); | |
712 | ||
bde1709a | 713 | dma_free_coherent(ohci->card.device, PAGE_SIZE, |
6b84236d | 714 | start, start_bus); |
32b46093 KH |
715 | ar_context_add_page(ctx); |
716 | } else { | |
717 | buffer = ctx->pointer; | |
718 | ctx->pointer = end = | |
719 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
720 | ||
721 | while (buffer < end) | |
722 | buffer = handle_ar_packet(ctx, buffer); | |
723 | } | |
ed568912 KH |
724 | } |
725 | ||
53dca511 SR |
726 | static int ar_context_init(struct ar_context *ctx, |
727 | struct fw_ohci *ohci, u32 regs) | |
ed568912 | 728 | { |
32b46093 | 729 | struct ar_buffer ab; |
ed568912 | 730 | |
72e318e0 KH |
731 | ctx->regs = regs; |
732 | ctx->ohci = ohci; | |
733 | ctx->last_buffer = &ab; | |
ed568912 KH |
734 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
735 | ||
32b46093 KH |
736 | ar_context_add_page(ctx); |
737 | ar_context_add_page(ctx); | |
738 | ctx->current_buffer = ab.next; | |
739 | ctx->pointer = ctx->current_buffer->data; | |
740 | ||
2aef469a KH |
741 | return 0; |
742 | } | |
743 | ||
744 | static void ar_context_run(struct ar_context *ctx) | |
745 | { | |
746 | struct ar_buffer *ab = ctx->current_buffer; | |
747 | dma_addr_t ab_bus; | |
748 | size_t offset; | |
749 | ||
750 | offset = offsetof(struct ar_buffer, data); | |
0a9972ba | 751 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
2aef469a KH |
752 | |
753 | reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); | |
a77754a7 | 754 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093 | 755 | flush_writes(ctx->ohci); |
ed568912 | 756 | } |
373b2edd | 757 | |
53dca511 | 758 | static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) |
a186b4a6 JW |
759 | { |
760 | int b, key; | |
761 | ||
762 | b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; | |
763 | key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; | |
764 | ||
765 | /* figure out which descriptor the branch address goes in */ | |
766 | if (z == 2 && (b == 3 || key == 2)) | |
767 | return d; | |
768 | else | |
769 | return d + z - 1; | |
770 | } | |
771 | ||
30200739 KH |
772 | static void context_tasklet(unsigned long data) |
773 | { | |
774 | struct context *ctx = (struct context *) data; | |
30200739 KH |
775 | struct descriptor *d, *last; |
776 | u32 address; | |
777 | int z; | |
fe5ca634 | 778 | struct descriptor_buffer *desc; |
30200739 | 779 | |
fe5ca634 DM |
780 | desc = list_entry(ctx->buffer_list.next, |
781 | struct descriptor_buffer, list); | |
782 | last = ctx->last; | |
30200739 | 783 | while (last->branch_address != 0) { |
fe5ca634 | 784 | struct descriptor_buffer *old_desc = desc; |
30200739 KH |
785 | address = le32_to_cpu(last->branch_address); |
786 | z = address & 0xf; | |
fe5ca634 DM |
787 | address &= ~0xf; |
788 | ||
789 | /* If the branch address points to a buffer outside of the | |
790 | * current buffer, advance to the next buffer. */ | |
791 | if (address < desc->buffer_bus || | |
792 | address >= desc->buffer_bus + desc->used) | |
793 | desc = list_entry(desc->list.next, | |
794 | struct descriptor_buffer, list); | |
795 | d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); | |
a186b4a6 | 796 | last = find_branch_descriptor(d, z); |
30200739 KH |
797 | |
798 | if (!ctx->callback(ctx, d, last)) | |
799 | break; | |
800 | ||
fe5ca634 DM |
801 | if (old_desc != desc) { |
802 | /* If we've advanced to the next buffer, move the | |
803 | * previous buffer to the free list. */ | |
804 | unsigned long flags; | |
805 | old_desc->used = 0; | |
806 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
807 | list_move_tail(&old_desc->list, &ctx->buffer_list); | |
808 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); | |
809 | } | |
810 | ctx->last = last; | |
30200739 KH |
811 | } |
812 | } | |
813 | ||
fe5ca634 DM |
814 | /* |
815 | * Allocate a new buffer and add it to the list of free buffers for this | |
816 | * context. Must be called with ohci->lock held. | |
817 | */ | |
53dca511 | 818 | static int context_add_buffer(struct context *ctx) |
fe5ca634 DM |
819 | { |
820 | struct descriptor_buffer *desc; | |
f5101d58 | 821 | dma_addr_t uninitialized_var(bus_addr); |
fe5ca634 DM |
822 | int offset; |
823 | ||
824 | /* | |
825 | * 16MB of descriptors should be far more than enough for any DMA | |
826 | * program. This will catch run-away userspace or DoS attacks. | |
827 | */ | |
828 | if (ctx->total_allocation >= 16*1024*1024) | |
829 | return -ENOMEM; | |
830 | ||
831 | desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
832 | &bus_addr, GFP_ATOMIC); | |
833 | if (!desc) | |
834 | return -ENOMEM; | |
835 | ||
836 | offset = (void *)&desc->buffer - (void *)desc; | |
837 | desc->buffer_size = PAGE_SIZE - offset; | |
838 | desc->buffer_bus = bus_addr + offset; | |
839 | desc->used = 0; | |
840 | ||
841 | list_add_tail(&desc->list, &ctx->buffer_list); | |
842 | ctx->total_allocation += PAGE_SIZE; | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
53dca511 SR |
847 | static int context_init(struct context *ctx, struct fw_ohci *ohci, |
848 | u32 regs, descriptor_callback_t callback) | |
30200739 KH |
849 | { |
850 | ctx->ohci = ohci; | |
851 | ctx->regs = regs; | |
fe5ca634 DM |
852 | ctx->total_allocation = 0; |
853 | ||
854 | INIT_LIST_HEAD(&ctx->buffer_list); | |
855 | if (context_add_buffer(ctx) < 0) | |
30200739 KH |
856 | return -ENOMEM; |
857 | ||
fe5ca634 DM |
858 | ctx->buffer_tail = list_entry(ctx->buffer_list.next, |
859 | struct descriptor_buffer, list); | |
860 | ||
30200739 KH |
861 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); |
862 | ctx->callback = callback; | |
863 | ||
c781c06d KH |
864 | /* |
865 | * We put a dummy descriptor in the buffer that has a NULL | |
30200739 | 866 | * branch address and looks like it's been sent. That way we |
fe5ca634 | 867 | * have a descriptor to append DMA programs to. |
c781c06d | 868 | */ |
fe5ca634 DM |
869 | memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); |
870 | ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); | |
871 | ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); | |
872 | ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); | |
873 | ctx->last = ctx->buffer_tail->buffer; | |
874 | ctx->prev = ctx->buffer_tail->buffer; | |
30200739 KH |
875 | |
876 | return 0; | |
877 | } | |
878 | ||
53dca511 | 879 | static void context_release(struct context *ctx) |
30200739 KH |
880 | { |
881 | struct fw_card *card = &ctx->ohci->card; | |
fe5ca634 | 882 | struct descriptor_buffer *desc, *tmp; |
30200739 | 883 | |
fe5ca634 DM |
884 | list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) |
885 | dma_free_coherent(card->device, PAGE_SIZE, desc, | |
886 | desc->buffer_bus - | |
887 | ((void *)&desc->buffer - (void *)desc)); | |
30200739 KH |
888 | } |
889 | ||
fe5ca634 | 890 | /* Must be called with ohci->lock held */ |
53dca511 SR |
891 | static struct descriptor *context_get_descriptors(struct context *ctx, |
892 | int z, dma_addr_t *d_bus) | |
30200739 | 893 | { |
fe5ca634 DM |
894 | struct descriptor *d = NULL; |
895 | struct descriptor_buffer *desc = ctx->buffer_tail; | |
896 | ||
897 | if (z * sizeof(*d) > desc->buffer_size) | |
898 | return NULL; | |
899 | ||
900 | if (z * sizeof(*d) > desc->buffer_size - desc->used) { | |
901 | /* No room for the descriptor in this buffer, so advance to the | |
902 | * next one. */ | |
30200739 | 903 | |
fe5ca634 DM |
904 | if (desc->list.next == &ctx->buffer_list) { |
905 | /* If there is no free buffer next in the list, | |
906 | * allocate one. */ | |
907 | if (context_add_buffer(ctx) < 0) | |
908 | return NULL; | |
909 | } | |
910 | desc = list_entry(desc->list.next, | |
911 | struct descriptor_buffer, list); | |
912 | ctx->buffer_tail = desc; | |
913 | } | |
30200739 | 914 | |
fe5ca634 | 915 | d = desc->buffer + desc->used / sizeof(*d); |
2d826cc5 | 916 | memset(d, 0, z * sizeof(*d)); |
fe5ca634 | 917 | *d_bus = desc->buffer_bus + desc->used; |
30200739 KH |
918 | |
919 | return d; | |
920 | } | |
921 | ||
295e3feb | 922 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
923 | { |
924 | struct fw_ohci *ohci = ctx->ohci; | |
925 | ||
a77754a7 | 926 | reg_write(ohci, COMMAND_PTR(ctx->regs), |
fe5ca634 | 927 | le32_to_cpu(ctx->last->branch_address)); |
a77754a7 KH |
928 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); |
929 | reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); | |
30200739 KH |
930 | flush_writes(ohci); |
931 | } | |
932 | ||
933 | static void context_append(struct context *ctx, | |
934 | struct descriptor *d, int z, int extra) | |
935 | { | |
936 | dma_addr_t d_bus; | |
fe5ca634 | 937 | struct descriptor_buffer *desc = ctx->buffer_tail; |
30200739 | 938 | |
fe5ca634 | 939 | d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); |
30200739 | 940 | |
fe5ca634 DM |
941 | desc->used += (z + extra) * sizeof(*d); |
942 | ctx->prev->branch_address = cpu_to_le32(d_bus | z); | |
943 | ctx->prev = find_branch_descriptor(d, z); | |
30200739 | 944 | |
a77754a7 | 945 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739 KH |
946 | flush_writes(ctx->ohci); |
947 | } | |
948 | ||
949 | static void context_stop(struct context *ctx) | |
950 | { | |
951 | u32 reg; | |
b8295668 | 952 | int i; |
30200739 | 953 | |
a77754a7 | 954 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b8295668 | 955 | flush_writes(ctx->ohci); |
30200739 | 956 | |
b8295668 | 957 | for (i = 0; i < 10; i++) { |
a77754a7 | 958 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b8295668 | 959 | if ((reg & CONTEXT_ACTIVE) == 0) |
b0068549 | 960 | return; |
b8295668 | 961 | |
b980f5a2 | 962 | mdelay(1); |
b8295668 | 963 | } |
b0068549 | 964 | fw_error("Error: DMA context still active (0x%08x)\n", reg); |
30200739 | 965 | } |
ed568912 | 966 | |
f319b6a0 KH |
967 | struct driver_data { |
968 | struct fw_packet *packet; | |
969 | }; | |
ed568912 | 970 | |
c781c06d KH |
971 | /* |
972 | * This function apppends a packet to the DMA queue for transmission. | |
f319b6a0 | 973 | * Must always be called with the ochi->lock held to ensure proper |
c781c06d KH |
974 | * generation handling and locking around packet queue manipulation. |
975 | */ | |
53dca511 SR |
976 | static int at_context_queue_packet(struct context *ctx, |
977 | struct fw_packet *packet) | |
ed568912 | 978 | { |
ed568912 | 979 | struct fw_ohci *ohci = ctx->ohci; |
4b6d51ec | 980 | dma_addr_t d_bus, uninitialized_var(payload_bus); |
f319b6a0 KH |
981 | struct driver_data *driver_data; |
982 | struct descriptor *d, *last; | |
983 | __le32 *header; | |
ed568912 | 984 | int z, tcode; |
f319b6a0 | 985 | u32 reg; |
ed568912 | 986 | |
f319b6a0 KH |
987 | d = context_get_descriptors(ctx, 4, &d_bus); |
988 | if (d == NULL) { | |
989 | packet->ack = RCODE_SEND_ERROR; | |
990 | return -1; | |
ed568912 KH |
991 | } |
992 | ||
a77754a7 | 993 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a0 KH |
994 | d[0].res_count = cpu_to_le16(packet->timestamp); |
995 | ||
c781c06d KH |
996 | /* |
997 | * The DMA format for asyncronous link packets is different | |
ed568912 KH |
998 | * from the IEEE1394 layout, so shift the fields around |
999 | * accordingly. If header_length is 8, it's a PHY packet, to | |
c781c06d KH |
1000 | * which we need to prepend an extra quadlet. |
1001 | */ | |
f319b6a0 KH |
1002 | |
1003 | header = (__le32 *) &d[1]; | |
f8c2287c JF |
1004 | switch (packet->header_length) { |
1005 | case 16: | |
1006 | case 12: | |
f319b6a0 KH |
1007 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
1008 | (packet->speed << 16)); | |
1009 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
1010 | (packet->header[0] & 0xffff0000)); | |
1011 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 KH |
1012 | |
1013 | tcode = (packet->header[0] >> 4) & 0x0f; | |
1014 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
f319b6a0 | 1015 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 1016 | else |
f319b6a0 KH |
1017 | header[3] = (__force __le32) packet->header[3]; |
1018 | ||
1019 | d[0].req_count = cpu_to_le16(packet->header_length); | |
f8c2287c JF |
1020 | break; |
1021 | ||
1022 | case 8: | |
f319b6a0 KH |
1023 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
1024 | (packet->speed << 16)); | |
1025 | header[1] = cpu_to_le32(packet->header[0]); | |
1026 | header[2] = cpu_to_le32(packet->header[1]); | |
1027 | d[0].req_count = cpu_to_le16(12); | |
f8c2287c JF |
1028 | break; |
1029 | ||
1030 | case 4: | |
1031 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | | |
1032 | (packet->speed << 16)); | |
1033 | header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); | |
1034 | d[0].req_count = cpu_to_le16(8); | |
1035 | break; | |
1036 | ||
1037 | default: | |
1038 | /* BUG(); */ | |
1039 | packet->ack = RCODE_SEND_ERROR; | |
1040 | return -1; | |
ed568912 KH |
1041 | } |
1042 | ||
f319b6a0 KH |
1043 | driver_data = (struct driver_data *) &d[3]; |
1044 | driver_data->packet = packet; | |
20d11673 | 1045 | packet->driver_data = driver_data; |
a186b4a6 | 1046 | |
f319b6a0 KH |
1047 | if (packet->payload_length > 0) { |
1048 | payload_bus = | |
1049 | dma_map_single(ohci->card.device, packet->payload, | |
1050 | packet->payload_length, DMA_TO_DEVICE); | |
8d8bb39b | 1051 | if (dma_mapping_error(ohci->card.device, payload_bus)) { |
f319b6a0 KH |
1052 | packet->ack = RCODE_SEND_ERROR; |
1053 | return -1; | |
1054 | } | |
19593ffd SR |
1055 | packet->payload_bus = payload_bus; |
1056 | packet->payload_mapped = true; | |
f319b6a0 KH |
1057 | |
1058 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
1059 | d[2].data_address = cpu_to_le32(payload_bus); | |
1060 | last = &d[2]; | |
1061 | z = 3; | |
ed568912 | 1062 | } else { |
f319b6a0 KH |
1063 | last = &d[0]; |
1064 | z = 2; | |
ed568912 | 1065 | } |
ed568912 | 1066 | |
a77754a7 KH |
1067 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
1068 | DESCRIPTOR_IRQ_ALWAYS | | |
1069 | DESCRIPTOR_BRANCH_ALWAYS); | |
ed568912 | 1070 | |
76f73ca1 JW |
1071 | /* |
1072 | * If the controller and packet generations don't match, we need to | |
1073 | * bail out and try again. If IntEvent.busReset is set, the AT context | |
1074 | * is halted, so appending to the context and trying to run it is | |
1075 | * futile. Most controllers do the right thing and just flush the AT | |
1076 | * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but | |
1077 | * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind | |
1078 | * up stalling out. So we just bail out in software and try again | |
1079 | * later, and everyone is happy. | |
1080 | * FIXME: Document how the locking works. | |
1081 | */ | |
1082 | if (ohci->generation != packet->generation || | |
1083 | reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { | |
19593ffd | 1084 | if (packet->payload_mapped) |
ab88ca48 SR |
1085 | dma_unmap_single(ohci->card.device, payload_bus, |
1086 | packet->payload_length, DMA_TO_DEVICE); | |
f319b6a0 KH |
1087 | packet->ack = RCODE_GENERATION; |
1088 | return -1; | |
1089 | } | |
1090 | ||
1091 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 1092 | |
f319b6a0 | 1093 | /* If the context isn't already running, start it up. */ |
a77754a7 | 1094 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b3080 | 1095 | if ((reg & CONTEXT_RUN) == 0) |
f319b6a0 KH |
1096 | context_run(ctx, 0); |
1097 | ||
1098 | return 0; | |
ed568912 KH |
1099 | } |
1100 | ||
f319b6a0 KH |
1101 | static int handle_at_packet(struct context *context, |
1102 | struct descriptor *d, | |
1103 | struct descriptor *last) | |
ed568912 | 1104 | { |
f319b6a0 | 1105 | struct driver_data *driver_data; |
ed568912 | 1106 | struct fw_packet *packet; |
f319b6a0 | 1107 | struct fw_ohci *ohci = context->ohci; |
ed568912 KH |
1108 | int evt; |
1109 | ||
f319b6a0 KH |
1110 | if (last->transfer_status == 0) |
1111 | /* This descriptor isn't done yet, stop iteration. */ | |
1112 | return 0; | |
ed568912 | 1113 | |
f319b6a0 KH |
1114 | driver_data = (struct driver_data *) &d[3]; |
1115 | packet = driver_data->packet; | |
1116 | if (packet == NULL) | |
1117 | /* This packet was cancelled, just continue. */ | |
1118 | return 1; | |
730c32f5 | 1119 | |
19593ffd | 1120 | if (packet->payload_mapped) |
1d1dc5e8 | 1121 | dma_unmap_single(ohci->card.device, packet->payload_bus, |
ed568912 | 1122 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 1123 | |
f319b6a0 KH |
1124 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
1125 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 1126 | |
ad3c0fe8 SR |
1127 | log_ar_at_event('T', packet->speed, packet->header, evt); |
1128 | ||
f319b6a0 KH |
1129 | switch (evt) { |
1130 | case OHCI1394_evt_timeout: | |
1131 | /* Async response transmit timed out. */ | |
1132 | packet->ack = RCODE_CANCELLED; | |
1133 | break; | |
ed568912 | 1134 | |
f319b6a0 | 1135 | case OHCI1394_evt_flushed: |
c781c06d KH |
1136 | /* |
1137 | * The packet was flushed should give same error as | |
1138 | * when we try to use a stale generation count. | |
1139 | */ | |
f319b6a0 KH |
1140 | packet->ack = RCODE_GENERATION; |
1141 | break; | |
ed568912 | 1142 | |
f319b6a0 | 1143 | case OHCI1394_evt_missing_ack: |
c781c06d KH |
1144 | /* |
1145 | * Using a valid (current) generation count, but the | |
1146 | * node is not on the bus or not sending acks. | |
1147 | */ | |
f319b6a0 KH |
1148 | packet->ack = RCODE_NO_ACK; |
1149 | break; | |
ed568912 | 1150 | |
f319b6a0 KH |
1151 | case ACK_COMPLETE + 0x10: |
1152 | case ACK_PENDING + 0x10: | |
1153 | case ACK_BUSY_X + 0x10: | |
1154 | case ACK_BUSY_A + 0x10: | |
1155 | case ACK_BUSY_B + 0x10: | |
1156 | case ACK_DATA_ERROR + 0x10: | |
1157 | case ACK_TYPE_ERROR + 0x10: | |
1158 | packet->ack = evt - 0x10; | |
1159 | break; | |
ed568912 | 1160 | |
f319b6a0 KH |
1161 | default: |
1162 | packet->ack = RCODE_SEND_ERROR; | |
1163 | break; | |
1164 | } | |
ed568912 | 1165 | |
f319b6a0 | 1166 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 1167 | |
f319b6a0 | 1168 | return 1; |
ed568912 KH |
1169 | } |
1170 | ||
a77754a7 KH |
1171 | #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) |
1172 | #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) | |
1173 | #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) | |
1174 | #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) | |
1175 | #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) | |
93c4cceb | 1176 | |
53dca511 SR |
1177 | static void handle_local_rom(struct fw_ohci *ohci, |
1178 | struct fw_packet *packet, u32 csr) | |
93c4cceb KH |
1179 | { |
1180 | struct fw_packet response; | |
1181 | int tcode, length, i; | |
1182 | ||
a77754a7 | 1183 | tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb | 1184 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a7 | 1185 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb KH |
1186 | else |
1187 | length = 4; | |
1188 | ||
1189 | i = csr - CSR_CONFIG_ROM; | |
1190 | if (i + length > CONFIG_ROM_SIZE) { | |
1191 | fw_fill_response(&response, packet->header, | |
1192 | RCODE_ADDRESS_ERROR, NULL, 0); | |
1193 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
1194 | fw_fill_response(&response, packet->header, | |
1195 | RCODE_TYPE_ERROR, NULL, 0); | |
1196 | } else { | |
1197 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
1198 | (void *) ohci->config_rom + i, length); | |
1199 | } | |
1200 | ||
1201 | fw_core_handle_response(&ohci->card, &response); | |
1202 | } | |
1203 | ||
53dca511 SR |
1204 | static void handle_local_lock(struct fw_ohci *ohci, |
1205 | struct fw_packet *packet, u32 csr) | |
93c4cceb KH |
1206 | { |
1207 | struct fw_packet response; | |
1208 | int tcode, length, ext_tcode, sel; | |
1209 | __be32 *payload, lock_old; | |
1210 | u32 lock_arg, lock_data; | |
1211 | ||
a77754a7 KH |
1212 | tcode = HEADER_GET_TCODE(packet->header[0]); |
1213 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); | |
93c4cceb | 1214 | payload = packet->payload; |
a77754a7 | 1215 | ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb KH |
1216 | |
1217 | if (tcode == TCODE_LOCK_REQUEST && | |
1218 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
1219 | lock_arg = be32_to_cpu(payload[0]); | |
1220 | lock_data = be32_to_cpu(payload[1]); | |
1221 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
1222 | lock_arg = 0; | |
1223 | lock_data = 0; | |
1224 | } else { | |
1225 | fw_fill_response(&response, packet->header, | |
1226 | RCODE_TYPE_ERROR, NULL, 0); | |
1227 | goto out; | |
1228 | } | |
1229 | ||
1230 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
1231 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
1232 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
1233 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
1234 | ||
1235 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
1236 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
1237 | else | |
1238 | fw_notify("swap not done yet\n"); | |
1239 | ||
1240 | fw_fill_response(&response, packet->header, | |
2d826cc5 | 1241 | RCODE_COMPLETE, &lock_old, sizeof(lock_old)); |
93c4cceb KH |
1242 | out: |
1243 | fw_core_handle_response(&ohci->card, &response); | |
1244 | } | |
1245 | ||
53dca511 | 1246 | static void handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb KH |
1247 | { |
1248 | u64 offset; | |
1249 | u32 csr; | |
1250 | ||
473d28c7 KH |
1251 | if (ctx == &ctx->ohci->at_request_ctx) { |
1252 | packet->ack = ACK_PENDING; | |
1253 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1254 | } | |
93c4cceb KH |
1255 | |
1256 | offset = | |
1257 | ((unsigned long long) | |
a77754a7 | 1258 | HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb KH |
1259 | packet->header[2]; |
1260 | csr = offset - CSR_REGISTER_BASE; | |
1261 | ||
1262 | /* Handle config rom reads. */ | |
1263 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
1264 | handle_local_rom(ctx->ohci, packet, csr); | |
1265 | else switch (csr) { | |
1266 | case CSR_BUS_MANAGER_ID: | |
1267 | case CSR_BANDWIDTH_AVAILABLE: | |
1268 | case CSR_CHANNELS_AVAILABLE_HI: | |
1269 | case CSR_CHANNELS_AVAILABLE_LO: | |
1270 | handle_local_lock(ctx->ohci, packet, csr); | |
1271 | break; | |
1272 | default: | |
1273 | if (ctx == &ctx->ohci->at_request_ctx) | |
1274 | fw_core_handle_request(&ctx->ohci->card, packet); | |
1275 | else | |
1276 | fw_core_handle_response(&ctx->ohci->card, packet); | |
1277 | break; | |
1278 | } | |
473d28c7 KH |
1279 | |
1280 | if (ctx == &ctx->ohci->at_response_ctx) { | |
1281 | packet->ack = ACK_COMPLETE; | |
1282 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1283 | } | |
93c4cceb | 1284 | } |
e636fe25 | 1285 | |
53dca511 | 1286 | static void at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 1287 | { |
ed568912 | 1288 | unsigned long flags; |
2dbd7d7e | 1289 | int ret; |
ed568912 KH |
1290 | |
1291 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
1292 | ||
a77754a7 | 1293 | if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe25 | 1294 | ctx->ohci->generation == packet->generation) { |
93c4cceb KH |
1295 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1296 | handle_local_request(ctx, packet); | |
1297 | return; | |
e636fe25 | 1298 | } |
ed568912 | 1299 | |
2dbd7d7e | 1300 | ret = at_context_queue_packet(ctx, packet); |
ed568912 KH |
1301 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1302 | ||
2dbd7d7e | 1303 | if (ret < 0) |
f319b6a0 | 1304 | packet->callback(packet, &ctx->ohci->card, packet->ack); |
a186b4a6 | 1305 | |
ed568912 KH |
1306 | } |
1307 | ||
1308 | static void bus_reset_tasklet(unsigned long data) | |
1309 | { | |
1310 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 1311 | int self_id_count, i, j, reg; |
ed568912 KH |
1312 | int generation, new_generation; |
1313 | unsigned long flags; | |
4eaff7d6 SR |
1314 | void *free_rom = NULL; |
1315 | dma_addr_t free_rom_bus = 0; | |
ed568912 KH |
1316 | |
1317 | reg = reg_read(ohci, OHCI1394_NodeID); | |
1318 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
02ff8f8e | 1319 | fw_notify("node ID not valid, new bus reset in progress\n"); |
ed568912 KH |
1320 | return; |
1321 | } | |
02ff8f8e SR |
1322 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { |
1323 | fw_notify("malconfigured bus\n"); | |
1324 | return; | |
1325 | } | |
1326 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | | |
1327 | OHCI1394_NodeID_nodeNumber); | |
ed568912 | 1328 | |
c8a9a498 SR |
1329 | reg = reg_read(ohci, OHCI1394_SelfIDCount); |
1330 | if (reg & OHCI1394_SelfIDCount_selfIDError) { | |
1331 | fw_notify("inconsistent self IDs\n"); | |
1332 | return; | |
1333 | } | |
c781c06d KH |
1334 | /* |
1335 | * The count in the SelfIDCount register is the number of | |
ed568912 KH |
1336 | * bytes in the self ID receive buffer. Since we also receive |
1337 | * the inverted quadlets and a header quadlet, we shift one | |
c781c06d KH |
1338 | * bit extra to get the actual number of self IDs. |
1339 | */ | |
928ec5f1 SR |
1340 | self_id_count = (reg >> 3) & 0xff; |
1341 | if (self_id_count == 0 || self_id_count > 252) { | |
016bf3df SR |
1342 | fw_notify("inconsistent self IDs\n"); |
1343 | return; | |
1344 | } | |
11bf20ad | 1345 | generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; |
ee71c2f9 | 1346 | rmb(); |
ed568912 KH |
1347 | |
1348 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
c8a9a498 SR |
1349 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { |
1350 | fw_notify("inconsistent self IDs\n"); | |
1351 | return; | |
1352 | } | |
11bf20ad SR |
1353 | ohci->self_id_buffer[j] = |
1354 | cond_le32_to_cpu(ohci->self_id_cpu[i]); | |
ed568912 | 1355 | } |
ee71c2f9 | 1356 | rmb(); |
ed568912 | 1357 | |
c781c06d KH |
1358 | /* |
1359 | * Check the consistency of the self IDs we just read. The | |
ed568912 KH |
1360 | * problem we face is that a new bus reset can start while we |
1361 | * read out the self IDs from the DMA buffer. If this happens, | |
1362 | * the DMA buffer will be overwritten with new self IDs and we | |
1363 | * will read out inconsistent data. The OHCI specification | |
1364 | * (section 11.2) recommends a technique similar to | |
1365 | * linux/seqlock.h, where we remember the generation of the | |
1366 | * self IDs in the buffer before reading them out and compare | |
1367 | * it to the current generation after reading them out. If | |
1368 | * the two generations match we know we have a consistent set | |
c781c06d KH |
1369 | * of self IDs. |
1370 | */ | |
ed568912 KH |
1371 | |
1372 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
1373 | if (new_generation != generation) { | |
1374 | fw_notify("recursive bus reset detected, " | |
1375 | "discarding self ids\n"); | |
1376 | return; | |
1377 | } | |
1378 | ||
1379 | /* FIXME: Document how the locking works. */ | |
1380 | spin_lock_irqsave(&ohci->lock, flags); | |
1381 | ||
1382 | ohci->generation = generation; | |
f319b6a0 KH |
1383 | context_stop(&ohci->at_request_ctx); |
1384 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
1385 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
1386 | ||
4a635593 | 1387 | if (ohci->quirks & QUIRK_RESET_PACKET) |
d34316a4 SR |
1388 | ohci->request_generation = generation; |
1389 | ||
c781c06d KH |
1390 | /* |
1391 | * This next bit is unrelated to the AT context stuff but we | |
ed568912 KH |
1392 | * have to do it under the spinlock also. If a new config rom |
1393 | * was set up before this reset, the old one is now no longer | |
1394 | * in use and we can free it. Update the config rom pointers | |
1395 | * to point to the current config rom and clear the | |
c781c06d KH |
1396 | * next_config_rom pointer so a new udpate can take place. |
1397 | */ | |
ed568912 KH |
1398 | |
1399 | if (ohci->next_config_rom != NULL) { | |
0bd243c4 KH |
1400 | if (ohci->next_config_rom != ohci->config_rom) { |
1401 | free_rom = ohci->config_rom; | |
1402 | free_rom_bus = ohci->config_rom_bus; | |
1403 | } | |
ed568912 KH |
1404 | ohci->config_rom = ohci->next_config_rom; |
1405 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
1406 | ohci->next_config_rom = NULL; | |
1407 | ||
c781c06d KH |
1408 | /* |
1409 | * Restore config_rom image and manually update | |
ed568912 KH |
1410 | * config_rom registers. Writing the header quadlet |
1411 | * will indicate that the config rom is ready, so we | |
c781c06d KH |
1412 | * do that last. |
1413 | */ | |
ed568912 KH |
1414 | reg_write(ohci, OHCI1394_BusOptions, |
1415 | be32_to_cpu(ohci->config_rom[2])); | |
8e85973e SR |
1416 | ohci->config_rom[0] = ohci->next_header; |
1417 | reg_write(ohci, OHCI1394_ConfigROMhdr, | |
1418 | be32_to_cpu(ohci->next_header)); | |
ed568912 KH |
1419 | } |
1420 | ||
080de8c2 SR |
1421 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1422 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); | |
1423 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); | |
1424 | #endif | |
1425 | ||
ed568912 KH |
1426 | spin_unlock_irqrestore(&ohci->lock, flags); |
1427 | ||
4eaff7d6 SR |
1428 | if (free_rom) |
1429 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1430 | free_rom, free_rom_bus); | |
1431 | ||
08ddb2f4 SR |
1432 | log_selfids(ohci->node_id, generation, |
1433 | self_id_count, ohci->self_id_buffer); | |
ad3c0fe8 | 1434 | |
e636fe25 | 1435 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
1436 | self_id_count, ohci->self_id_buffer); |
1437 | } | |
1438 | ||
1439 | static irqreturn_t irq_handler(int irq, void *data) | |
1440 | { | |
1441 | struct fw_ohci *ohci = data; | |
168cf9af | 1442 | u32 event, iso_event; |
ed568912 KH |
1443 | int i; |
1444 | ||
1445 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1446 | ||
a515958d | 1447 | if (!event || !~event) |
ed568912 KH |
1448 | return IRQ_NONE; |
1449 | ||
a007bb85 SR |
1450 | /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */ |
1451 | reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset); | |
ad3c0fe8 | 1452 | log_irqs(event); |
ed568912 KH |
1453 | |
1454 | if (event & OHCI1394_selfIDComplete) | |
1455 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1456 | ||
1457 | if (event & OHCI1394_RQPkt) | |
1458 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1459 | ||
1460 | if (event & OHCI1394_RSPkt) | |
1461 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1462 | ||
1463 | if (event & OHCI1394_reqTxComplete) | |
1464 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1465 | ||
1466 | if (event & OHCI1394_respTxComplete) | |
1467 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1468 | ||
c889475f | 1469 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1470 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1471 | ||
1472 | while (iso_event) { | |
1473 | i = ffs(iso_event) - 1; | |
30200739 | 1474 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1475 | iso_event &= ~(1 << i); |
1476 | } | |
1477 | ||
c889475f | 1478 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1479 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1480 | ||
1481 | while (iso_event) { | |
1482 | i = ffs(iso_event) - 1; | |
30200739 | 1483 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1484 | iso_event &= ~(1 << i); |
1485 | } | |
1486 | ||
75f7832e JW |
1487 | if (unlikely(event & OHCI1394_regAccessFail)) |
1488 | fw_error("Register access failure - " | |
1489 | "please notify linux1394-devel@lists.sf.net\n"); | |
1490 | ||
e524f616 SR |
1491 | if (unlikely(event & OHCI1394_postedWriteErr)) |
1492 | fw_error("PCI posted write error\n"); | |
1493 | ||
bb9f2206 SR |
1494 | if (unlikely(event & OHCI1394_cycleTooLong)) { |
1495 | if (printk_ratelimit()) | |
1496 | fw_notify("isochronous cycle too long\n"); | |
1497 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1498 | OHCI1394_LinkControl_cycleMaster); | |
1499 | } | |
1500 | ||
5ed1f321 JF |
1501 | if (unlikely(event & OHCI1394_cycleInconsistent)) { |
1502 | /* | |
1503 | * We need to clear this event bit in order to make | |
1504 | * cycleMatch isochronous I/O work. In theory we should | |
1505 | * stop active cycleMatch iso contexts now and restart | |
1506 | * them at least two cycles later. (FIXME?) | |
1507 | */ | |
1508 | if (printk_ratelimit()) | |
1509 | fw_notify("isochronous cycle inconsistent\n"); | |
1510 | } | |
1511 | ||
ed568912 KH |
1512 | return IRQ_HANDLED; |
1513 | } | |
1514 | ||
2aef469a KH |
1515 | static int software_reset(struct fw_ohci *ohci) |
1516 | { | |
1517 | int i; | |
1518 | ||
1519 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1520 | ||
1521 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1522 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1523 | OHCI1394_HCControl_softReset) == 0) | |
1524 | return 0; | |
1525 | msleep(1); | |
1526 | } | |
1527 | ||
1528 | return -EBUSY; | |
1529 | } | |
1530 | ||
8e85973e SR |
1531 | static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) |
1532 | { | |
1533 | size_t size = length * 4; | |
1534 | ||
1535 | memcpy(dest, src, size); | |
1536 | if (size < CONFIG_ROM_SIZE) | |
1537 | memset(&dest[length], 0, CONFIG_ROM_SIZE - size); | |
1538 | } | |
1539 | ||
925e7a65 CL |
1540 | static int configure_1394a_enhancements(struct fw_ohci *ohci) |
1541 | { | |
1542 | bool enable_1394a; | |
35d999b1 | 1543 | int ret, clear, set, offset; |
925e7a65 CL |
1544 | |
1545 | /* Check if the driver should configure link and PHY. */ | |
1546 | if (!(reg_read(ohci, OHCI1394_HCControlSet) & | |
1547 | OHCI1394_HCControl_programPhyEnable)) | |
1548 | return 0; | |
1549 | ||
1550 | /* Paranoia: check whether the PHY supports 1394a, too. */ | |
1551 | enable_1394a = false; | |
35d999b1 SR |
1552 | ret = read_phy_reg(ohci, 2); |
1553 | if (ret < 0) | |
1554 | return ret; | |
1555 | if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { | |
1556 | ret = read_paged_phy_reg(ohci, 1, 8); | |
1557 | if (ret < 0) | |
1558 | return ret; | |
1559 | if (ret >= 1) | |
925e7a65 CL |
1560 | enable_1394a = true; |
1561 | } | |
1562 | ||
1563 | if (ohci->quirks & QUIRK_NO_1394A) | |
1564 | enable_1394a = false; | |
1565 | ||
1566 | /* Configure PHY and link consistently. */ | |
1567 | if (enable_1394a) { | |
1568 | clear = 0; | |
1569 | set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; | |
1570 | } else { | |
1571 | clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; | |
1572 | set = 0; | |
1573 | } | |
35d999b1 SR |
1574 | ret = ohci_update_phy_reg(&ohci->card, 5, clear, set); |
1575 | if (ret < 0) | |
1576 | return ret; | |
925e7a65 CL |
1577 | |
1578 | if (enable_1394a) | |
1579 | offset = OHCI1394_HCControlSet; | |
1580 | else | |
1581 | offset = OHCI1394_HCControlClear; | |
1582 | reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); | |
1583 | ||
1584 | /* Clean up: configuration has been taken care of. */ | |
1585 | reg_write(ohci, OHCI1394_HCControlClear, | |
1586 | OHCI1394_HCControl_programPhyEnable); | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
8e85973e SR |
1591 | static int ohci_enable(struct fw_card *card, |
1592 | const __be32 *config_rom, size_t length) | |
ed568912 KH |
1593 | { |
1594 | struct fw_ohci *ohci = fw_ohci(card); | |
1595 | struct pci_dev *dev = to_pci_dev(card->device); | |
02214724 | 1596 | u32 lps; |
35d999b1 | 1597 | int i, ret; |
ed568912 | 1598 | |
2aef469a KH |
1599 | if (software_reset(ohci)) { |
1600 | fw_error("Failed to reset ohci card.\n"); | |
1601 | return -EBUSY; | |
1602 | } | |
1603 | ||
1604 | /* | |
1605 | * Now enable LPS, which we need in order to start accessing | |
1606 | * most of the registers. In fact, on some cards (ALI M5251), | |
1607 | * accessing registers in the SClk domain without LPS enabled | |
1608 | * will lock up the machine. Wait 50msec to make sure we have | |
02214724 JW |
1609 | * full link enabled. However, with some cards (well, at least |
1610 | * a JMicron PCIe card), we have to try again sometimes. | |
2aef469a KH |
1611 | */ |
1612 | reg_write(ohci, OHCI1394_HCControlSet, | |
1613 | OHCI1394_HCControl_LPS | | |
1614 | OHCI1394_HCControl_postedWriteEnable); | |
1615 | flush_writes(ohci); | |
02214724 JW |
1616 | |
1617 | for (lps = 0, i = 0; !lps && i < 3; i++) { | |
1618 | msleep(50); | |
1619 | lps = reg_read(ohci, OHCI1394_HCControlSet) & | |
1620 | OHCI1394_HCControl_LPS; | |
1621 | } | |
1622 | ||
1623 | if (!lps) { | |
1624 | fw_error("Failed to set Link Power Status\n"); | |
1625 | return -EIO; | |
1626 | } | |
2aef469a KH |
1627 | |
1628 | reg_write(ohci, OHCI1394_HCControlClear, | |
1629 | OHCI1394_HCControl_noByteSwapData); | |
1630 | ||
affc9c24 | 1631 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); |
e896ec43 SR |
1632 | reg_write(ohci, OHCI1394_LinkControlClear, |
1633 | OHCI1394_LinkControl_rcvPhyPkt); | |
2aef469a KH |
1634 | reg_write(ohci, OHCI1394_LinkControlSet, |
1635 | OHCI1394_LinkControl_rcvSelfID | | |
1636 | OHCI1394_LinkControl_cycleTimerEnable | | |
1637 | OHCI1394_LinkControl_cycleMaster); | |
1638 | ||
1639 | reg_write(ohci, OHCI1394_ATRetries, | |
1640 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1641 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1642 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1643 | ||
1644 | ar_context_run(&ohci->ar_request_ctx); | |
1645 | ar_context_run(&ohci->ar_response_ctx); | |
1646 | ||
2aef469a KH |
1647 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); |
1648 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1649 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1650 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1651 | OHCI1394_selfIDComplete | | |
1652 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1653 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1654 | OHCI1394_isochRx | OHCI1394_isochTx | | |
bb9f2206 | 1655 | OHCI1394_postedWriteErr | OHCI1394_cycleTooLong | |
168cf9af | 1656 | OHCI1394_cycleInconsistent | OHCI1394_regAccessFail | |
75f7832e | 1657 | OHCI1394_masterIntEnable); |
a007bb85 SR |
1658 | if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) |
1659 | reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); | |
2aef469a | 1660 | |
35d999b1 SR |
1661 | ret = configure_1394a_enhancements(ohci); |
1662 | if (ret < 0) | |
1663 | return ret; | |
925e7a65 | 1664 | |
2aef469a | 1665 | /* Activate link_on bit and contender bit in our self ID packets.*/ |
35d999b1 SR |
1666 | ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); |
1667 | if (ret < 0) | |
1668 | return ret; | |
2aef469a | 1669 | |
c781c06d KH |
1670 | /* |
1671 | * When the link is not yet enabled, the atomic config rom | |
ed568912 KH |
1672 | * update mechanism described below in ohci_set_config_rom() |
1673 | * is not active. We have to update ConfigRomHeader and | |
1674 | * BusOptions manually, and the write to ConfigROMmap takes | |
1675 | * effect immediately. We tie this to the enabling of the | |
1676 | * link, so we have a valid config rom before enabling - the | |
1677 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1678 | * values before enabling. | |
1679 | * | |
1680 | * However, when the ConfigROMmap is written, some controllers | |
1681 | * always read back quadlets 0 and 2 from the config rom to | |
1682 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1683 | * They shouldn't do that in this initial case where the link | |
1684 | * isn't enabled. This means we have to use the same | |
1685 | * workaround here, setting the bus header to 0 and then write | |
1686 | * the right values in the bus reset tasklet. | |
1687 | */ | |
1688 | ||
0bd243c4 KH |
1689 | if (config_rom) { |
1690 | ohci->next_config_rom = | |
1691 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1692 | &ohci->next_config_rom_bus, | |
1693 | GFP_KERNEL); | |
1694 | if (ohci->next_config_rom == NULL) | |
1695 | return -ENOMEM; | |
ed568912 | 1696 | |
8e85973e | 1697 | copy_config_rom(ohci->next_config_rom, config_rom, length); |
0bd243c4 KH |
1698 | } else { |
1699 | /* | |
1700 | * In the suspend case, config_rom is NULL, which | |
1701 | * means that we just reuse the old config rom. | |
1702 | */ | |
1703 | ohci->next_config_rom = ohci->config_rom; | |
1704 | ohci->next_config_rom_bus = ohci->config_rom_bus; | |
1705 | } | |
ed568912 | 1706 | |
8e85973e | 1707 | ohci->next_header = ohci->next_config_rom[0]; |
ed568912 KH |
1708 | ohci->next_config_rom[0] = 0; |
1709 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
0bd243c4 KH |
1710 | reg_write(ohci, OHCI1394_BusOptions, |
1711 | be32_to_cpu(ohci->next_config_rom[2])); | |
ed568912 KH |
1712 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); |
1713 | ||
1714 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1715 | ||
1716 | if (request_irq(dev->irq, irq_handler, | |
65efffa8 | 1717 | IRQF_SHARED, ohci_driver_name, ohci)) { |
ed568912 KH |
1718 | fw_error("Failed to allocate shared interrupt %d.\n", |
1719 | dev->irq); | |
1720 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1721 | ohci->config_rom, ohci->config_rom_bus); | |
1722 | return -EIO; | |
1723 | } | |
1724 | ||
1725 | reg_write(ohci, OHCI1394_HCControlSet, | |
1726 | OHCI1394_HCControl_linkEnable | | |
1727 | OHCI1394_HCControl_BIBimageValid); | |
1728 | flush_writes(ohci); | |
1729 | ||
c781c06d KH |
1730 | /* |
1731 | * We are ready to go, initiate bus reset to finish the | |
1732 | * initialization. | |
1733 | */ | |
ed568912 KH |
1734 | |
1735 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1736 | ||
1737 | return 0; | |
1738 | } | |
1739 | ||
53dca511 | 1740 | static int ohci_set_config_rom(struct fw_card *card, |
8e85973e | 1741 | const __be32 *config_rom, size_t length) |
ed568912 KH |
1742 | { |
1743 | struct fw_ohci *ohci; | |
1744 | unsigned long flags; | |
2dbd7d7e | 1745 | int ret = -EBUSY; |
ed568912 | 1746 | __be32 *next_config_rom; |
f5101d58 | 1747 | dma_addr_t uninitialized_var(next_config_rom_bus); |
ed568912 KH |
1748 | |
1749 | ohci = fw_ohci(card); | |
1750 | ||
c781c06d KH |
1751 | /* |
1752 | * When the OHCI controller is enabled, the config rom update | |
ed568912 KH |
1753 | * mechanism is a bit tricky, but easy enough to use. See |
1754 | * section 5.5.6 in the OHCI specification. | |
1755 | * | |
1756 | * The OHCI controller caches the new config rom address in a | |
1757 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1758 | * for the changes to take place. When the bus reset is | |
1759 | * detected, the controller loads the new values for the | |
1760 | * ConfigRomHeader and BusOptions registers from the specified | |
1761 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1762 | * shadow register. All automatically and atomically. | |
1763 | * | |
1764 | * Now, there's a twist to this story. The automatic load of | |
1765 | * ConfigRomHeader and BusOptions doesn't honor the | |
1766 | * noByteSwapData bit, so with a be32 config rom, the | |
1767 | * controller will load be32 values in to these registers | |
1768 | * during the atomic update, even on litte endian | |
1769 | * architectures. The workaround we use is to put a 0 in the | |
1770 | * header quadlet; 0 is endian agnostic and means that the | |
1771 | * config rom isn't ready yet. In the bus reset tasklet we | |
1772 | * then set up the real values for the two registers. | |
1773 | * | |
1774 | * We use ohci->lock to avoid racing with the code that sets | |
1775 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1776 | */ | |
1777 | ||
1778 | next_config_rom = | |
1779 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1780 | &next_config_rom_bus, GFP_KERNEL); | |
1781 | if (next_config_rom == NULL) | |
1782 | return -ENOMEM; | |
1783 | ||
1784 | spin_lock_irqsave(&ohci->lock, flags); | |
1785 | ||
1786 | if (ohci->next_config_rom == NULL) { | |
1787 | ohci->next_config_rom = next_config_rom; | |
1788 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1789 | ||
8e85973e | 1790 | copy_config_rom(ohci->next_config_rom, config_rom, length); |
ed568912 KH |
1791 | |
1792 | ohci->next_header = config_rom[0]; | |
1793 | ohci->next_config_rom[0] = 0; | |
1794 | ||
1795 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1796 | ohci->next_config_rom_bus); | |
2dbd7d7e | 1797 | ret = 0; |
ed568912 KH |
1798 | } |
1799 | ||
1800 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1801 | ||
c781c06d KH |
1802 | /* |
1803 | * Now initiate a bus reset to have the changes take | |
ed568912 KH |
1804 | * effect. We clean up the old config rom memory and DMA |
1805 | * mappings in the bus reset tasklet, since the OHCI | |
1806 | * controller could need to access it before the bus reset | |
c781c06d KH |
1807 | * takes effect. |
1808 | */ | |
2dbd7d7e | 1809 | if (ret == 0) |
ed568912 | 1810 | fw_core_initiate_bus_reset(&ohci->card, 1); |
4eaff7d6 SR |
1811 | else |
1812 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1813 | next_config_rom, next_config_rom_bus); | |
ed568912 | 1814 | |
2dbd7d7e | 1815 | return ret; |
ed568912 KH |
1816 | } |
1817 | ||
1818 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1819 | { | |
1820 | struct fw_ohci *ohci = fw_ohci(card); | |
1821 | ||
1822 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1823 | } | |
1824 | ||
1825 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1826 | { | |
1827 | struct fw_ohci *ohci = fw_ohci(card); | |
1828 | ||
1829 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1830 | } | |
1831 | ||
730c32f5 KH |
1832 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1833 | { | |
1834 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
1835 | struct context *ctx = &ohci->at_request_ctx; |
1836 | struct driver_data *driver_data = packet->driver_data; | |
2dbd7d7e | 1837 | int ret = -ENOENT; |
730c32f5 | 1838 | |
f319b6a0 | 1839 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 1840 | |
f319b6a0 KH |
1841 | if (packet->ack != 0) |
1842 | goto out; | |
730c32f5 | 1843 | |
19593ffd | 1844 | if (packet->payload_mapped) |
1d1dc5e8 SR |
1845 | dma_unmap_single(ohci->card.device, packet->payload_bus, |
1846 | packet->payload_length, DMA_TO_DEVICE); | |
1847 | ||
ad3c0fe8 | 1848 | log_ar_at_event('T', packet->speed, packet->header, 0x20); |
f319b6a0 KH |
1849 | driver_data->packet = NULL; |
1850 | packet->ack = RCODE_CANCELLED; | |
1851 | packet->callback(packet, &ohci->card, packet->ack); | |
2dbd7d7e | 1852 | ret = 0; |
f319b6a0 KH |
1853 | out: |
1854 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 1855 | |
2dbd7d7e | 1856 | return ret; |
730c32f5 KH |
1857 | } |
1858 | ||
53dca511 SR |
1859 | static int ohci_enable_phys_dma(struct fw_card *card, |
1860 | int node_id, int generation) | |
ed568912 | 1861 | { |
080de8c2 SR |
1862 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1863 | return 0; | |
1864 | #else | |
ed568912 KH |
1865 | struct fw_ohci *ohci = fw_ohci(card); |
1866 | unsigned long flags; | |
2dbd7d7e | 1867 | int n, ret = 0; |
ed568912 | 1868 | |
c781c06d KH |
1869 | /* |
1870 | * FIXME: Make sure this bitmask is cleared when we clear the busReset | |
1871 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. | |
1872 | */ | |
ed568912 KH |
1873 | |
1874 | spin_lock_irqsave(&ohci->lock, flags); | |
1875 | ||
1876 | if (ohci->generation != generation) { | |
2dbd7d7e | 1877 | ret = -ESTALE; |
ed568912 KH |
1878 | goto out; |
1879 | } | |
1880 | ||
c781c06d KH |
1881 | /* |
1882 | * Note, if the node ID contains a non-local bus ID, physical DMA is | |
1883 | * enabled for _all_ nodes on remote buses. | |
1884 | */ | |
907293d7 SR |
1885 | |
1886 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1887 | if (n < 32) | |
1888 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1889 | else | |
1890 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1891 | ||
ed568912 | 1892 | flush_writes(ohci); |
ed568912 | 1893 | out: |
6cad95fe | 1894 | spin_unlock_irqrestore(&ohci->lock, flags); |
2dbd7d7e SR |
1895 | |
1896 | return ret; | |
080de8c2 | 1897 | #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ |
ed568912 | 1898 | } |
373b2edd | 1899 | |
4a9bde9b | 1900 | static u32 cycle_timer_ticks(u32 cycle_timer) |
b677532b CL |
1901 | { |
1902 | u32 ticks; | |
1903 | ||
1904 | ticks = cycle_timer & 0xfff; | |
1905 | ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); | |
1906 | ticks += (3072 * 8000) * (cycle_timer >> 25); | |
4a9bde9b | 1907 | |
b677532b CL |
1908 | return ticks; |
1909 | } | |
1910 | ||
4a9bde9b SR |
1911 | /* |
1912 | * Some controllers exhibit one or more of the following bugs when updating the | |
1913 | * iso cycle timer register: | |
1914 | * - When the lowest six bits are wrapping around to zero, a read that happens | |
1915 | * at the same time will return garbage in the lowest ten bits. | |
1916 | * - When the cycleOffset field wraps around to zero, the cycleCount field is | |
1917 | * not incremented for about 60 ns. | |
1918 | * - Occasionally, the entire register reads zero. | |
1919 | * | |
1920 | * To catch these, we read the register three times and ensure that the | |
1921 | * difference between each two consecutive reads is approximately the same, i.e. | |
1922 | * less than twice the other. Furthermore, any negative difference indicates an | |
1923 | * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to | |
1924 | * execute, so we have enough precision to compute the ratio of the differences.) | |
1925 | */ | |
168cf9af | 1926 | static u32 ohci_get_cycle_time(struct fw_card *card) |
d60d7f1d KH |
1927 | { |
1928 | struct fw_ohci *ohci = fw_ohci(card); | |
b677532b CL |
1929 | u32 c0, c1, c2; |
1930 | u32 t0, t1, t2; | |
1931 | s32 diff01, diff12; | |
4a9bde9b | 1932 | int i; |
d60d7f1d | 1933 | |
4a9bde9b SR |
1934 | c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); |
1935 | ||
4a635593 | 1936 | if (ohci->quirks & QUIRK_CYCLE_TIMER) { |
4a9bde9b SR |
1937 | i = 0; |
1938 | c1 = c2; | |
b677532b | 1939 | c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); |
b677532b | 1940 | do { |
4a9bde9b SR |
1941 | c0 = c1; |
1942 | c1 = c2; | |
b677532b CL |
1943 | c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); |
1944 | t0 = cycle_timer_ticks(c0); | |
1945 | t1 = cycle_timer_ticks(c1); | |
1946 | t2 = cycle_timer_ticks(c2); | |
1947 | diff01 = t1 - t0; | |
1948 | diff12 = t2 - t1; | |
4a9bde9b SR |
1949 | } while ((diff01 <= 0 || diff12 <= 0 || |
1950 | diff01 / diff12 >= 2 || diff12 / diff01 >= 2) | |
1951 | && i++ < 20); | |
b677532b | 1952 | } |
d60d7f1d | 1953 | |
168cf9af | 1954 | return c2; |
d60d7f1d KH |
1955 | } |
1956 | ||
1aa292bb DM |
1957 | static void copy_iso_headers(struct iso_context *ctx, void *p) |
1958 | { | |
1959 | int i = ctx->header_length; | |
1960 | ||
1961 | if (i + ctx->base.header_size > PAGE_SIZE) | |
1962 | return; | |
1963 | ||
1964 | /* | |
1965 | * The iso header is byteswapped to little endian by | |
1966 | * the controller, but the remaining header quadlets | |
1967 | * are big endian. We want to present all the headers | |
1968 | * as big endian, so we have to swap the first quadlet. | |
1969 | */ | |
1970 | if (ctx->base.header_size > 0) | |
1971 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); | |
1972 | if (ctx->base.header_size > 4) | |
1973 | *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); | |
1974 | if (ctx->base.header_size > 8) | |
1975 | memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); | |
1976 | ctx->header_length += ctx->base.header_size; | |
1977 | } | |
1978 | ||
a186b4a6 JW |
1979 | static int handle_ir_packet_per_buffer(struct context *context, |
1980 | struct descriptor *d, | |
1981 | struct descriptor *last) | |
1982 | { | |
1983 | struct iso_context *ctx = | |
1984 | container_of(context, struct iso_context, context); | |
bcee893c | 1985 | struct descriptor *pd; |
a186b4a6 | 1986 | __le32 *ir_header; |
bcee893c | 1987 | void *p; |
a186b4a6 | 1988 | |
bcee893c DM |
1989 | for (pd = d; pd <= last; pd++) { |
1990 | if (pd->transfer_status) | |
1991 | break; | |
1992 | } | |
1993 | if (pd > last) | |
a186b4a6 JW |
1994 | /* Descriptor(s) not done yet, stop iteration */ |
1995 | return 0; | |
1996 | ||
1aa292bb DM |
1997 | p = last + 1; |
1998 | copy_iso_headers(ctx, p); | |
a186b4a6 | 1999 | |
bcee893c DM |
2000 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { |
2001 | ir_header = (__le32 *) p; | |
a186b4a6 JW |
2002 | ctx->base.callback(&ctx->base, |
2003 | le32_to_cpu(ir_header[0]) & 0xffff, | |
2004 | ctx->header_length, ctx->header, | |
2005 | ctx->base.callback_data); | |
2006 | ctx->header_length = 0; | |
2007 | } | |
2008 | ||
a186b4a6 JW |
2009 | return 1; |
2010 | } | |
2011 | ||
30200739 KH |
2012 | static int handle_it_packet(struct context *context, |
2013 | struct descriptor *d, | |
2014 | struct descriptor *last) | |
ed568912 | 2015 | { |
30200739 KH |
2016 | struct iso_context *ctx = |
2017 | container_of(context, struct iso_context, context); | |
31769cef JF |
2018 | int i; |
2019 | struct descriptor *pd; | |
373b2edd | 2020 | |
31769cef JF |
2021 | for (pd = d; pd <= last; pd++) |
2022 | if (pd->transfer_status) | |
2023 | break; | |
2024 | if (pd > last) | |
2025 | /* Descriptor(s) not done yet, stop iteration */ | |
30200739 KH |
2026 | return 0; |
2027 | ||
31769cef JF |
2028 | i = ctx->header_length; |
2029 | if (i + 4 < PAGE_SIZE) { | |
2030 | /* Present this value as big-endian to match the receive code */ | |
2031 | *(__be32 *)(ctx->header + i) = cpu_to_be32( | |
2032 | ((u32)le16_to_cpu(pd->transfer_status) << 16) | | |
2033 | le16_to_cpu(pd->res_count)); | |
2034 | ctx->header_length += 4; | |
2035 | } | |
2036 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { | |
9b32d5f3 | 2037 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
31769cef JF |
2038 | ctx->header_length, ctx->header, |
2039 | ctx->base.callback_data); | |
2040 | ctx->header_length = 0; | |
2041 | } | |
30200739 | 2042 | return 1; |
ed568912 KH |
2043 | } |
2044 | ||
53dca511 | 2045 | static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, |
4817ed24 | 2046 | int type, int channel, size_t header_size) |
ed568912 KH |
2047 | { |
2048 | struct fw_ohci *ohci = fw_ohci(card); | |
2049 | struct iso_context *ctx, *list; | |
30200739 | 2050 | descriptor_callback_t callback; |
4817ed24 | 2051 | u64 *channels, dont_care = ~0ULL; |
295e3feb | 2052 | u32 *mask, regs; |
ed568912 | 2053 | unsigned long flags; |
2dbd7d7e | 2054 | int index, ret = -ENOMEM; |
ed568912 KH |
2055 | |
2056 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
4817ed24 | 2057 | channels = &dont_care; |
ed568912 KH |
2058 | mask = &ohci->it_context_mask; |
2059 | list = ohci->it_context_list; | |
30200739 | 2060 | callback = handle_it_packet; |
ed568912 | 2061 | } else { |
4817ed24 | 2062 | channels = &ohci->ir_context_channels; |
373b2edd SR |
2063 | mask = &ohci->ir_context_mask; |
2064 | list = ohci->ir_context_list; | |
6498ba04 | 2065 | callback = handle_ir_packet_per_buffer; |
ed568912 KH |
2066 | } |
2067 | ||
2068 | spin_lock_irqsave(&ohci->lock, flags); | |
4817ed24 SR |
2069 | index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; |
2070 | if (index >= 0) { | |
2071 | *channels &= ~(1ULL << channel); | |
ed568912 | 2072 | *mask &= ~(1 << index); |
4817ed24 | 2073 | } |
ed568912 KH |
2074 | spin_unlock_irqrestore(&ohci->lock, flags); |
2075 | ||
2076 | if (index < 0) | |
2077 | return ERR_PTR(-EBUSY); | |
2078 | ||
373b2edd SR |
2079 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
2080 | regs = OHCI1394_IsoXmitContextBase(index); | |
2081 | else | |
2082 | regs = OHCI1394_IsoRcvContextBase(index); | |
2083 | ||
ed568912 | 2084 | ctx = &list[index]; |
2d826cc5 | 2085 | memset(ctx, 0, sizeof(*ctx)); |
9b32d5f3 KH |
2086 | ctx->header_length = 0; |
2087 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
2088 | if (ctx->header == NULL) | |
2089 | goto out; | |
2090 | ||
2dbd7d7e SR |
2091 | ret = context_init(&ctx->context, ohci, regs, callback); |
2092 | if (ret < 0) | |
9b32d5f3 | 2093 | goto out_with_header; |
ed568912 KH |
2094 | |
2095 | return &ctx->base; | |
9b32d5f3 KH |
2096 | |
2097 | out_with_header: | |
2098 | free_page((unsigned long)ctx->header); | |
2099 | out: | |
2100 | spin_lock_irqsave(&ohci->lock, flags); | |
2101 | *mask |= 1 << index; | |
2102 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2103 | ||
2dbd7d7e | 2104 | return ERR_PTR(ret); |
ed568912 KH |
2105 | } |
2106 | ||
eb0306ea KH |
2107 | static int ohci_start_iso(struct fw_iso_context *base, |
2108 | s32 cycle, u32 sync, u32 tags) | |
ed568912 | 2109 | { |
373b2edd | 2110 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 2111 | struct fw_ohci *ohci = ctx->context.ohci; |
8a2f7d93 | 2112 | u32 control, match; |
ed568912 KH |
2113 | int index; |
2114 | ||
295e3feb KH |
2115 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
2116 | index = ctx - ohci->it_context_list; | |
8a2f7d93 KH |
2117 | match = 0; |
2118 | if (cycle >= 0) | |
2119 | match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
295e3feb | 2120 | (cycle & 0x7fff) << 16; |
21efb3cf | 2121 | |
295e3feb KH |
2122 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
2123 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
8a2f7d93 | 2124 | context_run(&ctx->context, match); |
295e3feb KH |
2125 | } else { |
2126 | index = ctx - ohci->ir_context_list; | |
a186b4a6 | 2127 | control = IR_CONTEXT_ISOCH_HEADER; |
8a2f7d93 KH |
2128 | match = (tags << 28) | (sync << 8) | ctx->base.channel; |
2129 | if (cycle >= 0) { | |
2130 | match |= (cycle & 0x07fff) << 12; | |
2131 | control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; | |
2132 | } | |
ed568912 | 2133 | |
295e3feb KH |
2134 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
2135 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
a77754a7 | 2136 | reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d93 | 2137 | context_run(&ctx->context, control); |
295e3feb | 2138 | } |
ed568912 KH |
2139 | |
2140 | return 0; | |
2141 | } | |
2142 | ||
b8295668 KH |
2143 | static int ohci_stop_iso(struct fw_iso_context *base) |
2144 | { | |
2145 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 2146 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
2147 | int index; |
2148 | ||
2149 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
2150 | index = ctx - ohci->it_context_list; | |
2151 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
2152 | } else { | |
2153 | index = ctx - ohci->ir_context_list; | |
2154 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
2155 | } | |
2156 | flush_writes(ohci); | |
2157 | context_stop(&ctx->context); | |
2158 | ||
2159 | return 0; | |
2160 | } | |
2161 | ||
ed568912 KH |
2162 | static void ohci_free_iso_context(struct fw_iso_context *base) |
2163 | { | |
2164 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 2165 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
2166 | unsigned long flags; |
2167 | int index; | |
2168 | ||
b8295668 KH |
2169 | ohci_stop_iso(base); |
2170 | context_release(&ctx->context); | |
9b32d5f3 | 2171 | free_page((unsigned long)ctx->header); |
b8295668 | 2172 | |
ed568912 KH |
2173 | spin_lock_irqsave(&ohci->lock, flags); |
2174 | ||
2175 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
2176 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
2177 | ohci->it_context_mask |= 1 << index; |
2178 | } else { | |
2179 | index = ctx - ohci->ir_context_list; | |
ed568912 | 2180 | ohci->ir_context_mask |= 1 << index; |
4817ed24 | 2181 | ohci->ir_context_channels |= 1ULL << base->channel; |
ed568912 | 2182 | } |
ed568912 KH |
2183 | |
2184 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2185 | } | |
2186 | ||
53dca511 SR |
2187 | static int ohci_queue_iso_transmit(struct fw_iso_context *base, |
2188 | struct fw_iso_packet *packet, | |
2189 | struct fw_iso_buffer *buffer, | |
2190 | unsigned long payload) | |
ed568912 | 2191 | { |
373b2edd | 2192 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 2193 | struct descriptor *d, *last, *pd; |
ed568912 KH |
2194 | struct fw_iso_packet *p; |
2195 | __le32 *header; | |
9aad8125 | 2196 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
2197 | u32 z, header_z, payload_z, irq; |
2198 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 2199 | int page, end_page, i, length, offset; |
ed568912 | 2200 | |
ed568912 | 2201 | p = packet; |
9aad8125 | 2202 | payload_index = payload; |
ed568912 KH |
2203 | |
2204 | if (p->skip) | |
2205 | z = 1; | |
2206 | else | |
2207 | z = 2; | |
2208 | if (p->header_length > 0) | |
2209 | z++; | |
2210 | ||
2211 | /* Determine the first page the payload isn't contained in. */ | |
2212 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
2213 | if (p->payload_length > 0) | |
2214 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
2215 | else | |
2216 | payload_z = 0; | |
2217 | ||
2218 | z += payload_z; | |
2219 | ||
2220 | /* Get header size in number of descriptors. */ | |
2d826cc5 | 2221 | header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed568912 | 2222 | |
30200739 KH |
2223 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
2224 | if (d == NULL) | |
2225 | return -ENOMEM; | |
ed568912 KH |
2226 | |
2227 | if (!p->skip) { | |
a77754a7 | 2228 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed568912 | 2229 | d[0].req_count = cpu_to_le16(8); |
7f51a100 CL |
2230 | /* |
2231 | * Link the skip address to this descriptor itself. This causes | |
2232 | * a context to skip a cycle whenever lost cycles or FIFO | |
2233 | * overruns occur, without dropping the data. The application | |
2234 | * should then decide whether this is an error condition or not. | |
2235 | * FIXME: Make the context's cycle-lost behaviour configurable? | |
2236 | */ | |
2237 | d[0].branch_address = cpu_to_le32(d_bus | z); | |
ed568912 KH |
2238 | |
2239 | header = (__le32 *) &d[1]; | |
a77754a7 KH |
2240 | header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | |
2241 | IT_HEADER_TAG(p->tag) | | |
2242 | IT_HEADER_TCODE(TCODE_STREAM_DATA) | | |
2243 | IT_HEADER_CHANNEL(ctx->base.channel) | | |
2244 | IT_HEADER_SPEED(ctx->base.speed)); | |
ed568912 | 2245 | header[1] = |
a77754a7 | 2246 | cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed568912 KH |
2247 | p->payload_length)); |
2248 | } | |
2249 | ||
2250 | if (p->header_length > 0) { | |
2251 | d[2].req_count = cpu_to_le16(p->header_length); | |
2d826cc5 | 2252 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed568912 KH |
2253 | memcpy(&d[z], p->header, p->header_length); |
2254 | } | |
2255 | ||
2256 | pd = d + z - payload_z; | |
2257 | payload_end_index = payload_index + p->payload_length; | |
2258 | for (i = 0; i < payload_z; i++) { | |
2259 | page = payload_index >> PAGE_SHIFT; | |
2260 | offset = payload_index & ~PAGE_MASK; | |
2261 | next_page_index = (page + 1) << PAGE_SHIFT; | |
2262 | length = | |
2263 | min(next_page_index, payload_end_index) - payload_index; | |
2264 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
2265 | |
2266 | page_bus = page_private(buffer->pages[page]); | |
2267 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
2268 | |
2269 | payload_index += length; | |
2270 | } | |
2271 | ||
ed568912 | 2272 | if (p->interrupt) |
a77754a7 | 2273 | irq = DESCRIPTOR_IRQ_ALWAYS; |
ed568912 | 2274 | else |
a77754a7 | 2275 | irq = DESCRIPTOR_NO_IRQ; |
ed568912 | 2276 | |
30200739 | 2277 | last = z == 2 ? d : d + z - 1; |
a77754a7 KH |
2278 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
2279 | DESCRIPTOR_STATUS | | |
2280 | DESCRIPTOR_BRANCH_ALWAYS | | |
cbb59da7 | 2281 | irq); |
ed568912 | 2282 | |
30200739 | 2283 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
2284 | |
2285 | return 0; | |
2286 | } | |
373b2edd | 2287 | |
53dca511 SR |
2288 | static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base, |
2289 | struct fw_iso_packet *packet, | |
2290 | struct fw_iso_buffer *buffer, | |
2291 | unsigned long payload) | |
a186b4a6 JW |
2292 | { |
2293 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
8c0c0cc2 | 2294 | struct descriptor *d, *pd; |
bcee893c | 2295 | struct fw_iso_packet *p = packet; |
a186b4a6 JW |
2296 | dma_addr_t d_bus, page_bus; |
2297 | u32 z, header_z, rest; | |
bcee893c DM |
2298 | int i, j, length; |
2299 | int page, offset, packet_count, header_size, payload_per_buffer; | |
a186b4a6 JW |
2300 | |
2301 | /* | |
1aa292bb DM |
2302 | * The OHCI controller puts the isochronous header and trailer in the |
2303 | * buffer, so we need at least 8 bytes. | |
a186b4a6 JW |
2304 | */ |
2305 | packet_count = p->header_length / ctx->base.header_size; | |
1aa292bb | 2306 | header_size = max(ctx->base.header_size, (size_t)8); |
a186b4a6 JW |
2307 | |
2308 | /* Get header size in number of descriptors. */ | |
2309 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); | |
2310 | page = payload >> PAGE_SHIFT; | |
2311 | offset = payload & ~PAGE_MASK; | |
bcee893c | 2312 | payload_per_buffer = p->payload_length / packet_count; |
a186b4a6 JW |
2313 | |
2314 | for (i = 0; i < packet_count; i++) { | |
2315 | /* d points to the header descriptor */ | |
bcee893c | 2316 | z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; |
a186b4a6 | 2317 | d = context_get_descriptors(&ctx->context, |
bcee893c | 2318 | z + header_z, &d_bus); |
a186b4a6 JW |
2319 | if (d == NULL) |
2320 | return -ENOMEM; | |
2321 | ||
bcee893c DM |
2322 | d->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2323 | DESCRIPTOR_INPUT_MORE); | |
2324 | if (p->skip && i == 0) | |
2325 | d->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
a186b4a6 JW |
2326 | d->req_count = cpu_to_le16(header_size); |
2327 | d->res_count = d->req_count; | |
bcee893c | 2328 | d->transfer_status = 0; |
a186b4a6 JW |
2329 | d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); |
2330 | ||
bcee893c | 2331 | rest = payload_per_buffer; |
8c0c0cc2 | 2332 | pd = d; |
bcee893c | 2333 | for (j = 1; j < z; j++) { |
8c0c0cc2 | 2334 | pd++; |
bcee893c DM |
2335 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2336 | DESCRIPTOR_INPUT_MORE); | |
2337 | ||
2338 | if (offset + rest < PAGE_SIZE) | |
2339 | length = rest; | |
2340 | else | |
2341 | length = PAGE_SIZE - offset; | |
2342 | pd->req_count = cpu_to_le16(length); | |
2343 | pd->res_count = pd->req_count; | |
2344 | pd->transfer_status = 0; | |
2345 | ||
2346 | page_bus = page_private(buffer->pages[page]); | |
2347 | pd->data_address = cpu_to_le32(page_bus + offset); | |
2348 | ||
2349 | offset = (offset + length) & ~PAGE_MASK; | |
2350 | rest -= length; | |
2351 | if (offset == 0) | |
2352 | page++; | |
2353 | } | |
a186b4a6 JW |
2354 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2355 | DESCRIPTOR_INPUT_LAST | | |
2356 | DESCRIPTOR_BRANCH_ALWAYS); | |
bcee893c | 2357 | if (p->interrupt && i == packet_count - 1) |
a186b4a6 JW |
2358 | pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
2359 | ||
a186b4a6 JW |
2360 | context_append(&ctx->context, d, z, header_z); |
2361 | } | |
2362 | ||
2363 | return 0; | |
2364 | } | |
2365 | ||
53dca511 SR |
2366 | static int ohci_queue_iso(struct fw_iso_context *base, |
2367 | struct fw_iso_packet *packet, | |
2368 | struct fw_iso_buffer *buffer, | |
2369 | unsigned long payload) | |
295e3feb | 2370 | { |
e364cf4e | 2371 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
fe5ca634 | 2372 | unsigned long flags; |
2dbd7d7e | 2373 | int ret; |
e364cf4e | 2374 | |
fe5ca634 | 2375 | spin_lock_irqsave(&ctx->context.ohci->lock, flags); |
295e3feb | 2376 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
2dbd7d7e | 2377 | ret = ohci_queue_iso_transmit(base, packet, buffer, payload); |
e364cf4e | 2378 | else |
2dbd7d7e SR |
2379 | ret = ohci_queue_iso_receive_packet_per_buffer(base, packet, |
2380 | buffer, payload); | |
fe5ca634 DM |
2381 | spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); |
2382 | ||
2dbd7d7e | 2383 | return ret; |
295e3feb KH |
2384 | } |
2385 | ||
21ebcd12 | 2386 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
2387 | .enable = ohci_enable, |
2388 | .update_phy_reg = ohci_update_phy_reg, | |
2389 | .set_config_rom = ohci_set_config_rom, | |
2390 | .send_request = ohci_send_request, | |
2391 | .send_response = ohci_send_response, | |
730c32f5 | 2392 | .cancel_packet = ohci_cancel_packet, |
ed568912 | 2393 | .enable_phys_dma = ohci_enable_phys_dma, |
168cf9af | 2394 | .get_cycle_time = ohci_get_cycle_time, |
ed568912 KH |
2395 | |
2396 | .allocate_iso_context = ohci_allocate_iso_context, | |
2397 | .free_iso_context = ohci_free_iso_context, | |
2398 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 2399 | .start_iso = ohci_start_iso, |
b8295668 | 2400 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
2401 | }; |
2402 | ||
ea8d006b | 2403 | #ifdef CONFIG_PPC_PMAC |
2ed0f181 SR |
2404 | static void ohci_pmac_on(struct pci_dev *dev) |
2405 | { | |
ea8d006b SR |
2406 | if (machine_is(powermac)) { |
2407 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2408 | ||
2409 | if (ofn) { | |
2410 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); | |
2411 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); | |
2412 | } | |
2413 | } | |
2ed0f181 SR |
2414 | } |
2415 | ||
2416 | static void ohci_pmac_off(struct pci_dev *dev) | |
2417 | { | |
2418 | if (machine_is(powermac)) { | |
2419 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2420 | ||
2421 | if (ofn) { | |
2422 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); | |
2423 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); | |
2424 | } | |
2425 | } | |
2426 | } | |
2427 | #else | |
2428 | #define ohci_pmac_on(dev) | |
2429 | #define ohci_pmac_off(dev) | |
ea8d006b SR |
2430 | #endif /* CONFIG_PPC_PMAC */ |
2431 | ||
53dca511 SR |
2432 | static int __devinit pci_probe(struct pci_dev *dev, |
2433 | const struct pci_device_id *ent) | |
2ed0f181 SR |
2434 | { |
2435 | struct fw_ohci *ohci; | |
54672386 | 2436 | u32 bus_options, max_receive, link_speed, version, link_enh; |
2ed0f181 | 2437 | u64 guid; |
6fdb2ee2 | 2438 | int i, err, n_ir, n_it; |
2ed0f181 SR |
2439 | size_t size; |
2440 | ||
2d826cc5 | 2441 | ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed568912 | 2442 | if (ohci == NULL) { |
7007a076 SR |
2443 | err = -ENOMEM; |
2444 | goto fail; | |
ed568912 KH |
2445 | } |
2446 | ||
2447 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
2448 | ||
130d5496 SR |
2449 | ohci_pmac_on(dev); |
2450 | ||
d79406dd KH |
2451 | err = pci_enable_device(dev); |
2452 | if (err) { | |
7007a076 | 2453 | fw_error("Failed to enable OHCI hardware\n"); |
bd7dee63 | 2454 | goto fail_free; |
ed568912 KH |
2455 | } |
2456 | ||
2457 | pci_set_master(dev); | |
2458 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
2459 | pci_set_drvdata(dev, ohci); | |
2460 | ||
2461 | spin_lock_init(&ohci->lock); | |
2462 | ||
2463 | tasklet_init(&ohci->bus_reset_tasklet, | |
2464 | bus_reset_tasklet, (unsigned long)ohci); | |
2465 | ||
d79406dd KH |
2466 | err = pci_request_region(dev, 0, ohci_driver_name); |
2467 | if (err) { | |
ed568912 | 2468 | fw_error("MMIO resource unavailable\n"); |
d79406dd | 2469 | goto fail_disable; |
ed568912 KH |
2470 | } |
2471 | ||
2472 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
2473 | if (ohci->registers == NULL) { | |
2474 | fw_error("Failed to remap registers\n"); | |
d79406dd KH |
2475 | err = -ENXIO; |
2476 | goto fail_iomem; | |
ed568912 KH |
2477 | } |
2478 | ||
4a635593 SR |
2479 | for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) |
2480 | if (ohci_quirks[i].vendor == dev->vendor && | |
2481 | (ohci_quirks[i].device == dev->device || | |
2482 | ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) { | |
2483 | ohci->quirks = ohci_quirks[i].flags; | |
2484 | break; | |
2485 | } | |
3e9cc2f3 SR |
2486 | if (param_quirks) |
2487 | ohci->quirks = param_quirks; | |
b677532b | 2488 | |
54672386 CL |
2489 | /* TI OHCI-Lynx and compatible: set recommended configuration bits. */ |
2490 | if (dev->vendor == PCI_VENDOR_ID_TI) { | |
2491 | pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh); | |
2492 | ||
2493 | /* adjust latency of ATx FIFO: use 1.7 KB threshold */ | |
2494 | link_enh &= ~TI_LinkEnh_atx_thresh_mask; | |
2495 | link_enh |= TI_LinkEnh_atx_thresh_1_7K; | |
2496 | ||
2497 | /* use priority arbitration for asynchronous responses */ | |
2498 | link_enh |= TI_LinkEnh_enab_unfair; | |
2499 | ||
2500 | /* required for aPhyEnhanceEnable to work */ | |
2501 | link_enh |= TI_LinkEnh_enab_accel; | |
2502 | ||
2503 | pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh); | |
2504 | } | |
2505 | ||
ed568912 KH |
2506 | ar_context_init(&ohci->ar_request_ctx, ohci, |
2507 | OHCI1394_AsReqRcvContextControlSet); | |
2508 | ||
2509 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
2510 | OHCI1394_AsRspRcvContextControlSet); | |
2511 | ||
fe5ca634 | 2512 | context_init(&ohci->at_request_ctx, ohci, |
f319b6a0 | 2513 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); |
ed568912 | 2514 | |
fe5ca634 | 2515 | context_init(&ohci->at_response_ctx, ohci, |
f319b6a0 | 2516 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); |
ed568912 | 2517 | |
ed568912 | 2518 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); |
4802f16d SR |
2519 | ohci->ir_context_channels = ~0ULL; |
2520 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
ed568912 | 2521 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); |
6fdb2ee2 SR |
2522 | n_ir = hweight32(ohci->ir_context_mask); |
2523 | size = sizeof(struct iso_context) * n_ir; | |
4802f16d | 2524 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); |
ed568912 KH |
2525 | |
2526 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
4802f16d | 2527 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); |
ed568912 | 2528 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); |
6fdb2ee2 SR |
2529 | n_it = hweight32(ohci->it_context_mask); |
2530 | size = sizeof(struct iso_context) * n_it; | |
4802f16d | 2531 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); |
ed568912 KH |
2532 | |
2533 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
d79406dd | 2534 | err = -ENOMEM; |
7007a076 | 2535 | goto fail_contexts; |
ed568912 KH |
2536 | } |
2537 | ||
2538 | /* self-id dma buffer allocation */ | |
2539 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
2540 | SELF_ID_BUF_SIZE, | |
2541 | &ohci->self_id_bus, | |
2542 | GFP_KERNEL); | |
2543 | if (ohci->self_id_cpu == NULL) { | |
d79406dd | 2544 | err = -ENOMEM; |
7007a076 | 2545 | goto fail_contexts; |
ed568912 KH |
2546 | } |
2547 | ||
ed568912 KH |
2548 | bus_options = reg_read(ohci, OHCI1394_BusOptions); |
2549 | max_receive = (bus_options >> 12) & 0xf; | |
2550 | link_speed = bus_options & 0x7; | |
2551 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
2552 | reg_read(ohci, OHCI1394_GUIDLo); | |
2553 | ||
d79406dd | 2554 | err = fw_card_add(&ohci->card, max_receive, link_speed, guid); |
e1eff7a3 | 2555 | if (err) |
d79406dd | 2556 | goto fail_self_id; |
ed568912 | 2557 | |
6fdb2ee2 SR |
2558 | version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
2559 | fw_notify("Added fw-ohci device %s, OHCI v%x.%x, " | |
2560 | "%d IR + %d IT contexts, quirks 0x%x\n", | |
2561 | dev_name(&dev->dev), version >> 16, version & 0xff, | |
2562 | n_ir, n_it, ohci->quirks); | |
e1eff7a3 | 2563 | |
ed568912 | 2564 | return 0; |
d79406dd KH |
2565 | |
2566 | fail_self_id: | |
2567 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
2568 | ohci->self_id_cpu, ohci->self_id_bus); | |
7007a076 | 2569 | fail_contexts: |
d79406dd | 2570 | kfree(ohci->ir_context_list); |
7007a076 SR |
2571 | kfree(ohci->it_context_list); |
2572 | context_release(&ohci->at_response_ctx); | |
2573 | context_release(&ohci->at_request_ctx); | |
2574 | ar_context_release(&ohci->ar_response_ctx); | |
2575 | ar_context_release(&ohci->ar_request_ctx); | |
d79406dd KH |
2576 | pci_iounmap(dev, ohci->registers); |
2577 | fail_iomem: | |
2578 | pci_release_region(dev, 0); | |
2579 | fail_disable: | |
2580 | pci_disable_device(dev); | |
bd7dee63 SR |
2581 | fail_free: |
2582 | kfree(&ohci->card); | |
130d5496 | 2583 | ohci_pmac_off(dev); |
7007a076 SR |
2584 | fail: |
2585 | if (err == -ENOMEM) | |
2586 | fw_error("Out of memory\n"); | |
d79406dd KH |
2587 | |
2588 | return err; | |
ed568912 KH |
2589 | } |
2590 | ||
2591 | static void pci_remove(struct pci_dev *dev) | |
2592 | { | |
2593 | struct fw_ohci *ohci; | |
2594 | ||
2595 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
2596 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
2597 | flush_writes(ohci); | |
ed568912 KH |
2598 | fw_core_remove_card(&ohci->card); |
2599 | ||
c781c06d KH |
2600 | /* |
2601 | * FIXME: Fail all pending packets here, now that the upper | |
2602 | * layers can't queue any more. | |
2603 | */ | |
ed568912 KH |
2604 | |
2605 | software_reset(ohci); | |
2606 | free_irq(dev->irq, ohci); | |
a55709ba JF |
2607 | |
2608 | if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) | |
2609 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
2610 | ohci->next_config_rom, ohci->next_config_rom_bus); | |
2611 | if (ohci->config_rom) | |
2612 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
2613 | ohci->config_rom, ohci->config_rom_bus); | |
d79406dd KH |
2614 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, |
2615 | ohci->self_id_cpu, ohci->self_id_bus); | |
a55709ba JF |
2616 | ar_context_release(&ohci->ar_request_ctx); |
2617 | ar_context_release(&ohci->ar_response_ctx); | |
2618 | context_release(&ohci->at_request_ctx); | |
2619 | context_release(&ohci->at_response_ctx); | |
d79406dd KH |
2620 | kfree(ohci->it_context_list); |
2621 | kfree(ohci->ir_context_list); | |
2622 | pci_iounmap(dev, ohci->registers); | |
2623 | pci_release_region(dev, 0); | |
2624 | pci_disable_device(dev); | |
bd7dee63 | 2625 | kfree(&ohci->card); |
2ed0f181 | 2626 | ohci_pmac_off(dev); |
ea8d006b | 2627 | |
ed568912 KH |
2628 | fw_notify("Removed fw-ohci device.\n"); |
2629 | } | |
2630 | ||
2aef469a | 2631 | #ifdef CONFIG_PM |
2ed0f181 | 2632 | static int pci_suspend(struct pci_dev *dev, pm_message_t state) |
2aef469a | 2633 | { |
2ed0f181 | 2634 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2635 | int err; |
2636 | ||
2637 | software_reset(ohci); | |
2ed0f181 SR |
2638 | free_irq(dev->irq, ohci); |
2639 | err = pci_save_state(dev); | |
2aef469a | 2640 | if (err) { |
8a8cea27 | 2641 | fw_error("pci_save_state failed\n"); |
2aef469a KH |
2642 | return err; |
2643 | } | |
2ed0f181 | 2644 | err = pci_set_power_state(dev, pci_choose_state(dev, state)); |
55111428 SR |
2645 | if (err) |
2646 | fw_error("pci_set_power_state failed with %d\n", err); | |
2ed0f181 | 2647 | ohci_pmac_off(dev); |
ea8d006b | 2648 | |
2aef469a KH |
2649 | return 0; |
2650 | } | |
2651 | ||
2ed0f181 | 2652 | static int pci_resume(struct pci_dev *dev) |
2aef469a | 2653 | { |
2ed0f181 | 2654 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2655 | int err; |
2656 | ||
2ed0f181 SR |
2657 | ohci_pmac_on(dev); |
2658 | pci_set_power_state(dev, PCI_D0); | |
2659 | pci_restore_state(dev); | |
2660 | err = pci_enable_device(dev); | |
2aef469a | 2661 | if (err) { |
8a8cea27 | 2662 | fw_error("pci_enable_device failed\n"); |
2aef469a KH |
2663 | return err; |
2664 | } | |
2665 | ||
0bd243c4 | 2666 | return ohci_enable(&ohci->card, NULL, 0); |
2aef469a KH |
2667 | } |
2668 | #endif | |
2669 | ||
a67483d2 | 2670 | static const struct pci_device_id pci_table[] = { |
ed568912 KH |
2671 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, |
2672 | { } | |
2673 | }; | |
2674 | ||
2675 | MODULE_DEVICE_TABLE(pci, pci_table); | |
2676 | ||
2677 | static struct pci_driver fw_ohci_pci_driver = { | |
2678 | .name = ohci_driver_name, | |
2679 | .id_table = pci_table, | |
2680 | .probe = pci_probe, | |
2681 | .remove = pci_remove, | |
2aef469a KH |
2682 | #ifdef CONFIG_PM |
2683 | .resume = pci_resume, | |
2684 | .suspend = pci_suspend, | |
2685 | #endif | |
ed568912 KH |
2686 | }; |
2687 | ||
2688 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
2689 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
2690 | MODULE_LICENSE("GPL"); | |
2691 | ||
1e4c7b0d OH |
2692 | /* Provide a module alias so root-on-sbp2 initrds don't break. */ |
2693 | #ifndef CONFIG_IEEE1394_OHCI1394_MODULE | |
2694 | MODULE_ALIAS("ohci1394"); | |
2695 | #endif | |
2696 | ||
ed568912 KH |
2697 | static int __init fw_ohci_init(void) |
2698 | { | |
2699 | return pci_register_driver(&fw_ohci_pci_driver); | |
2700 | } | |
2701 | ||
2702 | static void __exit fw_ohci_cleanup(void) | |
2703 | { | |
2704 | pci_unregister_driver(&fw_ohci_pci_driver); | |
2705 | } | |
2706 | ||
2707 | module_init(fw_ohci_init); | |
2708 | module_exit(fw_ohci_cleanup); |