[net-next-2.6.git] / drivers / edac / e7xxx_edac.c

/*
 * Intel e7xxx Memory Controller kernel module
 * (C) 2003 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * See "enum e7xxx_chips" below for supported chipsets
 *
 * Written by Thayne Harbaugh
 * Based on work by Dan Hollis <goemon at anime dot net> and others.
 *	http://www.anime.net/~goemon/linux-ecc/
 *
 * Contributors:
 * 	Eric Biederman (Linux Networx)
 * 	Tom Zimmerman (Linux Networx)
 * 	Jim Garlick (Lawrence Livermore National Labs)
 *	Dave Peterson (Lawrence Livermore National Labs)
 *	That One Guy (Some other place)
 *	Wang Zhenyu (intel.com)
 *
 * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 */


#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include "edac_mc.h"


#ifndef PCI_DEVICE_ID_INTEL_7205_0
#define PCI_DEVICE_ID_INTEL_7205_0	0x255d
#endif				/* PCI_DEVICE_ID_INTEL_7205_0 */

#ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
#define PCI_DEVICE_ID_INTEL_7205_1_ERR	0x2551
#endif				/* PCI_DEVICE_ID_INTEL_7205_1_ERR */

#ifndef PCI_DEVICE_ID_INTEL_7500_0
#define PCI_DEVICE_ID_INTEL_7500_0	0x2540
#endif				/* PCI_DEVICE_ID_INTEL_7500_0 */

#ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
#define PCI_DEVICE_ID_INTEL_7500_1_ERR	0x2541
#endif				/* PCI_DEVICE_ID_INTEL_7500_1_ERR */

#ifndef PCI_DEVICE_ID_INTEL_7501_0
#define PCI_DEVICE_ID_INTEL_7501_0	0x254c
#endif				/* PCI_DEVICE_ID_INTEL_7501_0 */

#ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
#define PCI_DEVICE_ID_INTEL_7501_1_ERR	0x2541
#endif				/* PCI_DEVICE_ID_INTEL_7501_1_ERR */

#ifndef PCI_DEVICE_ID_INTEL_7505_0
#define PCI_DEVICE_ID_INTEL_7505_0	0x2550
#endif				/* PCI_DEVICE_ID_INTEL_7505_0 */

#ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
#define PCI_DEVICE_ID_INTEL_7505_1_ERR	0x2551
#endif				/* PCI_DEVICE_ID_INTEL_7505_1_ERR */


#define E7XXX_NR_CSROWS		8	/* number of csrows */
#define E7XXX_NR_DIMMS		8	/* FIXME - is this correct? */


/* E7XXX register addresses - device 0 function 0 */
#define E7XXX_DRB		0x60	/* DRAM row boundary register (8b) */
#define E7XXX_DRA		0x70	/* DRAM row attribute register (8b) */
					/*
					 * 31   Device width row 7 0=x8 1=x4
					 * 27   Device width row 6
					 * 23   Device width row 5
					 * 19   Device width row 4
					 * 15   Device width row 3
					 * 11   Device width row 2
					 *  7   Device width row 1
					 *  3   Device width row 0
					 */
#define E7XXX_DRC		0x7C	/* DRAM controller mode reg (32b) */
					/*
					 * 22    Number channels 0=1,1=2
					 * 19:18 DRB Granularity 32/64MB
					 */
#define E7XXX_TOLM		0xC4	/* DRAM top of low memory reg (16b) */
#define E7XXX_REMAPBASE		0xC6	/* DRAM remap base address reg (16b) */
#define E7XXX_REMAPLIMIT	0xC8	/* DRAM remap limit address reg (16b) */

/* E7XXX register addresses - device 0 function 1 */
#define E7XXX_DRAM_FERR		0x80	/* DRAM first error register (8b) */
#define E7XXX_DRAM_NERR		0x82	/* DRAM next error register (8b) */
#define E7XXX_DRAM_CELOG_ADD	0xA0	/* DRAM first correctable memory */
					/*     error address register (32b) */
					/*
					 * 31:28 Reserved
					 * 27:6  CE address (4k block 33:12)
					 *  5:0  Reserved
					 */
#define E7XXX_DRAM_UELOG_ADD	0xB0	/* DRAM first uncorrectable memory */
					/*     error address register (32b) */
					/*
					 * 31:28 Reserved
					 * 27:6  CE address (4k block 33:12)
					 *  5:0  Reserved
					 */
#define E7XXX_DRAM_CELOG_SYNDROME 0xD0	/* DRAM first correctable memory */
					/*     error syndrome register (16b) */

enum e7xxx_chips {
	E7500 = 0,
	E7501,
	E7505,
	E7205,
};


struct e7xxx_pvt {
	struct pci_dev *bridge_ck;
	u32 tolm;
	u32 remapbase;
	u32 remaplimit;
	const struct e7xxx_dev_info *dev_info;
};


struct e7xxx_dev_info {
	u16 err_dev;
	const char *ctl_name;
};


struct e7xxx_error_info {
	u8 dram_ferr;
	u8 dram_nerr;
	u32 dram_celog_add;
	u16 dram_celog_syndrome;
	u32 dram_uelog_add;
};

static const struct e7xxx_dev_info e7xxx_devs[] = {
	[E7500] = {
		   .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
		   .ctl_name = "E7500"},
	[E7501] = {
		   .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
		   .ctl_name = "E7501"},
	[E7505] = {
		   .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
		   .ctl_name = "E7505"},
	[E7205] = {
		   .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
		   .ctl_name = "E7205"},
};


/* FIXME - is this valid for both SECDED and S4ECD4ED? */
static inline int e7xxx_find_channel(u16 syndrome)
{
	debugf3("MC: " __FILE__ ": %s()\n", __func__);

	if ((syndrome & 0xff00) == 0)
		return 0;
	if ((syndrome & 0x00ff) == 0)
		return 1;
	if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
		return 0;
	return 1;
}


static unsigned long
ctl_page_to_phys(struct mem_ctl_info *mci, unsigned long page)
{
	u32 remap;
	struct e7xxx_pvt *pvt = (struct e7xxx_pvt *) mci->pvt_info;

	debugf3("MC: " __FILE__ ": %s()\n", __func__);

	if ((page < pvt->tolm) ||
	    ((page >= 0x100000) && (page < pvt->remapbase)))
		return page;
	remap = (page - pvt->tolm) + pvt->remapbase;
	if (remap < pvt->remaplimit)
		return remap;
	printk(KERN_ERR "Invalid page %lx - out of range\n", page);
	return pvt->tolm - 1;
}


static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
{
	u32 error_1b, page;
	u16 syndrome;
	int row;
	int channel;

	debugf3("MC: " __FILE__ ": %s()\n", __func__);

	/* read the error address */
	error_1b = info->dram_celog_add;
	/* FIXME - should use PAGE_SHIFT */
	page = error_1b >> 6;	/* convert the address to 4k page */
	/* read the syndrome */
	syndrome = info->dram_celog_syndrome;
	/* FIXME - check for -1 */
	row = edac_mc_find_csrow_by_page(mci, page);
	/* convert syndrome to channel */
	channel = e7xxx_find_channel(syndrome);
	edac_mc_handle_ce(mci, page, 0, syndrome, row, channel,
			       "e7xxx CE");
}


static void process_ce_no_info(struct mem_ctl_info *mci)
{
	debugf3("MC: " __FILE__ ": %s()\n", __func__);
	edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
}


static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
{
	u32 error_2b, block_page;
	int row;

	debugf3("MC: " __FILE__ ": %s()\n", __func__);

	/* read the error address */
	error_2b = info->dram_uelog_add;
	/* FIXME - should use PAGE_SHIFT */
	block_page = error_2b >> 6;	/* convert to 4k address */
	row = edac_mc_find_csrow_by_page(mci, block_page);
	edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
}


static void process_ue_no_info(struct mem_ctl_info *mci)
{
	debugf3("MC: " __FILE__ ": %s()\n", __func__);
	edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
}


static void e7xxx_get_error_info (struct mem_ctl_info *mci,
		struct e7xxx_error_info *info)
{
	struct e7xxx_pvt *pvt;

	pvt = (struct e7xxx_pvt *) mci->pvt_info;
	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR,
	    &info->dram_ferr);
	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR,
	    &info->dram_nerr);

	if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
		pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
		    &info->dram_celog_add);
		pci_read_config_word(pvt->bridge_ck,
		    E7XXX_DRAM_CELOG_SYNDROME, &info->dram_celog_syndrome);
	}

	if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
		pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
		    &info->dram_uelog_add);

	if (info->dram_ferr & 3)
		pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03,
		    0x03);

	if (info->dram_nerr & 3)
		pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03,
		    0x03);
}


static int e7xxx_process_error_info (struct mem_ctl_info *mci,
		struct e7xxx_error_info *info, int handle_errors)
{
	int error_found;

	error_found = 0;

	/* decode and report errors */
	if (info->dram_ferr & 1) {	/* check first error correctable */
		error_found = 1;

		if (handle_errors)
			process_ce(mci, info);
	}

	if (info->dram_ferr & 2) {	/* check first error uncorrectable */
		error_found = 1;

		if (handle_errors)
			process_ue(mci, info);
	}

	if (info->dram_nerr & 1) {	/* check next error correctable */
		error_found = 1;

		if (handle_errors) {
			if (info->dram_ferr & 1)
				process_ce_no_info(mci);
			else
				process_ce(mci, info);
		}
	}

	if (info->dram_nerr & 2) {	/* check next error uncorrectable */
		error_found = 1;

		if (handle_errors) {
			if (info->dram_ferr & 2)
				process_ue_no_info(mci);
			else
				process_ue(mci, info);
		}
	}

	return error_found;
}


static void e7xxx_check(struct mem_ctl_info *mci)
{
	struct e7xxx_error_info info;

	debugf3("MC: " __FILE__ ": %s()\n", __func__);
	e7xxx_get_error_info(mci, &info);
	e7xxx_process_error_info(mci, &info, 1);
}


static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc = -ENODEV;
	int index;
	u16 pci_data;
	struct mem_ctl_info *mci = NULL;
	struct e7xxx_pvt *pvt = NULL;
	u32 drc;
	int drc_chan = 1;	/* Number of channels 0=1chan,1=2chan */
	int drc_drbg = 1;	/* DRB granularity 0=32mb,1=64mb */
	int drc_ddim;		/* DRAM Data Integrity Mode 0=none,2=edac */
	u32 dra;
	unsigned long last_cumul_size;


	debugf0("MC: " __FILE__ ": %s(): mci\n", __func__);

	/* need to find out the number of channels */
	pci_read_config_dword(pdev, E7XXX_DRC, &drc);
	/* only e7501 can be single channel */
	if (dev_idx == E7501) {
		drc_chan = ((drc >> 22) & 0x1);
		drc_drbg = (drc >> 18) & 0x3;
	}
	drc_ddim = (drc >> 20) & 0x3;

	mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1);

	if (mci == NULL) {
		rc = -ENOMEM;
		goto fail;
	}

	debugf3("MC: " __FILE__ ": %s(): init mci\n", __func__);

	mci->mtype_cap = MEM_FLAG_RDDR;
	mci->edac_ctl_cap =
	    EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED;
	/* FIXME - what if different memory types are in different csrows? */
	mci->mod_name = BS_MOD_STR;
	mci->mod_ver = "$Revision: 1.5.2.9 $";
	mci->pdev = pdev;

	debugf3("MC: " __FILE__ ": %s(): init pvt\n", __func__);
	pvt = (struct e7xxx_pvt *) mci->pvt_info;
	pvt->dev_info = &e7xxx_devs[dev_idx];
	pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
					 pvt->dev_info->err_dev,
					 pvt->bridge_ck);
	if (!pvt->bridge_ck) {
		printk(KERN_ERR
		       "MC: error reporting device not found:"
		       "vendor %x device 0x%x (broken BIOS?)\n",
		       PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
		goto fail;
	}

	debugf3("MC: " __FILE__ ": %s(): more mci init\n", __func__);
	mci->ctl_name = pvt->dev_info->ctl_name;

	mci->edac_check = e7xxx_check;
	mci->ctl_page_to_phys = ctl_page_to_phys;

	/* find out the device types */
	pci_read_config_dword(pdev, E7XXX_DRA, &dra);

	/*
	 * The dram row boundary (DRB) reg values are boundary address
	 * for each DRAM row with a granularity of 32 or 64MB (single/dual
	 * channel operation).  DRB regs are cumulative; therefore DRB7 will
	 * contain the total memory contained in all eight rows.
	 */
	for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
		u8 value;
		u32 cumul_size;
		/* mem_dev 0=x8, 1=x4 */
		int mem_dev = (dra >> (index * 4 + 3)) & 0x1;
		struct csrow_info *csrow = &mci->csrows[index];

		pci_read_config_byte(mci->pdev, E7XXX_DRB + index, &value);
		/* convert a 64 or 32 MiB DRB to a page size. */
		cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
		debugf3("MC: " __FILE__ ": %s(): (%d) cumul_size 0x%x\n",
			__func__, index, cumul_size);
		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		csrow->nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;
		csrow->grain = 1 << 12;	/* 4KiB - resolution of CELOG */
		csrow->mtype = MEM_RDDR;	/* only one type supported */
		csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;

		/*
		 * if single channel or x8 devices then SECDED
		 * if dual channel and x4 then S4ECD4ED
		 */
		if (drc_ddim) {
			if (drc_chan && mem_dev) {
				csrow->edac_mode = EDAC_S4ECD4ED;
				mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
			} else {
				csrow->edac_mode = EDAC_SECDED;
				mci->edac_cap |= EDAC_FLAG_SECDED;
			}
		} else
			csrow->edac_mode = EDAC_NONE;
	}

	mci->edac_cap |= EDAC_FLAG_NONE;

	debugf3("MC: " __FILE__ ": %s(): tolm, remapbase, remaplimit\n",
		__func__);
	/* load the top of low memory, remap base, and remap limit vars */
	pci_read_config_word(mci->pdev, E7XXX_TOLM, &pci_data);
	pvt->tolm = ((u32) pci_data) << 4;
	pci_read_config_word(mci->pdev, E7XXX_REMAPBASE, &pci_data);
	pvt->remapbase = ((u32) pci_data) << 14;
	pci_read_config_word(mci->pdev, E7XXX_REMAPLIMIT, &pci_data);
	pvt->remaplimit = ((u32) pci_data) << 14;
	printk("tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
	       pvt->remapbase, pvt->remaplimit);

	/* clear any pending errors, or initial state bits */
	pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
	pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);

	if (edac_mc_add_mc(mci) != 0) {
		debugf3("MC: " __FILE__
			": %s(): failed edac_mc_add_mc()\n",
			__func__);
		goto fail;
	}

	/* get this far and it's successful */
	debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
	return 0;

fail:
	if (mci != NULL) {
		if(pvt != NULL && pvt->bridge_ck)
			pci_dev_put(pvt->bridge_ck);
		edac_mc_free(mci);
	}

	return rc;
}

/* returns count (>= 0), or negative on error */
static int __devinit
e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	debugf0("MC: " __FILE__ ": %s()\n", __func__);

	/* wake up and enable device */
	return pci_enable_device(pdev) ?
	    -EIO : e7xxx_probe1(pdev, ent->driver_data);
}


static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;
	struct e7xxx_pvt *pvt;

	debugf0(__FILE__ ": %s()\n", __func__);

	if (((mci = edac_mc_find_mci_by_pdev(pdev)) != 0) &&
	    edac_mc_del_mc(mci)) {
		pvt = (struct e7xxx_pvt *) mci->pvt_info;
		pci_dev_put(pvt->bridge_ck);
		edac_mc_free(mci);
	}
}


static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
	{PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 E7205},
	{PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 E7500},
	{PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 E7501},
	{PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 E7505},
	{0,}			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);


static struct pci_driver e7xxx_driver = {
	.name = BS_MOD_STR,
	.probe = e7xxx_init_one,
	.remove = __devexit_p(e7xxx_remove_one),
	.id_table = e7xxx_pci_tbl,
};


static int __init e7xxx_init(void)
{
	return pci_register_driver(&e7xxx_driver);
}


static void __exit e7xxx_exit(void)
{
	pci_unregister_driver(&e7xxx_driver);
}

module_init(e7xxx_init);
module_exit(e7xxx_exit);


MODULE_LICENSE("GPL");
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
	      "Based on.work by Dan Hollis et al");
MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
Commit	Line	Data
806c35f5 AC	1	/*
	2	* Intel e7xxx Memory Controller kernel module
	3	* (C) 2003 Linux Networx (http://lnxi.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* See "enum e7xxx_chips" below for supported chipsets
	8	*
	9	* Written by Thayne Harbaugh
	10	* Based on work by Dan Hollis <goemon at anime dot net> and others.
	11	* http://www.anime.net/~goemon/linux-ecc/
	12	*
	13	* Contributors:
	14	* Eric Biederman (Linux Networx)
	15	* Tom Zimmerman (Linux Networx)
	16	* Jim Garlick (Lawrence Livermore National Labs)
	17	* Dave Peterson (Lawrence Livermore National Labs)
	18	* That One Guy (Some other place)
	19	* Wang Zhenyu (intel.com)
	20	*
	21	* $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
	22	*
	23	*/
	24
	25
	26	#include <linux/config.h>
	27	#include <linux/module.h>
	28	#include <linux/init.h>
	29	#include <linux/pci.h>
	30	#include <linux/pci_ids.h>
	31	#include <linux/slab.h>
	32	#include "edac_mc.h"
	33
	34
	35	#ifndef PCI_DEVICE_ID_INTEL_7205_0
	36	#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
	37	#endif /* PCI_DEVICE_ID_INTEL_7205_0 */
	38
	39	#ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
	40	#define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
	41	#endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
	42
	43	#ifndef PCI_DEVICE_ID_INTEL_7500_0
	44	#define PCI_DEVICE_ID_INTEL_7500_0 0x2540
	45	#endif /* PCI_DEVICE_ID_INTEL_7500_0 */
	46
	47	#ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
	48	#define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
	49	#endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
	50
	51	#ifndef PCI_DEVICE_ID_INTEL_7501_0
	52	#define PCI_DEVICE_ID_INTEL_7501_0 0x254c
	53	#endif /* PCI_DEVICE_ID_INTEL_7501_0 */
	54
	55	#ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
	56	#define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
	57	#endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
	58
	59	#ifndef PCI_DEVICE_ID_INTEL_7505_0
	60	#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
	61	#endif /* PCI_DEVICE_ID_INTEL_7505_0 */
	62
	63	#ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
	64	#define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
65	#endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
66
67
68	#define E7XXX_NR_CSROWS 8 /* number of csrows */
69	#define E7XXX_NR_DIMMS 8 /* FIXME - is this correct? */
70
71
72	/* E7XXX register addresses - device 0 function 0 */
73	#define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
74	#define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
75	/*
76	* 31 Device width row 7 0=x8 1=x4
77	* 27 Device width row 6
78	* 23 Device width row 5
79	* 19 Device width row 4
80	* 15 Device width row 3
81	* 11 Device width row 2
82	* 7 Device width row 1
83	* 3 Device width row 0
84	*/
85	#define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
86	/*
87	* 22 Number channels 0=1,1=2
88	* 19:18 DRB Granularity 32/64MB
89	*/
90	#define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
91	#define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
92	#define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
93
94	/* E7XXX register addresses - device 0 function 1 */
95	#define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
96	#define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
97	#define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
98	/* error address register (32b) */
99	/*
100	* 31:28 Reserved
101	* 27:6 CE address (4k block 33:12)
102	* 5:0 Reserved
103	*/
104	#define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
105	/* error address register (32b) */
106	/*
107	* 31:28 Reserved
108	* 27:6 CE address (4k block 33:12)
109	* 5:0 Reserved
110	*/
111	#define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
112	/* error syndrome register (16b) */
113
114	enum e7xxx_chips {
115	E7500 = 0,
116	E7501,
117	E7505,
118	E7205,
119	};
120
121
122	struct e7xxx_pvt {
123	struct pci_dev *bridge_ck;
124	u32 tolm;
125	u32 remapbase;
126	u32 remaplimit;
127	const struct e7xxx_dev_info *dev_info;
128	};
129
130
131	struct e7xxx_dev_info {
132	u16 err_dev;
133	const char *ctl_name;
134	};
135
136
137	struct e7xxx_error_info {
138	u8 dram_ferr;
139	u8 dram_nerr;
140	u32 dram_celog_add;
141	u16 dram_celog_syndrome;
142	u32 dram_uelog_add;
143	};
144
145	static const struct e7xxx_dev_info e7xxx_devs[] = {
146	[E7500] = {
147	.err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
148	.ctl_name = "E7500"},
149	[E7501] = {
150	.err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
151	.ctl_name = "E7501"},
152	[E7505] = {
153	.err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
154	.ctl_name = "E7505"},
155	[E7205] = {
156	.err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
157	.ctl_name = "E7205"},
158	};
159
160
161	/* FIXME - is this valid for both SECDED and S4ECD4ED? */
162	static inline int e7xxx_find_channel(u16 syndrome)
163	{
164	debugf3("MC: " __FILE__ ": %s()\n", __func__);
165
166	if ((syndrome & 0xff00) == 0)
167	return 0;
168	if ((syndrome & 0x00ff) == 0)
169	return 1;
170	if ((syndrome & 0xf000) == 0 \|\| (syndrome & 0x0f00) == 0)
171	return 0;
172	return 1;
173	}
174
175
176	static unsigned long
177	ctl_page_to_phys(struct mem_ctl_info *mci, unsigned long page)
178	{
179	u32 remap;
180	struct e7xxx_pvt pvt = (struct e7xxx_pvt ) mci->pvt_info;
181
182	debugf3("MC: " __FILE__ ": %s()\n", __func__);
183
184	if ((page < pvt->tolm) \|\|
185	((page >= 0x100000) && (page < pvt->remapbase)))
186	return page;
187	remap = (page - pvt->tolm) + pvt->remapbase;
188	if (remap < pvt->remaplimit)
189	return remap;
190	printk(KERN_ERR "Invalid page %lx - out of range\n", page);
191	return pvt->tolm - 1;
192	}
193
194
195	static void process_ce(struct mem_ctl_info mci, struct e7xxx_error_info info)
196	{
197	u32 error_1b, page;
198	u16 syndrome;
199	int row;
200	int channel;
201
202	debugf3("MC: " __FILE__ ": %s()\n", __func__);
203
204	/* read the error address */
205	error_1b = info->dram_celog_add;
206	/* FIXME - should use PAGE_SHIFT */
207	page = error_1b >> 6; /* convert the address to 4k page */
208	/* read the syndrome */
209	syndrome = info->dram_celog_syndrome;
210	/* FIXME - check for -1 */
211	row = edac_mc_find_csrow_by_page(mci, page);
212	/* convert syndrome to channel */
213	channel = e7xxx_find_channel(syndrome);
214	edac_mc_handle_ce(mci, page, 0, syndrome, row, channel,
215	"e7xxx CE");
216	}
217
218
219	static void process_ce_no_info(struct mem_ctl_info *mci)
220	{
221	debugf3("MC: " __FILE__ ": %s()\n", __func__);
222	edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
223	}
224
225
226	static void process_ue(struct mem_ctl_info mci, struct e7xxx_error_info info)
227	{
228	u32 error_2b, block_page;
229	int row;
230
231	debugf3("MC: " __FILE__ ": %s()\n", __func__);
232
233	/* read the error address */
234	error_2b = info->dram_uelog_add;
235	/* FIXME - should use PAGE_SHIFT */
236	block_page = error_2b >> 6; /* convert to 4k address */
237	row = edac_mc_find_csrow_by_page(mci, block_page);
238	edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
239	}
240
241
242	static void process_ue_no_info(struct mem_ctl_info *mci)
243	{
244	debugf3("MC: " __FILE__ ": %s()\n", __func__);
245	edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
246	}
247
248
249	static void e7xxx_get_error_info (struct mem_ctl_info *mci,
250	struct e7xxx_error_info *info)
251	{
252	struct e7xxx_pvt *pvt;
253
254	pvt = (struct e7xxx_pvt *) mci->pvt_info;
255	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR,
256	&info->dram_ferr);
257	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR,
258	&info->dram_nerr);
259
260	if ((info->dram_ferr & 1) \|\| (info->dram_nerr & 1)) {
261	pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
262	&info->dram_celog_add);
263	pci_read_config_word(pvt->bridge_ck,
264	E7XXX_DRAM_CELOG_SYNDROME, &info->dram_celog_syndrome);
265	}
266
267	if ((info->dram_ferr & 2) \|\| (info->dram_nerr & 2))
268	pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
269	&info->dram_uelog_add);
270
271	if (info->dram_ferr & 3)
272	pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03,
273	0x03);
274
275	if (info->dram_nerr & 3)
276	pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03,
277	0x03);
278	}
279
280
281	static int e7xxx_process_error_info (struct mem_ctl_info *mci,
282	struct e7xxx_error_info *info, int handle_errors)
283	{
284	int error_found;
285
286	error_found = 0;
287
288	/* decode and report errors */
289	if (info->dram_ferr & 1) { /* check first error correctable */
290	error_found = 1;
291
292	if (handle_errors)
293	process_ce(mci, info);
294	}
295
296	if (info->dram_ferr & 2) { /* check first error uncorrectable */
297	error_found = 1;
298
299	if (handle_errors)
300	process_ue(mci, info);
301	}
302
303	if (info->dram_nerr & 1) { /* check next error correctable */
304	error_found = 1;
305
306	if (handle_errors) {
307	if (info->dram_ferr & 1)
308	process_ce_no_info(mci);
309	else
310	process_ce(mci, info);
311	}
312	}
313
314	if (info->dram_nerr & 2) { /* check next error uncorrectable */
315	error_found = 1;
316
317	if (handle_errors) {
318	if (info->dram_ferr & 2)
319	process_ue_no_info(mci);
320	else
321	process_ue(mci, info);
322	}
323	}
324
325	return error_found;
326	}
327
328
329	static void e7xxx_check(struct mem_ctl_info *mci)
330	{
331	struct e7xxx_error_info info;
332
333	debugf3("MC: " __FILE__ ": %s()\n", __func__);
334	e7xxx_get_error_info(mci, &info);
335	e7xxx_process_error_info(mci, &info, 1);
336	}
337
338
339	static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
340	{
341	int rc = -ENODEV;
342	int index;
343	u16 pci_data;
344	struct mem_ctl_info *mci = NULL;
345	struct e7xxx_pvt *pvt = NULL;
346	u32 drc;
347	int drc_chan = 1; /* Number of channels 0=1chan,1=2chan */
348	int drc_drbg = 1; /* DRB granularity 0=32mb,1=64mb */
349	int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
350	u32 dra;
351	unsigned long last_cumul_size;
352
353
354	debugf0("MC: " __FILE__ ": %s(): mci\n", __func__);
355
356	/* need to find out the number of channels */
357	pci_read_config_dword(pdev, E7XXX_DRC, &drc);
358	/* only e7501 can be single channel */
359	if (dev_idx == E7501) {
360	drc_chan = ((drc >> 22) & 0x1);
361	drc_drbg = (drc >> 18) & 0x3;
362	}
363	drc_ddim = (drc >> 20) & 0x3;
364
365	mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1);
366
367	if (mci == NULL) {
368	rc = -ENOMEM;
369	goto fail;
370	}
371
372	debugf3("MC: " __FILE__ ": %s(): init mci\n", __func__);
373
374	mci->mtype_cap = MEM_FLAG_RDDR;
375	mci->edac_ctl_cap =
376	EDAC_FLAG_NONE \| EDAC_FLAG_SECDED \| EDAC_FLAG_S4ECD4ED;
377	/* FIXME - what if different memory types are in different csrows? */
378	mci->mod_name = BS_MOD_STR;
379	mci->mod_ver = "$Revision: 1.5.2.9 $";
380	mci->pdev = pdev;
381
382	debugf3("MC: " __FILE__ ": %s(): init pvt\n", __func__);
383	pvt = (struct e7xxx_pvt *) mci->pvt_info;
384	pvt->dev_info = &e7xxx_devs[dev_idx];
385	pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
386	pvt->dev_info->err_dev,
387	pvt->bridge_ck);
388	if (!pvt->bridge_ck) {
389	printk(KERN_ERR
390	"MC: error reporting device not found:"
391	"vendor %x device 0x%x (broken BIOS?)\n",
392	PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
393	goto fail;
394	}
395
396	debugf3("MC: " __FILE__ ": %s(): more mci init\n", __func__);
397	mci->ctl_name = pvt->dev_info->ctl_name;
398
399	mci->edac_check = e7xxx_check;
400	mci->ctl_page_to_phys = ctl_page_to_phys;
401
402	/* find out the device types */
403	pci_read_config_dword(pdev, E7XXX_DRA, &dra);
404
405	/*
406	* The dram row boundary (DRB) reg values are boundary address
407	* for each DRAM row with a granularity of 32 or 64MB (single/dual
408	* channel operation). DRB regs are cumulative; therefore DRB7 will
409	* contain the total memory contained in all eight rows.
410	*/
411	for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
412	u8 value;
413	u32 cumul_size;
414	/* mem_dev 0=x8, 1=x4 */
415	int mem_dev = (dra >> (index * 4 + 3)) & 0x1;
416	struct csrow_info *csrow = &mci->csrows[index];
417
418	pci_read_config_byte(mci->pdev, E7XXX_DRB + index, &value);
419	/* convert a 64 or 32 MiB DRB to a page size. */
420	cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
421	debugf3("MC: " __FILE__ ": %s(): (%d) cumul_size 0x%x\n",
422	__func__, index, cumul_size);
423	if (cumul_size == last_cumul_size)
424	continue; /* not populated */
425
426	csrow->first_page = last_cumul_size;
427	csrow->last_page = cumul_size - 1;
428	csrow->nr_pages = cumul_size - last_cumul_size;
429	last_cumul_size = cumul_size;
430	csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
431	csrow->mtype = MEM_RDDR; /* only one type supported */
432	csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
433
434	/*
435	* if single channel or x8 devices then SECDED
436	* if dual channel and x4 then S4ECD4ED
437	*/
438	if (drc_ddim) {
439	if (drc_chan && mem_dev) {
440	csrow->edac_mode = EDAC_S4ECD4ED;
441	mci->edac_cap \|= EDAC_FLAG_S4ECD4ED;
442	} else {
443	csrow->edac_mode = EDAC_SECDED;
444	mci->edac_cap \|= EDAC_FLAG_SECDED;
445	}
446	} else
447	csrow->edac_mode = EDAC_NONE;
448	}
449
450	mci->edac_cap \|= EDAC_FLAG_NONE;
451
452	debugf3("MC: " __FILE__ ": %s(): tolm, remapbase, remaplimit\n",
453	__func__);
454	/* load the top of low memory, remap base, and remap limit vars */
455	pci_read_config_word(mci->pdev, E7XXX_TOLM, &pci_data);
456	pvt->tolm = ((u32) pci_data) << 4;
457	pci_read_config_word(mci->pdev, E7XXX_REMAPBASE, &pci_data);
458	pvt->remapbase = ((u32) pci_data) << 14;
459	pci_read_config_word(mci->pdev, E7XXX_REMAPLIMIT, &pci_data);
460	pvt->remaplimit = ((u32) pci_data) << 14;
461	printk("tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
462	pvt->remapbase, pvt->remaplimit);
463
464	/* clear any pending errors, or initial state bits */
465	pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
466	pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
467
468	if (edac_mc_add_mc(mci) != 0) {
469	debugf3("MC: " __FILE__
470	": %s(): failed edac_mc_add_mc()\n",
471	__func__);
472	goto fail;
473	}
474
475	/* get this far and it's successful */
476	debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
477	return 0;
478
479	fail:
480	if (mci != NULL) {
481	if(pvt != NULL && pvt->bridge_ck)
482	pci_dev_put(pvt->bridge_ck);
483	edac_mc_free(mci);
484	}
485
486	return rc;
487	}
488
489	/* returns count (>= 0), or negative on error */
490	static int __devinit
491	e7xxx_init_one(struct pci_dev pdev, const struct pci_device_id ent)
492	{
493	debugf0("MC: " __FILE__ ": %s()\n", __func__);
494
495	/* wake up and enable device */
496	return pci_enable_device(pdev) ?
497	-EIO : e7xxx_probe1(pdev, ent->driver_data);
498	}
499
500
501	static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
502	{
503	struct mem_ctl_info *mci;
504	struct e7xxx_pvt *pvt;
505
506	debugf0(__FILE__ ": %s()\n", __func__);
507
508	if (((mci = edac_mc_find_mci_by_pdev(pdev)) != 0) &&
509	edac_mc_del_mc(mci)) {
510	pvt = (struct e7xxx_pvt *) mci->pvt_info;
511	pci_dev_put(pvt->bridge_ck);
512	edac_mc_free(mci);
513	}
514	}
515
516
517	static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
518	{PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
519	E7205},
520	{PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
521	E7500},
522	{PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
523	E7501},
524	{PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
525	E7505},
526	{0,} /* 0 terminated list. */
527	};
528
529	MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
530
531
532	static struct pci_driver e7xxx_driver = {
533	.name = BS_MOD_STR,
534	.probe = e7xxx_init_one,
535	.remove = __devexit_p(e7xxx_remove_one),
536	.id_table = e7xxx_pci_tbl,
537	};
538
539
da9bb1d2	540	static int __init e7xxx_init(void)
806c35f5 AC	541	{
	542	return pci_register_driver(&e7xxx_driver);
	543	}
	544
	545
	546	static void __exit e7xxx_exit(void)
	547	{
	548	pci_unregister_driver(&e7xxx_driver);
	549	}
	550
	551	module_init(e7xxx_init);
	552	module_exit(e7xxx_exit);
	553
	554
	555	MODULE_LICENSE("GPL");
	556	MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
	557	"Based on.work by Dan Hollis et al");
	558	MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");