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bf40a686 DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * | |
22 | * The full GNU General Public License is included in this distribution in | |
23 | * the file called "COPYING". | |
24 | * | |
25 | * BSD LICENSE | |
26 | * | |
27 | * Copyright(c) 2004-2009 Intel Corporation. All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions are met: | |
31 | * | |
32 | * * Redistributions of source code must retain the above copyright | |
33 | * notice, this list of conditions and the following disclaimer. | |
34 | * * Redistributions in binary form must reproduce the above copyright | |
35 | * notice, this list of conditions and the following disclaimer in | |
36 | * the documentation and/or other materials provided with the | |
37 | * distribution. | |
38 | * * Neither the name of Intel Corporation nor the names of its | |
39 | * contributors may be used to endorse or promote products derived | |
40 | * from this software without specific prior written permission. | |
41 | * | |
42 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
43 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
44 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
45 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
46 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
47 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
48 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
49 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
50 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
51 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
52 | * POSSIBILITY OF SUCH DAMAGE. | |
53 | */ | |
54 | ||
55 | /* | |
56 | * Support routines for v3+ hardware | |
57 | */ | |
58 | ||
59 | #include <linux/pci.h> | |
60 | #include <linux/dmaengine.h> | |
61 | #include <linux/dma-mapping.h> | |
62 | #include "registers.h" | |
63 | #include "hw.h" | |
64 | #include "dma.h" | |
65 | #include "dma_v2.h" | |
66 | ||
b094ad3b DW |
67 | /* ioat hardware assumes at least two sources for raid operations */ |
68 | #define src_cnt_to_sw(x) ((x) + 2) | |
69 | #define src_cnt_to_hw(x) ((x) - 2) | |
70 | ||
71 | /* provide a lookup table for setting the source address in the base or | |
d69d235b | 72 | * extended descriptor of an xor or pq descriptor |
b094ad3b DW |
73 | */ |
74 | static const u8 xor_idx_to_desc __read_mostly = 0xd0; | |
75 | static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 }; | |
d69d235b DW |
76 | static const u8 pq_idx_to_desc __read_mostly = 0xf8; |
77 | static const u8 pq_idx_to_field[] __read_mostly = { 1, 4, 5, 0, 1, 2, 4, 5 }; | |
b094ad3b DW |
78 | |
79 | static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) | |
80 | { | |
81 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
82 | ||
83 | return raw->field[xor_idx_to_field[idx]]; | |
84 | } | |
85 | ||
86 | static void xor_set_src(struct ioat_raw_descriptor *descs[2], | |
87 | dma_addr_t addr, u32 offset, int idx) | |
88 | { | |
89 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
90 | ||
91 | raw->field[xor_idx_to_field[idx]] = addr + offset; | |
92 | } | |
93 | ||
d69d235b DW |
94 | static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
95 | { | |
96 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
97 | ||
98 | return raw->field[pq_idx_to_field[idx]]; | |
99 | } | |
100 | ||
101 | static void pq_set_src(struct ioat_raw_descriptor *descs[2], | |
102 | dma_addr_t addr, u32 offset, u8 coef, int idx) | |
103 | { | |
104 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; | |
105 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
106 | ||
107 | raw->field[pq_idx_to_field[idx]] = addr + offset; | |
108 | pq->coef[idx] = coef; | |
109 | } | |
110 | ||
bf40a686 | 111 | static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, |
b094ad3b | 112 | struct ioat_ring_ent *desc, int idx) |
bf40a686 DW |
113 | { |
114 | struct ioat_chan_common *chan = &ioat->base; | |
115 | struct pci_dev *pdev = chan->device->pdev; | |
116 | size_t len = desc->len; | |
117 | size_t offset = len - desc->hw->size; | |
118 | struct dma_async_tx_descriptor *tx = &desc->txd; | |
119 | enum dma_ctrl_flags flags = tx->flags; | |
120 | ||
121 | switch (desc->hw->ctl_f.op) { | |
122 | case IOAT_OP_COPY: | |
58c8649e DW |
123 | if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */ |
124 | ioat_dma_unmap(chan, flags, len, desc->hw); | |
bf40a686 DW |
125 | break; |
126 | case IOAT_OP_FILL: { | |
127 | struct ioat_fill_descriptor *hw = desc->fill; | |
128 | ||
129 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
130 | ioat_unmap(pdev, hw->dst_addr - offset, len, | |
131 | PCI_DMA_FROMDEVICE, flags, 1); | |
132 | break; | |
133 | } | |
b094ad3b DW |
134 | case IOAT_OP_XOR_VAL: |
135 | case IOAT_OP_XOR: { | |
136 | struct ioat_xor_descriptor *xor = desc->xor; | |
137 | struct ioat_ring_ent *ext; | |
138 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
139 | int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt); | |
140 | struct ioat_raw_descriptor *descs[2]; | |
141 | int i; | |
142 | ||
143 | if (src_cnt > 5) { | |
144 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
145 | xor_ex = ext->xor_ex; | |
146 | } | |
147 | ||
148 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
149 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
150 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
151 | for (i = 0; i < src_cnt; i++) { | |
152 | dma_addr_t src = xor_get_src(descs, i); | |
153 | ||
154 | ioat_unmap(pdev, src - offset, len, | |
155 | PCI_DMA_TODEVICE, flags, 0); | |
156 | } | |
157 | ||
158 | /* dest is a source in xor validate operations */ | |
159 | if (xor->ctl_f.op == IOAT_OP_XOR_VAL) { | |
160 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
161 | PCI_DMA_TODEVICE, flags, 1); | |
162 | break; | |
163 | } | |
164 | } | |
165 | ||
166 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
167 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
168 | PCI_DMA_FROMDEVICE, flags, 1); | |
169 | break; | |
170 | } | |
d69d235b DW |
171 | case IOAT_OP_PQ_VAL: |
172 | case IOAT_OP_PQ: { | |
173 | struct ioat_pq_descriptor *pq = desc->pq; | |
174 | struct ioat_ring_ent *ext; | |
175 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
176 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
177 | struct ioat_raw_descriptor *descs[2]; | |
178 | int i; | |
179 | ||
180 | if (src_cnt > 3) { | |
181 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
182 | pq_ex = ext->pq_ex; | |
183 | } | |
184 | ||
185 | /* in the 'continue' case don't unmap the dests as sources */ | |
186 | if (dmaf_p_disabled_continue(flags)) | |
187 | src_cnt--; | |
188 | else if (dmaf_continue(flags)) | |
189 | src_cnt -= 3; | |
190 | ||
191 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
192 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
193 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
194 | for (i = 0; i < src_cnt; i++) { | |
195 | dma_addr_t src = pq_get_src(descs, i); | |
196 | ||
197 | ioat_unmap(pdev, src - offset, len, | |
198 | PCI_DMA_TODEVICE, flags, 0); | |
199 | } | |
200 | ||
201 | /* the dests are sources in pq validate operations */ | |
202 | if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { | |
203 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
204 | ioat_unmap(pdev, pq->p_addr - offset, | |
205 | len, PCI_DMA_TODEVICE, flags, 0); | |
206 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
207 | ioat_unmap(pdev, pq->q_addr - offset, | |
208 | len, PCI_DMA_TODEVICE, flags, 0); | |
209 | break; | |
210 | } | |
211 | } | |
212 | ||
213 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
214 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
215 | ioat_unmap(pdev, pq->p_addr - offset, len, | |
216 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
217 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
218 | ioat_unmap(pdev, pq->q_addr - offset, len, | |
219 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
220 | } | |
221 | break; | |
222 | } | |
bf40a686 DW |
223 | default: |
224 | dev_err(&pdev->dev, "%s: unknown op type: %#x\n", | |
225 | __func__, desc->hw->ctl_f.op); | |
226 | } | |
227 | } | |
228 | ||
b094ad3b DW |
229 | static bool desc_has_ext(struct ioat_ring_ent *desc) |
230 | { | |
231 | struct ioat_dma_descriptor *hw = desc->hw; | |
232 | ||
233 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
234 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
235 | struct ioat_xor_descriptor *xor = desc->xor; | |
bf40a686 | 236 | |
b094ad3b DW |
237 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) |
238 | return true; | |
d69d235b DW |
239 | } else if (hw->ctl_f.op == IOAT_OP_PQ || |
240 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
241 | struct ioat_pq_descriptor *pq = desc->pq; | |
242 | ||
243 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
244 | return true; | |
b094ad3b DW |
245 | } |
246 | ||
247 | return false; | |
248 | } | |
249 | ||
250 | /** | |
251 | * __cleanup - reclaim used descriptors | |
252 | * @ioat: channel (ring) to clean | |
253 | * | |
254 | * The difference from the dma_v2.c __cleanup() is that this routine | |
255 | * handles extended descriptors and dma-unmapping raid operations. | |
256 | */ | |
bf40a686 DW |
257 | static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) |
258 | { | |
259 | struct ioat_chan_common *chan = &ioat->base; | |
260 | struct ioat_ring_ent *desc; | |
261 | bool seen_current = false; | |
262 | u16 active; | |
263 | int i; | |
264 | ||
265 | dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
266 | __func__, ioat->head, ioat->tail, ioat->issued); | |
267 | ||
268 | active = ioat2_ring_active(ioat); | |
269 | for (i = 0; i < active && !seen_current; i++) { | |
270 | struct dma_async_tx_descriptor *tx; | |
271 | ||
272 | prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1)); | |
273 | desc = ioat2_get_ring_ent(ioat, ioat->tail + i); | |
274 | dump_desc_dbg(ioat, desc); | |
275 | tx = &desc->txd; | |
276 | if (tx->cookie) { | |
277 | chan->completed_cookie = tx->cookie; | |
b094ad3b | 278 | ioat3_dma_unmap(ioat, desc, ioat->tail + i); |
bf40a686 DW |
279 | tx->cookie = 0; |
280 | if (tx->callback) { | |
281 | tx->callback(tx->callback_param); | |
282 | tx->callback = NULL; | |
283 | } | |
284 | } | |
285 | ||
286 | if (tx->phys == phys_complete) | |
287 | seen_current = true; | |
b094ad3b DW |
288 | |
289 | /* skip extended descriptors */ | |
290 | if (desc_has_ext(desc)) { | |
291 | BUG_ON(i + 1 >= active); | |
292 | i++; | |
293 | } | |
bf40a686 DW |
294 | } |
295 | ioat->tail += i; | |
296 | BUG_ON(!seen_current); /* no active descs have written a completion? */ | |
297 | chan->last_completion = phys_complete; | |
298 | if (ioat->head == ioat->tail) { | |
299 | dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", | |
300 | __func__); | |
301 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); | |
302 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
303 | } | |
304 | } | |
305 | ||
306 | static void ioat3_cleanup(struct ioat2_dma_chan *ioat) | |
307 | { | |
308 | struct ioat_chan_common *chan = &ioat->base; | |
309 | unsigned long phys_complete; | |
310 | ||
311 | prefetch(chan->completion); | |
312 | ||
313 | if (!spin_trylock_bh(&chan->cleanup_lock)) | |
314 | return; | |
315 | ||
316 | if (!ioat_cleanup_preamble(chan, &phys_complete)) { | |
317 | spin_unlock_bh(&chan->cleanup_lock); | |
318 | return; | |
319 | } | |
320 | ||
321 | if (!spin_trylock_bh(&ioat->ring_lock)) { | |
322 | spin_unlock_bh(&chan->cleanup_lock); | |
323 | return; | |
324 | } | |
325 | ||
326 | __cleanup(ioat, phys_complete); | |
327 | ||
328 | spin_unlock_bh(&ioat->ring_lock); | |
329 | spin_unlock_bh(&chan->cleanup_lock); | |
330 | } | |
331 | ||
332 | static void ioat3_cleanup_tasklet(unsigned long data) | |
333 | { | |
334 | struct ioat2_dma_chan *ioat = (void *) data; | |
335 | ||
336 | ioat3_cleanup(ioat); | |
e61dacae DW |
337 | writew(IOAT_CHANCTRL_RUN | IOAT3_CHANCTRL_COMPL_DCA_EN, |
338 | ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); | |
bf40a686 DW |
339 | } |
340 | ||
341 | static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) | |
342 | { | |
343 | struct ioat_chan_common *chan = &ioat->base; | |
344 | unsigned long phys_complete; | |
345 | u32 status; | |
346 | ||
347 | status = ioat_chansts(chan); | |
348 | if (is_ioat_active(status) || is_ioat_idle(status)) | |
349 | ioat_suspend(chan); | |
350 | while (is_ioat_active(status) || is_ioat_idle(status)) { | |
351 | status = ioat_chansts(chan); | |
352 | cpu_relax(); | |
353 | } | |
354 | ||
355 | if (ioat_cleanup_preamble(chan, &phys_complete)) | |
356 | __cleanup(ioat, phys_complete); | |
357 | ||
358 | __ioat2_restart_chan(ioat); | |
359 | } | |
360 | ||
361 | static void ioat3_timer_event(unsigned long data) | |
362 | { | |
363 | struct ioat2_dma_chan *ioat = (void *) data; | |
364 | struct ioat_chan_common *chan = &ioat->base; | |
365 | ||
366 | spin_lock_bh(&chan->cleanup_lock); | |
367 | if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) { | |
368 | unsigned long phys_complete; | |
369 | u64 status; | |
370 | ||
371 | spin_lock_bh(&ioat->ring_lock); | |
372 | status = ioat_chansts(chan); | |
373 | ||
374 | /* when halted due to errors check for channel | |
375 | * programming errors before advancing the completion state | |
376 | */ | |
377 | if (is_ioat_halted(status)) { | |
378 | u32 chanerr; | |
379 | ||
380 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
381 | BUG_ON(is_ioat_bug(chanerr)); | |
382 | } | |
383 | ||
384 | /* if we haven't made progress and we have already | |
385 | * acknowledged a pending completion once, then be more | |
386 | * forceful with a restart | |
387 | */ | |
388 | if (ioat_cleanup_preamble(chan, &phys_complete)) | |
389 | __cleanup(ioat, phys_complete); | |
390 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) | |
391 | ioat3_restart_channel(ioat); | |
392 | else { | |
393 | set_bit(IOAT_COMPLETION_ACK, &chan->state); | |
394 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
395 | } | |
396 | spin_unlock_bh(&ioat->ring_lock); | |
397 | } else { | |
398 | u16 active; | |
399 | ||
400 | /* if the ring is idle, empty, and oversized try to step | |
401 | * down the size | |
402 | */ | |
403 | spin_lock_bh(&ioat->ring_lock); | |
404 | active = ioat2_ring_active(ioat); | |
405 | if (active == 0 && ioat->alloc_order > ioat_get_alloc_order()) | |
406 | reshape_ring(ioat, ioat->alloc_order-1); | |
407 | spin_unlock_bh(&ioat->ring_lock); | |
408 | ||
409 | /* keep shrinking until we get back to our minimum | |
410 | * default size | |
411 | */ | |
412 | if (ioat->alloc_order > ioat_get_alloc_order()) | |
413 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
414 | } | |
415 | spin_unlock_bh(&chan->cleanup_lock); | |
416 | } | |
417 | ||
418 | static enum dma_status | |
419 | ioat3_is_complete(struct dma_chan *c, dma_cookie_t cookie, | |
420 | dma_cookie_t *done, dma_cookie_t *used) | |
421 | { | |
422 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
423 | ||
424 | if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) | |
425 | return DMA_SUCCESS; | |
426 | ||
427 | ioat3_cleanup(ioat); | |
428 | ||
429 | return ioat_is_complete(c, cookie, done, used); | |
430 | } | |
431 | ||
432 | static struct dma_async_tx_descriptor * | |
433 | ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value, | |
434 | size_t len, unsigned long flags) | |
435 | { | |
436 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
437 | struct ioat_ring_ent *desc; | |
438 | size_t total_len = len; | |
439 | struct ioat_fill_descriptor *fill; | |
440 | int num_descs; | |
441 | u64 src_data = (0x0101010101010101ULL) * (value & 0xff); | |
442 | u16 idx; | |
443 | int i; | |
444 | ||
445 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
446 | if (likely(num_descs) && | |
447 | ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0) | |
448 | /* pass */; | |
449 | else | |
450 | return NULL; | |
cdef57db DW |
451 | i = 0; |
452 | do { | |
bf40a686 DW |
453 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); |
454 | ||
455 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
456 | fill = desc->fill; | |
457 | ||
458 | fill->size = xfer_size; | |
459 | fill->src_data = src_data; | |
460 | fill->dst_addr = dest; | |
461 | fill->ctl = 0; | |
462 | fill->ctl_f.op = IOAT_OP_FILL; | |
463 | ||
464 | len -= xfer_size; | |
465 | dest += xfer_size; | |
466 | dump_desc_dbg(ioat, desc); | |
cdef57db | 467 | } while (++i < num_descs); |
bf40a686 DW |
468 | |
469 | desc->txd.flags = flags; | |
470 | desc->len = total_len; | |
471 | fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
472 | fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
473 | fill->ctl_f.compl_write = 1; | |
474 | dump_desc_dbg(ioat, desc); | |
475 | ||
476 | /* we leave the channel locked to ensure in order submission */ | |
477 | return &desc->txd; | |
478 | } | |
479 | ||
b094ad3b DW |
480 | static struct dma_async_tx_descriptor * |
481 | __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, | |
482 | dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, | |
483 | size_t len, unsigned long flags) | |
484 | { | |
485 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
486 | struct ioat_ring_ent *compl_desc; | |
487 | struct ioat_ring_ent *desc; | |
488 | struct ioat_ring_ent *ext; | |
489 | size_t total_len = len; | |
490 | struct ioat_xor_descriptor *xor; | |
491 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
492 | struct ioat_dma_descriptor *hw; | |
493 | u32 offset = 0; | |
494 | int num_descs; | |
495 | int with_ext; | |
496 | int i; | |
497 | u16 idx; | |
498 | u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; | |
499 | ||
500 | BUG_ON(src_cnt < 2); | |
501 | ||
502 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
503 | /* we need 2x the number of descriptors to cover greater than 5 | |
504 | * sources | |
505 | */ | |
506 | if (src_cnt > 5) { | |
507 | with_ext = 1; | |
508 | num_descs *= 2; | |
509 | } else | |
510 | with_ext = 0; | |
511 | ||
512 | /* completion writes from the raid engine may pass completion | |
513 | * writes from the legacy engine, so we need one extra null | |
514 | * (legacy) descriptor to ensure all completion writes arrive in | |
515 | * order. | |
516 | */ | |
517 | if (likely(num_descs) && | |
518 | ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0) | |
519 | /* pass */; | |
520 | else | |
521 | return NULL; | |
cdef57db DW |
522 | i = 0; |
523 | do { | |
b094ad3b DW |
524 | struct ioat_raw_descriptor *descs[2]; |
525 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
526 | int s; | |
527 | ||
528 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
529 | xor = desc->xor; | |
530 | ||
531 | /* save a branch by unconditionally retrieving the | |
532 | * extended descriptor xor_set_src() knows to not write | |
533 | * to it in the single descriptor case | |
534 | */ | |
535 | ext = ioat2_get_ring_ent(ioat, idx + i + 1); | |
536 | xor_ex = ext->xor_ex; | |
537 | ||
538 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
539 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
540 | for (s = 0; s < src_cnt; s++) | |
541 | xor_set_src(descs, src[s], offset, s); | |
542 | xor->size = xfer_size; | |
543 | xor->dst_addr = dest + offset; | |
544 | xor->ctl = 0; | |
545 | xor->ctl_f.op = op; | |
546 | xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); | |
547 | ||
548 | len -= xfer_size; | |
549 | offset += xfer_size; | |
550 | dump_desc_dbg(ioat, desc); | |
cdef57db | 551 | } while ((i += 1 + with_ext) < num_descs); |
b094ad3b DW |
552 | |
553 | /* last xor descriptor carries the unmap parameters and fence bit */ | |
554 | desc->txd.flags = flags; | |
555 | desc->len = total_len; | |
556 | if (result) | |
557 | desc->result = result; | |
558 | xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
559 | ||
560 | /* completion descriptor carries interrupt bit */ | |
561 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
562 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
563 | hw = compl_desc->hw; | |
564 | hw->ctl = 0; | |
565 | hw->ctl_f.null = 1; | |
566 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
567 | hw->ctl_f.compl_write = 1; | |
568 | hw->size = NULL_DESC_BUFFER_SIZE; | |
569 | dump_desc_dbg(ioat, compl_desc); | |
570 | ||
571 | /* we leave the channel locked to ensure in order submission */ | |
572 | return &desc->txd; | |
573 | } | |
574 | ||
575 | static struct dma_async_tx_descriptor * | |
576 | ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
577 | unsigned int src_cnt, size_t len, unsigned long flags) | |
578 | { | |
579 | return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); | |
580 | } | |
581 | ||
582 | struct dma_async_tx_descriptor * | |
583 | ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, | |
584 | unsigned int src_cnt, size_t len, | |
585 | enum sum_check_flags *result, unsigned long flags) | |
586 | { | |
587 | /* the cleanup routine only sets bits on validate failure, it | |
588 | * does not clear bits on validate success... so clear it here | |
589 | */ | |
590 | *result = 0; | |
591 | ||
592 | return __ioat3_prep_xor_lock(chan, result, src[0], &src[1], | |
593 | src_cnt - 1, len, flags); | |
594 | } | |
595 | ||
d69d235b DW |
596 | static void |
597 | dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext) | |
598 | { | |
599 | struct device *dev = to_dev(&ioat->base); | |
600 | struct ioat_pq_descriptor *pq = desc->pq; | |
601 | struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; | |
602 | struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; | |
603 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
604 | int i; | |
605 | ||
606 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
607 | " sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n", | |
608 | desc_id(desc), (unsigned long long) desc->txd.phys, | |
609 | (unsigned long long) (pq_ex ? pq_ex->next : pq->next), | |
610 | desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en, | |
611 | pq->ctl_f.compl_write, | |
612 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
613 | pq->ctl_f.src_cnt); | |
614 | for (i = 0; i < src_cnt; i++) | |
615 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
616 | (unsigned long long) pq_get_src(descs, i), pq->coef[i]); | |
617 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
618 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
619 | } | |
620 | ||
621 | static struct dma_async_tx_descriptor * | |
622 | __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, | |
623 | const dma_addr_t *dst, const dma_addr_t *src, | |
624 | unsigned int src_cnt, const unsigned char *scf, | |
625 | size_t len, unsigned long flags) | |
626 | { | |
627 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
628 | struct ioat_chan_common *chan = &ioat->base; | |
629 | struct ioat_ring_ent *compl_desc; | |
630 | struct ioat_ring_ent *desc; | |
631 | struct ioat_ring_ent *ext; | |
632 | size_t total_len = len; | |
633 | struct ioat_pq_descriptor *pq; | |
634 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
635 | struct ioat_dma_descriptor *hw; | |
636 | u32 offset = 0; | |
637 | int num_descs; | |
638 | int with_ext; | |
639 | int i, s; | |
640 | u16 idx; | |
641 | u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; | |
642 | ||
643 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
644 | /* the engine requires at least two sources (we provide | |
645 | * at least 1 implied source in the DMA_PREP_CONTINUE case) | |
646 | */ | |
647 | BUG_ON(src_cnt + dmaf_continue(flags) < 2); | |
648 | ||
649 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
650 | /* we need 2x the number of descriptors to cover greater than 3 | |
651 | * sources | |
652 | */ | |
653 | if (src_cnt > 3 || flags & DMA_PREP_CONTINUE) { | |
654 | with_ext = 1; | |
655 | num_descs *= 2; | |
656 | } else | |
657 | with_ext = 0; | |
658 | ||
659 | /* completion writes from the raid engine may pass completion | |
660 | * writes from the legacy engine, so we need one extra null | |
661 | * (legacy) descriptor to ensure all completion writes arrive in | |
662 | * order. | |
663 | */ | |
664 | if (likely(num_descs) && | |
665 | ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0) | |
666 | /* pass */; | |
667 | else | |
668 | return NULL; | |
cdef57db DW |
669 | i = 0; |
670 | do { | |
d69d235b DW |
671 | struct ioat_raw_descriptor *descs[2]; |
672 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
673 | ||
674 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
675 | pq = desc->pq; | |
676 | ||
677 | /* save a branch by unconditionally retrieving the | |
678 | * extended descriptor pq_set_src() knows to not write | |
679 | * to it in the single descriptor case | |
680 | */ | |
681 | ext = ioat2_get_ring_ent(ioat, idx + i + with_ext); | |
682 | pq_ex = ext->pq_ex; | |
683 | ||
684 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
685 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
686 | ||
687 | for (s = 0; s < src_cnt; s++) | |
688 | pq_set_src(descs, src[s], offset, scf[s], s); | |
689 | ||
690 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
691 | if (dmaf_p_disabled_continue(flags)) | |
692 | pq_set_src(descs, dst[1], offset, 1, s++); | |
693 | else if (dmaf_continue(flags)) { | |
694 | pq_set_src(descs, dst[0], offset, 0, s++); | |
695 | pq_set_src(descs, dst[1], offset, 1, s++); | |
696 | pq_set_src(descs, dst[1], offset, 0, s++); | |
697 | } | |
698 | pq->size = xfer_size; | |
699 | pq->p_addr = dst[0] + offset; | |
700 | pq->q_addr = dst[1] + offset; | |
701 | pq->ctl = 0; | |
702 | pq->ctl_f.op = op; | |
703 | pq->ctl_f.src_cnt = src_cnt_to_hw(s); | |
704 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); | |
705 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
706 | ||
707 | len -= xfer_size; | |
708 | offset += xfer_size; | |
cdef57db | 709 | } while ((i += 1 + with_ext) < num_descs); |
d69d235b DW |
710 | |
711 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
712 | desc->txd.flags = flags; | |
713 | desc->len = total_len; | |
714 | if (result) | |
715 | desc->result = result; | |
716 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
717 | dump_pq_desc_dbg(ioat, desc, ext); | |
718 | ||
719 | /* completion descriptor carries interrupt bit */ | |
720 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
721 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
722 | hw = compl_desc->hw; | |
723 | hw->ctl = 0; | |
724 | hw->ctl_f.null = 1; | |
725 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
726 | hw->ctl_f.compl_write = 1; | |
727 | hw->size = NULL_DESC_BUFFER_SIZE; | |
728 | dump_desc_dbg(ioat, compl_desc); | |
729 | ||
730 | /* we leave the channel locked to ensure in order submission */ | |
731 | return &desc->txd; | |
732 | } | |
733 | ||
734 | static struct dma_async_tx_descriptor * | |
735 | ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
736 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
737 | unsigned long flags) | |
738 | { | |
de581b65 DW |
739 | /* specify valid address for disabled result */ |
740 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
741 | dst[0] = dst[1]; | |
742 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
743 | dst[1] = dst[0]; | |
744 | ||
d69d235b DW |
745 | /* handle the single source multiply case from the raid6 |
746 | * recovery path | |
747 | */ | |
de581b65 | 748 | if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) { |
d69d235b DW |
749 | dma_addr_t single_source[2]; |
750 | unsigned char single_source_coef[2]; | |
751 | ||
752 | BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); | |
753 | single_source[0] = src[0]; | |
754 | single_source[1] = src[0]; | |
755 | single_source_coef[0] = scf[0]; | |
756 | single_source_coef[1] = 0; | |
757 | ||
758 | return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2, | |
759 | single_source_coef, len, flags); | |
760 | } else | |
761 | return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf, | |
762 | len, flags); | |
763 | } | |
764 | ||
765 | struct dma_async_tx_descriptor * | |
766 | ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
767 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
768 | enum sum_check_flags *pqres, unsigned long flags) | |
769 | { | |
de581b65 DW |
770 | /* specify valid address for disabled result */ |
771 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
772 | pq[0] = pq[1]; | |
773 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
774 | pq[1] = pq[0]; | |
775 | ||
d69d235b DW |
776 | /* the cleanup routine only sets bits on validate failure, it |
777 | * does not clear bits on validate success... so clear it here | |
778 | */ | |
779 | *pqres = 0; | |
780 | ||
781 | return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, | |
782 | flags); | |
783 | } | |
784 | ||
ae786624 DW |
785 | static struct dma_async_tx_descriptor * |
786 | ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, | |
787 | unsigned int src_cnt, size_t len, unsigned long flags) | |
788 | { | |
789 | unsigned char scf[src_cnt]; | |
790 | dma_addr_t pq[2]; | |
791 | ||
792 | memset(scf, 0, src_cnt); | |
ae786624 | 793 | pq[0] = dst; |
de581b65 DW |
794 | flags |= DMA_PREP_PQ_DISABLE_Q; |
795 | pq[1] = dst; /* specify valid address for disabled result */ | |
ae786624 DW |
796 | |
797 | return __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, | |
798 | flags); | |
799 | } | |
800 | ||
801 | struct dma_async_tx_descriptor * | |
802 | ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, | |
803 | unsigned int src_cnt, size_t len, | |
804 | enum sum_check_flags *result, unsigned long flags) | |
805 | { | |
806 | unsigned char scf[src_cnt]; | |
807 | dma_addr_t pq[2]; | |
808 | ||
809 | /* the cleanup routine only sets bits on validate failure, it | |
810 | * does not clear bits on validate success... so clear it here | |
811 | */ | |
812 | *result = 0; | |
813 | ||
814 | memset(scf, 0, src_cnt); | |
ae786624 | 815 | pq[0] = src[0]; |
de581b65 DW |
816 | flags |= DMA_PREP_PQ_DISABLE_Q; |
817 | pq[1] = pq[0]; /* specify valid address for disabled result */ | |
ae786624 DW |
818 | |
819 | return __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, scf, | |
820 | len, flags); | |
821 | } | |
822 | ||
58c8649e DW |
823 | static struct dma_async_tx_descriptor * |
824 | ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) | |
825 | { | |
826 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
827 | struct ioat_ring_ent *desc; | |
828 | struct ioat_dma_descriptor *hw; | |
829 | u16 idx; | |
830 | ||
831 | if (ioat2_alloc_and_lock(&idx, ioat, 1) == 0) | |
832 | desc = ioat2_get_ring_ent(ioat, idx); | |
833 | else | |
834 | return NULL; | |
835 | ||
836 | hw = desc->hw; | |
837 | hw->ctl = 0; | |
838 | hw->ctl_f.null = 1; | |
839 | hw->ctl_f.int_en = 1; | |
840 | hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
841 | hw->ctl_f.compl_write = 1; | |
842 | hw->size = NULL_DESC_BUFFER_SIZE; | |
843 | hw->src_addr = 0; | |
844 | hw->dst_addr = 0; | |
845 | ||
846 | desc->txd.flags = flags; | |
847 | desc->len = 1; | |
848 | ||
849 | dump_desc_dbg(ioat, desc); | |
850 | ||
851 | /* we leave the channel locked to ensure in order submission */ | |
852 | return &desc->txd; | |
853 | } | |
854 | ||
9de6fc71 DW |
855 | static void __devinit ioat3_dma_test_callback(void *dma_async_param) |
856 | { | |
857 | struct completion *cmp = dma_async_param; | |
858 | ||
859 | complete(cmp); | |
860 | } | |
861 | ||
862 | #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ | |
863 | static int __devinit ioat_xor_val_self_test(struct ioatdma_device *device) | |
864 | { | |
865 | int i, src_idx; | |
866 | struct page *dest; | |
867 | struct page *xor_srcs[IOAT_NUM_SRC_TEST]; | |
868 | struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; | |
869 | dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; | |
870 | dma_addr_t dma_addr, dest_dma; | |
871 | struct dma_async_tx_descriptor *tx; | |
872 | struct dma_chan *dma_chan; | |
873 | dma_cookie_t cookie; | |
874 | u8 cmp_byte = 0; | |
875 | u32 cmp_word; | |
876 | u32 xor_val_result; | |
877 | int err = 0; | |
878 | struct completion cmp; | |
879 | unsigned long tmo; | |
880 | struct device *dev = &device->pdev->dev; | |
881 | struct dma_device *dma = &device->common; | |
882 | ||
883 | dev_dbg(dev, "%s\n", __func__); | |
884 | ||
885 | if (!dma_has_cap(DMA_XOR, dma->cap_mask)) | |
886 | return 0; | |
887 | ||
888 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
889 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
890 | if (!xor_srcs[src_idx]) { | |
891 | while (src_idx--) | |
892 | __free_page(xor_srcs[src_idx]); | |
893 | return -ENOMEM; | |
894 | } | |
895 | } | |
896 | ||
897 | dest = alloc_page(GFP_KERNEL); | |
898 | if (!dest) { | |
899 | while (src_idx--) | |
900 | __free_page(xor_srcs[src_idx]); | |
901 | return -ENOMEM; | |
902 | } | |
903 | ||
904 | /* Fill in src buffers */ | |
905 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
906 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
907 | for (i = 0; i < PAGE_SIZE; i++) | |
908 | ptr[i] = (1 << src_idx); | |
909 | } | |
910 | ||
911 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) | |
912 | cmp_byte ^= (u8) (1 << src_idx); | |
913 | ||
914 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
915 | (cmp_byte << 8) | cmp_byte; | |
916 | ||
917 | memset(page_address(dest), 0, PAGE_SIZE); | |
918 | ||
919 | dma_chan = container_of(dma->channels.next, struct dma_chan, | |
920 | device_node); | |
921 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { | |
922 | err = -ENODEV; | |
923 | goto out; | |
924 | } | |
925 | ||
926 | /* test xor */ | |
927 | dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
928 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
929 | dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, | |
930 | DMA_TO_DEVICE); | |
931 | tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
932 | IOAT_NUM_SRC_TEST, PAGE_SIZE, | |
933 | DMA_PREP_INTERRUPT); | |
934 | ||
935 | if (!tx) { | |
936 | dev_err(dev, "Self-test xor prep failed\n"); | |
937 | err = -ENODEV; | |
938 | goto free_resources; | |
939 | } | |
940 | ||
941 | async_tx_ack(tx); | |
942 | init_completion(&cmp); | |
943 | tx->callback = ioat3_dma_test_callback; | |
944 | tx->callback_param = &cmp; | |
945 | cookie = tx->tx_submit(tx); | |
946 | if (cookie < 0) { | |
947 | dev_err(dev, "Self-test xor setup failed\n"); | |
948 | err = -ENODEV; | |
949 | goto free_resources; | |
950 | } | |
951 | dma->device_issue_pending(dma_chan); | |
952 | ||
953 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
954 | ||
955 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
956 | dev_err(dev, "Self-test xor timed out\n"); | |
957 | err = -ENODEV; | |
958 | goto free_resources; | |
959 | } | |
960 | ||
961 | dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); | |
962 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
963 | u32 *ptr = page_address(dest); | |
964 | if (ptr[i] != cmp_word) { | |
965 | dev_err(dev, "Self-test xor failed compare\n"); | |
966 | err = -ENODEV; | |
967 | goto free_resources; | |
968 | } | |
969 | } | |
970 | dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE); | |
971 | ||
972 | /* skip validate if the capability is not present */ | |
973 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) | |
974 | goto free_resources; | |
975 | ||
976 | /* validate the sources with the destintation page */ | |
977 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
978 | xor_val_srcs[i] = xor_srcs[i]; | |
979 | xor_val_srcs[i] = dest; | |
980 | ||
981 | xor_val_result = 1; | |
982 | ||
983 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
984 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
985 | DMA_TO_DEVICE); | |
986 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
987 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
988 | &xor_val_result, DMA_PREP_INTERRUPT); | |
989 | if (!tx) { | |
990 | dev_err(dev, "Self-test zero prep failed\n"); | |
991 | err = -ENODEV; | |
992 | goto free_resources; | |
993 | } | |
994 | ||
995 | async_tx_ack(tx); | |
996 | init_completion(&cmp); | |
997 | tx->callback = ioat3_dma_test_callback; | |
998 | tx->callback_param = &cmp; | |
999 | cookie = tx->tx_submit(tx); | |
1000 | if (cookie < 0) { | |
1001 | dev_err(dev, "Self-test zero setup failed\n"); | |
1002 | err = -ENODEV; | |
1003 | goto free_resources; | |
1004 | } | |
1005 | dma->device_issue_pending(dma_chan); | |
1006 | ||
1007 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1008 | ||
1009 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1010 | dev_err(dev, "Self-test validate timed out\n"); | |
1011 | err = -ENODEV; | |
1012 | goto free_resources; | |
1013 | } | |
1014 | ||
1015 | if (xor_val_result != 0) { | |
1016 | dev_err(dev, "Self-test validate failed compare\n"); | |
1017 | err = -ENODEV; | |
1018 | goto free_resources; | |
1019 | } | |
1020 | ||
1021 | /* skip memset if the capability is not present */ | |
1022 | if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask)) | |
1023 | goto free_resources; | |
1024 | ||
1025 | /* test memset */ | |
1026 | dma_addr = dma_map_page(dev, dest, 0, | |
1027 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1028 | tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, | |
1029 | DMA_PREP_INTERRUPT); | |
1030 | if (!tx) { | |
1031 | dev_err(dev, "Self-test memset prep failed\n"); | |
1032 | err = -ENODEV; | |
1033 | goto free_resources; | |
1034 | } | |
1035 | ||
1036 | async_tx_ack(tx); | |
1037 | init_completion(&cmp); | |
1038 | tx->callback = ioat3_dma_test_callback; | |
1039 | tx->callback_param = &cmp; | |
1040 | cookie = tx->tx_submit(tx); | |
1041 | if (cookie < 0) { | |
1042 | dev_err(dev, "Self-test memset setup failed\n"); | |
1043 | err = -ENODEV; | |
1044 | goto free_resources; | |
1045 | } | |
1046 | dma->device_issue_pending(dma_chan); | |
1047 | ||
1048 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1049 | ||
1050 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1051 | dev_err(dev, "Self-test memset timed out\n"); | |
1052 | err = -ENODEV; | |
1053 | goto free_resources; | |
1054 | } | |
1055 | ||
1056 | for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) { | |
1057 | u32 *ptr = page_address(dest); | |
1058 | if (ptr[i]) { | |
1059 | dev_err(dev, "Self-test memset failed compare\n"); | |
1060 | err = -ENODEV; | |
1061 | goto free_resources; | |
1062 | } | |
1063 | } | |
1064 | ||
1065 | /* test for non-zero parity sum */ | |
1066 | xor_val_result = 0; | |
1067 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1068 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1069 | DMA_TO_DEVICE); | |
1070 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1071 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
1072 | &xor_val_result, DMA_PREP_INTERRUPT); | |
1073 | if (!tx) { | |
1074 | dev_err(dev, "Self-test 2nd zero prep failed\n"); | |
1075 | err = -ENODEV; | |
1076 | goto free_resources; | |
1077 | } | |
1078 | ||
1079 | async_tx_ack(tx); | |
1080 | init_completion(&cmp); | |
1081 | tx->callback = ioat3_dma_test_callback; | |
1082 | tx->callback_param = &cmp; | |
1083 | cookie = tx->tx_submit(tx); | |
1084 | if (cookie < 0) { | |
1085 | dev_err(dev, "Self-test 2nd zero setup failed\n"); | |
1086 | err = -ENODEV; | |
1087 | goto free_resources; | |
1088 | } | |
1089 | dma->device_issue_pending(dma_chan); | |
1090 | ||
1091 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1092 | ||
1093 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1094 | dev_err(dev, "Self-test 2nd validate timed out\n"); | |
1095 | err = -ENODEV; | |
1096 | goto free_resources; | |
1097 | } | |
1098 | ||
1099 | if (xor_val_result != SUM_CHECK_P_RESULT) { | |
1100 | dev_err(dev, "Self-test validate failed compare\n"); | |
1101 | err = -ENODEV; | |
1102 | goto free_resources; | |
1103 | } | |
1104 | ||
1105 | free_resources: | |
1106 | dma->device_free_chan_resources(dma_chan); | |
1107 | out: | |
1108 | src_idx = IOAT_NUM_SRC_TEST; | |
1109 | while (src_idx--) | |
1110 | __free_page(xor_srcs[src_idx]); | |
1111 | __free_page(dest); | |
1112 | return err; | |
1113 | } | |
1114 | ||
1115 | static int __devinit ioat3_dma_self_test(struct ioatdma_device *device) | |
1116 | { | |
1117 | int rc = ioat_dma_self_test(device); | |
1118 | ||
1119 | if (rc) | |
1120 | return rc; | |
1121 | ||
1122 | rc = ioat_xor_val_self_test(device); | |
1123 | if (rc) | |
1124 | return rc; | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
bf40a686 DW |
1129 | int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) |
1130 | { | |
1131 | struct pci_dev *pdev = device->pdev; | |
228c4f5c | 1132 | int dca_en = system_has_dca_enabled(pdev); |
bf40a686 DW |
1133 | struct dma_device *dma; |
1134 | struct dma_chan *c; | |
1135 | struct ioat_chan_common *chan; | |
e3232714 | 1136 | bool is_raid_device = false; |
bf40a686 DW |
1137 | int err; |
1138 | u16 dev_id; | |
1139 | u32 cap; | |
1140 | ||
1141 | device->enumerate_channels = ioat2_enumerate_channels; | |
9de6fc71 | 1142 | device->self_test = ioat3_dma_self_test; |
bf40a686 DW |
1143 | dma = &device->common; |
1144 | dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; | |
1145 | dma->device_issue_pending = ioat2_issue_pending; | |
1146 | dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; | |
1147 | dma->device_free_chan_resources = ioat2_free_chan_resources; | |
58c8649e DW |
1148 | |
1149 | dma_cap_set(DMA_INTERRUPT, dma->cap_mask); | |
1150 | dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; | |
1151 | ||
bf40a686 | 1152 | cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); |
228c4f5c DW |
1153 | |
1154 | /* dca is incompatible with raid operations */ | |
1155 | if (dca_en && (cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) | |
1156 | cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); | |
1157 | ||
b094ad3b | 1158 | if (cap & IOAT_CAP_XOR) { |
e3232714 | 1159 | is_raid_device = true; |
b094ad3b DW |
1160 | dma->max_xor = 8; |
1161 | dma->xor_align = 2; | |
1162 | ||
1163 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1164 | dma->device_prep_dma_xor = ioat3_prep_xor; | |
1165 | ||
1166 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1167 | dma->device_prep_dma_xor_val = ioat3_prep_xor_val; | |
1168 | } | |
d69d235b | 1169 | if (cap & IOAT_CAP_PQ) { |
e3232714 | 1170 | is_raid_device = true; |
d69d235b DW |
1171 | dma_set_maxpq(dma, 8, 0); |
1172 | dma->pq_align = 2; | |
1173 | ||
1174 | dma_cap_set(DMA_PQ, dma->cap_mask); | |
1175 | dma->device_prep_dma_pq = ioat3_prep_pq; | |
1176 | ||
1177 | dma_cap_set(DMA_PQ_VAL, dma->cap_mask); | |
1178 | dma->device_prep_dma_pq_val = ioat3_prep_pq_val; | |
ae786624 DW |
1179 | |
1180 | if (!(cap & IOAT_CAP_XOR)) { | |
1181 | dma->max_xor = 8; | |
1182 | dma->xor_align = 2; | |
1183 | ||
1184 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1185 | dma->device_prep_dma_xor = ioat3_prep_pqxor; | |
1186 | ||
1187 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1188 | dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; | |
1189 | } | |
d69d235b | 1190 | } |
e3232714 DW |
1191 | if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) { |
1192 | dma_cap_set(DMA_MEMSET, dma->cap_mask); | |
1193 | dma->device_prep_dma_memset = ioat3_prep_memset_lock; | |
1194 | } | |
1195 | ||
1196 | ||
1197 | if (is_raid_device) { | |
1198 | dma->device_is_tx_complete = ioat3_is_complete; | |
1199 | device->cleanup_tasklet = ioat3_cleanup_tasklet; | |
1200 | device->timer_fn = ioat3_timer_event; | |
1201 | } else { | |
1202 | dma->device_is_tx_complete = ioat2_is_complete; | |
1203 | device->cleanup_tasklet = ioat2_cleanup_tasklet; | |
1204 | device->timer_fn = ioat2_timer_event; | |
1205 | } | |
bf40a686 DW |
1206 | |
1207 | /* -= IOAT ver.3 workarounds =- */ | |
1208 | /* Write CHANERRMSK_INT with 3E07h to mask out the errors | |
1209 | * that can cause stability issues for IOAT ver.3 | |
1210 | */ | |
1211 | pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07); | |
1212 | ||
1213 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit | |
1214 | * (workaround for spurious config parity error after restart) | |
1215 | */ | |
1216 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
1217 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) | |
1218 | pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); | |
1219 | ||
1220 | err = ioat_probe(device); | |
1221 | if (err) | |
1222 | return err; | |
1223 | ioat_set_tcp_copy_break(262144); | |
1224 | ||
1225 | list_for_each_entry(c, &dma->channels, device_node) { | |
1226 | chan = to_chan_common(c); | |
1227 | writel(IOAT_DMA_DCA_ANY_CPU, | |
1228 | chan->reg_base + IOAT_DCACTRL_OFFSET); | |
1229 | } | |
1230 | ||
1231 | err = ioat_register(device); | |
1232 | if (err) | |
1233 | return err; | |
5669e31c DW |
1234 | |
1235 | ioat_kobject_add(device, &ioat2_ktype); | |
1236 | ||
bf40a686 DW |
1237 | if (dca) |
1238 | device->dca = ioat3_dca_init(pdev, device->reg_base); | |
1239 | ||
1240 | return 0; | |
1241 | } |