[net-next-2.6.git] / drivers / dma / ioat / dma.h

/*
 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
#ifndef IOATDMA_H
#define IOATDMA_H

#include <linux/dmaengine.h>
#include "hw.h"
#include "registers.h"
#include <linux/init.h>
#include <linux/dmapool.h>
#include <linux/cache.h>
#include <linux/pci_ids.h>
#include <net/tcp.h>

#define IOAT_DMA_VERSION  "4.00"

#define IOAT_LOW_COMPLETION_MASK	0xffffffc0
#define IOAT_DMA_DCA_ANY_CPU		~0

#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)

#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)

/*
 * workaround for IOAT ver.3.0 null descriptor issue
 * (channel returns error when size is 0)
 */
#define NULL_DESC_BUFFER_SIZE 1

/**
 * struct ioatdma_device - internal representation of a IOAT device
 * @pdev: PCI-Express device
 * @reg_base: MMIO register space base address
 * @dma_pool: for allocating DMA descriptors
 * @common: embedded struct dma_device
 * @version: version of ioatdma device
 * @msix_entries: irq handlers
 * @idx: per channel data
 * @dca: direct cache access context
 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
 * @enumerate_channels: hw version specific channel enumeration
 * @reset_hw: hw version specific channel (re)initialization
 * @cleanup_fn: select between the v2 and v3 cleanup routines
 * @timer_fn: select between the v2 and v3 timer watchdog routines
 * @self_test: hardware version specific self test for each supported op type
 *
 * Note: the v3 cleanup routine supports raid operations
 */
struct ioatdma_device {
	struct pci_dev *pdev;
	void __iomem *reg_base;
	struct pci_pool *dma_pool;
	struct pci_pool *completion_pool;
	struct dma_device common;
	u8 version;
	struct msix_entry msix_entries[4];
	struct ioat_chan_common *idx[4];
	struct dca_provider *dca;
	void (*intr_quirk)(struct ioatdma_device *device);
	int (*enumerate_channels)(struct ioatdma_device *device);
	int (*reset_hw)(struct ioat_chan_common *chan);
	void (*cleanup_fn)(unsigned long data);
	void (*timer_fn)(unsigned long data);
	int (*self_test)(struct ioatdma_device *device);
};

struct ioat_chan_common {
	struct dma_chan common;
	void __iomem *reg_base;
	unsigned long last_completion;
	spinlock_t cleanup_lock;
	dma_cookie_t completed_cookie;
	unsigned long state;
	#define IOAT_COMPLETION_PENDING 0
	#define IOAT_COMPLETION_ACK 1
	#define IOAT_RESET_PENDING 2
	#define IOAT_KOBJ_INIT_FAIL 3
	struct timer_list timer;
	#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
	#define IDLE_TIMEOUT msecs_to_jiffies(2000)
	#define RESET_DELAY msecs_to_jiffies(100)
	struct ioatdma_device *device;
	dma_addr_t completion_dma;
	u64 *completion;
	struct tasklet_struct cleanup_task;
	struct kobject kobj;
};

struct ioat_sysfs_entry {
	struct attribute attr;
	ssize_t (*show)(struct dma_chan *, char *);
};

/**
 * struct ioat_dma_chan - internal representation of a DMA channel
 */
struct ioat_dma_chan {
	struct ioat_chan_common base;

	size_t xfercap;	/* XFERCAP register value expanded out */

	spinlock_t desc_lock;
	struct list_head free_desc;
	struct list_head used_desc;

	int pending;
	u16 desccount;
	u16 active;
};

static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
{
	return container_of(c, struct ioat_chan_common, common);
}

static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
{
	struct ioat_chan_common *chan = to_chan_common(c);

	return container_of(chan, struct ioat_dma_chan, base);
}

/**
 * ioat_tx_status - poll the status of an ioat transaction
 * @c: channel handle
 * @cookie: transaction identifier
 * @txstate: if set, updated with the transaction state
 */
static inline enum dma_status
ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
		 struct dma_tx_state *txstate)
{
	struct ioat_chan_common *chan = to_chan_common(c);
	dma_cookie_t last_used;
	dma_cookie_t last_complete;

	last_used = c->cookie;
	last_complete = chan->completed_cookie;

	dma_set_tx_state(txstate, last_complete, last_used, 0);

	return dma_async_is_complete(cookie, last_complete, last_used);
}

/* wrapper around hardware descriptor format + additional software fields */

/**
 * struct ioat_desc_sw - wrapper around hardware descriptor
 * @hw: hardware DMA descriptor (for memcpy)
 * @node: this descriptor will either be on the free list,
 *     or attached to a transaction list (tx_list)
 * @txd: the generic software descriptor for all engines
 * @id: identifier for debug
 */
struct ioat_desc_sw {
	struct ioat_dma_descriptor *hw;
	struct list_head node;
	size_t len;
	struct list_head tx_list;
	struct dma_async_tx_descriptor txd;
	#ifdef DEBUG
	int id;
	#endif
};

#ifdef DEBUG
#define set_desc_id(desc, i) ((desc)->id = (i))
#define desc_id(desc) ((desc)->id)
#else
#define set_desc_id(desc, i)
#define desc_id(desc) (0)
#endif

static inline void
__dump_desc_dbg(struct ioat_chan_common *chan, struct ioat_dma_descriptor *hw,
		struct dma_async_tx_descriptor *tx, int id)
{
	struct device *dev = to_dev(chan);

	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
		" ctl: %#x (op: %d int_en: %d compl: %d)\n", id,
		(unsigned long long) tx->phys,
		(unsigned long long) hw->next, tx->cookie, tx->flags,
		hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
}

#define dump_desc_dbg(c, d) \
	({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })

static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
{
	#ifdef CONFIG_NET_DMA
	sysctl_tcp_dma_copybreak = copybreak;
	#endif
}

static inline struct ioat_chan_common *
ioat_chan_by_index(struct ioatdma_device *device, int index)
{
	return device->idx[index];
}

static inline u64 ioat_chansts(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u64 status;
	u32 status_lo;

	/* We need to read the low address first as this causes the
	 * chipset to latch the upper bits for the subsequent read
	 */
	status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
	status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
	status <<= 32;
	status |= status_lo;

	return status;
}

static inline void ioat_start(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline u64 ioat_chansts_to_addr(u64 status)
{
	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
}

static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
{
	return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
}

static inline void ioat_suspend(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline void ioat_reset(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;

	writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
}

static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
{
	u8 ver = chan->device->version;
	u8 cmd;

	cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
}

static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
{
	struct ioat_chan_common *chan = &ioat->base;

	writel(addr & 0x00000000FFFFFFFF,
	       chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
	writel(addr >> 32,
	       chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
}

static inline bool is_ioat_active(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
}

static inline bool is_ioat_idle(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
}

static inline bool is_ioat_halted(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
}

static inline bool is_ioat_suspended(unsigned long status)
{
	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
}

/* channel was fatally programmed */
static inline bool is_ioat_bug(unsigned long err)
{
	return !!err;
}

static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
			      int direction, enum dma_ctrl_flags flags, bool dst)
{
	if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) ||
	    (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
		pci_unmap_single(pdev, addr, len, direction);
	else
		pci_unmap_page(pdev, addr, len, direction);
}

int __devinit ioat_probe(struct ioatdma_device *device);
int __devinit ioat_register(struct ioatdma_device *device);
int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca);
int __devinit ioat_dma_self_test(struct ioatdma_device *device);
void __devexit ioat_dma_remove(struct ioatdma_device *device);
struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev,
					      void __iomem *iobase);
unsigned long ioat_get_current_completion(struct ioat_chan_common *chan);
void ioat_init_channel(struct ioatdma_device *device,
		       struct ioat_chan_common *chan, int idx);
enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
				   struct dma_tx_state *txstate);
void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
		    size_t len, struct ioat_dma_descriptor *hw);
bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
			   unsigned long *phys_complete);
void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type);
void ioat_kobject_del(struct ioatdma_device *device);
extern const struct sysfs_ops ioat_sysfs_ops;
extern struct ioat_sysfs_entry ioat_version_attr;
extern struct ioat_sysfs_entry ioat_cap_attr;
#endif /* IOATDMA_H */
Commit	Line	Data
0bbd5f4e	1	/*
211a22ce	2	* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
0bbd5f4e CL	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59
	16	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called COPYING.
	20	*/
	21	#ifndef IOATDMA_H
	22	#define IOATDMA_H
	23
	24	#include <linux/dmaengine.h>
584ec227	25	#include "hw.h"
09c8a5b8	26	#include "registers.h"
0bbd5f4e CL	27	#include <linux/init.h>
	28	#include <linux/dmapool.h>
	29	#include <linux/cache.h>
57c651f7	30	#include <linux/pci_ids.h>
16a37aca	31	#include <net/tcp.h>
0bbd5f4e	32
3208ca52	33	#define IOAT_DMA_VERSION "4.00"
5149fd01	34
0bbd5f4e	35	#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
7bb67c14 SN	36	#define IOAT_DMA_DCA_ANY_CPU ~0
7bb67c14 SN	37
1f27adc2 DW	38	#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
1f27adc2 DW	39	#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
bc3c7025 DW	40	#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
bc3c7025 DW	41	#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
1f27adc2 DW	42
	43	#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
	44
1f27adc2 DW	45	/*
	46	* workaround for IOAT ver.3.0 null descriptor issue
	47	* (channel returns error when size is 0)
	48	*/
	49	#define NULL_DESC_BUFFER_SIZE 1
	50
0bbd5f4e	51	/**
8ab89567	52	* struct ioatdma_device - internal representation of a IOAT device
0bbd5f4e CL	53	* @pdev: PCI-Express device
	54	* @reg_base: MMIO register space base address
	55	* @dma_pool: for allocating DMA descriptors
	56	* @common: embedded struct dma_device
8ab89567	57	* @version: version of ioatdma device
7bb67c14 SN	58	* @msix_entries: irq handlers
7bb67c14 SN	59	* @idx: per channel data
f2427e27 DW	60	* @dca: direct cache access context
f2427e27 DW	61	* @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
5cbafa65	62	* @enumerate_channels: hw version specific channel enumeration
a6d52d70	63	* @reset_hw: hw version specific channel (re)initialization
aa4d72ae	64	* @cleanup_fn: select between the v2 and v3 cleanup routines
bf40a686	65	* @timer_fn: select between the v2 and v3 timer watchdog routines
9de6fc71	66	* @self_test: hardware version specific self test for each supported op type
bf40a686 DW	67	*
bf40a686 DW	68	* Note: the v3 cleanup routine supports raid operations
0bbd5f4e	69	*/
8ab89567	70	struct ioatdma_device {
0bbd5f4e	71	struct pci_dev *pdev;
47b16539	72	void __iomem *reg_base;
0bbd5f4e CL	73	struct pci_pool *dma_pool;
0bbd5f4e CL	74	struct pci_pool *completion_pool;
0bbd5f4e	75	struct dma_device common;
8ab89567	76	u8 version;
3e037454	77	struct msix_entry msix_entries[4];
dcbc853a	78	struct ioat_chan_common *idx[4];
f2427e27 DW	79	struct dca_provider *dca;
f2427e27 DW	80	void (intr_quirk)(struct ioatdma_device device);
5cbafa65	81	int (enumerate_channels)(struct ioatdma_device device);
a6d52d70	82	int (reset_hw)(struct ioat_chan_common chan);
aa4d72ae	83	void (*cleanup_fn)(unsigned long data);
bf40a686	84	void (*timer_fn)(unsigned long data);
9de6fc71	85	int (self_test)(struct ioatdma_device device);
0bbd5f4e CL	86	};
0bbd5f4e CL	87
dcbc853a	88	struct ioat_chan_common {
09c8a5b8	89	struct dma_chan common;
47b16539	90	void __iomem *reg_base;
0bbd5f4e	91	unsigned long last_completion;
0bbd5f4e	92	spinlock_t cleanup_lock;
dcbc853a	93	dma_cookie_t completed_cookie;
09c8a5b8 DW	94	unsigned long state;
	95	#define IOAT_COMPLETION_PENDING 0
	96	#define IOAT_COMPLETION_ACK 1
	97	#define IOAT_RESET_PENDING 2
5669e31c	98	#define IOAT_KOBJ_INIT_FAIL 3
09c8a5b8 DW	99	struct timer_list timer;
09c8a5b8 DW	100	#define COMPLETION_TIMEOUT msecs_to_jiffies(100)
a309218a	101	#define IDLE_TIMEOUT msecs_to_jiffies(2000)
09c8a5b8	102	#define RESET_DELAY msecs_to_jiffies(100)
8ab89567	103	struct ioatdma_device *device;
4fb9b9e8 DW	104	dma_addr_t completion_dma;
4fb9b9e8 DW	105	u64 *completion;
3e037454	106	struct tasklet_struct cleanup_task;
5669e31c	107	struct kobject kobj;
0bbd5f4e CL	108	};
0bbd5f4e CL	109
5669e31c DW	110	struct ioat_sysfs_entry {
	111	struct attribute attr;
	112	ssize_t (show)(struct dma_chan , char *);
	113	};
5cbafa65	114
dcbc853a DW	115	/**
	116	* struct ioat_dma_chan - internal representation of a DMA channel
	117	*/
	118	struct ioat_dma_chan {
	119	struct ioat_chan_common base;
	120
	121	size_t xfercap; /* XFERCAP register value expanded out */
	122
	123	spinlock_t desc_lock;
	124	struct list_head free_desc;
	125	struct list_head used_desc;
	126
	127	int pending;
dcbc853a	128	u16 desccount;
5669e31c	129	u16 active;
dcbc853a DW	130	};
	131
	132	static inline struct ioat_chan_common to_chan_common(struct dma_chan c)
	133	{
	134	return container_of(c, struct ioat_chan_common, common);
	135	}
	136
	137	static inline struct ioat_dma_chan to_ioat_chan(struct dma_chan c)
	138	{
	139	struct ioat_chan_common *chan = to_chan_common(c);
	140
	141	return container_of(chan, struct ioat_dma_chan, base);
	142	}
	143
5cbafa65	144	/**
07934481	145	* ioat_tx_status - poll the status of an ioat transaction
5cbafa65 DW	146	* @c: channel handle
5cbafa65 DW	147	* @cookie: transaction identifier
07934481	148	* @txstate: if set, updated with the transaction state
5cbafa65 DW	149	*/
5cbafa65 DW	150	static inline enum dma_status
07934481 LW	151	ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
07934481 LW	152	struct dma_tx_state *txstate)
5cbafa65 DW	153	{
	154	struct ioat_chan_common *chan = to_chan_common(c);
	155	dma_cookie_t last_used;
	156	dma_cookie_t last_complete;
	157
	158	last_used = c->cookie;
	159	last_complete = chan->completed_cookie;
5cbafa65	160
bca34692	161	dma_set_tx_state(txstate, last_complete, last_used, 0);
5cbafa65 DW	162
	163	return dma_async_is_complete(cookie, last_complete, last_used);
	164	}
	165
0bbd5f4e CL	166	/* wrapper around hardware descriptor format + additional software fields */
	167
	168	/**
	169	* struct ioat_desc_sw - wrapper around hardware descriptor
2aec048c	170	* @hw: hardware DMA descriptor (for memcpy)
7405f74b	171	* @node: this descriptor will either be on the free list,
ea25968a	172	* or attached to a transaction list (tx_list)
bc3c7025	173	* @txd: the generic software descriptor for all engines
6df9183a	174	* @id: identifier for debug
0bbd5f4e	175	*/
0bbd5f4e CL	176	struct ioat_desc_sw {
	177	struct ioat_dma_descriptor *hw;
	178	struct list_head node;
7f2b291f	179	size_t len;
ea25968a	180	struct list_head tx_list;
bc3c7025	181	struct dma_async_tx_descriptor txd;
6df9183a DW	182	#ifdef DEBUG
	183	int id;
	184	#endif
0bbd5f4e CL	185	};
0bbd5f4e CL	186
6df9183a DW	187	#ifdef DEBUG
	188	#define set_desc_id(desc, i) ((desc)->id = (i))
	189	#define desc_id(desc) ((desc)->id)
	190	#else
	191	#define set_desc_id(desc, i)
	192	#define desc_id(desc) (0)
	193	#endif
	194
	195	static inline void
	196	__dump_desc_dbg(struct ioat_chan_common chan, struct ioat_dma_descriptor hw,
	197	struct dma_async_tx_descriptor *tx, int id)
	198	{
	199	struct device *dev = to_dev(chan);
	200
	201	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
	202	" ctl: %#x (op: %d int_en: %d compl: %d)\n", id,
	203	(unsigned long long) tx->phys,
	204	(unsigned long long) hw->next, tx->cookie, tx->flags,
	205	hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
	206	}
	207
	208	#define dump_desc_dbg(c, d) \
	209	({ if (d) __dump_desc_dbg(&c->base, d->hw, &d->txd, desc_id(d)); 0; })
	210
f2427e27	211	static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
16a37aca MS	212	{
16a37aca MS	213	#ifdef CONFIG_NET_DMA
f2427e27	214	sysctl_tcp_dma_copybreak = copybreak;
16a37aca MS	215	#endif
	216	}
	217
5cbafa65 DW	218	static inline struct ioat_chan_common *
	219	ioat_chan_by_index(struct ioatdma_device *device, int index)
	220	{
	221	return device->idx[index];
	222	}
	223
09c8a5b8 DW	224	static inline u64 ioat_chansts(struct ioat_chan_common *chan)
	225	{
	226	u8 ver = chan->device->version;
	227	u64 status;
	228	u32 status_lo;
	229
	230	/* We need to read the low address first as this causes the
	231	* chipset to latch the upper bits for the subsequent read
	232	*/
	233	status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
	234	status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
	235	status <<= 32;
	236	status \|= status_lo;
	237
	238	return status;
	239	}
	240
	241	static inline void ioat_start(struct ioat_chan_common *chan)
	242	{
	243	u8 ver = chan->device->version;
	244
	245	writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	246	}
	247
	248	static inline u64 ioat_chansts_to_addr(u64 status)
	249	{
	250	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
	251	}
	252
	253	static inline u32 ioat_chanerr(struct ioat_chan_common *chan)
	254	{
	255	return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
	256	}
	257
	258	static inline void ioat_suspend(struct ioat_chan_common *chan)
	259	{
	260	u8 ver = chan->device->version;
	261
	262	writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	263	}
	264
a6d52d70 DW	265	static inline void ioat_reset(struct ioat_chan_common *chan)
	266	{
	267	u8 ver = chan->device->version;
	268
	269	writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	270	}
	271
	272	static inline bool ioat_reset_pending(struct ioat_chan_common *chan)
	273	{
	274	u8 ver = chan->device->version;
	275	u8 cmd;
	276
	277	cmd = readb(chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
	278	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
	279	}
	280
09c8a5b8 DW	281	static inline void ioat_set_chainaddr(struct ioat_dma_chan *ioat, u64 addr)
	282	{
	283	struct ioat_chan_common *chan = &ioat->base;
	284
	285	writel(addr & 0x00000000FFFFFFFF,
	286	chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
	287	writel(addr >> 32,
	288	chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
	289	}
	290
	291	static inline bool is_ioat_active(unsigned long status)
	292	{
	293	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
	294	}
	295
	296	static inline bool is_ioat_idle(unsigned long status)
	297	{
	298	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
	299	}
	300
	301	static inline bool is_ioat_halted(unsigned long status)
	302	{
	303	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
	304	}
	305
	306	static inline bool is_ioat_suspended(unsigned long status)
	307	{
	308	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
	309	}
	310
	311	/* channel was fatally programmed */
	312	static inline bool is_ioat_bug(unsigned long err)
	313	{
b57014de	314	return !!err;
09c8a5b8 DW	315	}
09c8a5b8 DW	316
bf40a686 DW	317	static inline void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
	318	int direction, enum dma_ctrl_flags flags, bool dst)
	319	{
	320	if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) \|\|
	321	(!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE)))
	322	pci_unmap_single(pdev, addr, len, direction);
	323	else
	324	pci_unmap_page(pdev, addr, len, direction);
	325	}
	326
345d8523 DW	327	int __devinit ioat_probe(struct ioatdma_device *device);
	328	int __devinit ioat_register(struct ioatdma_device *device);
	329	int __devinit ioat1_dma_probe(struct ioatdma_device *dev, int dca);
9de6fc71	330	int __devinit ioat_dma_self_test(struct ioatdma_device *device);
345d8523 DW	331	void __devexit ioat_dma_remove(struct ioatdma_device *device);
	332	struct dca_provider * __devinit ioat_dca_init(struct pci_dev *pdev,
	333	void __iomem *iobase);
5cbafa65 DW	334	unsigned long ioat_get_current_completion(struct ioat_chan_common *chan);
5cbafa65 DW	335	void ioat_init_channel(struct ioatdma_device *device,
aa4d72ae	336	struct ioat_chan_common *chan, int idx);
07934481 LW	337	enum dma_status ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
07934481 LW	338	struct dma_tx_state *txstate);
5cbafa65 DW	339	void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
5cbafa65 DW	340	size_t len, struct ioat_dma_descriptor *hw);
09c8a5b8 DW	341	bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
09c8a5b8 DW	342	unsigned long *phys_complete);
5669e31c DW	343	void ioat_kobject_add(struct ioatdma_device device, struct kobj_type type);
5669e31c DW	344	void ioat_kobject_del(struct ioatdma_device *device);
52cf25d0	345	extern const struct sysfs_ops ioat_sysfs_ops;
5669e31c DW	346	extern struct ioat_sysfs_entry ioat_version_attr;
5669e31c DW	347	extern struct ioat_sysfs_entry ioat_cap_attr;
0bbd5f4e	348	#endif /* IOATDMA_H */