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0bbd5f4e | 1 | /* |
43d6e369 | 2 | * Intel I/OAT DMA Linux driver |
211a22ce | 3 | * Copyright(c) 2004 - 2009 Intel Corporation. |
0bbd5f4e CL |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
43d6e369 SN |
6 | * under the terms and conditions of the GNU General Public License, |
7 | * version 2, as published by the Free Software Foundation. | |
0bbd5f4e CL |
8 | * |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
43d6e369 SN |
15 | * this program; if not, write to the Free Software Foundation, Inc., |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
0bbd5f4e | 20 | * |
0bbd5f4e CL |
21 | */ |
22 | ||
23 | /* | |
24 | * This driver supports an Intel I/OAT DMA engine, which does asynchronous | |
25 | * copy operations. | |
26 | */ | |
27 | ||
28 | #include <linux/init.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
6b00c92c | 34 | #include <linux/dma-mapping.h> |
09177e85 | 35 | #include <linux/workqueue.h> |
3ad0b02e | 36 | #include <linux/i7300_idle.h> |
584ec227 DW |
37 | #include "dma.h" |
38 | #include "registers.h" | |
39 | #include "hw.h" | |
0bbd5f4e | 40 | |
5cbafa65 | 41 | int ioat_pending_level = 4; |
7bb67c14 SN |
42 | module_param(ioat_pending_level, int, 0644); |
43 | MODULE_PARM_DESC(ioat_pending_level, | |
44 | "high-water mark for pushing ioat descriptors (default: 4)"); | |
45 | ||
0bbd5f4e | 46 | /* internal functions */ |
5cbafa65 DW |
47 | static void ioat1_cleanup(struct ioat_dma_chan *ioat); |
48 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat); | |
3e037454 SN |
49 | |
50 | /** | |
51 | * ioat_dma_do_interrupt - handler used for single vector interrupt mode | |
52 | * @irq: interrupt id | |
53 | * @data: interrupt data | |
54 | */ | |
55 | static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) | |
56 | { | |
57 | struct ioatdma_device *instance = data; | |
dcbc853a | 58 | struct ioat_chan_common *chan; |
3e037454 SN |
59 | unsigned long attnstatus; |
60 | int bit; | |
61 | u8 intrctrl; | |
62 | ||
63 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
64 | ||
65 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) | |
66 | return IRQ_NONE; | |
67 | ||
68 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { | |
69 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
70 | return IRQ_NONE; | |
71 | } | |
72 | ||
73 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); | |
74 | for_each_bit(bit, &attnstatus, BITS_PER_LONG) { | |
dcbc853a DW |
75 | chan = ioat_chan_by_index(instance, bit); |
76 | tasklet_schedule(&chan->cleanup_task); | |
3e037454 SN |
77 | } |
78 | ||
79 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
80 | return IRQ_HANDLED; | |
81 | } | |
82 | ||
83 | /** | |
84 | * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode | |
85 | * @irq: interrupt id | |
86 | * @data: interrupt data | |
87 | */ | |
88 | static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) | |
89 | { | |
dcbc853a | 90 | struct ioat_chan_common *chan = data; |
3e037454 | 91 | |
dcbc853a | 92 | tasklet_schedule(&chan->cleanup_task); |
3e037454 SN |
93 | |
94 | return IRQ_HANDLED; | |
95 | } | |
96 | ||
5cbafa65 DW |
97 | static void ioat1_cleanup_tasklet(unsigned long data); |
98 | ||
99 | /* common channel initialization */ | |
100 | void ioat_init_channel(struct ioatdma_device *device, | |
101 | struct ioat_chan_common *chan, int idx, | |
102 | work_func_t work_fn, void (*tasklet)(unsigned long), | |
103 | unsigned long tasklet_data) | |
104 | { | |
105 | struct dma_device *dma = &device->common; | |
106 | ||
107 | chan->device = device; | |
108 | chan->reg_base = device->reg_base + (0x80 * (idx + 1)); | |
109 | INIT_DELAYED_WORK(&chan->work, work_fn); | |
110 | spin_lock_init(&chan->cleanup_lock); | |
111 | chan->common.device = dma; | |
112 | list_add_tail(&chan->common.device_node, &dma->channels); | |
113 | device->idx[idx] = chan; | |
114 | tasklet_init(&chan->cleanup_task, tasklet, tasklet_data); | |
115 | tasklet_disable(&chan->cleanup_task); | |
116 | } | |
117 | ||
118 | static void ioat1_reset_part2(struct work_struct *work); | |
3e037454 SN |
119 | |
120 | /** | |
5cbafa65 | 121 | * ioat1_dma_enumerate_channels - find and initialize the device's channels |
3e037454 SN |
122 | * @device: the device to be enumerated |
123 | */ | |
5cbafa65 | 124 | static int ioat1_enumerate_channels(struct ioatdma_device *device) |
0bbd5f4e CL |
125 | { |
126 | u8 xfercap_scale; | |
127 | u32 xfercap; | |
128 | int i; | |
dcbc853a | 129 | struct ioat_dma_chan *ioat; |
e6c0b69a | 130 | struct device *dev = &device->pdev->dev; |
f2427e27 | 131 | struct dma_device *dma = &device->common; |
0bbd5f4e | 132 | |
f2427e27 DW |
133 | INIT_LIST_HEAD(&dma->channels); |
134 | dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); | |
e3828811 | 135 | xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); |
0bbd5f4e CL |
136 | xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); |
137 | ||
f371be63 | 138 | #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL |
f2427e27 DW |
139 | if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) |
140 | dma->chancnt--; | |
27471fdb | 141 | #endif |
f2427e27 | 142 | for (i = 0; i < dma->chancnt; i++) { |
dcbc853a | 143 | ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL); |
5cbafa65 | 144 | if (!ioat) |
0bbd5f4e | 145 | break; |
0bbd5f4e | 146 | |
5cbafa65 DW |
147 | ioat_init_channel(device, &ioat->base, i, |
148 | ioat1_reset_part2, | |
149 | ioat1_cleanup_tasklet, | |
150 | (unsigned long) ioat); | |
dcbc853a | 151 | ioat->xfercap = xfercap; |
dcbc853a DW |
152 | spin_lock_init(&ioat->desc_lock); |
153 | INIT_LIST_HEAD(&ioat->free_desc); | |
154 | INIT_LIST_HEAD(&ioat->used_desc); | |
0bbd5f4e | 155 | } |
5cbafa65 DW |
156 | dma->chancnt = i; |
157 | return i; | |
0bbd5f4e CL |
158 | } |
159 | ||
711924b1 SN |
160 | /** |
161 | * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended | |
162 | * descriptors to hw | |
163 | * @chan: DMA channel handle | |
164 | */ | |
bc3c7025 | 165 | static inline void |
dcbc853a | 166 | __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat) |
711924b1 | 167 | { |
dcbc853a DW |
168 | void __iomem *reg_base = ioat->base.reg_base; |
169 | ||
170 | ioat->pending = 0; | |
171 | writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET); | |
711924b1 SN |
172 | } |
173 | ||
174 | static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) | |
175 | { | |
dcbc853a | 176 | struct ioat_dma_chan *ioat = to_ioat_chan(chan); |
711924b1 | 177 | |
dcbc853a DW |
178 | if (ioat->pending > 0) { |
179 | spin_lock_bh(&ioat->desc_lock); | |
180 | __ioat1_dma_memcpy_issue_pending(ioat); | |
181 | spin_unlock_bh(&ioat->desc_lock); | |
711924b1 SN |
182 | } |
183 | } | |
184 | ||
09177e85 | 185 | /** |
5cbafa65 | 186 | * ioat1_reset_part2 - reinit the channel after a reset |
09177e85 | 187 | */ |
5cbafa65 | 188 | static void ioat1_reset_part2(struct work_struct *work) |
09177e85 | 189 | { |
dcbc853a DW |
190 | struct ioat_chan_common *chan; |
191 | struct ioat_dma_chan *ioat; | |
09177e85 | 192 | struct ioat_desc_sw *desc; |
5cbafa65 DW |
193 | int dmacount; |
194 | bool start_null = false; | |
09177e85 | 195 | |
dcbc853a DW |
196 | chan = container_of(work, struct ioat_chan_common, work.work); |
197 | ioat = container_of(chan, struct ioat_dma_chan, base); | |
198 | spin_lock_bh(&chan->cleanup_lock); | |
199 | spin_lock_bh(&ioat->desc_lock); | |
09177e85 | 200 | |
dcbc853a DW |
201 | chan->completion_virt->low = 0; |
202 | chan->completion_virt->high = 0; | |
203 | ioat->pending = 0; | |
09177e85 | 204 | |
5cbafa65 DW |
205 | /* count the descriptors waiting */ |
206 | dmacount = 0; | |
dcbc853a DW |
207 | if (ioat->used_desc.prev) { |
208 | desc = to_ioat_desc(ioat->used_desc.prev); | |
09177e85 | 209 | do { |
5cbafa65 | 210 | dmacount++; |
09177e85 | 211 | desc = to_ioat_desc(desc->node.next); |
dcbc853a | 212 | } while (&desc->node != ioat->used_desc.next); |
09177e85 MS |
213 | } |
214 | ||
5cbafa65 DW |
215 | if (dmacount) { |
216 | /* | |
217 | * write the new starting descriptor address | |
218 | * this puts channel engine into ARMED state | |
219 | */ | |
220 | desc = to_ioat_desc(ioat->used_desc.prev); | |
bc3c7025 | 221 | writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, |
dcbc853a | 222 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); |
bc3c7025 | 223 | writel(((u64) desc->txd.phys) >> 32, |
dcbc853a | 224 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); |
09177e85 | 225 | |
dcbc853a DW |
226 | writeb(IOAT_CHANCMD_START, chan->reg_base |
227 | + IOAT_CHANCMD_OFFSET(chan->device->version)); | |
5cbafa65 DW |
228 | } else |
229 | start_null = true; | |
230 | spin_unlock_bh(&ioat->desc_lock); | |
231 | spin_unlock_bh(&chan->cleanup_lock); | |
09177e85 | 232 | |
dcbc853a | 233 | dev_err(to_dev(chan), |
09177e85 | 234 | "chan%d reset - %d descs waiting, %d total desc\n", |
5cbafa65 | 235 | chan_num(chan), dmacount, ioat->desccount); |
09177e85 | 236 | |
5cbafa65 DW |
237 | if (start_null) |
238 | ioat1_dma_start_null_desc(ioat); | |
09177e85 MS |
239 | } |
240 | ||
241 | /** | |
5cbafa65 | 242 | * ioat1_reset_channel - restart a channel |
dcbc853a | 243 | * @ioat: IOAT DMA channel handle |
09177e85 | 244 | */ |
5cbafa65 | 245 | static void ioat1_reset_channel(struct ioat_dma_chan *ioat) |
09177e85 | 246 | { |
dcbc853a DW |
247 | struct ioat_chan_common *chan = &ioat->base; |
248 | void __iomem *reg_base = chan->reg_base; | |
09177e85 MS |
249 | u32 chansts, chanerr; |
250 | ||
dcbc853a | 251 | if (!ioat->used_desc.prev) |
09177e85 MS |
252 | return; |
253 | ||
dcbc853a DW |
254 | chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); |
255 | chansts = (chan->completion_virt->low | |
09177e85 MS |
256 | & IOAT_CHANSTS_DMA_TRANSFER_STATUS); |
257 | if (chanerr) { | |
dcbc853a | 258 | dev_err(to_dev(chan), |
09177e85 | 259 | "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", |
dcbc853a DW |
260 | chan_num(chan), chansts, chanerr); |
261 | writel(chanerr, reg_base + IOAT_CHANERR_OFFSET); | |
09177e85 MS |
262 | } |
263 | ||
264 | /* | |
265 | * whack it upside the head with a reset | |
266 | * and wait for things to settle out. | |
267 | * force the pending count to a really big negative | |
268 | * to make sure no one forces an issue_pending | |
269 | * while we're waiting. | |
270 | */ | |
271 | ||
dcbc853a DW |
272 | spin_lock_bh(&ioat->desc_lock); |
273 | ioat->pending = INT_MIN; | |
09177e85 | 274 | writeb(IOAT_CHANCMD_RESET, |
dcbc853a DW |
275 | reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
276 | spin_unlock_bh(&ioat->desc_lock); | |
09177e85 MS |
277 | |
278 | /* schedule the 2nd half instead of sleeping a long time */ | |
dcbc853a | 279 | schedule_delayed_work(&chan->work, RESET_DELAY); |
09177e85 MS |
280 | } |
281 | ||
282 | /** | |
5cbafa65 | 283 | * ioat1_chan_watchdog - watch for stuck channels |
09177e85 | 284 | */ |
5cbafa65 | 285 | static void ioat1_chan_watchdog(struct work_struct *work) |
09177e85 MS |
286 | { |
287 | struct ioatdma_device *device = | |
288 | container_of(work, struct ioatdma_device, work.work); | |
dcbc853a DW |
289 | struct ioat_dma_chan *ioat; |
290 | struct ioat_chan_common *chan; | |
09177e85 MS |
291 | int i; |
292 | ||
293 | union { | |
294 | u64 full; | |
295 | struct { | |
296 | u32 low; | |
297 | u32 high; | |
298 | }; | |
299 | } completion_hw; | |
300 | unsigned long compl_desc_addr_hw; | |
301 | ||
302 | for (i = 0; i < device->common.chancnt; i++) { | |
dcbc853a DW |
303 | chan = ioat_chan_by_index(device, i); |
304 | ioat = container_of(chan, struct ioat_dma_chan, base); | |
09177e85 | 305 | |
5cbafa65 DW |
306 | if (/* have we started processing anything yet */ |
307 | chan->last_completion | |
308 | /* have we completed any since last watchdog cycle? */ | |
dcbc853a | 309 | && (chan->last_completion == chan->watchdog_completion) |
5cbafa65 | 310 | /* has TCP stuck on one cookie since last watchdog? */ |
dcbc853a DW |
311 | && (chan->watchdog_tcp_cookie == chan->watchdog_last_tcp_cookie) |
312 | && (chan->watchdog_tcp_cookie != chan->completed_cookie) | |
5cbafa65 DW |
313 | /* is there something in the chain to be processed? */ |
314 | /* CB1 chain always has at least the last one processed */ | |
dcbc853a DW |
315 | && (ioat->used_desc.prev != ioat->used_desc.next) |
316 | && ioat->pending == 0) { | |
09177e85 MS |
317 | |
318 | /* | |
319 | * check CHANSTS register for completed | |
320 | * descriptor address. | |
321 | * if it is different than completion writeback, | |
322 | * it is not zero | |
323 | * and it has changed since the last watchdog | |
324 | * we can assume that channel | |
325 | * is still working correctly | |
326 | * and the problem is in completion writeback. | |
327 | * update completion writeback | |
328 | * with actual CHANSTS value | |
329 | * else | |
330 | * try resetting the channel | |
331 | */ | |
332 | ||
dcbc853a DW |
333 | completion_hw.low = readl(chan->reg_base + |
334 | IOAT_CHANSTS_OFFSET_LOW(chan->device->version)); | |
335 | completion_hw.high = readl(chan->reg_base + | |
336 | IOAT_CHANSTS_OFFSET_HIGH(chan->device->version)); | |
09177e85 MS |
337 | #if (BITS_PER_LONG == 64) |
338 | compl_desc_addr_hw = | |
339 | completion_hw.full | |
340 | & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; | |
341 | #else | |
342 | compl_desc_addr_hw = | |
343 | completion_hw.low & IOAT_LOW_COMPLETION_MASK; | |
344 | #endif | |
345 | ||
346 | if ((compl_desc_addr_hw != 0) | |
dcbc853a DW |
347 | && (compl_desc_addr_hw != chan->watchdog_completion) |
348 | && (compl_desc_addr_hw != chan->last_compl_desc_addr_hw)) { | |
349 | chan->last_compl_desc_addr_hw = compl_desc_addr_hw; | |
350 | chan->completion_virt->low = completion_hw.low; | |
351 | chan->completion_virt->high = completion_hw.high; | |
09177e85 | 352 | } else { |
5cbafa65 | 353 | ioat1_reset_channel(ioat); |
dcbc853a DW |
354 | chan->watchdog_completion = 0; |
355 | chan->last_compl_desc_addr_hw = 0; | |
09177e85 | 356 | } |
09177e85 | 357 | } else { |
dcbc853a DW |
358 | chan->last_compl_desc_addr_hw = 0; |
359 | chan->watchdog_completion = chan->last_completion; | |
09177e85 | 360 | } |
5cbafa65 | 361 | |
dcbc853a | 362 | chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie; |
09177e85 MS |
363 | } |
364 | ||
365 | schedule_delayed_work(&device->work, WATCHDOG_DELAY); | |
366 | } | |
367 | ||
7bb67c14 | 368 | static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) |
7405f74b | 369 | { |
dcbc853a DW |
370 | struct dma_chan *c = tx->chan; |
371 | struct ioat_dma_chan *ioat = to_ioat_chan(c); | |
a0587bcf DW |
372 | struct ioat_desc_sw *desc = tx_to_ioat_desc(tx); |
373 | struct ioat_desc_sw *first; | |
374 | struct ioat_desc_sw *chain_tail; | |
7405f74b | 375 | dma_cookie_t cookie; |
7405f74b | 376 | |
dcbc853a | 377 | spin_lock_bh(&ioat->desc_lock); |
7405f74b | 378 | /* cookie incr and addition to used_list must be atomic */ |
dcbc853a | 379 | cookie = c->cookie; |
7405f74b DW |
380 | cookie++; |
381 | if (cookie < 0) | |
382 | cookie = 1; | |
dcbc853a DW |
383 | c->cookie = cookie; |
384 | tx->cookie = cookie; | |
7405f74b DW |
385 | |
386 | /* write address into NextDescriptor field of last desc in chain */ | |
a0587bcf | 387 | first = to_ioat_desc(tx->tx_list.next); |
dcbc853a | 388 | chain_tail = to_ioat_desc(ioat->used_desc.prev); |
a0587bcf DW |
389 | /* make descriptor updates globally visible before chaining */ |
390 | wmb(); | |
391 | chain_tail->hw->next = first->txd.phys; | |
dcbc853a | 392 | list_splice_tail_init(&tx->tx_list, &ioat->used_desc); |
a0587bcf | 393 | |
dcbc853a DW |
394 | ioat->pending += desc->tx_cnt; |
395 | if (ioat->pending >= ioat_pending_level) | |
396 | __ioat1_dma_memcpy_issue_pending(ioat); | |
397 | spin_unlock_bh(&ioat->desc_lock); | |
7405f74b | 398 | |
7bb67c14 SN |
399 | return cookie; |
400 | } | |
401 | ||
7bb67c14 SN |
402 | /** |
403 | * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair | |
dcbc853a | 404 | * @ioat: the channel supplying the memory pool for the descriptors |
7bb67c14 SN |
405 | * @flags: allocation flags |
406 | */ | |
bc3c7025 | 407 | static struct ioat_desc_sw * |
dcbc853a | 408 | ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) |
0bbd5f4e CL |
409 | { |
410 | struct ioat_dma_descriptor *desc; | |
411 | struct ioat_desc_sw *desc_sw; | |
8ab89567 | 412 | struct ioatdma_device *ioatdma_device; |
0bbd5f4e CL |
413 | dma_addr_t phys; |
414 | ||
dcbc853a | 415 | ioatdma_device = ioat->base.device; |
8ab89567 | 416 | desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys); |
0bbd5f4e CL |
417 | if (unlikely(!desc)) |
418 | return NULL; | |
419 | ||
420 | desc_sw = kzalloc(sizeof(*desc_sw), flags); | |
421 | if (unlikely(!desc_sw)) { | |
8ab89567 | 422 | pci_pool_free(ioatdma_device->dma_pool, desc, phys); |
0bbd5f4e CL |
423 | return NULL; |
424 | } | |
425 | ||
426 | memset(desc, 0, sizeof(*desc)); | |
7bb67c14 | 427 | |
5cbafa65 DW |
428 | dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common); |
429 | desc_sw->txd.tx_submit = ioat1_tx_submit; | |
0bbd5f4e | 430 | desc_sw->hw = desc; |
bc3c7025 | 431 | desc_sw->txd.phys = phys; |
0bbd5f4e CL |
432 | |
433 | return desc_sw; | |
434 | } | |
435 | ||
7bb67c14 SN |
436 | static int ioat_initial_desc_count = 256; |
437 | module_param(ioat_initial_desc_count, int, 0644); | |
438 | MODULE_PARM_DESC(ioat_initial_desc_count, | |
5cbafa65 | 439 | "ioat1: initial descriptors per channel (default: 256)"); |
7bb67c14 | 440 | /** |
5cbafa65 | 441 | * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors |
7bb67c14 SN |
442 | * @chan: the channel to be filled out |
443 | */ | |
5cbafa65 | 444 | static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) |
0bbd5f4e | 445 | { |
dcbc853a DW |
446 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
447 | struct ioat_chan_common *chan = &ioat->base; | |
711924b1 | 448 | struct ioat_desc_sw *desc; |
0bbd5f4e CL |
449 | u16 chanctrl; |
450 | u32 chanerr; | |
451 | int i; | |
452 | LIST_HEAD(tmp_list); | |
453 | ||
e4223976 | 454 | /* have we already been set up? */ |
dcbc853a DW |
455 | if (!list_empty(&ioat->free_desc)) |
456 | return ioat->desccount; | |
0bbd5f4e | 457 | |
43d6e369 | 458 | /* Setup register to interrupt and write completion status on error */ |
e4223976 | 459 | chanctrl = IOAT_CHANCTRL_ERR_INT_EN | |
0bbd5f4e CL |
460 | IOAT_CHANCTRL_ANY_ERR_ABORT_EN | |
461 | IOAT_CHANCTRL_ERR_COMPLETION_EN; | |
dcbc853a | 462 | writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET); |
0bbd5f4e | 463 | |
dcbc853a | 464 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
0bbd5f4e | 465 | if (chanerr) { |
dcbc853a DW |
466 | dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr); |
467 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
0bbd5f4e CL |
468 | } |
469 | ||
470 | /* Allocate descriptors */ | |
7bb67c14 | 471 | for (i = 0; i < ioat_initial_desc_count; i++) { |
dcbc853a | 472 | desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL); |
0bbd5f4e | 473 | if (!desc) { |
dcbc853a | 474 | dev_err(to_dev(chan), "Only %d initial descriptors\n", i); |
0bbd5f4e CL |
475 | break; |
476 | } | |
477 | list_add_tail(&desc->node, &tmp_list); | |
478 | } | |
dcbc853a DW |
479 | spin_lock_bh(&ioat->desc_lock); |
480 | ioat->desccount = i; | |
481 | list_splice(&tmp_list, &ioat->free_desc); | |
dcbc853a | 482 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e CL |
483 | |
484 | /* allocate a completion writeback area */ | |
485 | /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ | |
dcbc853a DW |
486 | chan->completion_virt = pci_pool_alloc(chan->device->completion_pool, |
487 | GFP_KERNEL, | |
488 | &chan->completion_addr); | |
489 | memset(chan->completion_virt, 0, | |
490 | sizeof(*chan->completion_virt)); | |
491 | writel(((u64) chan->completion_addr) & 0x00000000FFFFFFFF, | |
492 | chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); | |
493 | writel(((u64) chan->completion_addr) >> 32, | |
494 | chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); | |
495 | ||
496 | tasklet_enable(&chan->cleanup_task); | |
5cbafa65 | 497 | ioat1_dma_start_null_desc(ioat); /* give chain to dma device */ |
dcbc853a | 498 | return ioat->desccount; |
0bbd5f4e CL |
499 | } |
500 | ||
7bb67c14 | 501 | /** |
5cbafa65 | 502 | * ioat1_dma_free_chan_resources - release all the descriptors |
7bb67c14 SN |
503 | * @chan: the channel to be cleaned |
504 | */ | |
5cbafa65 | 505 | static void ioat1_dma_free_chan_resources(struct dma_chan *c) |
0bbd5f4e | 506 | { |
dcbc853a DW |
507 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
508 | struct ioat_chan_common *chan = &ioat->base; | |
509 | struct ioatdma_device *ioatdma_device = chan->device; | |
0bbd5f4e | 510 | struct ioat_desc_sw *desc, *_desc; |
0bbd5f4e CL |
511 | int in_use_descs = 0; |
512 | ||
c3d4f44f MS |
513 | /* Before freeing channel resources first check |
514 | * if they have been previously allocated for this channel. | |
515 | */ | |
dcbc853a | 516 | if (ioat->desccount == 0) |
c3d4f44f MS |
517 | return; |
518 | ||
dcbc853a | 519 | tasklet_disable(&chan->cleanup_task); |
5cbafa65 | 520 | ioat1_cleanup(ioat); |
0bbd5f4e | 521 | |
3e037454 SN |
522 | /* Delay 100ms after reset to allow internal DMA logic to quiesce |
523 | * before removing DMA descriptor resources. | |
524 | */ | |
7bb67c14 | 525 | writeb(IOAT_CHANCMD_RESET, |
dcbc853a | 526 | chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
3e037454 | 527 | mdelay(100); |
0bbd5f4e | 528 | |
dcbc853a | 529 | spin_lock_bh(&ioat->desc_lock); |
5cbafa65 DW |
530 | list_for_each_entry_safe(desc, _desc, |
531 | &ioat->used_desc, node) { | |
532 | in_use_descs++; | |
533 | list_del(&desc->node); | |
534 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, | |
535 | desc->txd.phys); | |
536 | kfree(desc); | |
537 | } | |
538 | list_for_each_entry_safe(desc, _desc, | |
539 | &ioat->free_desc, node) { | |
540 | list_del(&desc->node); | |
8ab89567 | 541 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, |
bc3c7025 | 542 | desc->txd.phys); |
0bbd5f4e CL |
543 | kfree(desc); |
544 | } | |
dcbc853a | 545 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e | 546 | |
8ab89567 | 547 | pci_pool_free(ioatdma_device->completion_pool, |
dcbc853a DW |
548 | chan->completion_virt, |
549 | chan->completion_addr); | |
0bbd5f4e CL |
550 | |
551 | /* one is ok since we left it on there on purpose */ | |
552 | if (in_use_descs > 1) | |
dcbc853a | 553 | dev_err(to_dev(chan), "Freeing %d in use descriptors!\n", |
0bbd5f4e CL |
554 | in_use_descs - 1); |
555 | ||
dcbc853a DW |
556 | chan->last_completion = chan->completion_addr = 0; |
557 | chan->watchdog_completion = 0; | |
558 | chan->last_compl_desc_addr_hw = 0; | |
559 | chan->watchdog_tcp_cookie = chan->watchdog_last_tcp_cookie = 0; | |
560 | ioat->pending = 0; | |
dcbc853a | 561 | ioat->desccount = 0; |
3e037454 | 562 | } |
7f2b291f | 563 | |
3e037454 | 564 | /** |
dcbc853a DW |
565 | * ioat1_dma_get_next_descriptor - return the next available descriptor |
566 | * @ioat: IOAT DMA channel handle | |
3e037454 SN |
567 | * |
568 | * Gets the next descriptor from the chain, and must be called with the | |
569 | * channel's desc_lock held. Allocates more descriptors if the channel | |
570 | * has run out. | |
571 | */ | |
7f2b291f | 572 | static struct ioat_desc_sw * |
dcbc853a | 573 | ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat) |
3e037454 | 574 | { |
711924b1 | 575 | struct ioat_desc_sw *new; |
3e037454 | 576 | |
dcbc853a DW |
577 | if (!list_empty(&ioat->free_desc)) { |
578 | new = to_ioat_desc(ioat->free_desc.next); | |
3e037454 SN |
579 | list_del(&new->node); |
580 | } else { | |
581 | /* try to get another desc */ | |
dcbc853a | 582 | new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC); |
711924b1 | 583 | if (!new) { |
dcbc853a | 584 | dev_err(to_dev(&ioat->base), "alloc failed\n"); |
711924b1 SN |
585 | return NULL; |
586 | } | |
3e037454 SN |
587 | } |
588 | ||
589 | prefetch(new->hw); | |
590 | return new; | |
0bbd5f4e CL |
591 | } |
592 | ||
bc3c7025 | 593 | static struct dma_async_tx_descriptor * |
dcbc853a | 594 | ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, |
bc3c7025 | 595 | dma_addr_t dma_src, size_t len, unsigned long flags) |
0bbd5f4e | 596 | { |
dcbc853a | 597 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
a0587bcf DW |
598 | struct ioat_desc_sw *desc; |
599 | size_t copy; | |
600 | LIST_HEAD(chain); | |
601 | dma_addr_t src = dma_src; | |
602 | dma_addr_t dest = dma_dest; | |
603 | size_t total_len = len; | |
604 | struct ioat_dma_descriptor *hw = NULL; | |
605 | int tx_cnt = 0; | |
0bbd5f4e | 606 | |
dcbc853a | 607 | spin_lock_bh(&ioat->desc_lock); |
5cbafa65 | 608 | desc = ioat1_dma_get_next_descriptor(ioat); |
a0587bcf DW |
609 | do { |
610 | if (!desc) | |
611 | break; | |
0bbd5f4e | 612 | |
a0587bcf | 613 | tx_cnt++; |
dcbc853a | 614 | copy = min_t(size_t, len, ioat->xfercap); |
a0587bcf DW |
615 | |
616 | hw = desc->hw; | |
617 | hw->size = copy; | |
618 | hw->ctl = 0; | |
619 | hw->src_addr = src; | |
620 | hw->dst_addr = dest; | |
621 | ||
622 | list_add_tail(&desc->node, &chain); | |
623 | ||
624 | len -= copy; | |
625 | dest += copy; | |
626 | src += copy; | |
627 | if (len) { | |
628 | struct ioat_desc_sw *next; | |
629 | ||
630 | async_tx_ack(&desc->txd); | |
5cbafa65 | 631 | next = ioat1_dma_get_next_descriptor(ioat); |
a0587bcf DW |
632 | hw->next = next ? next->txd.phys : 0; |
633 | desc = next; | |
634 | } else | |
635 | hw->next = 0; | |
636 | } while (len); | |
637 | ||
638 | if (!desc) { | |
dcbc853a DW |
639 | struct ioat_chan_common *chan = &ioat->base; |
640 | ||
641 | dev_err(to_dev(chan), | |
5cbafa65 | 642 | "chan%d - get_next_desc failed\n", chan_num(chan)); |
dcbc853a DW |
643 | list_splice(&chain, &ioat->free_desc); |
644 | spin_unlock_bh(&ioat->desc_lock); | |
711924b1 | 645 | return NULL; |
09177e85 | 646 | } |
dcbc853a | 647 | spin_unlock_bh(&ioat->desc_lock); |
a0587bcf DW |
648 | |
649 | desc->txd.flags = flags; | |
650 | desc->tx_cnt = tx_cnt; | |
a0587bcf DW |
651 | desc->len = total_len; |
652 | list_splice(&chain, &desc->txd.tx_list); | |
653 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
654 | hw->ctl_f.compl_write = 1; | |
655 | ||
656 | return &desc->txd; | |
0bbd5f4e CL |
657 | } |
658 | ||
5cbafa65 | 659 | static void ioat1_cleanup_tasklet(unsigned long data) |
3e037454 SN |
660 | { |
661 | struct ioat_dma_chan *chan = (void *)data; | |
5cbafa65 | 662 | ioat1_cleanup(chan); |
3e037454 | 663 | writew(IOAT_CHANCTRL_INT_DISABLE, |
dcbc853a | 664 | chan->base.reg_base + IOAT_CHANCTRL_OFFSET); |
3e037454 SN |
665 | } |
666 | ||
5cbafa65 DW |
667 | static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, |
668 | int direction, enum dma_ctrl_flags flags, bool dst) | |
e1d181ef | 669 | { |
5cbafa65 DW |
670 | if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || |
671 | (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) | |
672 | pci_unmap_single(pdev, addr, len, direction); | |
673 | else | |
674 | pci_unmap_page(pdev, addr, len, direction); | |
e1d181ef DW |
675 | } |
676 | ||
5cbafa65 DW |
677 | |
678 | void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, | |
679 | size_t len, struct ioat_dma_descriptor *hw) | |
0bbd5f4e | 680 | { |
5cbafa65 DW |
681 | struct pci_dev *pdev = chan->device->pdev; |
682 | size_t offset = len - hw->size; | |
0bbd5f4e | 683 | |
5cbafa65 DW |
684 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) |
685 | ioat_unmap(pdev, hw->dst_addr - offset, len, | |
686 | PCI_DMA_FROMDEVICE, flags, 1); | |
0bbd5f4e | 687 | |
5cbafa65 DW |
688 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) |
689 | ioat_unmap(pdev, hw->src_addr - offset, len, | |
690 | PCI_DMA_TODEVICE, flags, 0); | |
691 | } | |
692 | ||
693 | unsigned long ioat_get_current_completion(struct ioat_chan_common *chan) | |
694 | { | |
695 | unsigned long phys_complete; | |
0bbd5f4e CL |
696 | |
697 | /* The completion writeback can happen at any time, | |
698 | so reads by the driver need to be atomic operations | |
699 | The descriptor physical addresses are limited to 32-bits | |
700 | when the CPU can only do a 32-bit mov */ | |
701 | ||
702 | #if (BITS_PER_LONG == 64) | |
703 | phys_complete = | |
dcbc853a | 704 | chan->completion_virt->full |
7f2b291f | 705 | & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; |
0bbd5f4e | 706 | #else |
dcbc853a | 707 | phys_complete = chan->completion_virt->low & IOAT_LOW_COMPLETION_MASK; |
0bbd5f4e CL |
708 | #endif |
709 | ||
dcbc853a | 710 | if ((chan->completion_virt->full |
7f2b291f | 711 | & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == |
43d6e369 | 712 | IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { |
dcbc853a DW |
713 | dev_err(to_dev(chan), "Channel halted, chanerr = %x\n", |
714 | readl(chan->reg_base + IOAT_CHANERR_OFFSET)); | |
0bbd5f4e CL |
715 | |
716 | /* TODO do something to salvage the situation */ | |
717 | } | |
718 | ||
5cbafa65 DW |
719 | return phys_complete; |
720 | } | |
721 | ||
722 | /** | |
723 | * ioat1_cleanup - cleanup up finished descriptors | |
724 | * @chan: ioat channel to be cleaned up | |
725 | */ | |
726 | static void ioat1_cleanup(struct ioat_dma_chan *ioat) | |
727 | { | |
728 | struct ioat_chan_common *chan = &ioat->base; | |
729 | unsigned long phys_complete; | |
730 | struct ioat_desc_sw *desc, *_desc; | |
731 | dma_cookie_t cookie = 0; | |
732 | struct dma_async_tx_descriptor *tx; | |
733 | ||
734 | prefetch(chan->completion_virt); | |
735 | ||
736 | if (!spin_trylock_bh(&chan->cleanup_lock)) | |
737 | return; | |
738 | ||
739 | phys_complete = ioat_get_current_completion(chan); | |
dcbc853a DW |
740 | if (phys_complete == chan->last_completion) { |
741 | spin_unlock_bh(&chan->cleanup_lock); | |
09177e85 MS |
742 | /* |
743 | * perhaps we're stuck so hard that the watchdog can't go off? | |
744 | * try to catch it after 2 seconds | |
745 | */ | |
5cbafa65 DW |
746 | if (time_after(jiffies, |
747 | chan->last_completion_time + HZ*WATCHDOG_DELAY)) { | |
748 | ioat1_chan_watchdog(&(chan->device->work.work)); | |
749 | chan->last_completion_time = jiffies; | |
09177e85 | 750 | } |
0bbd5f4e CL |
751 | return; |
752 | } | |
dcbc853a | 753 | chan->last_completion_time = jiffies; |
0bbd5f4e | 754 | |
3e037454 | 755 | cookie = 0; |
dcbc853a DW |
756 | if (!spin_trylock_bh(&ioat->desc_lock)) { |
757 | spin_unlock_bh(&chan->cleanup_lock); | |
09177e85 MS |
758 | return; |
759 | } | |
760 | ||
5cbafa65 DW |
761 | list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { |
762 | tx = &desc->txd; | |
763 | /* | |
764 | * Incoming DMA requests may use multiple descriptors, | |
765 | * due to exceeding xfercap, perhaps. If so, only the | |
766 | * last one will have a cookie, and require unmapping. | |
767 | */ | |
768 | if (tx->cookie) { | |
769 | cookie = tx->cookie; | |
770 | ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); | |
771 | if (tx->callback) { | |
772 | tx->callback(tx->callback_param); | |
773 | tx->callback = NULL; | |
95218430 | 774 | } |
5cbafa65 | 775 | } |
0bbd5f4e | 776 | |
5cbafa65 DW |
777 | if (tx->phys != phys_complete) { |
778 | /* | |
779 | * a completed entry, but not the last, so clean | |
780 | * up if the client is done with the descriptor | |
781 | */ | |
782 | if (async_tx_test_ack(tx)) | |
783 | list_move_tail(&desc->node, &ioat->free_desc); | |
784 | else | |
bc3c7025 | 785 | tx->cookie = 0; |
5cbafa65 DW |
786 | } else { |
787 | /* | |
788 | * last used desc. Do not remove, so we can | |
789 | * append from it, but don't look at it next | |
790 | * time, either | |
791 | */ | |
792 | tx->cookie = 0; | |
0bbd5f4e | 793 | |
5cbafa65 | 794 | /* TODO check status bits? */ |
0bbd5f4e CL |
795 | break; |
796 | } | |
797 | } | |
798 | ||
dcbc853a | 799 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e | 800 | |
dcbc853a | 801 | chan->last_completion = phys_complete; |
0bbd5f4e | 802 | if (cookie != 0) |
dcbc853a | 803 | chan->completed_cookie = cookie; |
0bbd5f4e | 804 | |
dcbc853a | 805 | spin_unlock_bh(&chan->cleanup_lock); |
0bbd5f4e CL |
806 | } |
807 | ||
bc3c7025 | 808 | static enum dma_status |
5cbafa65 DW |
809 | ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie, |
810 | dma_cookie_t *done, dma_cookie_t *used) | |
0bbd5f4e | 811 | { |
dcbc853a | 812 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
0bbd5f4e | 813 | |
5cbafa65 DW |
814 | if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) |
815 | return DMA_SUCCESS; | |
0bbd5f4e | 816 | |
5cbafa65 | 817 | ioat1_cleanup(ioat); |
0bbd5f4e | 818 | |
5cbafa65 | 819 | return ioat_is_complete(c, cookie, done, used); |
0bbd5f4e CL |
820 | } |
821 | ||
5cbafa65 | 822 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat) |
0bbd5f4e | 823 | { |
dcbc853a | 824 | struct ioat_chan_common *chan = &ioat->base; |
0bbd5f4e | 825 | struct ioat_desc_sw *desc; |
c7984f4e | 826 | struct ioat_dma_descriptor *hw; |
0bbd5f4e | 827 | |
dcbc853a | 828 | spin_lock_bh(&ioat->desc_lock); |
0bbd5f4e | 829 | |
5cbafa65 | 830 | desc = ioat1_dma_get_next_descriptor(ioat); |
7f1b358a MS |
831 | |
832 | if (!desc) { | |
dcbc853a | 833 | dev_err(to_dev(chan), |
7f1b358a | 834 | "Unable to start null desc - get next desc failed\n"); |
dcbc853a | 835 | spin_unlock_bh(&ioat->desc_lock); |
7f1b358a MS |
836 | return; |
837 | } | |
838 | ||
c7984f4e DW |
839 | hw = desc->hw; |
840 | hw->ctl = 0; | |
841 | hw->ctl_f.null = 1; | |
842 | hw->ctl_f.int_en = 1; | |
843 | hw->ctl_f.compl_write = 1; | |
7f1b358a | 844 | /* set size to non-zero value (channel returns error when size is 0) */ |
c7984f4e DW |
845 | hw->size = NULL_DESC_BUFFER_SIZE; |
846 | hw->src_addr = 0; | |
847 | hw->dst_addr = 0; | |
bc3c7025 | 848 | async_tx_ack(&desc->txd); |
5cbafa65 DW |
849 | hw->next = 0; |
850 | list_add_tail(&desc->node, &ioat->used_desc); | |
7bb67c14 | 851 | |
5cbafa65 DW |
852 | writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, |
853 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); | |
854 | writel(((u64) desc->txd.phys) >> 32, | |
855 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); | |
7bb67c14 | 856 | |
5cbafa65 DW |
857 | writeb(IOAT_CHANCMD_START, chan->reg_base |
858 | + IOAT_CHANCMD_OFFSET(chan->device->version)); | |
dcbc853a | 859 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e CL |
860 | } |
861 | ||
862 | /* | |
863 | * Perform a IOAT transaction to verify the HW works. | |
864 | */ | |
865 | #define IOAT_TEST_SIZE 2000 | |
866 | ||
95218430 SN |
867 | static void ioat_dma_test_callback(void *dma_async_param) |
868 | { | |
b9bdcbba DW |
869 | struct completion *cmp = dma_async_param; |
870 | ||
871 | complete(cmp); | |
95218430 SN |
872 | } |
873 | ||
3e037454 SN |
874 | /** |
875 | * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. | |
876 | * @device: device to be tested | |
877 | */ | |
878 | static int ioat_dma_self_test(struct ioatdma_device *device) | |
0bbd5f4e CL |
879 | { |
880 | int i; | |
881 | u8 *src; | |
882 | u8 *dest; | |
bc3c7025 DW |
883 | struct dma_device *dma = &device->common; |
884 | struct device *dev = &device->pdev->dev; | |
0bbd5f4e | 885 | struct dma_chan *dma_chan; |
711924b1 | 886 | struct dma_async_tx_descriptor *tx; |
0036731c | 887 | dma_addr_t dma_dest, dma_src; |
0bbd5f4e CL |
888 | dma_cookie_t cookie; |
889 | int err = 0; | |
b9bdcbba | 890 | struct completion cmp; |
0c33e1ca | 891 | unsigned long tmo; |
4f005dbe | 892 | unsigned long flags; |
0bbd5f4e | 893 | |
e94b1766 | 894 | src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
0bbd5f4e CL |
895 | if (!src) |
896 | return -ENOMEM; | |
e94b1766 | 897 | dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
0bbd5f4e CL |
898 | if (!dest) { |
899 | kfree(src); | |
900 | return -ENOMEM; | |
901 | } | |
902 | ||
903 | /* Fill in src buffer */ | |
904 | for (i = 0; i < IOAT_TEST_SIZE; i++) | |
905 | src[i] = (u8)i; | |
906 | ||
907 | /* Start copy, using first DMA channel */ | |
bc3c7025 | 908 | dma_chan = container_of(dma->channels.next, struct dma_chan, |
43d6e369 | 909 | device_node); |
bc3c7025 DW |
910 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { |
911 | dev_err(dev, "selftest cannot allocate chan resource\n"); | |
0bbd5f4e CL |
912 | err = -ENODEV; |
913 | goto out; | |
914 | } | |
915 | ||
bc3c7025 DW |
916 | dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); |
917 | dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); | |
a6a39ca1 DW |
918 | flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE | |
919 | DMA_PREP_INTERRUPT; | |
0036731c | 920 | tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src, |
4f005dbe | 921 | IOAT_TEST_SIZE, flags); |
5149fd01 | 922 | if (!tx) { |
bc3c7025 | 923 | dev_err(dev, "Self-test prep failed, disabling\n"); |
5149fd01 SN |
924 | err = -ENODEV; |
925 | goto free_resources; | |
926 | } | |
927 | ||
7405f74b | 928 | async_tx_ack(tx); |
b9bdcbba | 929 | init_completion(&cmp); |
95218430 | 930 | tx->callback = ioat_dma_test_callback; |
b9bdcbba | 931 | tx->callback_param = &cmp; |
7bb67c14 | 932 | cookie = tx->tx_submit(tx); |
7f2b291f | 933 | if (cookie < 0) { |
bc3c7025 | 934 | dev_err(dev, "Self-test setup failed, disabling\n"); |
7f2b291f SN |
935 | err = -ENODEV; |
936 | goto free_resources; | |
937 | } | |
bc3c7025 | 938 | dma->device_issue_pending(dma_chan); |
532d3b1f | 939 | |
0c33e1ca | 940 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
0bbd5f4e | 941 | |
0c33e1ca | 942 | if (tmo == 0 || |
bc3c7025 | 943 | dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) |
7bb67c14 | 944 | != DMA_SUCCESS) { |
bc3c7025 | 945 | dev_err(dev, "Self-test copy timed out, disabling\n"); |
0bbd5f4e CL |
946 | err = -ENODEV; |
947 | goto free_resources; | |
948 | } | |
949 | if (memcmp(src, dest, IOAT_TEST_SIZE)) { | |
bc3c7025 | 950 | dev_err(dev, "Self-test copy failed compare, disabling\n"); |
0bbd5f4e CL |
951 | err = -ENODEV; |
952 | goto free_resources; | |
953 | } | |
954 | ||
955 | free_resources: | |
bc3c7025 | 956 | dma->device_free_chan_resources(dma_chan); |
0bbd5f4e CL |
957 | out: |
958 | kfree(src); | |
959 | kfree(dest); | |
960 | return err; | |
961 | } | |
962 | ||
3e037454 SN |
963 | static char ioat_interrupt_style[32] = "msix"; |
964 | module_param_string(ioat_interrupt_style, ioat_interrupt_style, | |
965 | sizeof(ioat_interrupt_style), 0644); | |
966 | MODULE_PARM_DESC(ioat_interrupt_style, | |
967 | "set ioat interrupt style: msix (default), " | |
968 | "msix-single-vector, msi, intx)"); | |
969 | ||
970 | /** | |
971 | * ioat_dma_setup_interrupts - setup interrupt handler | |
972 | * @device: ioat device | |
973 | */ | |
974 | static int ioat_dma_setup_interrupts(struct ioatdma_device *device) | |
975 | { | |
dcbc853a | 976 | struct ioat_chan_common *chan; |
e6c0b69a DW |
977 | struct pci_dev *pdev = device->pdev; |
978 | struct device *dev = &pdev->dev; | |
979 | struct msix_entry *msix; | |
980 | int i, j, msixcnt; | |
981 | int err = -EINVAL; | |
3e037454 SN |
982 | u8 intrctrl = 0; |
983 | ||
984 | if (!strcmp(ioat_interrupt_style, "msix")) | |
985 | goto msix; | |
986 | if (!strcmp(ioat_interrupt_style, "msix-single-vector")) | |
987 | goto msix_single_vector; | |
988 | if (!strcmp(ioat_interrupt_style, "msi")) | |
989 | goto msi; | |
990 | if (!strcmp(ioat_interrupt_style, "intx")) | |
991 | goto intx; | |
e6c0b69a | 992 | dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); |
5149fd01 | 993 | goto err_no_irq; |
3e037454 SN |
994 | |
995 | msix: | |
996 | /* The number of MSI-X vectors should equal the number of channels */ | |
997 | msixcnt = device->common.chancnt; | |
998 | for (i = 0; i < msixcnt; i++) | |
999 | device->msix_entries[i].entry = i; | |
1000 | ||
e6c0b69a | 1001 | err = pci_enable_msix(pdev, device->msix_entries, msixcnt); |
3e037454 SN |
1002 | if (err < 0) |
1003 | goto msi; | |
1004 | if (err > 0) | |
1005 | goto msix_single_vector; | |
1006 | ||
1007 | for (i = 0; i < msixcnt; i++) { | |
e6c0b69a | 1008 | msix = &device->msix_entries[i]; |
dcbc853a | 1009 | chan = ioat_chan_by_index(device, i); |
e6c0b69a DW |
1010 | err = devm_request_irq(dev, msix->vector, |
1011 | ioat_dma_do_interrupt_msix, 0, | |
dcbc853a | 1012 | "ioat-msix", chan); |
3e037454 SN |
1013 | if (err) { |
1014 | for (j = 0; j < i; j++) { | |
e6c0b69a | 1015 | msix = &device->msix_entries[j]; |
dcbc853a DW |
1016 | chan = ioat_chan_by_index(device, j); |
1017 | devm_free_irq(dev, msix->vector, chan); | |
3e037454 SN |
1018 | } |
1019 | goto msix_single_vector; | |
1020 | } | |
1021 | } | |
1022 | intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; | |
3e037454 SN |
1023 | goto done; |
1024 | ||
1025 | msix_single_vector: | |
e6c0b69a DW |
1026 | msix = &device->msix_entries[0]; |
1027 | msix->entry = 0; | |
1028 | err = pci_enable_msix(pdev, device->msix_entries, 1); | |
3e037454 SN |
1029 | if (err) |
1030 | goto msi; | |
1031 | ||
e6c0b69a DW |
1032 | err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0, |
1033 | "ioat-msix", device); | |
3e037454 | 1034 | if (err) { |
e6c0b69a | 1035 | pci_disable_msix(pdev); |
3e037454 SN |
1036 | goto msi; |
1037 | } | |
3e037454 SN |
1038 | goto done; |
1039 | ||
1040 | msi: | |
e6c0b69a | 1041 | err = pci_enable_msi(pdev); |
3e037454 SN |
1042 | if (err) |
1043 | goto intx; | |
1044 | ||
e6c0b69a DW |
1045 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, |
1046 | "ioat-msi", device); | |
3e037454 | 1047 | if (err) { |
e6c0b69a | 1048 | pci_disable_msi(pdev); |
3e037454 SN |
1049 | goto intx; |
1050 | } | |
3e037454 SN |
1051 | goto done; |
1052 | ||
1053 | intx: | |
e6c0b69a DW |
1054 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, |
1055 | IRQF_SHARED, "ioat-intx", device); | |
3e037454 SN |
1056 | if (err) |
1057 | goto err_no_irq; | |
3e037454 SN |
1058 | |
1059 | done: | |
f2427e27 DW |
1060 | if (device->intr_quirk) |
1061 | device->intr_quirk(device); | |
3e037454 SN |
1062 | intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; |
1063 | writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET); | |
1064 | return 0; | |
1065 | ||
1066 | err_no_irq: | |
1067 | /* Disable all interrupt generation */ | |
1068 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); | |
e6c0b69a DW |
1069 | dev_err(dev, "no usable interrupts\n"); |
1070 | return err; | |
3e037454 SN |
1071 | } |
1072 | ||
e6c0b69a | 1073 | static void ioat_disable_interrupts(struct ioatdma_device *device) |
3e037454 | 1074 | { |
3e037454 SN |
1075 | /* Disable all interrupt generation */ |
1076 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); | |
3e037454 SN |
1077 | } |
1078 | ||
5cbafa65 | 1079 | int ioat_probe(struct ioatdma_device *device) |
0bbd5f4e | 1080 | { |
f2427e27 DW |
1081 | int err = -ENODEV; |
1082 | struct dma_device *dma = &device->common; | |
1083 | struct pci_dev *pdev = device->pdev; | |
e6c0b69a | 1084 | struct device *dev = &pdev->dev; |
0bbd5f4e CL |
1085 | |
1086 | /* DMA coherent memory pool for DMA descriptor allocations */ | |
1087 | device->dma_pool = pci_pool_create("dma_desc_pool", pdev, | |
8ab89567 SN |
1088 | sizeof(struct ioat_dma_descriptor), |
1089 | 64, 0); | |
0bbd5f4e CL |
1090 | if (!device->dma_pool) { |
1091 | err = -ENOMEM; | |
1092 | goto err_dma_pool; | |
1093 | } | |
1094 | ||
43d6e369 SN |
1095 | device->completion_pool = pci_pool_create("completion_pool", pdev, |
1096 | sizeof(u64), SMP_CACHE_BYTES, | |
1097 | SMP_CACHE_BYTES); | |
5cbafa65 | 1098 | |
0bbd5f4e CL |
1099 | if (!device->completion_pool) { |
1100 | err = -ENOMEM; | |
1101 | goto err_completion_pool; | |
1102 | } | |
1103 | ||
5cbafa65 | 1104 | device->enumerate_channels(device); |
0bbd5f4e | 1105 | |
f2427e27 | 1106 | dma_cap_set(DMA_MEMCPY, dma->cap_mask); |
f2427e27 | 1107 | dma->dev = &pdev->dev; |
7bb67c14 | 1108 | |
e6c0b69a | 1109 | dev_err(dev, "Intel(R) I/OAT DMA Engine found," |
5149fd01 | 1110 | " %d channels, device version 0x%02x, driver version %s\n", |
bc3c7025 | 1111 | dma->chancnt, device->version, IOAT_DMA_VERSION); |
8ab89567 | 1112 | |
bc3c7025 | 1113 | if (!dma->chancnt) { |
e6c0b69a | 1114 | dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: " |
8b794b14 MS |
1115 | "zero channels detected\n"); |
1116 | goto err_setup_interrupts; | |
1117 | } | |
1118 | ||
3e037454 | 1119 | err = ioat_dma_setup_interrupts(device); |
8ab89567 | 1120 | if (err) |
3e037454 | 1121 | goto err_setup_interrupts; |
0bbd5f4e | 1122 | |
3e037454 | 1123 | err = ioat_dma_self_test(device); |
0bbd5f4e CL |
1124 | if (err) |
1125 | goto err_self_test; | |
1126 | ||
f2427e27 | 1127 | return 0; |
0bbd5f4e CL |
1128 | |
1129 | err_self_test: | |
e6c0b69a | 1130 | ioat_disable_interrupts(device); |
3e037454 | 1131 | err_setup_interrupts: |
0bbd5f4e CL |
1132 | pci_pool_destroy(device->completion_pool); |
1133 | err_completion_pool: | |
1134 | pci_pool_destroy(device->dma_pool); | |
1135 | err_dma_pool: | |
f2427e27 DW |
1136 | return err; |
1137 | } | |
1138 | ||
5cbafa65 | 1139 | int ioat_register(struct ioatdma_device *device) |
f2427e27 DW |
1140 | { |
1141 | int err = dma_async_device_register(&device->common); | |
1142 | ||
1143 | if (err) { | |
1144 | ioat_disable_interrupts(device); | |
1145 | pci_pool_destroy(device->completion_pool); | |
1146 | pci_pool_destroy(device->dma_pool); | |
1147 | } | |
1148 | ||
1149 | return err; | |
1150 | } | |
1151 | ||
1152 | /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */ | |
1153 | static void ioat1_intr_quirk(struct ioatdma_device *device) | |
1154 | { | |
1155 | struct pci_dev *pdev = device->pdev; | |
1156 | u32 dmactrl; | |
1157 | ||
1158 | pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl); | |
1159 | if (pdev->msi_enabled) | |
1160 | dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; | |
1161 | else | |
1162 | dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN; | |
1163 | pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); | |
1164 | } | |
1165 | ||
1166 | int ioat1_dma_probe(struct ioatdma_device *device, int dca) | |
1167 | { | |
1168 | struct pci_dev *pdev = device->pdev; | |
1169 | struct dma_device *dma; | |
1170 | int err; | |
1171 | ||
1172 | device->intr_quirk = ioat1_intr_quirk; | |
5cbafa65 | 1173 | device->enumerate_channels = ioat1_enumerate_channels; |
f2427e27 DW |
1174 | dma = &device->common; |
1175 | dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; | |
1176 | dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; | |
5cbafa65 DW |
1177 | dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources; |
1178 | dma->device_free_chan_resources = ioat1_dma_free_chan_resources; | |
1179 | dma->device_is_tx_complete = ioat1_dma_is_complete; | |
f2427e27 DW |
1180 | |
1181 | err = ioat_probe(device); | |
1182 | if (err) | |
1183 | return err; | |
1184 | ioat_set_tcp_copy_break(4096); | |
1185 | err = ioat_register(device); | |
1186 | if (err) | |
1187 | return err; | |
1188 | if (dca) | |
1189 | device->dca = ioat_dca_init(pdev, device->reg_base); | |
1190 | ||
5cbafa65 | 1191 | INIT_DELAYED_WORK(&device->work, ioat1_chan_watchdog); |
f2427e27 DW |
1192 | schedule_delayed_work(&device->work, WATCHDOG_DELAY); |
1193 | ||
1194 | return err; | |
1195 | } | |
1196 | ||
8ab89567 | 1197 | void ioat_dma_remove(struct ioatdma_device *device) |
0bbd5f4e | 1198 | { |
bc3c7025 | 1199 | struct dma_device *dma = &device->common; |
0bbd5f4e | 1200 | |
2b8a6bf8 MS |
1201 | if (device->version != IOAT_VER_3_0) |
1202 | cancel_delayed_work(&device->work); | |
1203 | ||
e6c0b69a | 1204 | ioat_disable_interrupts(device); |
8ab89567 | 1205 | |
bc3c7025 | 1206 | dma_async_device_unregister(dma); |
dfe2299e | 1207 | |
0bbd5f4e CL |
1208 | pci_pool_destroy(device->dma_pool); |
1209 | pci_pool_destroy(device->completion_pool); | |
8ab89567 | 1210 | |
dcbc853a | 1211 | INIT_LIST_HEAD(&dma->channels); |
0bbd5f4e | 1212 | } |