[net-next-2.6.git] / drivers / dma / fsldma.h

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author:
 *   Zhang Wei <wei.zhang@freescale.com>, Jul 2007
 *   Ebony Zhu <ebony.zhu@freescale.com>, May 2007
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */
#ifndef __DMA_FSLDMA_H
#define __DMA_FSLDMA_H

#include <linux/device.h>
#include <linux/dmapool.h>
#include <linux/dmaengine.h>

/* Define data structures needed by Freescale
 * MPC8540 and MPC8349 DMA controller.
 */
#define FSL_DMA_MR_CS		0x00000001
#define FSL_DMA_MR_CC		0x00000002
#define FSL_DMA_MR_CA		0x00000008
#define FSL_DMA_MR_EIE		0x00000040
#define FSL_DMA_MR_XFE		0x00000020
#define FSL_DMA_MR_EOLNIE	0x00000100
#define FSL_DMA_MR_EOLSIE	0x00000080
#define FSL_DMA_MR_EOSIE	0x00000200
#define FSL_DMA_MR_CDSM		0x00000010
#define FSL_DMA_MR_CTM		0x00000004
#define FSL_DMA_MR_EMP_EN	0x00200000
#define FSL_DMA_MR_EMS_EN	0x00040000
#define FSL_DMA_MR_DAHE		0x00002000
#define FSL_DMA_MR_SAHE		0x00001000

/* Special MR definition for MPC8349 */
#define FSL_DMA_MR_EOTIE	0x00000080
#define FSL_DMA_MR_PRC_RM	0x00000800

#define FSL_DMA_SR_CH		0x00000020
#define FSL_DMA_SR_PE		0x00000010
#define FSL_DMA_SR_CB		0x00000004
#define FSL_DMA_SR_TE		0x00000080
#define FSL_DMA_SR_EOSI		0x00000002
#define FSL_DMA_SR_EOLSI	0x00000001
#define FSL_DMA_SR_EOCDI	0x00000001
#define FSL_DMA_SR_EOLNI	0x00000008

#define FSL_DMA_SATR_SBPATMU			0x20000000
#define FSL_DMA_SATR_STRANSINT_RIO		0x00c00000
#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ	0x00050000
#define FSL_DMA_SATR_SREADTYPE_BP_IORH		0x00020000
#define FSL_DMA_SATR_SREADTYPE_BP_NREAD		0x00040000
#define FSL_DMA_SATR_SREADTYPE_BP_MREAD		0x00070000

#define FSL_DMA_DATR_DBPATMU			0x20000000
#define FSL_DMA_DATR_DTRANSINT_RIO		0x00c00000
#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE	0x00050000
#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH	0x00010000

#define FSL_DMA_EOL		((u64)0x1)
#define FSL_DMA_SNEN		((u64)0x10)
#define FSL_DMA_EOSIE		0x8
#define FSL_DMA_NLDA_MASK	(~(u64)0x1f)

#define FSL_DMA_BCR_MAX_CNT	0x03ffffffu

#define FSL_DMA_DGSR_TE		0x80
#define FSL_DMA_DGSR_CH		0x20
#define FSL_DMA_DGSR_PE		0x10
#define FSL_DMA_DGSR_EOLNI	0x08
#define FSL_DMA_DGSR_CB		0x04
#define FSL_DMA_DGSR_EOSI	0x02
#define FSL_DMA_DGSR_EOLSI	0x01

typedef u64 __bitwise v64;
typedef u32 __bitwise v32;

struct fsl_dma_ld_hw {
	v64 src_addr;
	v64 dst_addr;
	v64 next_ln_addr;
	v32 count;
	v32 reserve;
} __attribute__((aligned(32)));

struct fsl_desc_sw {
	struct fsl_dma_ld_hw hw;
	struct list_head node;
	struct list_head tx_list;
	struct dma_async_tx_descriptor async_tx;
} __attribute__((aligned(32)));

struct fsldma_chan_regs {
	u32 mr;	/* 0x00 - Mode Register */
	u32 sr;	/* 0x04 - Status Register */
	u64 cdar;	/* 0x08 - Current descriptor address register */
	u64 sar;	/* 0x10 - Source Address Register */
	u64 dar;	/* 0x18 - Destination Address Register */
	u32 bcr;	/* 0x20 - Byte Count Register */
	u64 ndar;	/* 0x24 - Next Descriptor Address Register */
};

struct fsldma_chan;
#define FSL_DMA_MAX_CHANS_PER_DEVICE 4

struct fsldma_device {
	void __iomem *regs;	/* DGSR register base */
	struct device *dev;
	struct dma_device common;
	struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
	u32 feature;		/* The same as DMA channels */
	int irq;		/* Channel IRQ */
};

/* Define macros for fsldma_chan->feature property */
#define FSL_DMA_LITTLE_ENDIAN	0x00000000
#define FSL_DMA_BIG_ENDIAN	0x00000001

#define FSL_DMA_IP_MASK		0x00000ff0
#define FSL_DMA_IP_85XX		0x00000010
#define FSL_DMA_IP_83XX		0x00000020

#define FSL_DMA_CHAN_PAUSE_EXT	0x00001000
#define FSL_DMA_CHAN_START_EXT	0x00002000

struct fsldma_chan {
	struct fsldma_chan_regs __iomem *regs;
	dma_cookie_t completed_cookie;	/* The maximum cookie completed */
	spinlock_t desc_lock;		/* Descriptor operation lock */
	struct list_head ld_pending;	/* Link descriptors queue */
	struct list_head ld_running;	/* Link descriptors queue */
	struct dma_chan common;		/* DMA common channel */
	struct dma_pool *desc_pool;	/* Descriptors pool */
	struct device *dev;		/* Channel device */
	int irq;			/* Channel IRQ */
	int id;				/* Raw id of this channel */
	struct tasklet_struct tasklet;
	u32 feature;

	void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
	void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
	void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
	void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
	void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
};

#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)

#ifndef __powerpc64__
static u64 in_be64(const u64 __iomem *addr)
{
	return ((u64)in_be32((u32 __iomem *)addr) << 32) |
		(in_be32((u32 __iomem *)addr + 1));
}

static void out_be64(u64 __iomem *addr, u64 val)
{
	out_be32((u32 __iomem *)addr, val >> 32);
	out_be32((u32 __iomem *)addr + 1, (u32)val);
}

/* There is no asm instructions for 64 bits reverse loads and stores */
static u64 in_le64(const u64 __iomem *addr)
{
	return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
		(in_le32((u32 __iomem *)addr));
}

static void out_le64(u64 __iomem *addr, u64 val)
{
	out_le32((u32 __iomem *)addr + 1, val >> 32);
	out_le32((u32 __iomem *)addr, (u32)val);
}
#endif

#define DMA_IN(fsl_chan, addr, width)					\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			in_be##width(addr) : in_le##width(addr))
#define DMA_OUT(fsl_chan, addr, val, width)				\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			out_be##width(addr, val) : out_le##width(addr, val))

#define DMA_TO_CPU(fsl_chan, d, width)					\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			be##width##_to_cpu((__force __be##width)(v##width)d) : \
			le##width##_to_cpu((__force __le##width)(v##width)d))
#define CPU_TO_DMA(fsl_chan, c, width)					\
		(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ?		\
			(__force v##width)cpu_to_be##width(c) :		\
			(__force v##width)cpu_to_le##width(c))

#endif	/* __DMA_FSLDMA_H */
Commit	Line	Data
173acc7c ZW	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
	3	*
	4	* Author:
	5	* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
	6	* Ebony Zhu <ebony.zhu@freescale.com>, May 2007
	7	*
	8	* This is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*/
	14	#ifndef __DMA_FSLDMA_H
	15	#define __DMA_FSLDMA_H
	16
	17	#include <linux/device.h>
	18	#include <linux/dmapool.h>
	19	#include <linux/dmaengine.h>
	20
	21	/* Define data structures needed by Freescale
	22	* MPC8540 and MPC8349 DMA controller.
	23	*/
	24	#define FSL_DMA_MR_CS 0x00000001
	25	#define FSL_DMA_MR_CC 0x00000002
	26	#define FSL_DMA_MR_CA 0x00000008
	27	#define FSL_DMA_MR_EIE 0x00000040
	28	#define FSL_DMA_MR_XFE 0x00000020
	29	#define FSL_DMA_MR_EOLNIE 0x00000100
	30	#define FSL_DMA_MR_EOLSIE 0x00000080
	31	#define FSL_DMA_MR_EOSIE 0x00000200
	32	#define FSL_DMA_MR_CDSM 0x00000010
	33	#define FSL_DMA_MR_CTM 0x00000004
	34	#define FSL_DMA_MR_EMP_EN 0x00200000
	35	#define FSL_DMA_MR_EMS_EN 0x00040000
	36	#define FSL_DMA_MR_DAHE 0x00002000
	37	#define FSL_DMA_MR_SAHE 0x00001000
	38
	39	/* Special MR definition for MPC8349 */
	40	#define FSL_DMA_MR_EOTIE 0x00000080
a7aea373	41	#define FSL_DMA_MR_PRC_RM 0x00000800
173acc7c ZW	42
173acc7c ZW	43	#define FSL_DMA_SR_CH 0x00000020
f79abb62	44	#define FSL_DMA_SR_PE 0x00000010
173acc7c ZW	45	#define FSL_DMA_SR_CB 0x00000004
	46	#define FSL_DMA_SR_TE 0x00000080
	47	#define FSL_DMA_SR_EOSI 0x00000002
	48	#define FSL_DMA_SR_EOLSI 0x00000001
	49	#define FSL_DMA_SR_EOCDI 0x00000001
	50	#define FSL_DMA_SR_EOLNI 0x00000008
	51
	52	#define FSL_DMA_SATR_SBPATMU 0x20000000
	53	#define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
	54	#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
	55	#define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
	56	#define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
	57	#define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
	58
	59	#define FSL_DMA_DATR_DBPATMU 0x20000000
	60	#define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
	61	#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
	62	#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
	63
	64	#define FSL_DMA_EOL ((u64)0x1)
	65	#define FSL_DMA_SNEN ((u64)0x10)
	66	#define FSL_DMA_EOSIE 0x8
	67	#define FSL_DMA_NLDA_MASK (~(u64)0x1f)
	68
	69	#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
	70
	71	#define FSL_DMA_DGSR_TE 0x80
	72	#define FSL_DMA_DGSR_CH 0x20
	73	#define FSL_DMA_DGSR_PE 0x10
	74	#define FSL_DMA_DGSR_EOLNI 0x08
	75	#define FSL_DMA_DGSR_CB 0x04
	76	#define FSL_DMA_DGSR_EOSI 0x02
	77	#define FSL_DMA_DGSR_EOLSI 0x01
	78
a4e6d5d3 AV	79	typedef u64 __bitwise v64;
	80	typedef u32 __bitwise v32;
	81
173acc7c	82	struct fsl_dma_ld_hw {
a4e6d5d3 AV	83	v64 src_addr;
	84	v64 dst_addr;
	85	v64 next_ln_addr;
	86	v32 count;
	87	v32 reserve;
173acc7c ZW	88	} __attribute__((aligned(32)));
	89
	90	struct fsl_desc_sw {
	91	struct fsl_dma_ld_hw hw;
	92	struct list_head node;
eda34234	93	struct list_head tx_list;
173acc7c	94	struct dma_async_tx_descriptor async_tx;
173acc7c ZW	95	} __attribute__((aligned(32)));
173acc7c ZW	96
a4f56d4b	97	struct fsldma_chan_regs {
a4e6d5d3 AV	98	u32 mr; /* 0x00 - Mode Register */
	99	u32 sr; /* 0x04 - Status Register */
	100	u64 cdar; /* 0x08 - Current descriptor address register */
	101	u64 sar; /* 0x10 - Source Address Register */
	102	u64 dar; /* 0x18 - Destination Address Register */
	103	u32 bcr; /* 0x20 - Byte Count Register */
	104	u64 ndar; /* 0x24 - Next Descriptor Address Register */
173acc7c ZW	105	};
173acc7c ZW	106
a4f56d4b	107	struct fsldma_chan;
173acc7c ZW	108	#define FSL_DMA_MAX_CHANS_PER_DEVICE 4
173acc7c ZW	109
a4f56d4b	110	struct fsldma_device {
e7a29151	111	void __iomem regs; / DGSR register base */
173acc7c ZW	112	struct device *dev;
173acc7c ZW	113	struct dma_device common;
a4f56d4b	114	struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
173acc7c	115	u32 feature; /* The same as DMA channels */
77cd62e8	116	int irq; /* Channel IRQ */
173acc7c ZW	117	};
173acc7c ZW	118
a4f56d4b	119	/* Define macros for fsldma_chan->feature property */
173acc7c ZW	120	#define FSL_DMA_LITTLE_ENDIAN 0x00000000
	121	#define FSL_DMA_BIG_ENDIAN 0x00000001
	122
	123	#define FSL_DMA_IP_MASK 0x00000ff0
	124	#define FSL_DMA_IP_85XX 0x00000010
	125	#define FSL_DMA_IP_83XX 0x00000020
	126
	127	#define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
	128	#define FSL_DMA_CHAN_START_EXT 0x00002000
	129
a4f56d4b	130	struct fsldma_chan {
e7a29151	131	struct fsldma_chan_regs __iomem *regs;
173acc7c ZW	132	dma_cookie_t completed_cookie; /* The maximum cookie completed */
173acc7c ZW	133	spinlock_t desc_lock; /* Descriptor operation lock */
9c3a50b7 IS	134	struct list_head ld_pending; /* Link descriptors queue */
9c3a50b7 IS	135	struct list_head ld_running; /* Link descriptors queue */
173acc7c ZW	136	struct dma_chan common; /* DMA common channel */
	137	struct dma_pool desc_pool; / Descriptors pool */
	138	struct device dev; / Channel device */
173acc7c ZW	139	int irq; /* Channel IRQ */
	140	int id; /* Raw id of this channel */
	141	struct tasklet_struct tasklet;
	142	u32 feature;
	143
a4f56d4b IS	144	void (toggle_ext_pause)(struct fsldma_chan fsl_chan, int enable);
	145	void (toggle_ext_start)(struct fsldma_chan fsl_chan, int enable);
	146	void (set_src_loop_size)(struct fsldma_chan fsl_chan, int size);
738f5f7e	147	void (set_dst_loop_size)(struct fsldma_chan fsl_chan, int size);
a4f56d4b	148	void (set_request_count)(struct fsldma_chan fsl_chan, int size);
173acc7c ZW	149	};
173acc7c ZW	150
a4f56d4b	151	#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
173acc7c ZW	152	#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
	153	#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
	154
	155	#ifndef __powerpc64__
	156	static u64 in_be64(const u64 __iomem *addr)
	157	{
a4e6d5d3 AV	158	return ((u64)in_be32((u32 __iomem *)addr) << 32) \|
a4e6d5d3 AV	159	(in_be32((u32 __iomem *)addr + 1));
173acc7c ZW	160	}
	161
	162	static void out_be64(u64 __iomem *addr, u64 val)
	163	{
a4e6d5d3 AV	164	out_be32((u32 __iomem *)addr, val >> 32);
a4e6d5d3 AV	165	out_be32((u32 __iomem *)addr + 1, (u32)val);
173acc7c ZW	166	}
	167
	168	/* There is no asm instructions for 64 bits reverse loads and stores */
	169	static u64 in_le64(const u64 __iomem *addr)
	170	{
a4e6d5d3 AV	171	return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) \|
a4e6d5d3 AV	172	(in_le32((u32 __iomem *)addr));
173acc7c ZW	173	}
	174
	175	static void out_le64(u64 __iomem *addr, u64 val)
	176	{
a4e6d5d3 AV	177	out_le32((u32 __iomem *)addr + 1, val >> 32);
a4e6d5d3 AV	178	out_le32((u32 __iomem *)addr, (u32)val);
173acc7c ZW	179	}
	180	#endif
	181
	182	#define DMA_IN(fsl_chan, addr, width) \
	183	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
	184	in_be##width(addr) : in_le##width(addr))
	185	#define DMA_OUT(fsl_chan, addr, val, width) \
	186	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
	187	out_be##width(addr, val) : out_le##width(addr, val))
	188
	189	#define DMA_TO_CPU(fsl_chan, d, width) \
	190	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
a4e6d5d3 AV	191	be##width##_to_cpu((__force __be##width)(v##width)d) : \
a4e6d5d3 AV	192	le##width##_to_cpu((__force __le##width)(v##width)d))
173acc7c ZW	193	#define CPU_TO_DMA(fsl_chan, c, width) \
173acc7c ZW	194	(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
a4e6d5d3 AV	195	(__force v##width)cpu_to_be##width(c) : \
a4e6d5d3 AV	196	(__force v##width)cpu_to_le##width(c))
173acc7c ZW	197
173acc7c ZW	198	#endif /* __DMA_FSLDMA_H */