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Commit | Line | Data |
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173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
4 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
5 | * | |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
36 | #include <linux/of_platform.h> | |
37 | ||
38 | #include "fsldma.h" | |
39 | ||
c1433041 IS |
40 | static const char msg_ld_oom[] = "No free memory for link descriptor\n"; |
41 | ||
a1c03319 | 42 | static void dma_init(struct fsldma_chan *chan) |
173acc7c ZW |
43 | { |
44 | /* Reset the channel */ | |
a1c03319 | 45 | DMA_OUT(chan, &chan->regs->mr, 0, 32); |
173acc7c | 46 | |
a1c03319 | 47 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c ZW |
48 | case FSL_DMA_IP_85XX: |
49 | /* Set the channel to below modes: | |
50 | * EIE - Error interrupt enable | |
51 | * EOSIE - End of segments interrupt enable (basic mode) | |
52 | * EOLNIE - End of links interrupt enable | |
53 | */ | |
a1c03319 | 54 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE |
173acc7c ZW |
55 | | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); |
56 | break; | |
57 | case FSL_DMA_IP_83XX: | |
58 | /* Set the channel to below modes: | |
59 | * EOTIE - End-of-transfer interrupt enable | |
a7aea373 | 60 | * PRC_RM - PCI read multiple |
173acc7c | 61 | */ |
a1c03319 | 62 | DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE |
a7aea373 | 63 | | FSL_DMA_MR_PRC_RM, 32); |
173acc7c ZW |
64 | break; |
65 | } | |
173acc7c ZW |
66 | } |
67 | ||
a1c03319 | 68 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 69 | { |
a1c03319 | 70 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
71 | } |
72 | ||
a1c03319 | 73 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 74 | { |
a1c03319 | 75 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
76 | } |
77 | ||
a1c03319 | 78 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
79 | struct fsl_dma_ld_hw *hw, u32 count) |
80 | { | |
a1c03319 | 81 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
82 | } |
83 | ||
a1c03319 | 84 | static void set_desc_src(struct fsldma_chan *chan, |
173acc7c ZW |
85 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
86 | { | |
87 | u64 snoop_bits; | |
88 | ||
a1c03319 | 89 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 90 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 91 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
92 | } |
93 | ||
a1c03319 | 94 | static void set_desc_dst(struct fsldma_chan *chan, |
738f5f7e | 95 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
96 | { |
97 | u64 snoop_bits; | |
98 | ||
a1c03319 | 99 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 100 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 101 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
102 | } |
103 | ||
a1c03319 | 104 | static void set_desc_next(struct fsldma_chan *chan, |
173acc7c ZW |
105 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
106 | { | |
107 | u64 snoop_bits; | |
108 | ||
a1c03319 | 109 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 110 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 111 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
112 | } |
113 | ||
a1c03319 | 114 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
173acc7c | 115 | { |
a1c03319 | 116 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); |
173acc7c ZW |
117 | } |
118 | ||
a1c03319 | 119 | static dma_addr_t get_cdar(struct fsldma_chan *chan) |
173acc7c | 120 | { |
a1c03319 | 121 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; |
173acc7c ZW |
122 | } |
123 | ||
a1c03319 | 124 | static dma_addr_t get_ndar(struct fsldma_chan *chan) |
173acc7c | 125 | { |
a1c03319 | 126 | return DMA_IN(chan, &chan->regs->ndar, 64); |
173acc7c ZW |
127 | } |
128 | ||
a1c03319 | 129 | static u32 get_bcr(struct fsldma_chan *chan) |
f79abb62 | 130 | { |
a1c03319 | 131 | return DMA_IN(chan, &chan->regs->bcr, 32); |
f79abb62 ZW |
132 | } |
133 | ||
a1c03319 | 134 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 135 | { |
a1c03319 | 136 | u32 sr = get_sr(chan); |
173acc7c ZW |
137 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
138 | } | |
139 | ||
a1c03319 | 140 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 141 | { |
272ca655 IS |
142 | u32 mode; |
143 | ||
a1c03319 | 144 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 145 | |
a1c03319 IS |
146 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { |
147 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { | |
148 | DMA_OUT(chan, &chan->regs->bcr, 0, 32); | |
272ca655 IS |
149 | mode |= FSL_DMA_MR_EMP_EN; |
150 | } else { | |
151 | mode &= ~FSL_DMA_MR_EMP_EN; | |
152 | } | |
43a1a3ed | 153 | } |
173acc7c | 154 | |
a1c03319 | 155 | if (chan->feature & FSL_DMA_CHAN_START_EXT) |
272ca655 | 156 | mode |= FSL_DMA_MR_EMS_EN; |
173acc7c | 157 | else |
272ca655 | 158 | mode |= FSL_DMA_MR_CS; |
173acc7c | 159 | |
a1c03319 | 160 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
161 | } |
162 | ||
a1c03319 | 163 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 164 | { |
272ca655 | 165 | u32 mode; |
900325a6 DW |
166 | int i; |
167 | ||
a1c03319 | 168 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 169 | mode |= FSL_DMA_MR_CA; |
a1c03319 | 170 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
272ca655 IS |
171 | |
172 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); | |
a1c03319 | 173 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c | 174 | |
900325a6 | 175 | for (i = 0; i < 100; i++) { |
a1c03319 | 176 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
177 | return; |
178 | ||
173acc7c | 179 | udelay(10); |
900325a6 | 180 | } |
272ca655 | 181 | |
9c3a50b7 | 182 | if (!dma_is_idle(chan)) |
a1c03319 | 183 | dev_err(chan->dev, "DMA halt timeout!\n"); |
173acc7c ZW |
184 | } |
185 | ||
a1c03319 | 186 | static void set_ld_eol(struct fsldma_chan *chan, |
173acc7c ZW |
187 | struct fsl_desc_sw *desc) |
188 | { | |
776c8943 IS |
189 | u64 snoop_bits; |
190 | ||
a1c03319 | 191 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
776c8943 IS |
192 | ? FSL_DMA_SNEN : 0; |
193 | ||
a1c03319 IS |
194 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
195 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
776c8943 | 196 | | snoop_bits, 64); |
173acc7c ZW |
197 | } |
198 | ||
173acc7c ZW |
199 | /** |
200 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 201 | * @chan : Freescale DMA channel |
173acc7c ZW |
202 | * @size : Address loop size, 0 for disable loop |
203 | * | |
204 | * The set source address hold transfer size. The source | |
205 | * address hold or loop transfer size is when the DMA transfer | |
206 | * data from source address (SA), if the loop size is 4, the DMA will | |
207 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
208 | * SA + 1 ... and so on. | |
209 | */ | |
a1c03319 | 210 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 211 | { |
272ca655 IS |
212 | u32 mode; |
213 | ||
a1c03319 | 214 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 215 | |
173acc7c ZW |
216 | switch (size) { |
217 | case 0: | |
272ca655 | 218 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
219 | break; |
220 | case 1: | |
221 | case 2: | |
222 | case 4: | |
223 | case 8: | |
272ca655 | 224 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
225 | break; |
226 | } | |
272ca655 | 227 | |
a1c03319 | 228 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
229 | } |
230 | ||
231 | /** | |
738f5f7e | 232 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 233 | * @chan : Freescale DMA channel |
173acc7c ZW |
234 | * @size : Address loop size, 0 for disable loop |
235 | * | |
236 | * The set destination address hold transfer size. The destination | |
237 | * address hold or loop transfer size is when the DMA transfer | |
238 | * data to destination address (TA), if the loop size is 4, the DMA will | |
239 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
240 | * TA + 1 ... and so on. | |
241 | */ | |
a1c03319 | 242 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 243 | { |
272ca655 IS |
244 | u32 mode; |
245 | ||
a1c03319 | 246 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 | 247 | |
173acc7c ZW |
248 | switch (size) { |
249 | case 0: | |
272ca655 | 250 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
251 | break; |
252 | case 1: | |
253 | case 2: | |
254 | case 4: | |
255 | case 8: | |
272ca655 | 256 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
257 | break; |
258 | } | |
272ca655 | 259 | |
a1c03319 | 260 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
173acc7c ZW |
261 | } |
262 | ||
263 | /** | |
e6c7ecb6 | 264 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 265 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
266 | * @size : Number of bytes to transfer in a single request |
267 | * | |
268 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
269 | * The DMA request count is how many bytes are allowed to transfer before | |
270 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
271 | * operation. | |
173acc7c | 272 | * |
e6c7ecb6 | 273 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 274 | */ |
a1c03319 | 275 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 276 | { |
272ca655 IS |
277 | u32 mode; |
278 | ||
e6c7ecb6 | 279 | BUG_ON(size > 1024); |
272ca655 | 280 | |
a1c03319 | 281 | mode = DMA_IN(chan, &chan->regs->mr, 32); |
272ca655 IS |
282 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
283 | ||
a1c03319 | 284 | DMA_OUT(chan, &chan->regs->mr, mode, 32); |
e6c7ecb6 | 285 | } |
173acc7c | 286 | |
e6c7ecb6 IS |
287 | /** |
288 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 289 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
290 | * @enable : 0 is disabled, 1 is enabled. |
291 | * | |
292 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
293 | * The DMA Request Count feature should be used in addition to this feature | |
294 | * to set the number of bytes to transfer before pausing the channel. | |
295 | */ | |
a1c03319 | 296 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
297 | { |
298 | if (enable) | |
a1c03319 | 299 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 300 | else |
a1c03319 | 301 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
302 | } |
303 | ||
304 | /** | |
305 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 306 | * @chan : Freescale DMA channel |
173acc7c ZW |
307 | * @enable : 0 is disabled, 1 is enabled. |
308 | * | |
309 | * If enable the external start, the channel can be started by an | |
310 | * external DMA start pin. So the dma_start() does not start the | |
311 | * transfer immediately. The DMA channel will wait for the | |
312 | * control pin asserted. | |
313 | */ | |
a1c03319 | 314 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
315 | { |
316 | if (enable) | |
a1c03319 | 317 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 318 | else |
a1c03319 | 319 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
320 | } |
321 | ||
9c3a50b7 IS |
322 | static void append_ld_queue(struct fsldma_chan *chan, |
323 | struct fsl_desc_sw *desc) | |
324 | { | |
325 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
326 | ||
327 | if (list_empty(&chan->ld_pending)) | |
328 | goto out_splice; | |
329 | ||
330 | /* | |
331 | * Add the hardware descriptor to the chain of hardware descriptors | |
332 | * that already exists in memory. | |
333 | * | |
334 | * This will un-set the EOL bit of the existing transaction, and the | |
335 | * last link in this transaction will become the EOL descriptor. | |
336 | */ | |
337 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
338 | ||
339 | /* | |
340 | * Add the software descriptor and all children to the list | |
341 | * of pending transactions | |
342 | */ | |
343 | out_splice: | |
344 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
345 | } | |
346 | ||
173acc7c ZW |
347 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
348 | { | |
a1c03319 | 349 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
350 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
351 | struct fsl_desc_sw *child; | |
173acc7c ZW |
352 | unsigned long flags; |
353 | dma_cookie_t cookie; | |
354 | ||
a1c03319 | 355 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 356 | |
9c3a50b7 IS |
357 | /* |
358 | * assign cookies to all of the software descriptors | |
359 | * that make up this transaction | |
360 | */ | |
a1c03319 | 361 | cookie = chan->common.cookie; |
eda34234 | 362 | list_for_each_entry(child, &desc->tx_list, node) { |
bcfb7465 IS |
363 | cookie++; |
364 | if (cookie < 0) | |
365 | cookie = 1; | |
366 | ||
6ca3a7a9 | 367 | child->async_tx.cookie = cookie; |
bcfb7465 IS |
368 | } |
369 | ||
a1c03319 | 370 | chan->common.cookie = cookie; |
9c3a50b7 IS |
371 | |
372 | /* put this transaction onto the tail of the pending queue */ | |
a1c03319 | 373 | append_ld_queue(chan, desc); |
173acc7c | 374 | |
a1c03319 | 375 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
376 | |
377 | return cookie; | |
378 | } | |
379 | ||
380 | /** | |
381 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 382 | * @chan : Freescale DMA channel |
173acc7c ZW |
383 | * |
384 | * Return - The descriptor allocated. NULL for failed. | |
385 | */ | |
386 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor( | |
a1c03319 | 387 | struct fsldma_chan *chan) |
173acc7c | 388 | { |
9c3a50b7 | 389 | struct fsl_desc_sw *desc; |
173acc7c | 390 | dma_addr_t pdesc; |
9c3a50b7 IS |
391 | |
392 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
393 | if (!desc) { | |
394 | dev_dbg(chan->dev, "out of memory for link desc\n"); | |
395 | return NULL; | |
173acc7c ZW |
396 | } |
397 | ||
9c3a50b7 IS |
398 | memset(desc, 0, sizeof(*desc)); |
399 | INIT_LIST_HEAD(&desc->tx_list); | |
400 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
401 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
402 | desc->async_tx.phys = pdesc; | |
403 | ||
404 | return desc; | |
173acc7c ZW |
405 | } |
406 | ||
407 | ||
408 | /** | |
409 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 410 | * @chan : Freescale DMA channel |
173acc7c ZW |
411 | * |
412 | * This function will create a dma pool for descriptor allocation. | |
413 | * | |
414 | * Return - The number of descriptors allocated. | |
415 | */ | |
a1c03319 | 416 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 417 | { |
a1c03319 | 418 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
419 | |
420 | /* Has this channel already been allocated? */ | |
a1c03319 | 421 | if (chan->desc_pool) |
77cd62e8 | 422 | return 1; |
173acc7c | 423 | |
9c3a50b7 IS |
424 | /* |
425 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
426 | * for meeting FSL DMA specification requirement. |
427 | */ | |
a1c03319 | 428 | chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", |
9c3a50b7 IS |
429 | chan->dev, |
430 | sizeof(struct fsl_desc_sw), | |
431 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 432 | if (!chan->desc_pool) { |
9c3a50b7 IS |
433 | dev_err(chan->dev, "unable to allocate channel %d " |
434 | "descriptor pool\n", chan->id); | |
435 | return -ENOMEM; | |
173acc7c ZW |
436 | } |
437 | ||
9c3a50b7 | 438 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
439 | return 1; |
440 | } | |
441 | ||
9c3a50b7 IS |
442 | /** |
443 | * fsldma_free_desc_list - Free all descriptors in a queue | |
444 | * @chan: Freescae DMA channel | |
445 | * @list: the list to free | |
446 | * | |
447 | * LOCKING: must hold chan->desc_lock | |
448 | */ | |
449 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
450 | struct list_head *list) | |
451 | { | |
452 | struct fsl_desc_sw *desc, *_desc; | |
453 | ||
454 | list_for_each_entry_safe(desc, _desc, list, node) { | |
455 | list_del(&desc->node); | |
456 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
457 | } | |
458 | } | |
459 | ||
460 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
461 | struct list_head *list) | |
462 | { | |
463 | struct fsl_desc_sw *desc, *_desc; | |
464 | ||
465 | list_for_each_entry_safe_reverse(desc, _desc, list, node) { | |
466 | list_del(&desc->node); | |
467 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
468 | } | |
469 | } | |
470 | ||
173acc7c ZW |
471 | /** |
472 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 473 | * @chan : Freescale DMA channel |
173acc7c | 474 | */ |
a1c03319 | 475 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 476 | { |
a1c03319 | 477 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
478 | unsigned long flags; |
479 | ||
a1c03319 IS |
480 | dev_dbg(chan->dev, "Free all channel resources.\n"); |
481 | spin_lock_irqsave(&chan->desc_lock, flags); | |
9c3a50b7 IS |
482 | fsldma_free_desc_list(chan, &chan->ld_pending); |
483 | fsldma_free_desc_list(chan, &chan->ld_running); | |
a1c03319 | 484 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
77cd62e8 | 485 | |
9c3a50b7 | 486 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 487 | chan->desc_pool = NULL; |
173acc7c ZW |
488 | } |
489 | ||
2187c269 | 490 | static struct dma_async_tx_descriptor * |
a1c03319 | 491 | fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) |
2187c269 | 492 | { |
a1c03319 | 493 | struct fsldma_chan *chan; |
2187c269 ZW |
494 | struct fsl_desc_sw *new; |
495 | ||
a1c03319 | 496 | if (!dchan) |
2187c269 ZW |
497 | return NULL; |
498 | ||
a1c03319 | 499 | chan = to_fsl_chan(dchan); |
2187c269 | 500 | |
a1c03319 | 501 | new = fsl_dma_alloc_descriptor(chan); |
2187c269 | 502 | if (!new) { |
c1433041 | 503 | dev_err(chan->dev, msg_ld_oom); |
2187c269 ZW |
504 | return NULL; |
505 | } | |
506 | ||
507 | new->async_tx.cookie = -EBUSY; | |
636bdeaa | 508 | new->async_tx.flags = flags; |
2187c269 | 509 | |
f79abb62 | 510 | /* Insert the link descriptor to the LD ring */ |
eda34234 | 511 | list_add_tail(&new->node, &new->tx_list); |
f79abb62 | 512 | |
2187c269 | 513 | /* Set End-of-link to the last link descriptor of new list*/ |
a1c03319 | 514 | set_ld_eol(chan, new); |
2187c269 ZW |
515 | |
516 | return &new->async_tx; | |
517 | } | |
518 | ||
173acc7c | 519 | static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( |
a1c03319 | 520 | struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, |
173acc7c ZW |
521 | size_t len, unsigned long flags) |
522 | { | |
a1c03319 | 523 | struct fsldma_chan *chan; |
173acc7c ZW |
524 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
525 | size_t copy; | |
173acc7c | 526 | |
a1c03319 | 527 | if (!dchan) |
173acc7c ZW |
528 | return NULL; |
529 | ||
530 | if (!len) | |
531 | return NULL; | |
532 | ||
a1c03319 | 533 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
534 | |
535 | do { | |
536 | ||
537 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 538 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 539 | if (!new) { |
c1433041 | 540 | dev_err(chan->dev, msg_ld_oom); |
2e077f8e | 541 | goto fail; |
173acc7c ZW |
542 | } |
543 | #ifdef FSL_DMA_LD_DEBUG | |
a1c03319 | 544 | dev_dbg(chan->dev, "new link desc alloc %p\n", new); |
173acc7c ZW |
545 | #endif |
546 | ||
56822843 | 547 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 548 | |
a1c03319 IS |
549 | set_desc_cnt(chan, &new->hw, copy); |
550 | set_desc_src(chan, &new->hw, dma_src); | |
551 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
552 | |
553 | if (!first) | |
554 | first = new; | |
555 | else | |
a1c03319 | 556 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
557 | |
558 | new->async_tx.cookie = 0; | |
636bdeaa | 559 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
560 | |
561 | prev = new; | |
562 | len -= copy; | |
563 | dma_src += copy; | |
738f5f7e | 564 | dma_dst += copy; |
173acc7c ZW |
565 | |
566 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 567 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
568 | } while (len); |
569 | ||
636bdeaa | 570 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
571 | new->async_tx.cookie = -EBUSY; |
572 | ||
573 | /* Set End-of-link to the last link descriptor of new list*/ | |
a1c03319 | 574 | set_ld_eol(chan, new); |
173acc7c | 575 | |
2e077f8e IS |
576 | return &first->async_tx; |
577 | ||
578 | fail: | |
579 | if (!first) | |
580 | return NULL; | |
581 | ||
9c3a50b7 | 582 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 583 | return NULL; |
173acc7c ZW |
584 | } |
585 | ||
c1433041 IS |
586 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
587 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
588 | struct scatterlist *src_sg, unsigned int src_nents, | |
589 | unsigned long flags) | |
590 | { | |
591 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
592 | struct fsldma_chan *chan = to_fsl_chan(dchan); | |
593 | size_t dst_avail, src_avail; | |
594 | dma_addr_t dst, src; | |
595 | size_t len; | |
596 | ||
597 | /* basic sanity checks */ | |
598 | if (dst_nents == 0 || src_nents == 0) | |
599 | return NULL; | |
600 | ||
601 | if (dst_sg == NULL || src_sg == NULL) | |
602 | return NULL; | |
603 | ||
604 | /* | |
605 | * TODO: should we check that both scatterlists have the same | |
606 | * TODO: number of bytes in total? Is that really an error? | |
607 | */ | |
608 | ||
609 | /* get prepared for the loop */ | |
610 | dst_avail = sg_dma_len(dst_sg); | |
611 | src_avail = sg_dma_len(src_sg); | |
612 | ||
613 | /* run until we are out of scatterlist entries */ | |
614 | while (true) { | |
615 | ||
616 | /* create the largest transaction possible */ | |
617 | len = min_t(size_t, src_avail, dst_avail); | |
618 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); | |
619 | if (len == 0) | |
620 | goto fetch; | |
621 | ||
622 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
623 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
624 | ||
625 | /* allocate and populate the descriptor */ | |
626 | new = fsl_dma_alloc_descriptor(chan); | |
627 | if (!new) { | |
628 | dev_err(chan->dev, msg_ld_oom); | |
629 | goto fail; | |
630 | } | |
631 | #ifdef FSL_DMA_LD_DEBUG | |
632 | dev_dbg(chan->dev, "new link desc alloc %p\n", new); | |
633 | #endif | |
634 | ||
635 | set_desc_cnt(chan, &new->hw, len); | |
636 | set_desc_src(chan, &new->hw, src); | |
637 | set_desc_dst(chan, &new->hw, dst); | |
638 | ||
639 | if (!first) | |
640 | first = new; | |
641 | else | |
642 | set_desc_next(chan, &prev->hw, new->async_tx.phys); | |
643 | ||
644 | new->async_tx.cookie = 0; | |
645 | async_tx_ack(&new->async_tx); | |
646 | prev = new; | |
647 | ||
648 | /* Insert the link descriptor to the LD ring */ | |
649 | list_add_tail(&new->node, &first->tx_list); | |
650 | ||
651 | /* update metadata */ | |
652 | dst_avail -= len; | |
653 | src_avail -= len; | |
654 | ||
655 | fetch: | |
656 | /* fetch the next dst scatterlist entry */ | |
657 | if (dst_avail == 0) { | |
658 | ||
659 | /* no more entries: we're done */ | |
660 | if (dst_nents == 0) | |
661 | break; | |
662 | ||
663 | /* fetch the next entry: if there are no more: done */ | |
664 | dst_sg = sg_next(dst_sg); | |
665 | if (dst_sg == NULL) | |
666 | break; | |
667 | ||
668 | dst_nents--; | |
669 | dst_avail = sg_dma_len(dst_sg); | |
670 | } | |
671 | ||
672 | /* fetch the next src scatterlist entry */ | |
673 | if (src_avail == 0) { | |
674 | ||
675 | /* no more entries: we're done */ | |
676 | if (src_nents == 0) | |
677 | break; | |
678 | ||
679 | /* fetch the next entry: if there are no more: done */ | |
680 | src_sg = sg_next(src_sg); | |
681 | if (src_sg == NULL) | |
682 | break; | |
683 | ||
684 | src_nents--; | |
685 | src_avail = sg_dma_len(src_sg); | |
686 | } | |
687 | } | |
688 | ||
689 | new->async_tx.flags = flags; /* client is in control of this ack */ | |
690 | new->async_tx.cookie = -EBUSY; | |
691 | ||
692 | /* Set End-of-link to the last link descriptor of new list */ | |
693 | set_ld_eol(chan, new); | |
694 | ||
695 | return &first->async_tx; | |
696 | ||
697 | fail: | |
698 | if (!first) | |
699 | return NULL; | |
700 | ||
701 | fsldma_free_desc_list_reverse(chan, &first->tx_list); | |
702 | return NULL; | |
703 | } | |
704 | ||
bbea0b6e IS |
705 | /** |
706 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
707 | * @chan: DMA channel | |
708 | * @sgl: scatterlist to transfer to/from | |
709 | * @sg_len: number of entries in @scatterlist | |
710 | * @direction: DMA direction | |
711 | * @flags: DMAEngine flags | |
712 | * | |
713 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
714 | * DMA_SLAVE API, this gets the device-specific information from the | |
715 | * chan->private variable. | |
716 | */ | |
717 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 718 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
bbea0b6e IS |
719 | enum dma_data_direction direction, unsigned long flags) |
720 | { | |
bbea0b6e | 721 | /* |
968f19ae | 722 | * This operation is not supported on the Freescale DMA controller |
bbea0b6e | 723 | * |
968f19ae IS |
724 | * However, we need to provide the function pointer to allow the |
725 | * device_control() method to work. | |
bbea0b6e | 726 | */ |
bbea0b6e IS |
727 | return NULL; |
728 | } | |
729 | ||
c3635c78 | 730 | static int fsl_dma_device_control(struct dma_chan *dchan, |
05827630 | 731 | enum dma_ctrl_cmd cmd, unsigned long arg) |
bbea0b6e | 732 | { |
968f19ae | 733 | struct dma_slave_config *config; |
a1c03319 | 734 | struct fsldma_chan *chan; |
bbea0b6e | 735 | unsigned long flags; |
968f19ae | 736 | int size; |
c3635c78 | 737 | |
a1c03319 | 738 | if (!dchan) |
c3635c78 | 739 | return -EINVAL; |
bbea0b6e | 740 | |
a1c03319 | 741 | chan = to_fsl_chan(dchan); |
bbea0b6e | 742 | |
968f19ae IS |
743 | switch (cmd) { |
744 | case DMA_TERMINATE_ALL: | |
745 | /* Halt the DMA engine */ | |
746 | dma_halt(chan); | |
bbea0b6e | 747 | |
968f19ae | 748 | spin_lock_irqsave(&chan->desc_lock, flags); |
bbea0b6e | 749 | |
968f19ae IS |
750 | /* Remove and free all of the descriptors in the LD queue */ |
751 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
752 | fsldma_free_desc_list(chan, &chan->ld_running); | |
bbea0b6e | 753 | |
968f19ae IS |
754 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
755 | return 0; | |
756 | ||
757 | case DMA_SLAVE_CONFIG: | |
758 | config = (struct dma_slave_config *)arg; | |
759 | ||
760 | /* make sure the channel supports setting burst size */ | |
761 | if (!chan->set_request_count) | |
762 | return -ENXIO; | |
763 | ||
764 | /* we set the controller burst size depending on direction */ | |
765 | if (config->direction == DMA_TO_DEVICE) | |
766 | size = config->dst_addr_width * config->dst_maxburst; | |
767 | else | |
768 | size = config->src_addr_width * config->src_maxburst; | |
769 | ||
770 | chan->set_request_count(chan, size); | |
771 | return 0; | |
772 | ||
773 | case FSLDMA_EXTERNAL_START: | |
774 | ||
775 | /* make sure the channel supports external start */ | |
776 | if (!chan->toggle_ext_start) | |
777 | return -ENXIO; | |
778 | ||
779 | chan->toggle_ext_start(chan, arg); | |
780 | return 0; | |
781 | ||
782 | default: | |
783 | return -ENXIO; | |
784 | } | |
c3635c78 LW |
785 | |
786 | return 0; | |
bbea0b6e IS |
787 | } |
788 | ||
173acc7c ZW |
789 | /** |
790 | * fsl_dma_update_completed_cookie - Update the completed cookie. | |
a1c03319 | 791 | * @chan : Freescale DMA channel |
9c3a50b7 IS |
792 | * |
793 | * CONTEXT: hardirq | |
173acc7c | 794 | */ |
a1c03319 | 795 | static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) |
173acc7c | 796 | { |
9c3a50b7 IS |
797 | struct fsl_desc_sw *desc; |
798 | unsigned long flags; | |
799 | dma_cookie_t cookie; | |
173acc7c | 800 | |
9c3a50b7 | 801 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 802 | |
9c3a50b7 IS |
803 | if (list_empty(&chan->ld_running)) { |
804 | dev_dbg(chan->dev, "no running descriptors\n"); | |
805 | goto out_unlock; | |
173acc7c | 806 | } |
9c3a50b7 IS |
807 | |
808 | /* Get the last descriptor, update the cookie to that */ | |
809 | desc = to_fsl_desc(chan->ld_running.prev); | |
810 | if (dma_is_idle(chan)) | |
811 | cookie = desc->async_tx.cookie; | |
76bd061f | 812 | else { |
9c3a50b7 | 813 | cookie = desc->async_tx.cookie - 1; |
76bd061f SM |
814 | if (unlikely(cookie < DMA_MIN_COOKIE)) |
815 | cookie = DMA_MAX_COOKIE; | |
816 | } | |
9c3a50b7 IS |
817 | |
818 | chan->completed_cookie = cookie; | |
819 | ||
820 | out_unlock: | |
821 | spin_unlock_irqrestore(&chan->desc_lock, flags); | |
822 | } | |
823 | ||
824 | /** | |
825 | * fsldma_desc_status - Check the status of a descriptor | |
826 | * @chan: Freescale DMA channel | |
827 | * @desc: DMA SW descriptor | |
828 | * | |
829 | * This function will return the status of the given descriptor | |
830 | */ | |
831 | static enum dma_status fsldma_desc_status(struct fsldma_chan *chan, | |
832 | struct fsl_desc_sw *desc) | |
833 | { | |
834 | return dma_async_is_complete(desc->async_tx.cookie, | |
835 | chan->completed_cookie, | |
836 | chan->common.cookie); | |
173acc7c ZW |
837 | } |
838 | ||
839 | /** | |
840 | * fsl_chan_ld_cleanup - Clean up link descriptors | |
a1c03319 | 841 | * @chan : Freescale DMA channel |
173acc7c ZW |
842 | * |
843 | * This function clean up the ld_queue of DMA channel. | |
173acc7c | 844 | */ |
a1c03319 | 845 | static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) |
173acc7c ZW |
846 | { |
847 | struct fsl_desc_sw *desc, *_desc; | |
848 | unsigned long flags; | |
849 | ||
a1c03319 | 850 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 851 | |
9c3a50b7 IS |
852 | dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie); |
853 | list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { | |
173acc7c ZW |
854 | dma_async_tx_callback callback; |
855 | void *callback_param; | |
856 | ||
9c3a50b7 | 857 | if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS) |
173acc7c ZW |
858 | break; |
859 | ||
9c3a50b7 | 860 | /* Remove from the list of running transactions */ |
173acc7c ZW |
861 | list_del(&desc->node); |
862 | ||
173acc7c | 863 | /* Run the link descriptor callback function */ |
9c3a50b7 IS |
864 | callback = desc->async_tx.callback; |
865 | callback_param = desc->async_tx.callback_param; | |
173acc7c | 866 | if (callback) { |
a1c03319 | 867 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
9c3a50b7 | 868 | dev_dbg(chan->dev, "LD %p callback\n", desc); |
173acc7c | 869 | callback(callback_param); |
a1c03319 | 870 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 871 | } |
9c3a50b7 IS |
872 | |
873 | /* Run any dependencies, then free the descriptor */ | |
874 | dma_run_dependencies(&desc->async_tx); | |
875 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
173acc7c | 876 | } |
9c3a50b7 | 877 | |
a1c03319 | 878 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
879 | } |
880 | ||
881 | /** | |
9c3a50b7 | 882 | * fsl_chan_xfer_ld_queue - transfer any pending transactions |
a1c03319 | 883 | * @chan : Freescale DMA channel |
9c3a50b7 IS |
884 | * |
885 | * This will make sure that any pending transactions will be run. | |
886 | * If the DMA controller is idle, it will be started. Otherwise, | |
887 | * the DMA controller's interrupt handler will start any pending | |
888 | * transactions when it becomes idle. | |
173acc7c | 889 | */ |
a1c03319 | 890 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) |
173acc7c | 891 | { |
9c3a50b7 | 892 | struct fsl_desc_sw *desc; |
173acc7c ZW |
893 | unsigned long flags; |
894 | ||
a1c03319 | 895 | spin_lock_irqsave(&chan->desc_lock, flags); |
138ef018 | 896 | |
9c3a50b7 IS |
897 | /* |
898 | * If the list of pending descriptors is empty, then we | |
899 | * don't need to do any work at all | |
900 | */ | |
901 | if (list_empty(&chan->ld_pending)) { | |
902 | dev_dbg(chan->dev, "no pending LDs\n"); | |
138ef018 | 903 | goto out_unlock; |
9c3a50b7 | 904 | } |
173acc7c | 905 | |
9c3a50b7 IS |
906 | /* |
907 | * The DMA controller is not idle, which means the interrupt | |
908 | * handler will start any queued transactions when it runs | |
909 | * at the end of the current transaction | |
910 | */ | |
911 | if (!dma_is_idle(chan)) { | |
912 | dev_dbg(chan->dev, "DMA controller still busy\n"); | |
913 | goto out_unlock; | |
914 | } | |
915 | ||
916 | /* | |
917 | * TODO: | |
918 | * make sure the dma_halt() function really un-wedges the | |
919 | * controller as much as possible | |
920 | */ | |
a1c03319 | 921 | dma_halt(chan); |
173acc7c | 922 | |
9c3a50b7 IS |
923 | /* |
924 | * If there are some link descriptors which have not been | |
925 | * transferred, we need to start the controller | |
173acc7c | 926 | */ |
173acc7c | 927 | |
9c3a50b7 IS |
928 | /* |
929 | * Move all elements from the queue of pending transactions | |
930 | * onto the list of running transactions | |
931 | */ | |
932 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); | |
933 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
934 | ||
935 | /* | |
936 | * Program the descriptor's address into the DMA controller, | |
937 | * then start the DMA transaction | |
938 | */ | |
939 | set_cdar(chan, desc->async_tx.phys); | |
940 | dma_start(chan); | |
138ef018 IS |
941 | |
942 | out_unlock: | |
a1c03319 | 943 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
944 | } |
945 | ||
946 | /** | |
947 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 948 | * @chan : Freescale DMA channel |
173acc7c | 949 | */ |
a1c03319 | 950 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 951 | { |
a1c03319 | 952 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
a1c03319 | 953 | fsl_chan_xfer_ld_queue(chan); |
173acc7c ZW |
954 | } |
955 | ||
173acc7c | 956 | /** |
07934481 | 957 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 958 | * @chan : Freescale DMA channel |
173acc7c | 959 | */ |
07934481 | 960 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 961 | dma_cookie_t cookie, |
07934481 | 962 | struct dma_tx_state *txstate) |
173acc7c | 963 | { |
a1c03319 | 964 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
965 | dma_cookie_t last_used; |
966 | dma_cookie_t last_complete; | |
967 | ||
a1c03319 | 968 | fsl_chan_ld_cleanup(chan); |
173acc7c | 969 | |
a1c03319 IS |
970 | last_used = dchan->cookie; |
971 | last_complete = chan->completed_cookie; | |
173acc7c | 972 | |
bca34692 | 973 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
173acc7c ZW |
974 | |
975 | return dma_async_is_complete(cookie, last_complete, last_used); | |
976 | } | |
977 | ||
d3f620b2 IS |
978 | /*----------------------------------------------------------------------------*/ |
979 | /* Interrupt Handling */ | |
980 | /*----------------------------------------------------------------------------*/ | |
981 | ||
e7a29151 | 982 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 983 | { |
a1c03319 | 984 | struct fsldma_chan *chan = data; |
1c62979e ZW |
985 | int update_cookie = 0; |
986 | int xfer_ld_q = 0; | |
a1c03319 | 987 | u32 stat; |
173acc7c | 988 | |
9c3a50b7 | 989 | /* save and clear the status register */ |
a1c03319 | 990 | stat = get_sr(chan); |
9c3a50b7 IS |
991 | set_sr(chan, stat); |
992 | dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat); | |
173acc7c ZW |
993 | |
994 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); | |
995 | if (!stat) | |
996 | return IRQ_NONE; | |
997 | ||
998 | if (stat & FSL_DMA_SR_TE) | |
a1c03319 | 999 | dev_err(chan->dev, "Transfer Error!\n"); |
173acc7c | 1000 | |
9c3a50b7 IS |
1001 | /* |
1002 | * Programming Error | |
f79abb62 ZW |
1003 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
1004 | * triger a PE interrupt. | |
1005 | */ | |
1006 | if (stat & FSL_DMA_SR_PE) { | |
9c3a50b7 | 1007 | dev_dbg(chan->dev, "irq: Programming Error INT\n"); |
a1c03319 | 1008 | if (get_bcr(chan) == 0) { |
f79abb62 ZW |
1009 | /* BCR register is 0, this is a DMA_INTERRUPT async_tx. |
1010 | * Now, update the completed cookie, and continue the | |
1011 | * next uncompleted transfer. | |
1012 | */ | |
1c62979e ZW |
1013 | update_cookie = 1; |
1014 | xfer_ld_q = 1; | |
f79abb62 ZW |
1015 | } |
1016 | stat &= ~FSL_DMA_SR_PE; | |
1017 | } | |
1018 | ||
9c3a50b7 IS |
1019 | /* |
1020 | * If the link descriptor segment transfer finishes, | |
173acc7c ZW |
1021 | * we will recycle the used descriptor. |
1022 | */ | |
1023 | if (stat & FSL_DMA_SR_EOSI) { | |
9c3a50b7 IS |
1024 | dev_dbg(chan->dev, "irq: End-of-segments INT\n"); |
1025 | dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n", | |
a1c03319 IS |
1026 | (unsigned long long)get_cdar(chan), |
1027 | (unsigned long long)get_ndar(chan)); | |
173acc7c | 1028 | stat &= ~FSL_DMA_SR_EOSI; |
1c62979e ZW |
1029 | update_cookie = 1; |
1030 | } | |
1031 | ||
9c3a50b7 IS |
1032 | /* |
1033 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
1034 | * and start the next transfer if it exist. |
1035 | */ | |
1036 | if (stat & FSL_DMA_SR_EOCDI) { | |
9c3a50b7 | 1037 | dev_dbg(chan->dev, "irq: End-of-Chain link INT\n"); |
1c62979e ZW |
1038 | stat &= ~FSL_DMA_SR_EOCDI; |
1039 | update_cookie = 1; | |
1040 | xfer_ld_q = 1; | |
173acc7c ZW |
1041 | } |
1042 | ||
9c3a50b7 IS |
1043 | /* |
1044 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
1045 | * we should clear the Channel Start bit for |
1046 | * prepare next transfer. | |
1047 | */ | |
1c62979e | 1048 | if (stat & FSL_DMA_SR_EOLNI) { |
9c3a50b7 | 1049 | dev_dbg(chan->dev, "irq: End-of-link INT\n"); |
173acc7c | 1050 | stat &= ~FSL_DMA_SR_EOLNI; |
1c62979e | 1051 | xfer_ld_q = 1; |
173acc7c ZW |
1052 | } |
1053 | ||
1c62979e | 1054 | if (update_cookie) |
a1c03319 | 1055 | fsl_dma_update_completed_cookie(chan); |
1c62979e | 1056 | if (xfer_ld_q) |
a1c03319 | 1057 | fsl_chan_xfer_ld_queue(chan); |
173acc7c | 1058 | if (stat) |
9c3a50b7 | 1059 | dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat); |
173acc7c | 1060 | |
9c3a50b7 | 1061 | dev_dbg(chan->dev, "irq: Exit\n"); |
a1c03319 | 1062 | tasklet_schedule(&chan->tasklet); |
173acc7c ZW |
1063 | return IRQ_HANDLED; |
1064 | } | |
1065 | ||
d3f620b2 IS |
1066 | static void dma_do_tasklet(unsigned long data) |
1067 | { | |
a1c03319 IS |
1068 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
1069 | fsl_chan_ld_cleanup(chan); | |
d3f620b2 IS |
1070 | } |
1071 | ||
1072 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1073 | { |
a4f56d4b | 1074 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1075 | struct fsldma_chan *chan; |
1076 | unsigned int handled = 0; | |
1077 | u32 gsr, mask; | |
1078 | int i; | |
173acc7c | 1079 | |
e7a29151 | 1080 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1081 | : in_le32(fdev->regs); |
1082 | mask = 0xff000000; | |
1083 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1084 | |
d3f620b2 IS |
1085 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1086 | chan = fdev->chan[i]; | |
1087 | if (!chan) | |
1088 | continue; | |
1089 | ||
1090 | if (gsr & mask) { | |
1091 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1092 | fsldma_chan_irq(irq, chan); | |
1093 | handled++; | |
1094 | } | |
1095 | ||
1096 | gsr &= ~mask; | |
1097 | mask >>= 8; | |
1098 | } | |
1099 | ||
1100 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1101 | } |
1102 | ||
d3f620b2 | 1103 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1104 | { |
d3f620b2 IS |
1105 | struct fsldma_chan *chan; |
1106 | int i; | |
1107 | ||
1108 | if (fdev->irq != NO_IRQ) { | |
1109 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1110 | free_irq(fdev->irq, fdev); | |
1111 | return; | |
1112 | } | |
1113 | ||
1114 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1115 | chan = fdev->chan[i]; | |
1116 | if (chan && chan->irq != NO_IRQ) { | |
1117 | dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id); | |
1118 | free_irq(chan->irq, chan); | |
1119 | } | |
1120 | } | |
1121 | } | |
1122 | ||
1123 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1124 | { | |
1125 | struct fsldma_chan *chan; | |
1126 | int ret; | |
1127 | int i; | |
1128 | ||
1129 | /* if we have a per-controller IRQ, use that */ | |
1130 | if (fdev->irq != NO_IRQ) { | |
1131 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1132 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1133 | "fsldma-controller", fdev); | |
1134 | return ret; | |
1135 | } | |
1136 | ||
1137 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1138 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1139 | chan = fdev->chan[i]; | |
1140 | if (!chan) | |
1141 | continue; | |
1142 | ||
1143 | if (chan->irq == NO_IRQ) { | |
1144 | dev_err(fdev->dev, "no interrupts property defined for " | |
1145 | "DMA channel %d. Please fix your " | |
1146 | "device tree\n", chan->id); | |
1147 | ret = -ENODEV; | |
1148 | goto out_unwind; | |
1149 | } | |
1150 | ||
1151 | dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id); | |
1152 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, | |
1153 | "fsldma-chan", chan); | |
1154 | if (ret) { | |
1155 | dev_err(fdev->dev, "unable to request IRQ for DMA " | |
1156 | "channel %d\n", chan->id); | |
1157 | goto out_unwind; | |
1158 | } | |
1159 | } | |
1160 | ||
1161 | return 0; | |
1162 | ||
1163 | out_unwind: | |
1164 | for (/* none */; i >= 0; i--) { | |
1165 | chan = fdev->chan[i]; | |
1166 | if (!chan) | |
1167 | continue; | |
1168 | ||
1169 | if (chan->irq == NO_IRQ) | |
1170 | continue; | |
1171 | ||
1172 | free_irq(chan->irq, chan); | |
1173 | } | |
1174 | ||
1175 | return ret; | |
173acc7c ZW |
1176 | } |
1177 | ||
a4f56d4b IS |
1178 | /*----------------------------------------------------------------------------*/ |
1179 | /* OpenFirmware Subsystem */ | |
1180 | /*----------------------------------------------------------------------------*/ | |
1181 | ||
1182 | static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, | |
77cd62e8 | 1183 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1184 | { |
a1c03319 | 1185 | struct fsldma_chan *chan; |
4ce0e953 | 1186 | struct resource res; |
173acc7c ZW |
1187 | int err; |
1188 | ||
173acc7c | 1189 | /* alloc channel */ |
a1c03319 IS |
1190 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1191 | if (!chan) { | |
e7a29151 IS |
1192 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1193 | err = -ENOMEM; | |
1194 | goto out_return; | |
1195 | } | |
1196 | ||
1197 | /* ioremap registers for use */ | |
a1c03319 IS |
1198 | chan->regs = of_iomap(node, 0); |
1199 | if (!chan->regs) { | |
e7a29151 IS |
1200 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1201 | err = -ENOMEM; | |
a1c03319 | 1202 | goto out_free_chan; |
173acc7c ZW |
1203 | } |
1204 | ||
4ce0e953 | 1205 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1206 | if (err) { |
e7a29151 IS |
1207 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1208 | goto out_iounmap_regs; | |
173acc7c ZW |
1209 | } |
1210 | ||
a1c03319 | 1211 | chan->feature = feature; |
173acc7c | 1212 | if (!fdev->feature) |
a1c03319 | 1213 | fdev->feature = chan->feature; |
173acc7c | 1214 | |
e7a29151 IS |
1215 | /* |
1216 | * If the DMA device's feature is different than the feature | |
1217 | * of its channels, report the bug | |
173acc7c | 1218 | */ |
a1c03319 | 1219 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1220 | |
a1c03319 IS |
1221 | chan->dev = fdev->dev; |
1222 | chan->id = ((res.start - 0x100) & 0xfff) >> 7; | |
1223 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { | |
e7a29151 | 1224 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1225 | err = -EINVAL; |
e7a29151 | 1226 | goto out_iounmap_regs; |
173acc7c | 1227 | } |
173acc7c | 1228 | |
a1c03319 IS |
1229 | fdev->chan[chan->id] = chan; |
1230 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
e7a29151 IS |
1231 | |
1232 | /* Initialize the channel */ | |
a1c03319 | 1233 | dma_init(chan); |
173acc7c ZW |
1234 | |
1235 | /* Clear cdar registers */ | |
a1c03319 | 1236 | set_cdar(chan, 0); |
173acc7c | 1237 | |
a1c03319 | 1238 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1239 | case FSL_DMA_IP_85XX: |
a1c03319 | 1240 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1241 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1242 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1243 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1244 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1245 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1246 | } |
1247 | ||
a1c03319 | 1248 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1249 | INIT_LIST_HEAD(&chan->ld_pending); |
1250 | INIT_LIST_HEAD(&chan->ld_running); | |
173acc7c | 1251 | |
a1c03319 | 1252 | chan->common.device = &fdev->common; |
173acc7c | 1253 | |
d3f620b2 | 1254 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1255 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1256 | |
173acc7c | 1257 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1258 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1259 | fdev->common.chancnt++; |
1260 | ||
a1c03319 IS |
1261 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1262 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1263 | |
1264 | return 0; | |
51ee87f2 | 1265 | |
e7a29151 | 1266 | out_iounmap_regs: |
a1c03319 IS |
1267 | iounmap(chan->regs); |
1268 | out_free_chan: | |
1269 | kfree(chan); | |
e7a29151 | 1270 | out_return: |
173acc7c ZW |
1271 | return err; |
1272 | } | |
1273 | ||
a1c03319 | 1274 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1275 | { |
a1c03319 IS |
1276 | irq_dispose_mapping(chan->irq); |
1277 | list_del(&chan->common.device_node); | |
1278 | iounmap(chan->regs); | |
1279 | kfree(chan); | |
173acc7c ZW |
1280 | } |
1281 | ||
2dc11581 | 1282 | static int __devinit fsldma_of_probe(struct platform_device *op, |
173acc7c ZW |
1283 | const struct of_device_id *match) |
1284 | { | |
a4f56d4b | 1285 | struct fsldma_device *fdev; |
77cd62e8 | 1286 | struct device_node *child; |
e7a29151 | 1287 | int err; |
173acc7c | 1288 | |
a4f56d4b | 1289 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1290 | if (!fdev) { |
e7a29151 IS |
1291 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1292 | err = -ENOMEM; | |
1293 | goto out_return; | |
173acc7c | 1294 | } |
e7a29151 IS |
1295 | |
1296 | fdev->dev = &op->dev; | |
173acc7c ZW |
1297 | INIT_LIST_HEAD(&fdev->common.channels); |
1298 | ||
e7a29151 | 1299 | /* ioremap the registers for use */ |
61c7a080 | 1300 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1301 | if (!fdev->regs) { |
1302 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1303 | err = -ENOMEM; | |
1304 | goto out_free_fdev; | |
173acc7c ZW |
1305 | } |
1306 | ||
d3f620b2 | 1307 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1308 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1309 | |
173acc7c ZW |
1310 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
1311 | dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); | |
c1433041 | 1312 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
bbea0b6e | 1313 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1314 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1315 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
2187c269 | 1316 | fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; |
173acc7c | 1317 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; |
c1433041 | 1318 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
07934481 | 1319 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1320 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
bbea0b6e | 1321 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
c3635c78 | 1322 | fdev->common.device_control = fsl_dma_device_control; |
e7a29151 | 1323 | fdev->common.dev = &op->dev; |
173acc7c | 1324 | |
e7a29151 | 1325 | dev_set_drvdata(&op->dev, fdev); |
77cd62e8 | 1326 | |
e7a29151 IS |
1327 | /* |
1328 | * We cannot use of_platform_bus_probe() because there is no | |
1329 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1330 | * channel object. |
1331 | */ | |
61c7a080 | 1332 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1333 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1334 | fsl_dma_chan_probe(fdev, child, |
1335 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1336 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1337 | } |
1338 | ||
1339 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1340 | fsl_dma_chan_probe(fdev, child, |
1341 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1342 | "fsl,elo-dma-channel"); | |
e7a29151 | 1343 | } |
77cd62e8 | 1344 | } |
173acc7c | 1345 | |
d3f620b2 IS |
1346 | /* |
1347 | * Hookup the IRQ handler(s) | |
1348 | * | |
1349 | * If we have a per-controller interrupt, we prefer that to the | |
1350 | * per-channel interrupts to reduce the number of shared interrupt | |
1351 | * handlers on the same IRQ line | |
1352 | */ | |
1353 | err = fsldma_request_irqs(fdev); | |
1354 | if (err) { | |
1355 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1356 | goto out_free_fdev; | |
1357 | } | |
1358 | ||
173acc7c ZW |
1359 | dma_async_device_register(&fdev->common); |
1360 | return 0; | |
1361 | ||
e7a29151 | 1362 | out_free_fdev: |
d3f620b2 | 1363 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1364 | kfree(fdev); |
e7a29151 | 1365 | out_return: |
173acc7c ZW |
1366 | return err; |
1367 | } | |
1368 | ||
2dc11581 | 1369 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1370 | { |
a4f56d4b | 1371 | struct fsldma_device *fdev; |
77cd62e8 TT |
1372 | unsigned int i; |
1373 | ||
e7a29151 | 1374 | fdev = dev_get_drvdata(&op->dev); |
77cd62e8 TT |
1375 | dma_async_device_unregister(&fdev->common); |
1376 | ||
d3f620b2 IS |
1377 | fsldma_free_irqs(fdev); |
1378 | ||
e7a29151 | 1379 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1380 | if (fdev->chan[i]) |
1381 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1382 | } |
77cd62e8 | 1383 | |
e7a29151 IS |
1384 | iounmap(fdev->regs); |
1385 | dev_set_drvdata(&op->dev, NULL); | |
77cd62e8 | 1386 | kfree(fdev); |
77cd62e8 TT |
1387 | |
1388 | return 0; | |
1389 | } | |
1390 | ||
4b1cf1fa | 1391 | static const struct of_device_id fsldma_of_ids[] = { |
049c9d45 KG |
1392 | { .compatible = "fsl,eloplus-dma", }, |
1393 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1394 | {} |
1395 | }; | |
1396 | ||
a4f56d4b | 1397 | static struct of_platform_driver fsldma_of_driver = { |
4018294b GL |
1398 | .driver = { |
1399 | .name = "fsl-elo-dma", | |
1400 | .owner = THIS_MODULE, | |
1401 | .of_match_table = fsldma_of_ids, | |
1402 | }, | |
1403 | .probe = fsldma_of_probe, | |
1404 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1405 | }; |
1406 | ||
a4f56d4b IS |
1407 | /*----------------------------------------------------------------------------*/ |
1408 | /* Module Init / Exit */ | |
1409 | /*----------------------------------------------------------------------------*/ | |
1410 | ||
1411 | static __init int fsldma_init(void) | |
173acc7c | 1412 | { |
77cd62e8 TT |
1413 | int ret; |
1414 | ||
1415 | pr_info("Freescale Elo / Elo Plus DMA driver\n"); | |
1416 | ||
a4f56d4b | 1417 | ret = of_register_platform_driver(&fsldma_of_driver); |
77cd62e8 TT |
1418 | if (ret) |
1419 | pr_err("fsldma: failed to register platform driver\n"); | |
1420 | ||
1421 | return ret; | |
1422 | } | |
1423 | ||
a4f56d4b | 1424 | static void __exit fsldma_exit(void) |
77cd62e8 | 1425 | { |
a4f56d4b | 1426 | of_unregister_platform_driver(&fsldma_of_driver); |
173acc7c ZW |
1427 | } |
1428 | ||
a4f56d4b IS |
1429 | subsys_initcall(fsldma_init); |
1430 | module_exit(fsldma_exit); | |
77cd62e8 TT |
1431 | |
1432 | MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); | |
1433 | MODULE_LICENSE("GPL"); |