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[net-next-2.6.git] / drivers / dma / dmaengine.c
CommitLineData
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1/*
2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21
22/*
23 * This code implements the DMA subsystem. It provides a HW-neutral interface
24 * for other kernel code to use asynchronous memory copy capabilities,
25 * if present, and allows different HW DMA drivers to register as providing
26 * this capability.
27 *
28 * Due to the fact we are accelerating what is already a relatively fast
29 * operation, the code goes to great lengths to avoid additional overhead,
30 * such as locking.
31 *
32 * LOCKING:
33 *
aa1e6f1a
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34 * The subsystem keeps a global list of dma_device structs it is protected by a
35 * mutex, dma_list_mutex.
c13c8260 36 *
f27c580c
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37 * A subsystem can get access to a channel by calling dmaengine_get() followed
38 * by dma_find_channel(), or if it has need for an exclusive channel it can call
39 * dma_request_channel(). Once a channel is allocated a reference is taken
40 * against its corresponding driver to disable removal.
41 *
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42 * Each device has a channels list, which runs unlocked but is never modified
43 * once the device is registered, it's just setup by the driver.
44 *
f27c580c 45 * See Documentation/dmaengine.txt for more details
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46 */
47
48#include <linux/init.h>
49#include <linux/module.h>
7405f74b 50#include <linux/mm.h>
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51#include <linux/device.h>
52#include <linux/dmaengine.h>
53#include <linux/hardirq.h>
54#include <linux/spinlock.h>
55#include <linux/percpu.h>
56#include <linux/rcupdate.h>
57#include <linux/mutex.h>
7405f74b 58#include <linux/jiffies.h>
2ba05622 59#include <linux/rculist.h>
864498aa 60#include <linux/idr.h>
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61
62static DEFINE_MUTEX(dma_list_mutex);
63static LIST_HEAD(dma_device_list);
6f49a57a 64static long dmaengine_ref_count;
864498aa 65static struct idr dma_idr;
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66
67/* --- sysfs implementation --- */
68
41d5e59c
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69/**
70 * dev_to_dma_chan - convert a device pointer to the its sysfs container object
71 * @dev - device node
72 *
73 * Must be called under dma_list_mutex
74 */
75static struct dma_chan *dev_to_dma_chan(struct device *dev)
76{
77 struct dma_chan_dev *chan_dev;
78
79 chan_dev = container_of(dev, typeof(*chan_dev), device);
80 return chan_dev->chan;
81}
82
891f78ea 83static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
c13c8260 84{
41d5e59c 85 struct dma_chan *chan;
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86 unsigned long count = 0;
87 int i;
41d5e59c 88 int err;
c13c8260 89
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90 mutex_lock(&dma_list_mutex);
91 chan = dev_to_dma_chan(dev);
92 if (chan) {
93 for_each_possible_cpu(i)
94 count += per_cpu_ptr(chan->local, i)->memcpy_count;
95 err = sprintf(buf, "%lu\n", count);
96 } else
97 err = -ENODEV;
98 mutex_unlock(&dma_list_mutex);
c13c8260 99
41d5e59c 100 return err;
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101}
102
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103static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
104 char *buf)
c13c8260 105{
41d5e59c 106 struct dma_chan *chan;
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107 unsigned long count = 0;
108 int i;
41d5e59c 109 int err;
c13c8260 110
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111 mutex_lock(&dma_list_mutex);
112 chan = dev_to_dma_chan(dev);
113 if (chan) {
114 for_each_possible_cpu(i)
115 count += per_cpu_ptr(chan->local, i)->bytes_transferred;
116 err = sprintf(buf, "%lu\n", count);
117 } else
118 err = -ENODEV;
119 mutex_unlock(&dma_list_mutex);
c13c8260 120
41d5e59c 121 return err;
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122}
123
891f78ea 124static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
c13c8260 125{
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126 struct dma_chan *chan;
127 int err;
c13c8260 128
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129 mutex_lock(&dma_list_mutex);
130 chan = dev_to_dma_chan(dev);
131 if (chan)
132 err = sprintf(buf, "%d\n", chan->client_count);
133 else
134 err = -ENODEV;
135 mutex_unlock(&dma_list_mutex);
136
137 return err;
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138}
139
891f78ea 140static struct device_attribute dma_attrs[] = {
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141 __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
142 __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
143 __ATTR(in_use, S_IRUGO, show_in_use, NULL),
144 __ATTR_NULL
145};
146
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147static void chan_dev_release(struct device *dev)
148{
149 struct dma_chan_dev *chan_dev;
150
151 chan_dev = container_of(dev, typeof(*chan_dev), device);
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152 if (atomic_dec_and_test(chan_dev->idr_ref)) {
153 mutex_lock(&dma_list_mutex);
154 idr_remove(&dma_idr, chan_dev->dev_id);
155 mutex_unlock(&dma_list_mutex);
156 kfree(chan_dev->idr_ref);
157 }
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158 kfree(chan_dev);
159}
160
c13c8260 161static struct class dma_devclass = {
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162 .name = "dma",
163 .dev_attrs = dma_attrs,
41d5e59c 164 .dev_release = chan_dev_release,
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165};
166
167/* --- client and device registration --- */
168
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169#define dma_device_satisfies_mask(device, mask) \
170 __dma_device_satisfies_mask((device), &(mask))
d379b01e 171static int
59b5ec21 172__dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
d379b01e
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173{
174 dma_cap_mask_t has;
175
59b5ec21 176 bitmap_and(has.bits, want->bits, device->cap_mask.bits,
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177 DMA_TX_TYPE_END);
178 return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
179}
180
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181static struct module *dma_chan_to_owner(struct dma_chan *chan)
182{
183 return chan->device->dev->driver->owner;
184}
185
186/**
187 * balance_ref_count - catch up the channel reference count
188 * @chan - channel to balance ->client_count versus dmaengine_ref_count
189 *
190 * balance_ref_count must be called under dma_list_mutex
191 */
192static void balance_ref_count(struct dma_chan *chan)
193{
194 struct module *owner = dma_chan_to_owner(chan);
195
196 while (chan->client_count < dmaengine_ref_count) {
197 __module_get(owner);
198 chan->client_count++;
199 }
200}
201
202/**
203 * dma_chan_get - try to grab a dma channel's parent driver module
204 * @chan - channel to grab
205 *
206 * Must be called under dma_list_mutex
207 */
208static int dma_chan_get(struct dma_chan *chan)
209{
210 int err = -ENODEV;
211 struct module *owner = dma_chan_to_owner(chan);
212
213 if (chan->client_count) {
214 __module_get(owner);
215 err = 0;
216 } else if (try_module_get(owner))
217 err = 0;
218
219 if (err == 0)
220 chan->client_count++;
221
222 /* allocate upon first client reference */
223 if (chan->client_count == 1 && err == 0) {
aa1e6f1a 224 int desc_cnt = chan->device->device_alloc_chan_resources(chan);
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DW
225
226 if (desc_cnt < 0) {
227 err = desc_cnt;
228 chan->client_count = 0;
229 module_put(owner);
59b5ec21 230 } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
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DW
231 balance_ref_count(chan);
232 }
233
234 return err;
235}
236
237/**
238 * dma_chan_put - drop a reference to a dma channel's parent driver module
239 * @chan - channel to release
240 *
241 * Must be called under dma_list_mutex
242 */
243static void dma_chan_put(struct dma_chan *chan)
244{
245 if (!chan->client_count)
246 return; /* this channel failed alloc_chan_resources */
247 chan->client_count--;
248 module_put(dma_chan_to_owner(chan));
249 if (chan->client_count == 0)
250 chan->device->device_free_chan_resources(chan);
251}
252
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253enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
254{
255 enum dma_status status;
256 unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
257
258 dma_async_issue_pending(chan);
259 do {
260 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
261 if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
262 printk(KERN_ERR "dma_sync_wait_timeout!\n");
263 return DMA_ERROR;
264 }
265 } while (status == DMA_IN_PROGRESS);
266
267 return status;
268}
269EXPORT_SYMBOL(dma_sync_wait);
270
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271/**
272 * dma_cap_mask_all - enable iteration over all operation types
273 */
274static dma_cap_mask_t dma_cap_mask_all;
275
276/**
277 * dma_chan_tbl_ent - tracks channel allocations per core/operation
278 * @chan - associated channel for this entry
279 */
280struct dma_chan_tbl_ent {
281 struct dma_chan *chan;
282};
283
284/**
285 * channel_table - percpu lookup table for memory-to-memory offload providers
286 */
287static struct dma_chan_tbl_ent *channel_table[DMA_TX_TYPE_END];
288
289static int __init dma_channel_table_init(void)
290{
291 enum dma_transaction_type cap;
292 int err = 0;
293
294 bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
295
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296 /* 'interrupt', 'private', and 'slave' are channel capabilities,
297 * but are not associated with an operation so they do not need
298 * an entry in the channel_table
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299 */
300 clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
59b5ec21 301 clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
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302 clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
303
304 for_each_dma_cap_mask(cap, dma_cap_mask_all) {
305 channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
306 if (!channel_table[cap]) {
307 err = -ENOMEM;
308 break;
309 }
310 }
311
312 if (err) {
313 pr_err("dmaengine: initialization failure\n");
314 for_each_dma_cap_mask(cap, dma_cap_mask_all)
315 if (channel_table[cap])
316 free_percpu(channel_table[cap]);
317 }
318
319 return err;
320}
652afc27 321arch_initcall(dma_channel_table_init);
bec08513
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322
323/**
324 * dma_find_channel - find a channel to carry out the operation
325 * @tx_type: transaction type
326 */
327struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
328{
329 struct dma_chan *chan;
330 int cpu;
331
bec08513
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332 cpu = get_cpu();
333 chan = per_cpu_ptr(channel_table[tx_type], cpu)->chan;
334 put_cpu();
335
336 return chan;
337}
338EXPORT_SYMBOL(dma_find_channel);
339
2ba05622
DW
340/**
341 * dma_issue_pending_all - flush all pending operations across all channels
342 */
343void dma_issue_pending_all(void)
344{
345 struct dma_device *device;
346 struct dma_chan *chan;
347
2ba05622 348 rcu_read_lock();
59b5ec21
DW
349 list_for_each_entry_rcu(device, &dma_device_list, global_node) {
350 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
351 continue;
2ba05622
DW
352 list_for_each_entry(chan, &device->channels, device_node)
353 if (chan->client_count)
354 device->device_issue_pending(chan);
59b5ec21 355 }
2ba05622
DW
356 rcu_read_unlock();
357}
358EXPORT_SYMBOL(dma_issue_pending_all);
359
bec08513
DW
360/**
361 * nth_chan - returns the nth channel of the given capability
362 * @cap: capability to match
363 * @n: nth channel desired
364 *
365 * Defaults to returning the channel with the desired capability and the
366 * lowest reference count when 'n' cannot be satisfied. Must be called
367 * under dma_list_mutex.
368 */
369static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
370{
371 struct dma_device *device;
372 struct dma_chan *chan;
373 struct dma_chan *ret = NULL;
374 struct dma_chan *min = NULL;
375
376 list_for_each_entry(device, &dma_device_list, global_node) {
59b5ec21
DW
377 if (!dma_has_cap(cap, device->cap_mask) ||
378 dma_has_cap(DMA_PRIVATE, device->cap_mask))
bec08513
DW
379 continue;
380 list_for_each_entry(chan, &device->channels, device_node) {
381 if (!chan->client_count)
382 continue;
383 if (!min)
384 min = chan;
385 else if (chan->table_count < min->table_count)
386 min = chan;
387
388 if (n-- == 0) {
389 ret = chan;
390 break; /* done */
391 }
392 }
393 if (ret)
394 break; /* done */
395 }
396
397 if (!ret)
398 ret = min;
399
400 if (ret)
401 ret->table_count++;
402
403 return ret;
404}
405
406/**
407 * dma_channel_rebalance - redistribute the available channels
408 *
409 * Optimize for cpu isolation (each cpu gets a dedicated channel for an
410 * operation type) in the SMP case, and operation isolation (avoid
411 * multi-tasking channels) in the non-SMP case. Must be called under
412 * dma_list_mutex.
413 */
414static void dma_channel_rebalance(void)
415{
416 struct dma_chan *chan;
417 struct dma_device *device;
418 int cpu;
419 int cap;
420 int n;
421
422 /* undo the last distribution */
423 for_each_dma_cap_mask(cap, dma_cap_mask_all)
424 for_each_possible_cpu(cpu)
425 per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
426
59b5ec21
DW
427 list_for_each_entry(device, &dma_device_list, global_node) {
428 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
429 continue;
bec08513
DW
430 list_for_each_entry(chan, &device->channels, device_node)
431 chan->table_count = 0;
59b5ec21 432 }
bec08513
DW
433
434 /* don't populate the channel_table if no clients are available */
435 if (!dmaengine_ref_count)
436 return;
437
438 /* redistribute available channels */
439 n = 0;
440 for_each_dma_cap_mask(cap, dma_cap_mask_all)
441 for_each_online_cpu(cpu) {
442 if (num_possible_cpus() > 1)
443 chan = nth_chan(cap, n++);
444 else
445 chan = nth_chan(cap, -1);
446
447 per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
448 }
449}
450
e2346677
DW
451static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
452 dma_filter_fn fn, void *fn_param)
59b5ec21
DW
453{
454 struct dma_chan *chan;
59b5ec21
DW
455
456 if (!__dma_device_satisfies_mask(dev, mask)) {
457 pr_debug("%s: wrong capabilities\n", __func__);
458 return NULL;
459 }
460 /* devices with multiple channels need special handling as we need to
461 * ensure that all channels are either private or public.
462 */
463 if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
464 list_for_each_entry(chan, &dev->channels, device_node) {
465 /* some channels are already publicly allocated */
466 if (chan->client_count)
467 return NULL;
468 }
469
470 list_for_each_entry(chan, &dev->channels, device_node) {
471 if (chan->client_count) {
472 pr_debug("%s: %s busy\n",
41d5e59c 473 __func__, dma_chan_name(chan));
59b5ec21
DW
474 continue;
475 }
e2346677
DW
476 if (fn && !fn(chan, fn_param)) {
477 pr_debug("%s: %s filter said false\n",
478 __func__, dma_chan_name(chan));
479 continue;
480 }
481 return chan;
59b5ec21
DW
482 }
483
e2346677 484 return NULL;
59b5ec21
DW
485}
486
487/**
488 * dma_request_channel - try to allocate an exclusive channel
489 * @mask: capabilities that the channel must satisfy
490 * @fn: optional callback to disposition available channels
491 * @fn_param: opaque parameter to pass to dma_filter_fn
492 */
493struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
494{
495 struct dma_device *device, *_d;
496 struct dma_chan *chan = NULL;
59b5ec21
DW
497 int err;
498
499 /* Find a channel */
500 mutex_lock(&dma_list_mutex);
501 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
e2346677
DW
502 chan = private_candidate(mask, device, fn, fn_param);
503 if (chan) {
59b5ec21
DW
504 /* Found a suitable channel, try to grab, prep, and
505 * return it. We first set DMA_PRIVATE to disable
506 * balance_ref_count as this channel will not be
507 * published in the general-purpose allocator
508 */
509 dma_cap_set(DMA_PRIVATE, device->cap_mask);
510 err = dma_chan_get(chan);
511
512 if (err == -ENODEV) {
513 pr_debug("%s: %s module removed\n", __func__,
41d5e59c 514 dma_chan_name(chan));
59b5ec21
DW
515 list_del_rcu(&device->global_node);
516 } else if (err)
517 pr_err("dmaengine: failed to get %s: (%d)\n",
41d5e59c 518 dma_chan_name(chan), err);
59b5ec21
DW
519 else
520 break;
e2346677
DW
521 chan = NULL;
522 }
59b5ec21
DW
523 }
524 mutex_unlock(&dma_list_mutex);
525
526 pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
41d5e59c 527 chan ? dma_chan_name(chan) : NULL);
59b5ec21
DW
528
529 return chan;
530}
531EXPORT_SYMBOL_GPL(__dma_request_channel);
532
533void dma_release_channel(struct dma_chan *chan)
534{
535 mutex_lock(&dma_list_mutex);
536 WARN_ONCE(chan->client_count != 1,
537 "chan reference count %d != 1\n", chan->client_count);
538 dma_chan_put(chan);
539 mutex_unlock(&dma_list_mutex);
540}
541EXPORT_SYMBOL_GPL(dma_release_channel);
542
d379b01e 543/**
209b84a8 544 * dmaengine_get - register interest in dma_channels
d379b01e 545 */
209b84a8 546void dmaengine_get(void)
d379b01e 547{
6f49a57a
DW
548 struct dma_device *device, *_d;
549 struct dma_chan *chan;
550 int err;
551
c13c8260 552 mutex_lock(&dma_list_mutex);
6f49a57a
DW
553 dmaengine_ref_count++;
554
555 /* try to grab channels */
59b5ec21
DW
556 list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
557 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
558 continue;
6f49a57a
DW
559 list_for_each_entry(chan, &device->channels, device_node) {
560 err = dma_chan_get(chan);
561 if (err == -ENODEV) {
562 /* module removed before we could use it */
2ba05622 563 list_del_rcu(&device->global_node);
6f49a57a
DW
564 break;
565 } else if (err)
566 pr_err("dmaengine: failed to get %s: (%d)\n",
41d5e59c 567 dma_chan_name(chan), err);
6f49a57a 568 }
59b5ec21 569 }
6f49a57a 570
bec08513
DW
571 /* if this is the first reference and there were channels
572 * waiting we need to rebalance to get those channels
573 * incorporated into the channel table
574 */
575 if (dmaengine_ref_count == 1)
576 dma_channel_rebalance();
c13c8260 577 mutex_unlock(&dma_list_mutex);
c13c8260 578}
209b84a8 579EXPORT_SYMBOL(dmaengine_get);
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580
581/**
209b84a8 582 * dmaengine_put - let dma drivers be removed when ref_count == 0
c13c8260 583 */
209b84a8 584void dmaengine_put(void)
c13c8260 585{
d379b01e 586 struct dma_device *device;
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587 struct dma_chan *chan;
588
c13c8260 589 mutex_lock(&dma_list_mutex);
6f49a57a
DW
590 dmaengine_ref_count--;
591 BUG_ON(dmaengine_ref_count < 0);
592 /* drop channel references */
59b5ec21
DW
593 list_for_each_entry(device, &dma_device_list, global_node) {
594 if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
595 continue;
6f49a57a
DW
596 list_for_each_entry(chan, &device->channels, device_node)
597 dma_chan_put(chan);
59b5ec21 598 }
c13c8260 599 mutex_unlock(&dma_list_mutex);
c13c8260 600}
209b84a8 601EXPORT_SYMBOL(dmaengine_put);
c13c8260 602
c13c8260 603/**
6508871e 604 * dma_async_device_register - registers DMA devices found
c13c8260
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605 * @device: &dma_device
606 */
607int dma_async_device_register(struct dma_device *device)
608{
ff487fb7 609 int chancnt = 0, rc;
c13c8260 610 struct dma_chan* chan;
864498aa 611 atomic_t *idr_ref;
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612
613 if (!device)
614 return -ENODEV;
615
7405f74b
DW
616 /* validate device routines */
617 BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
618 !device->device_prep_dma_memcpy);
619 BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
620 !device->device_prep_dma_xor);
621 BUG_ON(dma_has_cap(DMA_ZERO_SUM, device->cap_mask) &&
622 !device->device_prep_dma_zero_sum);
623 BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
624 !device->device_prep_dma_memset);
9b941c66 625 BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
7405f74b 626 !device->device_prep_dma_interrupt);
dc0ee643
HS
627 BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
628 !device->device_prep_slave_sg);
629 BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
630 !device->device_terminate_all);
7405f74b
DW
631
632 BUG_ON(!device->device_alloc_chan_resources);
633 BUG_ON(!device->device_free_chan_resources);
7405f74b
DW
634 BUG_ON(!device->device_is_tx_complete);
635 BUG_ON(!device->device_issue_pending);
636 BUG_ON(!device->dev);
637
864498aa
DW
638 idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
639 if (!idr_ref)
640 return -ENOMEM;
641 atomic_set(idr_ref, 0);
642 idr_retry:
643 if (!idr_pre_get(&dma_idr, GFP_KERNEL))
644 return -ENOMEM;
b0b42b16 645 mutex_lock(&dma_list_mutex);
864498aa 646 rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
b0b42b16 647 mutex_unlock(&dma_list_mutex);
864498aa
DW
648 if (rc == -EAGAIN)
649 goto idr_retry;
650 else if (rc != 0)
651 return rc;
c13c8260
CL
652
653 /* represent channels in sysfs. Probably want devs too */
654 list_for_each_entry(chan, &device->channels, device_node) {
655 chan->local = alloc_percpu(typeof(*chan->local));
656 if (chan->local == NULL)
657 continue;
41d5e59c
DW
658 chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
659 if (chan->dev == NULL) {
660 free_percpu(chan->local);
661 continue;
662 }
c13c8260
CL
663
664 chan->chan_id = chancnt++;
41d5e59c
DW
665 chan->dev->device.class = &dma_devclass;
666 chan->dev->device.parent = device->dev;
667 chan->dev->chan = chan;
864498aa
DW
668 chan->dev->idr_ref = idr_ref;
669 chan->dev->dev_id = device->dev_id;
670 atomic_inc(idr_ref);
41d5e59c 671 dev_set_name(&chan->dev->device, "dma%dchan%d",
06190d84 672 device->dev_id, chan->chan_id);
c13c8260 673
41d5e59c 674 rc = device_register(&chan->dev->device);
ff487fb7 675 if (rc) {
ff487fb7
JG
676 free_percpu(chan->local);
677 chan->local = NULL;
678 goto err_out;
679 }
7cc5bf9a 680 chan->client_count = 0;
c13c8260 681 }
59b5ec21 682 device->chancnt = chancnt;
c13c8260
CL
683
684 mutex_lock(&dma_list_mutex);
59b5ec21
DW
685 /* take references on public channels */
686 if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
6f49a57a
DW
687 list_for_each_entry(chan, &device->channels, device_node) {
688 /* if clients are already waiting for channels we need
689 * to take references on their behalf
690 */
691 if (dma_chan_get(chan) == -ENODEV) {
692 /* note we can only get here for the first
693 * channel as the remaining channels are
694 * guaranteed to get a reference
695 */
696 rc = -ENODEV;
697 mutex_unlock(&dma_list_mutex);
698 goto err_out;
699 }
700 }
2ba05622 701 list_add_tail_rcu(&device->global_node, &dma_device_list);
bec08513 702 dma_channel_rebalance();
c13c8260
CL
703 mutex_unlock(&dma_list_mutex);
704
c13c8260 705 return 0;
ff487fb7
JG
706
707err_out:
708 list_for_each_entry(chan, &device->channels, device_node) {
709 if (chan->local == NULL)
710 continue;
41d5e59c
DW
711 mutex_lock(&dma_list_mutex);
712 chan->dev->chan = NULL;
713 mutex_unlock(&dma_list_mutex);
714 device_unregister(&chan->dev->device);
ff487fb7
JG
715 free_percpu(chan->local);
716 }
717 return rc;
c13c8260 718}
765e3d8a 719EXPORT_SYMBOL(dma_async_device_register);
c13c8260 720
6508871e 721/**
6f49a57a 722 * dma_async_device_unregister - unregister a DMA device
6508871e 723 * @device: &dma_device
f27c580c
DW
724 *
725 * This routine is called by dma driver exit routines, dmaengine holds module
726 * references to prevent it being called while channels are in use.
6508871e
RD
727 */
728void dma_async_device_unregister(struct dma_device *device)
c13c8260
CL
729{
730 struct dma_chan *chan;
c13c8260
CL
731
732 mutex_lock(&dma_list_mutex);
2ba05622 733 list_del_rcu(&device->global_node);
bec08513 734 dma_channel_rebalance();
c13c8260
CL
735 mutex_unlock(&dma_list_mutex);
736
737 list_for_each_entry(chan, &device->channels, device_node) {
6f49a57a
DW
738 WARN_ONCE(chan->client_count,
739 "%s called while %d clients hold a reference\n",
740 __func__, chan->client_count);
41d5e59c
DW
741 mutex_lock(&dma_list_mutex);
742 chan->dev->chan = NULL;
743 mutex_unlock(&dma_list_mutex);
744 device_unregister(&chan->dev->device);
c13c8260 745 }
c13c8260 746}
765e3d8a 747EXPORT_SYMBOL(dma_async_device_unregister);
c13c8260 748
7405f74b
DW
749/**
750 * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
751 * @chan: DMA channel to offload copy to
752 * @dest: destination address (virtual)
753 * @src: source address (virtual)
754 * @len: length
755 *
756 * Both @dest and @src must be mappable to a bus address according to the
757 * DMA mapping API rules for streaming mappings.
758 * Both @dest and @src must stay memory resident (kernel memory or locked
759 * user space pages).
760 */
761dma_cookie_t
762dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
763 void *src, size_t len)
764{
765 struct dma_device *dev = chan->device;
766 struct dma_async_tx_descriptor *tx;
0036731c 767 dma_addr_t dma_dest, dma_src;
7405f74b
DW
768 dma_cookie_t cookie;
769 int cpu;
770
0036731c
DW
771 dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
772 dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
636bdeaa
DW
773 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
774 DMA_CTRL_ACK);
0036731c
DW
775
776 if (!tx) {
777 dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
778 dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
7405f74b 779 return -ENOMEM;
0036731c 780 }
7405f74b 781
7405f74b 782 tx->callback = NULL;
7405f74b
DW
783 cookie = tx->tx_submit(tx);
784
785 cpu = get_cpu();
786 per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
787 per_cpu_ptr(chan->local, cpu)->memcpy_count++;
788 put_cpu();
789
790 return cookie;
791}
792EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
793
794/**
795 * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
796 * @chan: DMA channel to offload copy to
797 * @page: destination page
798 * @offset: offset in page to copy to
799 * @kdata: source address (virtual)
800 * @len: length
801 *
802 * Both @page/@offset and @kdata must be mappable to a bus address according
803 * to the DMA mapping API rules for streaming mappings.
804 * Both @page/@offset and @kdata must stay memory resident (kernel memory or
805 * locked user space pages)
806 */
807dma_cookie_t
808dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
809 unsigned int offset, void *kdata, size_t len)
810{
811 struct dma_device *dev = chan->device;
812 struct dma_async_tx_descriptor *tx;
0036731c 813 dma_addr_t dma_dest, dma_src;
7405f74b
DW
814 dma_cookie_t cookie;
815 int cpu;
816
0036731c
DW
817 dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
818 dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
636bdeaa
DW
819 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
820 DMA_CTRL_ACK);
0036731c
DW
821
822 if (!tx) {
823 dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
824 dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
7405f74b 825 return -ENOMEM;
0036731c 826 }
7405f74b 827
7405f74b 828 tx->callback = NULL;
7405f74b
DW
829 cookie = tx->tx_submit(tx);
830
831 cpu = get_cpu();
832 per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
833 per_cpu_ptr(chan->local, cpu)->memcpy_count++;
834 put_cpu();
835
836 return cookie;
837}
838EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
839
840/**
841 * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
842 * @chan: DMA channel to offload copy to
843 * @dest_pg: destination page
844 * @dest_off: offset in page to copy to
845 * @src_pg: source page
846 * @src_off: offset in page to copy from
847 * @len: length
848 *
849 * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
850 * address according to the DMA mapping API rules for streaming mappings.
851 * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
852 * (kernel memory or locked user space pages).
853 */
854dma_cookie_t
855dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
856 unsigned int dest_off, struct page *src_pg, unsigned int src_off,
857 size_t len)
858{
859 struct dma_device *dev = chan->device;
860 struct dma_async_tx_descriptor *tx;
0036731c 861 dma_addr_t dma_dest, dma_src;
7405f74b
DW
862 dma_cookie_t cookie;
863 int cpu;
864
0036731c
DW
865 dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
866 dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
867 DMA_FROM_DEVICE);
636bdeaa
DW
868 tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
869 DMA_CTRL_ACK);
0036731c
DW
870
871 if (!tx) {
872 dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
873 dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
7405f74b 874 return -ENOMEM;
0036731c 875 }
7405f74b 876
7405f74b 877 tx->callback = NULL;
7405f74b
DW
878 cookie = tx->tx_submit(tx);
879
880 cpu = get_cpu();
881 per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
882 per_cpu_ptr(chan->local, cpu)->memcpy_count++;
883 put_cpu();
884
885 return cookie;
886}
887EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
888
889void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
890 struct dma_chan *chan)
891{
892 tx->chan = chan;
893 spin_lock_init(&tx->lock);
7405f74b
DW
894}
895EXPORT_SYMBOL(dma_async_tx_descriptor_init);
896
07f2211e
DW
897/* dma_wait_for_async_tx - spin wait for a transaction to complete
898 * @tx: in-flight transaction to wait on
899 *
900 * This routine assumes that tx was obtained from a call to async_memcpy,
901 * async_xor, async_memset, etc which ensures that tx is "in-flight" (prepped
902 * and submitted). Walking the parent chain is only meant to cover for DMA
903 * drivers that do not implement the DMA_INTERRUPT capability and may race with
904 * the driver's descriptor cleanup routine.
905 */
906enum dma_status
907dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
908{
909 enum dma_status status;
910 struct dma_async_tx_descriptor *iter;
911 struct dma_async_tx_descriptor *parent;
912
913 if (!tx)
914 return DMA_SUCCESS;
915
916 WARN_ONCE(tx->parent, "%s: speculatively walking dependency chain for"
41d5e59c 917 " %s\n", __func__, dma_chan_name(tx->chan));
07f2211e
DW
918
919 /* poll through the dependency chain, return when tx is complete */
920 do {
921 iter = tx;
922
923 /* find the root of the unsubmitted dependency chain */
924 do {
925 parent = iter->parent;
926 if (!parent)
927 break;
928 else
929 iter = parent;
930 } while (parent);
931
932 /* there is a small window for ->parent == NULL and
933 * ->cookie == -EBUSY
934 */
935 while (iter->cookie == -EBUSY)
936 cpu_relax();
937
938 status = dma_sync_wait(iter->chan, iter->cookie);
939 } while (status == DMA_IN_PROGRESS || (iter != tx));
940
941 return status;
942}
943EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
944
945/* dma_run_dependencies - helper routine for dma drivers to process
946 * (start) dependent operations on their target channel
947 * @tx: transaction with dependencies
948 */
949void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
950{
951 struct dma_async_tx_descriptor *dep = tx->next;
952 struct dma_async_tx_descriptor *dep_next;
953 struct dma_chan *chan;
954
955 if (!dep)
956 return;
957
dd59b853
YT
958 /* we'll submit tx->next now, so clear the link */
959 tx->next = NULL;
07f2211e
DW
960 chan = dep->chan;
961
962 /* keep submitting up until a channel switch is detected
963 * in that case we will be called again as a result of
964 * processing the interrupt from async_tx_channel_switch
965 */
966 for (; dep; dep = dep_next) {
967 spin_lock_bh(&dep->lock);
968 dep->parent = NULL;
969 dep_next = dep->next;
970 if (dep_next && dep_next->chan == chan)
971 dep->next = NULL; /* ->next will be submitted */
972 else
973 dep_next = NULL; /* submit current dep and terminate */
974 spin_unlock_bh(&dep->lock);
975
976 dep->tx_submit(dep);
977 }
978
979 chan->device->device_issue_pending(chan);
980}
981EXPORT_SYMBOL_GPL(dma_run_dependencies);
982
c13c8260
CL
983static int __init dma_bus_init(void)
984{
864498aa 985 idr_init(&dma_idr);
c13c8260
CL
986 mutex_init(&dma_list_mutex);
987 return class_register(&dma_devclass);
988}
652afc27 989arch_initcall(dma_bus_init);
c13c8260 990
bec08513 991